radeonfb.c revision 1.64
1 /* $NetBSD: radeonfb.c,v 1.64 2012/10/04 10:29:24 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.64 2012/10/04 10:29:24 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 1, 0 }, 384 { 2, 1 }, 385 { 3, 4 }, 386 { 4, 2 }, 387 { 6, 6 }, 388 { 8, 3 }, 389 { 12, 7 }, 390 { 0, 0 } 391 }; 392 393 /* 394 * This table taken from X11. 395 */ 396 static const struct { 397 int family; 398 struct radeon_tmds_pll plls[4]; 399 } radeonfb_tmds_pll[] = { 400 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RS100, {{0, 0}}}, 403 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 407 { RADEON_RS300, {{0, 0}}}, 408 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 409 { RADEON_R300, {{-1, 0xb01cb}}}, 410 { RADEON_R350, {{-1, 0xb01cb}}}, 411 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 412 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_R420, {{-1, 0xb01cb}}}, 414 }; 415 416 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 417 418 419 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 420 radeonfb_match, radeonfb_attach, NULL, NULL); 421 422 static int 423 radeonfb_match(device_t parent, cfdata_t match, void *aux) 424 { 425 const struct pci_attach_args *pa = aux; 426 int i; 427 428 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 429 return 0; 430 431 for (i = 0; radeonfb_devices[i].devid; i++) { 432 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 433 return 100; /* high to defeat VGA/VESA */ 434 } 435 436 return 0; 437 } 438 439 static void 440 radeonfb_attach(device_t parent, device_t dev, void *aux) 441 { 442 struct radeonfb_softc *sc = device_private(dev); 443 const struct pci_attach_args *pa = aux; 444 const char *mptr; 445 bus_size_t bsz; 446 pcireg_t screg; 447 int i, j, fg, bg, ul, flags; 448 uint32_t v; 449 450 sc->sc_dev = dev; 451 sc->sc_id = pa->pa_id; 452 for (i = 0; radeonfb_devices[i].devid; i++) { 453 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 454 break; 455 } 456 457 pci_aprint_devinfo(pa, NULL); 458 459 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 460 461 KASSERT(radeonfb_devices[i].devid != 0); 462 sc->sc_pt = pa->pa_tag; 463 sc->sc_iot = pa->pa_iot; 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_family = radeonfb_devices[i].family; 466 sc->sc_flags = radeonfb_devices[i].flags; 467 468 /* enable memory and IO access */ 469 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 470 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 472 473 /* 474 * Some flags are general to entire chip families, and rather 475 * than clutter up the table with them, we go ahead and set 476 * them here. 477 */ 478 switch (sc->sc_family) { 479 case RADEON_RS100: 480 case RADEON_RS200: 481 sc->sc_flags |= RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_RV100: 485 case RADEON_RV200: 486 case RADEON_RV250: 487 case RADEON_RV280: 488 sc->sc_flags |= RFB_RV100; 489 break; 490 491 case RADEON_RS300: 492 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_R300: 496 case RADEON_RV350: 497 case RADEON_R350: 498 case RADEON_RV380: 499 case RADEON_R420: 500 /* newer chips */ 501 sc->sc_flags |= RFB_R300; 502 break; 503 504 case RADEON_R100: 505 sc->sc_flags |= RFB_NCRTC2; 506 break; 507 } 508 509 if ((sc->sc_family == RADEON_RV200) || 510 (sc->sc_family == RADEON_RV250) || 511 (sc->sc_family == RADEON_RV280) || 512 (sc->sc_family == RADEON_RV350)) { 513 bool inverted = 0; 514 /* backlight level is linear */ 515 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 516 prop_dictionary_get_bool(device_properties(sc->sc_dev), 517 "backlight_level_reverted", &inverted); 518 if (inverted) { 519 DPRINTF(("nope, it's inverted\n")); 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 } 522 } else 523 sc->sc_flags |= RFB_INV_BLIGHT; 524 525 /* 526 * XXX: to support true multihead, this must change. 527 */ 528 sc->sc_ndisplays = 1; 529 530 /* XXX: */ 531 if (!HAS_CRTC2(sc)) { 532 sc->sc_ndisplays = 1; 533 } 534 535 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 536 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 537 &sc->sc_regsz) != 0) { 538 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 539 goto error; 540 } 541 542 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 543 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 544 { 545 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 546 goto error; 547 } 548 sc->sc_romt = sc->sc_memt; 549 550 /* scratch register test... */ 551 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 552 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 553 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 554 goto error; 555 } 556 557 PRINTREG(RADEON_BIOS_4_SCRATCH); 558 PRINTREG(RADEON_FP_GEN_CNTL); 559 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 560 PRINTREG(RADEON_FP2_GEN_CNTL); 561 PRINTREG(RADEON_TMDS_CNTL); 562 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 563 PRINTREG(RADEON_TMDS_PLL_CNTL); 564 PRINTREG(RADEON_LVDS_GEN_CNTL); 565 PRINTREG(RADEON_FP_HORZ_STRETCH); 566 PRINTREG(RADEON_FP_VERT_STRETCH); 567 568 /* XXX: RV100 specific */ 569 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 570 571 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 572 RADEON_TMDS_TRANSMITTER_PLLEN, 573 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 574 575 radeonfb_i2c_init(sc); 576 577 radeonfb_loadbios(sc, pa); 578 579 #ifdef RADEONFB_BIOS_INIT 580 if (radeonfb_bios_init(sc)) { 581 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 582 } 583 #endif 584 585 if (radeonfb_getclocks(sc)) { 586 aprint_error("%s: Unable to get reference clocks from BIOS\n", 587 XNAME(sc)); 588 goto error; 589 } 590 591 if (radeonfb_gettmds(sc)) { 592 aprint_error("%s: Unable to identify TMDS PLL settings\n", 593 XNAME(sc)); 594 goto error; 595 } 596 597 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 598 "minpll = %d, maxpll = %d\n", XNAME(sc), 599 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 600 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 601 602 radeonfb_getconnectors(sc); 603 604 radeonfb_set_fbloc(sc); 605 606 for (i = 0; radeonfb_limits[i].size; i++) { 607 if (sc->sc_memsz >= radeonfb_limits[i].size) { 608 sc->sc_maxx = radeonfb_limits[i].maxx; 609 sc->sc_maxy = radeonfb_limits[i].maxy; 610 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 611 /* framebuffer offset, start at a 4K page */ 612 sc->sc_fboffset = sc->sc_memsz / 613 radeonfb_limits[i].maxdisp; 614 /* 615 * we use the fbsize to figure out where we can store 616 * things like cursor data. 617 */ 618 sc->sc_fbsize = 619 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 620 RADEON_STRIDEALIGN) * sc->sc_maxy, 621 4096); 622 break; 623 } 624 } 625 626 627 radeonfb_init_misc(sc); 628 radeonfb_init_palette(sc, 0); 629 if (HAS_CRTC2(sc)) 630 radeonfb_init_palette(sc, 1); 631 632 /* program the DAC wirings */ 633 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 634 switch (sc->sc_ports[i].rp_dac_type) { 635 case RADEON_DAC_PRIMARY: 636 PATCH32(sc, RADEON_DAC_CNTL2, 637 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 638 ~RADEON_DAC2_DAC_CLK_SEL); 639 break; 640 case RADEON_DAC_TVDAC: 641 /* we always use the TVDAC to drive a secondary analog 642 * CRT for now. if we ever support TV-out this will 643 * have to change. 644 */ 645 SET32(sc, RADEON_DAC_CNTL2, 646 RADEON_DAC2_DAC2_CLK_SEL); 647 PATCH32(sc, RADEON_DISP_HW_DEBUG, 648 i ? 0 : RADEON_CRT2_DISP1_SEL, 649 ~RADEON_CRT2_DISP1_SEL); 650 break; 651 } 652 } 653 PRINTREG(RADEON_DAC_CNTL2); 654 PRINTREG(RADEON_DISP_HW_DEBUG); 655 656 /* other DAC programming */ 657 v = GET32(sc, RADEON_DAC_CNTL); 658 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 659 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 660 PUT32(sc, RADEON_DAC_CNTL, v); 661 PRINTREG(RADEON_DAC_CNTL); 662 663 /* XXX: this may need more investigation */ 664 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 665 PRINTREG(RADEON_TV_DAC_CNTL); 666 667 /* enable TMDS */ 668 SET32(sc, RADEON_FP_GEN_CNTL, 669 RADEON_FP_TMDS_EN | 670 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 671 RADEON_FP_CRTC_DONT_SHADOW_HEND); 672 /* 673 * XXX 674 * no idea why this is necessary - if I do not clear this bit on my 675 * iBook G4 the screen remains black, even though it's already clear. 676 * It needs to be set on my Sun XVR-100 for the DVI port to work 677 */ 678 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 679 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 680 } else 681 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 682 683 if (HAS_CRTC2(sc)) 684 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 685 686 /* 687 * we use bus_space_map instead of pci_mapreg, because we don't 688 * need the full aperature space. no point in wasting virtual 689 * address space we don't intend to use, right? 690 */ 691 if ((sc->sc_memsz < (4096 * 1024)) || 692 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 693 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 694 (bsz < sc->sc_memsz)) { 695 sc->sc_memsz = 0; 696 aprint_error("%s: Bad frame buffer configuration\n", 697 XNAME(sc)); 698 goto error; 699 } 700 701 /* 64 MB should be enough -- more just wastes map entries */ 702 if (sc->sc_memsz > (64 << 20)) 703 sc->sc_memsz = (64 << 20); 704 705 sc->sc_memt = pa->pa_memt; 706 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 707 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 708 sc->sc_memsz = 0; 709 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 710 goto error; 711 } 712 713 aprint_normal("%s: %d MB aperture at 0x%08x, " 714 "%d KB registers at 0x%08x\n", XNAME(sc), 715 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 716 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 717 718 /* setup default video mode from devprop (allows PROM override) */ 719 sc->sc_defaultmode = radeonfb_default_mode; 720 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 721 "videomode", &mptr)) { 722 723 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 724 sc->sc_defaultmode = sc->sc_modebuf; 725 } 726 727 /* initialize some basic display parameters */ 728 for (i = 0; i < sc->sc_ndisplays; i++) { 729 struct radeonfb_display *dp = &sc->sc_displays[i]; 730 struct rasops_info *ri; 731 long defattr; 732 struct wsemuldisplaydev_attach_args aa; 733 734 /* 735 * Figure out how many "displays" (desktops) we are going to 736 * support. If more than one, then each CRTC gets its own 737 * programming. 738 * 739 * XXX: this code needs to change to support mergedfb. 740 * XXX: would be nice to allow this to be overridden 741 */ 742 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 743 DPRINTF(("dual crtcs!\n")); 744 dp->rd_ncrtcs = 2; 745 dp->rd_crtcs[0].rc_number = 0; 746 dp->rd_crtcs[1].rc_number = 1; 747 } else { 748 dp->rd_ncrtcs = 1; 749 dp->rd_crtcs[0].rc_number = i; 750 } 751 752 /* set up port pointer */ 753 for (j = 0; j < dp->rd_ncrtcs; j++) { 754 dp->rd_crtcs[j].rc_port = 755 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 756 } 757 758 dp->rd_softc = sc; 759 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 760 dp->rd_bg = WS_DEFAULT_BG; 761 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 762 763 /* for text mode, we pick a resolution that won't 764 * require panning */ 765 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 766 767 aprint_normal("%s: display %d: " 768 "initial virtual resolution %dx%d at %d bpp\n", 769 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 770 771 /* now select the *video mode* that we will use */ 772 for (j = 0; j < dp->rd_ncrtcs; j++) { 773 const struct videomode *vmp; 774 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 775 dp->rd_virtx, dp->rd_virty); 776 777 /* 778 * virtual resolution should be at least as high as 779 * physical 780 */ 781 if (dp->rd_virtx < vmp->hdisplay || 782 dp->rd_virty < vmp->vdisplay) { 783 dp->rd_virtx = vmp->hdisplay; 784 dp->rd_virty = vmp->vdisplay; 785 } 786 787 dp->rd_crtcs[j].rc_videomode = *vmp; 788 printf("%s: port %d: physical %dx%d %dHz\n", 789 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 790 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 791 vmp->htotal), vmp->vtotal)); 792 } 793 794 /* N.B.: radeon wants 64-byte aligned stride */ 795 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 796 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 797 798 dp->rd_offset = sc->sc_fboffset * i; 799 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 800 sc->sc_memh) + dp->rd_offset; 801 dp->rd_curoff = sc->sc_fbsize; 802 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 803 804 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 805 806 switch (dp->rd_bpp) { 807 case 8: 808 dp->rd_format = 2; 809 break; 810 case 32: 811 dp->rd_format = 6; 812 break; 813 default: 814 aprint_error("%s: bad depth %d\n", XNAME(sc), 815 dp->rd_bpp); 816 goto error; 817 } 818 819 DPRINTF(("init engine\n")); 820 /* XXX: this seems suspicious - per display engine 821 initialization? */ 822 radeonfb_engine_init(dp); 823 824 /* copy the template into place */ 825 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 826 dp->rd_wsscreens = dp->rd_wsscreens_storage; 827 828 /* and make up the list */ 829 dp->rd_wsscreenlist.nscreens = 1; 830 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 831 832 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 833 &radeonfb_accessops); 834 835 dp->rd_vd.init_screen = radeonfb_init_screen; 836 837 #ifdef RADEONFB_DEBUG 838 dp->rd_virty -= 200; 839 #endif 840 841 dp->rd_console = 0; 842 prop_dictionary_get_bool(device_properties(sc->sc_dev), 843 "is_console", &dp->rd_console); 844 845 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 846 847 848 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 849 dp->rd_console, &defattr); 850 851 ri = &dp->rd_vscreen.scr_ri; 852 853 /* clear the screen */ 854 rasops_unpack_attr(defattr, &fg, &bg, &ul); 855 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 856 ri->ri_devcmap[bg & 0xf]); 857 858 dp->rd_wsscreens->textops = &ri->ri_ops; 859 dp->rd_wsscreens->capabilities = ri->ri_caps; 860 dp->rd_wsscreens->nrows = ri->ri_rows; 861 dp->rd_wsscreens->ncols = ri->ri_cols; 862 863 #ifdef SPLASHSCREEN 864 dp->rd_splash.si_depth = ri->ri_depth; 865 dp->rd_splash.si_bits = ri->ri_bits; 866 dp->rd_splash.si_hwbits = ri->ri_hwbits; 867 dp->rd_splash.si_width = ri->ri_width; 868 dp->rd_splash.si_height = ri->ri_height; 869 dp->rd_splash.si_stride = ri->ri_stride; 870 dp->rd_splash.si_fillrect = NULL; 871 #endif 872 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 873 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 874 dp->rd_gc.gc_rop = RADEON_ROP3_S; 875 dp->rd_gc.gc_blitcookie = dp; 876 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 877 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 878 dp->rd_virtx, 879 ri->ri_font->fontwidth, 880 ri->ri_font->fontheight, 881 defattr); 882 if (dp->rd_console) { 883 884 radeonfb_modeswitch(dp); 885 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 886 defattr); 887 #ifdef SPLASHSCREEN 888 if (splash_render(&dp->rd_splash, 889 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 890 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 891 else 892 #endif 893 vcons_replay_msgbuf(&dp->rd_vscreen); 894 } else { 895 896 /* 897 * since we're not the console we can postpone 898 * the rest until someone actually allocates a 899 * screen for us. but we do clear the screen 900 * at least. 901 */ 902 memset(ri->ri_bits, 0, 1024); 903 904 radeonfb_modeswitch(dp); 905 #ifdef SPLASHSCREEN 906 if (splash_render(&dp->rd_splash, 907 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 908 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 909 #endif 910 } 911 912 aa.console = dp->rd_console; 913 aa.scrdata = &dp->rd_wsscreenlist; 914 aa.accessops = &radeonfb_accessops; 915 aa.accesscookie = &dp->rd_vd; 916 917 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 918 919 radeonfb_blank(dp, 0); 920 921 /* Initialise delayed lvds operations for backlight. */ 922 callout_init(&dp->rd_bl_lvds_co, 0); 923 callout_setfunc(&dp->rd_bl_lvds_co, 924 radeonfb_lvds_callout, dp); 925 dp->rd_bl_on = 1; 926 dp->rd_bl_level = radeonfb_get_backlight(dp); 927 radeonfb_set_backlight(dp, dp->rd_bl_level); 928 } 929 930 /* 931 * if we have console output via firmware like on sparc64 it may 932 * interfere with DAC programming so program the palette again 933 * here after we took over 934 */ 935 radeonfb_init_palette(sc, 0); 936 if (HAS_CRTC2(sc)) 937 radeonfb_init_palette(sc, 1); 938 939 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 940 radeonfb_brightness_up, TRUE); 941 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 942 radeonfb_brightness_down, TRUE); 943 944 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 945 946 return; 947 948 error: 949 if (sc->sc_biossz) 950 free(sc->sc_bios, M_DEVBUF); 951 952 if (sc->sc_regsz) 953 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 954 955 if (sc->sc_memsz) 956 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 957 } 958 959 static void 960 radeonfb_map(struct radeonfb_softc *sc) 961 { 962 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 963 &sc->sc_regh) != 0) { 964 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 965 return; 966 } 967 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 968 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 969 sc->sc_memsz = 0; 970 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 971 return; 972 } 973 } 974 975 static void 976 radeonfb_unmap(struct radeonfb_softc *sc) 977 { 978 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 979 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 980 } 981 982 static int 983 radeonfb_drm_print(void *aux, const char *pnp) 984 { 985 if (pnp) 986 aprint_normal("drm at %s", pnp); 987 return (UNCONF); 988 } 989 990 int 991 radeonfb_ioctl(void *v, void *vs, 992 unsigned long cmd, void *d, int flag, struct lwp *l) 993 { 994 struct vcons_data *vd; 995 struct radeonfb_display *dp; 996 struct radeonfb_softc *sc; 997 struct wsdisplay_param *param; 998 999 vd = (struct vcons_data *)v; 1000 dp = (struct radeonfb_display *)vd->cookie; 1001 sc = dp->rd_softc; 1002 1003 switch (cmd) { 1004 case WSDISPLAYIO_GTYPE: 1005 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1006 return 0; 1007 1008 case WSDISPLAYIO_GINFO: 1009 if (vd->active != NULL) { 1010 struct wsdisplay_fbinfo *fb; 1011 fb = (struct wsdisplay_fbinfo *)d; 1012 fb->width = dp->rd_virtx; 1013 fb->height = dp->rd_virty; 1014 fb->depth = dp->rd_bpp; 1015 fb->cmsize = 256; 1016 return 0; 1017 } else 1018 return ENODEV; 1019 case WSDISPLAYIO_GVIDEO: 1020 if (radeonfb_isblank(dp)) 1021 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1022 else 1023 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1024 return 0; 1025 1026 case WSDISPLAYIO_SVIDEO: 1027 radeonfb_blank(dp, 1028 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1029 return 0; 1030 1031 case WSDISPLAYIO_GETCMAP: 1032 #if 0 1033 if (dp->rd_bpp == 8) 1034 return radeonfb_getcmap(sc, 1035 (struct wsdisplay_cmap *)d); 1036 #endif 1037 return EINVAL; 1038 1039 case WSDISPLAYIO_PUTCMAP: 1040 #if 0 1041 if (dp->rd_bpp == 8) 1042 return radeonfb_putcmap(sc, 1043 (struct wsdisplay_cmap *)d); 1044 #endif 1045 return EINVAL; 1046 1047 case WSDISPLAYIO_LINEBYTES: 1048 *(unsigned *)d = dp->rd_stride; 1049 return 0; 1050 1051 case WSDISPLAYIO_SMODE: 1052 if (*(int *)d != dp->rd_wsmode) { 1053 dp->rd_wsmode = *(int *)d; 1054 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1055 (dp->rd_vd.active)) { 1056 radeonfb_map(sc); 1057 radeonfb_engine_init(dp); 1058 glyphcache_wipe(&dp->rd_gc); 1059 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1060 radeonfb_modeswitch(dp); 1061 vcons_redraw_screen(dp->rd_vd.active); 1062 } else { 1063 radeonfb_unmap(sc); 1064 } 1065 } 1066 return 0; 1067 1068 case WSDISPLAYIO_GCURMAX: 1069 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1070 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1071 return 0; 1072 1073 case WSDISPLAYIO_SCURSOR: 1074 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1075 1076 case WSDISPLAYIO_GCURSOR: 1077 return EPASSTHROUGH; 1078 1079 case WSDISPLAYIO_GCURPOS: 1080 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1081 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1082 return 0; 1083 1084 case WSDISPLAYIO_SCURPOS: 1085 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1086 1087 case WSDISPLAYIO_SSPLASH: 1088 #if defined(SPLASHSCREEN) 1089 if (*(int *)d == 1) { 1090 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1091 splash_render(&dp->rd_splash, 1092 SPLASH_F_CENTER|SPLASH_F_FILL); 1093 } else 1094 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1095 return 0; 1096 #else 1097 return ENODEV; 1098 #endif 1099 case WSDISPLAYIO_GETPARAM: 1100 param = (struct wsdisplay_param *)d; 1101 switch (param->param) { 1102 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1103 param->min = 0; 1104 param->max = 255; 1105 param->curval = dp->rd_bl_level; 1106 return 0; 1107 case WSDISPLAYIO_PARAM_BACKLIGHT: 1108 param->min = 0; 1109 param->max = RADEONFB_BACKLIGHT_MAX; 1110 param->curval = dp->rd_bl_on; 1111 return 0; 1112 } 1113 return EPASSTHROUGH; 1114 1115 case WSDISPLAYIO_SETPARAM: 1116 param = (struct wsdisplay_param *)d; 1117 switch (param->param) { 1118 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1119 radeonfb_set_backlight(dp, param->curval); 1120 return 0; 1121 case WSDISPLAYIO_PARAM_BACKLIGHT: 1122 radeonfb_switch_backlight(dp, param->curval); 1123 return 0; 1124 } 1125 return EPASSTHROUGH; 1126 1127 /* PCI config read/write passthrough. */ 1128 case PCI_IOC_CFGREAD: 1129 case PCI_IOC_CFGWRITE: 1130 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1131 1132 case WSDISPLAYIO_GET_BUSID: 1133 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1134 sc->sc_pt, d); 1135 1136 case WSDISPLAYIO_GET_EDID: { 1137 struct wsdisplayio_edid_info *ei = d; 1138 return wsdisplayio_get_edid(sc->sc_dev, ei); 1139 } 1140 1141 default: 1142 return EPASSTHROUGH; 1143 } 1144 } 1145 1146 paddr_t 1147 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1148 { 1149 struct vcons_data *vd; 1150 struct radeonfb_display *dp; 1151 struct radeonfb_softc *sc; 1152 paddr_t pa; 1153 1154 vd = (struct vcons_data *)v; 1155 dp = (struct radeonfb_display *)vd->cookie; 1156 sc = dp->rd_softc; 1157 1158 /* XXX: note that we don't allow mapping of registers right now */ 1159 /* XXX: this means that the XFree86 radeon driver won't work */ 1160 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1161 pa = bus_space_mmap(sc->sc_memt, 1162 sc->sc_memaddr + dp->rd_offset + offset, 0, 1163 prot, BUS_SPACE_MAP_LINEAR); 1164 return pa; 1165 } 1166 1167 #ifdef RADEONFB_MMAP_BARS 1168 /* 1169 * restrict all other mappings to processes with superuser privileges 1170 * or the kernel itself 1171 */ 1172 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1173 NULL, NULL, NULL, NULL) != 0) { 1174 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1175 return -1; 1176 } 1177 1178 if ((offset >= sc->sc_regaddr) && 1179 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1180 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1181 BUS_SPACE_MAP_LINEAR); 1182 } 1183 1184 if ((offset >= sc->sc_memaddr) && 1185 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1186 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1187 BUS_SPACE_MAP_LINEAR); 1188 } 1189 1190 if ((offset >= sc->sc_romaddr) && 1191 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1192 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1193 BUS_SPACE_MAP_LINEAR); 1194 } 1195 1196 #ifdef PCI_MAGIC_IO_RANGE 1197 /* allow mapping of IO space */ 1198 if ((offset >= PCI_MAGIC_IO_RANGE) && 1199 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1200 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1201 0, prot, 0); 1202 return pa; 1203 } 1204 #endif /* PCI_MAGIC_IO_RANGE */ 1205 1206 #endif /* RADEONFB_MMAP_BARS */ 1207 1208 return -1; 1209 } 1210 1211 static void 1212 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1213 { 1214 bus_space_tag_t romt; 1215 bus_space_handle_t romh, biosh; 1216 bus_size_t romsz; 1217 bus_addr_t ptr; 1218 1219 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1220 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1221 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1222 return; 1223 } 1224 1225 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1226 &sc->sc_biossz); 1227 if (sc->sc_biossz == 0) { 1228 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1229 return; 1230 } 1231 1232 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1233 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1234 1235 /* unmap the PCI expansion rom */ 1236 bus_space_unmap(romt, romh, romsz); 1237 1238 /* turn off rom decoder now */ 1239 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1240 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1241 ~PCI_MAPREG_ROM_ENABLE); 1242 1243 ptr = GETBIOS16(sc, 0x48); 1244 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1245 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1246 sc->sc_flags |= RFB_ATOM; 1247 } 1248 1249 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1250 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1251 } 1252 1253 1254 uint32_t 1255 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1256 { 1257 1258 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1259 } 1260 1261 void 1262 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1263 { 1264 1265 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1266 } 1267 1268 void 1269 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1270 { 1271 1272 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1273 } 1274 1275 void 1276 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1277 uint32_t andmask, uint32_t ormask) 1278 { 1279 int s; 1280 uint32_t val; 1281 1282 s = splhigh(); 1283 val = radeonfb_get32(sc, reg); 1284 val = (val & andmask) | ormask; 1285 radeonfb_put32(sc, reg, val); 1286 splx(s); 1287 } 1288 1289 uint32_t 1290 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1291 { 1292 int s; 1293 uint32_t val; 1294 1295 s = splhigh(); 1296 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1297 val = radeonfb_get32(sc, RADEON_MM_DATA); 1298 splx(s); 1299 1300 return (val); 1301 } 1302 1303 void 1304 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1305 { 1306 int s; 1307 1308 s = splhigh(); 1309 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1310 radeonfb_put32(sc, RADEON_MM_DATA, val); 1311 splx(s); 1312 } 1313 1314 void 1315 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1316 uint32_t andmask, uint32_t ormask) 1317 { 1318 int s; 1319 uint32_t val; 1320 1321 s = splhigh(); 1322 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1323 val = radeonfb_get32(sc, RADEON_MM_DATA); 1324 val = (val & andmask) | ormask; 1325 radeonfb_put32(sc, RADEON_MM_DATA, val); 1326 splx(s); 1327 } 1328 1329 uint32_t 1330 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1331 { 1332 int s; 1333 uint32_t val; 1334 1335 s = splhigh(); 1336 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1337 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1338 if (HAS_R300CG(sc)) 1339 radeonfb_r300cg_workaround(sc); 1340 splx(s); 1341 1342 return (val); 1343 } 1344 1345 void 1346 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1347 { 1348 int s; 1349 1350 s = splhigh(); 1351 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1352 RADEON_PLL_WR_EN); 1353 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1354 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1355 splx(s); 1356 } 1357 1358 void 1359 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1360 uint32_t andmask, uint32_t ormask) 1361 { 1362 int s; 1363 uint32_t val; 1364 1365 s = splhigh(); 1366 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1367 RADEON_PLL_WR_EN); 1368 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1369 val = (val & andmask) | ormask; 1370 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1371 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1372 splx(s); 1373 } 1374 1375 int 1376 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1377 { 1378 uint32_t saved; 1379 1380 saved = GET32(sc, reg); 1381 PUT32(sc, reg, v); 1382 if (GET32(sc, reg) != v) { 1383 return -1; 1384 } 1385 PUT32(sc, reg, saved); 1386 return 0; 1387 } 1388 1389 uintmax_t 1390 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1391 uintmax_t defval) 1392 { 1393 prop_number_t pn; 1394 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1395 if (pn == NULL) { 1396 return defval; 1397 } 1398 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1399 return (prop_number_integer_value(pn)); 1400 } 1401 1402 int 1403 radeonfb_getclocks(struct radeonfb_softc *sc) 1404 { 1405 bus_addr_t ptr; 1406 int refclk = 0; 1407 int refdiv = 0; 1408 int minpll = 0; 1409 int maxpll = 0; 1410 1411 /* load initial property values if port/board provides them */ 1412 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1413 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1414 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1415 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1416 1417 if (refclk && refdiv && minpll && maxpll) 1418 goto dontprobe; 1419 1420 if (!sc->sc_biossz) { 1421 /* no BIOS */ 1422 aprint_verbose("%s: No video BIOS, using default clocks\n", 1423 XNAME(sc)); 1424 if (IS_IGP(sc)) 1425 refclk = refclk ? refclk : 1432; 1426 else 1427 refclk = refclk ? refclk : 2700; 1428 refdiv = refdiv ? refdiv : 12; 1429 minpll = minpll ? minpll : 12500; 1430 maxpll = maxpll ? maxpll : 35000; 1431 } else if (IS_ATOM(sc)) { 1432 /* ATOM BIOS */ 1433 ptr = GETBIOS16(sc, 0x48); 1434 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1435 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1436 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1437 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1438 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1439 /* 1440 * ATOM BIOS doesn't supply a reference divider, so we 1441 * have to probe for it. 1442 */ 1443 if (refdiv < 2) 1444 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1445 RADEON_PPLL_REF_DIV_MASK; 1446 /* 1447 * if probe is zero, just assume one that should work 1448 * for most parts 1449 */ 1450 if (refdiv < 2) 1451 refdiv = 12; 1452 1453 } else { 1454 /* Legacy BIOS */ 1455 ptr = GETBIOS16(sc, 0x48); 1456 ptr = GETBIOS16(sc, ptr + 0x30); 1457 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1458 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1459 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1460 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1461 } 1462 1463 1464 dontprobe: 1465 sc->sc_refclk = refclk * 10; 1466 sc->sc_refdiv = refdiv; 1467 sc->sc_minpll = minpll * 10; 1468 sc->sc_maxpll = maxpll * 10; 1469 return 0; 1470 } 1471 1472 int 1473 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1474 uint32_t *postdivbit, uint32_t *feedbackdiv) 1475 { 1476 int i; 1477 uint32_t outfreq; 1478 int div; 1479 1480 DPRINTF(("dot clock: %u\n", dotclock)); 1481 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1482 outfreq = div * dotclock; 1483 if ((outfreq >= sc->sc_minpll) && 1484 (outfreq <= sc->sc_maxpll)) { 1485 DPRINTF(("outfreq: %u\n", outfreq)); 1486 *postdivbit = 1487 ((uint32_t)radeonfb_dividers[i].mask << 16); 1488 DPRINTF(("post divider: %d (mask %x)\n", div, 1489 *postdivbit)); 1490 break; 1491 } 1492 } 1493 1494 if (div == 0) 1495 return 1; 1496 1497 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1498 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1499 return 0; 1500 } 1501 1502 #if 0 1503 #ifdef RADEONFB_DEBUG 1504 static void 1505 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1506 { 1507 char asc[17]; 1508 unsigned ptr = (unsigned)buffer; 1509 char *start = (char *)(ptr & ~0xf); 1510 char *end = (char *)(ptr + size); 1511 1512 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1513 1514 if (pfx == NULL) { 1515 pfx = ""; 1516 } 1517 1518 while (start < end) { 1519 unsigned offset = (unsigned)start & 0xf; 1520 if (offset == 0) { 1521 printf("%s%x: ", pfx, (unsigned)start); 1522 } 1523 if (((unsigned)start < ptr) || 1524 ((unsigned)start >= (ptr + size))) { 1525 printf(" "); 1526 asc[offset] = ' '; 1527 } else { 1528 printf("%02x", *(unsigned char *)start); 1529 if ((*start >= ' ') && (*start <= '~')) { 1530 asc[offset] = *start; 1531 } else { 1532 asc[offset] = '.'; 1533 } 1534 } 1535 asc[offset + 1] = 0; 1536 if (offset % 2) { 1537 printf(" "); 1538 } 1539 if (offset == 15) { 1540 printf(" %s\n", asc); 1541 } 1542 start++; 1543 } 1544 } 1545 #endif 1546 #endif 1547 1548 int 1549 radeonfb_getconnectors(struct radeonfb_softc *sc) 1550 { 1551 int i; 1552 int found = 0; 1553 1554 for (i = 0; i < 2; i++) { 1555 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1556 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1557 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1558 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1559 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1560 } 1561 1562 /* 1563 * This logic is borrowed from Xorg's radeon driver. 1564 */ 1565 if (!sc->sc_biossz) 1566 goto nobios; 1567 1568 if (IS_ATOM(sc)) { 1569 /* not done yet */ 1570 } else { 1571 uint16_t ptr; 1572 int port = 0; 1573 1574 ptr = GETBIOS16(sc, 0x48); 1575 ptr = GETBIOS16(sc, ptr + 0x50); 1576 for (i = 1; i < 4; i++) { 1577 uint16_t entry; 1578 uint8_t conn, ddc, dac, tmds; 1579 1580 /* 1581 * Parse the connector table. From reading the code, 1582 * it appears to made up of 16-bit entries for each 1583 * connector. The 16-bits are defined as: 1584 * 1585 * bits 12-15 - connector type (0 == end of table) 1586 * bits 8-11 - DDC type 1587 * bits 5-7 - ??? 1588 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1589 * bits 1-3 - ??? 1590 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1591 */ 1592 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1593 break; 1594 entry = GETBIOS16(sc, ptr + i * 2); 1595 1596 conn = (entry >> 12) & 0xf; 1597 ddc = (entry >> 8) & 0xf; 1598 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1599 RADEON_DAC_PRIMARY; 1600 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1601 RADEON_TMDS_INT; 1602 1603 if (conn == RADEON_CONN_NONE) 1604 continue; /* no connector */ 1605 1606 if ((found > 0) && 1607 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1608 /* duplicate entry for same connector */ 1609 continue; 1610 } 1611 1612 /* internal DDC_DVI port gets priority */ 1613 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1614 port = 0; 1615 else 1616 port = 1; 1617 1618 sc->sc_ports[port].rp_ddc_type = 1619 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1620 sc->sc_ports[port].rp_dac_type = dac; 1621 sc->sc_ports[port].rp_conn_type = 1622 min(conn, RADEON_CONN_UNSUPPORTED) ; 1623 1624 sc->sc_ports[port].rp_tmds_type = tmds; 1625 1626 if ((conn != RADEON_CONN_DVI_I) && 1627 (conn != RADEON_CONN_DVI_D) && 1628 (tmds == RADEON_TMDS_INT)) 1629 sc->sc_ports[port].rp_tmds_type = 1630 RADEON_TMDS_UNKNOWN; 1631 1632 found += (port + 1); 1633 } 1634 } 1635 1636 nobios: 1637 if (!found) { 1638 DPRINTF(("No connector info in BIOS!\n")); 1639 /* default, port 0 = internal TMDS, port 1 = CRT */ 1640 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1641 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1642 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1643 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1644 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1645 1646 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1647 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1648 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1649 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1650 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1651 } 1652 1653 /* 1654 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1655 * these chips should use TVDAC for the VGA port. 1656 */ 1657 if (HAS_SDAC(sc)) { 1658 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1659 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1660 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1661 } else { 1662 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1663 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1664 } 1665 } else if (!HAS_CRTC2(sc)) { 1666 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1667 } 1668 1669 for (i = 0; i < 2; i++) { 1670 char edid[128]; 1671 uint8_t ddc; 1672 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1673 prop_data_t edid_data; 1674 1675 DPRINTF(("Port #%d:\n", i)); 1676 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1677 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1678 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1679 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1680 1681 sc->sc_ports[i].rp_edid_valid = 0; 1682 /* first look for static EDID data */ 1683 if ((edid_data = prop_dictionary_get(device_properties( 1684 sc->sc_dev), "EDID")) != NULL) { 1685 1686 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1687 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1688 if (edid_parse(edid, eip) == 0) { 1689 1690 sc->sc_ports[i].rp_edid_valid = 1; 1691 } 1692 } 1693 /* if we didn't find any we'll try to talk to the monitor */ 1694 if (sc->sc_ports[i].rp_edid_valid != 1) { 1695 1696 ddc = sc->sc_ports[i].rp_ddc_type; 1697 if (ddc != RADEON_DDC_NONE) { 1698 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1699 == 0) && (edid_parse(edid, eip) == 0)) { 1700 1701 sc->sc_ports[i].rp_edid_valid = 1; 1702 #ifdef RADEONFB_DEBUG 1703 edid_print(eip); 1704 #endif 1705 } 1706 } 1707 } 1708 } 1709 1710 return found; 1711 } 1712 1713 int 1714 radeonfb_gettmds(struct radeonfb_softc *sc) 1715 { 1716 int i; 1717 1718 if (!sc->sc_biossz) { 1719 goto nobios; 1720 } 1721 1722 if (IS_ATOM(sc)) { 1723 /* XXX: not done yet */ 1724 } else { 1725 uint16_t ptr; 1726 int n; 1727 1728 ptr = GETBIOS16(sc, 0x48); 1729 ptr = GETBIOS16(sc, ptr + 0x34); 1730 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1731 if (GETBIOS8(sc, ptr) == 3) { 1732 /* revision three table */ 1733 n = GETBIOS8(sc, ptr + 5) + 1; 1734 n = min(n, 4); 1735 1736 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1737 for (i = 0; i < n; i++) { 1738 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1739 ptr + i * 10 + 8); 1740 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1741 ptr + i * 10 + 0x10); 1742 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1743 sc->sc_tmds_pll[i].rtp_freq, 1744 sc->sc_tmds_pll[i].rtp_pll)); 1745 } 1746 return 0; 1747 } 1748 } 1749 1750 nobios: 1751 DPRINTF(("no suitable DFP table present\n")); 1752 for (i = 0; 1753 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1754 i++) { 1755 int j; 1756 1757 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1758 continue; 1759 1760 for (j = 0; j < 4; j++) { 1761 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1762 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1763 sc->sc_tmds_pll[j].rtp_freq, 1764 sc->sc_tmds_pll[j].rtp_pll)); 1765 } 1766 return 0; 1767 } 1768 1769 return -1; 1770 } 1771 1772 const struct videomode * 1773 radeonfb_modelookup(const char *name) 1774 { 1775 int i; 1776 1777 for (i = 0; i < videomode_count; i++) 1778 if (!strcmp(name, videomode_list[i].name)) 1779 return &videomode_list[i]; 1780 1781 return NULL; 1782 } 1783 1784 void 1785 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1786 { 1787 if (crtc) { 1788 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1789 RADEON_P2PLL_ATOMIC_UPDATE_R); 1790 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1791 } else { 1792 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1793 RADEON_PPLL_ATOMIC_UPDATE_R); 1794 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1795 } 1796 } 1797 1798 void 1799 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1800 { 1801 int i; 1802 1803 for (i = 10000; i; i--) { 1804 if (crtc) { 1805 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1806 RADEON_P2PLL_ATOMIC_UPDATE_R) 1807 break; 1808 } else { 1809 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1810 RADEON_PPLL_ATOMIC_UPDATE_R) 1811 break; 1812 } 1813 } 1814 } 1815 1816 void 1817 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1818 { 1819 uint32_t pbit = 0; 1820 uint32_t feed = 0; 1821 uint32_t data; 1822 #if 1 1823 int i; 1824 #endif 1825 1826 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1827 1828 if (crtc == 0) { 1829 1830 /* XXXX: mobility workaround missing */ 1831 /* XXXX: R300 stuff missing */ 1832 1833 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1834 RADEON_VCLK_SRC_SEL_CPUCLK, 1835 ~RADEON_VCLK_SRC_SEL_MASK); 1836 1837 /* put vclk into reset, use atomic updates */ 1838 SETPLL(sc, RADEON_PPLL_CNTL, 1839 RADEON_PPLL_REFCLK_SEL | 1840 RADEON_PPLL_FBCLK_SEL | 1841 RADEON_PPLL_RESET | 1842 RADEON_PPLL_ATOMIC_UPDATE_EN | 1843 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1844 1845 /* select clock 3 */ 1846 #if 0 1847 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1848 ~RADEON_PLL_DIV_SEL); 1849 #else 1850 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1851 ~RADEON_PLL_DIV_SEL); 1852 #endif 1853 1854 /* XXX: R300 family -- program divider differently? */ 1855 1856 /* program reference divider */ 1857 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1858 ~RADEON_PPLL_REF_DIV_MASK); 1859 PRINTPLL(RADEON_PPLL_REF_DIV); 1860 1861 #if 0 1862 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1863 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1864 RADEON_PPLL_POST3_DIV_MASK); 1865 data |= pbit; 1866 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1867 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1868 #else 1869 for (i = 0; i < 4; i++) { 1870 } 1871 #endif 1872 1873 /* use the atomic update */ 1874 radeonfb_pllwriteupdate(sc, crtc); 1875 1876 /* and wait for it to complete */ 1877 radeonfb_pllwaitatomicread(sc, crtc); 1878 1879 /* program HTOTAL (why?) */ 1880 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1881 1882 /* drop reset */ 1883 CLRPLL(sc, RADEON_PPLL_CNTL, 1884 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1885 RADEON_PPLL_ATOMIC_UPDATE_EN | 1886 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1887 1888 PRINTPLL(RADEON_PPLL_CNTL); 1889 1890 /* give clock time to lock */ 1891 delay(50000); 1892 1893 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1894 RADEON_VCLK_SRC_SEL_PPLLCLK, 1895 ~RADEON_VCLK_SRC_SEL_MASK); 1896 1897 } else { 1898 1899 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1900 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1901 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1902 1903 /* put vclk into reset, use atomic updates */ 1904 SETPLL(sc, RADEON_P2PLL_CNTL, 1905 RADEON_P2PLL_RESET | 1906 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1907 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1908 1909 /* XXX: R300 family -- program divider differently? */ 1910 1911 /* program reference divider */ 1912 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1913 ~RADEON_P2PLL_REF_DIV_MASK); 1914 1915 /* program feedback and post dividers */ 1916 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1917 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1918 RADEON_P2PLL_POST0_DIV_MASK); 1919 data |= pbit; 1920 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1921 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1922 1923 /* use the atomic update */ 1924 radeonfb_pllwriteupdate(sc, crtc); 1925 1926 /* and wait for it to complete */ 1927 radeonfb_pllwaitatomicread(sc, crtc); 1928 1929 /* program HTOTAL (why?) */ 1930 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1931 1932 /* drop reset */ 1933 CLRPLL(sc, RADEON_P2PLL_CNTL, 1934 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1935 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1936 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1937 1938 /* allow time for clock to lock */ 1939 delay(50000); 1940 1941 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1942 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1943 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1944 } 1945 PRINTREG(RADEON_CRTC_MORE_CNTL); 1946 } 1947 1948 void 1949 radeonfb_modeswitch(struct radeonfb_display *dp) 1950 { 1951 struct radeonfb_softc *sc = dp->rd_softc; 1952 int i; 1953 1954 /* blank the display while we switch modes */ 1955 radeonfb_blank(dp, 1); 1956 1957 #if 0 1958 SET32(sc, RADEON_CRTC_EXT_CNTL, 1959 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1960 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1961 #endif 1962 1963 /* these registers might get in the way... */ 1964 PUT32(sc, RADEON_OVR_CLR, 0); 1965 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1966 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1967 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1968 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1969 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1970 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1971 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1972 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1973 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1974 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1975 1976 for (i = 0; i < dp->rd_ncrtcs; i++) 1977 radeonfb_setcrtc(dp, i); 1978 1979 /* activate the display */ 1980 radeonfb_blank(dp, 0); 1981 } 1982 1983 void 1984 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1985 { 1986 int crtc; 1987 struct videomode *mode; 1988 struct radeonfb_softc *sc; 1989 struct radeonfb_crtc *cp; 1990 uint32_t v; 1991 uint32_t gencntl; 1992 uint32_t htotaldisp; 1993 uint32_t hsyncstrt; 1994 uint32_t vtotaldisp; 1995 uint32_t vsyncstrt; 1996 uint32_t fphsyncstrt; 1997 uint32_t fpvsyncstrt; 1998 uint32_t fphtotaldisp; 1999 uint32_t fpvtotaldisp; 2000 uint32_t pitch; 2001 2002 sc = dp->rd_softc; 2003 cp = &dp->rd_crtcs[index]; 2004 crtc = cp->rc_number; 2005 mode = &cp->rc_videomode; 2006 2007 #if 1 2008 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 2009 (dp->rd_bpp * 8)); 2010 #else 2011 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2012 (sc->sc_maxbpp * 8)); 2013 #endif 2014 2015 switch (crtc) { 2016 case 0: 2017 gencntl = RADEON_CRTC_GEN_CNTL; 2018 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2019 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2020 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2021 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2022 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2023 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2024 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2025 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2026 break; 2027 case 1: 2028 gencntl = RADEON_CRTC2_GEN_CNTL; 2029 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2030 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2031 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2032 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2033 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2034 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2035 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2036 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2037 break; 2038 default: 2039 panic("Bad CRTC!"); 2040 break; 2041 } 2042 2043 /* 2044 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2045 */ 2046 /* only bother with 32bpp and 8bpp */ 2047 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2048 2049 if (crtc == 1) { 2050 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2051 } else { 2052 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2053 } 2054 2055 if (mode->flags & VID_DBLSCAN) 2056 v |= RADEON_CRTC2_DBL_SCAN_EN; 2057 2058 if (mode->flags & VID_INTERLACE) 2059 v |= RADEON_CRTC2_INTERLACE_EN; 2060 2061 if (mode->flags & VID_CSYNC) { 2062 v |= RADEON_CRTC2_CSYNC_EN; 2063 if (crtc == 1) 2064 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2065 } 2066 2067 PUT32(sc, gencntl, v); 2068 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2069 2070 /* 2071 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2072 */ 2073 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2074 if (crtc == 0) { 2075 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2076 RADEON_CRTC_DISPLAY_DIS); 2077 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2078 if (mode->flags & VID_CSYNC) 2079 v |= RADEON_CRTC_VSYNC_TRISTAT; 2080 } 2081 /* unconditional turn on CRT, in case first CRTC is DFP */ 2082 v |= RADEON_CRTC_CRT_ON; 2083 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2084 PRINTREG(RADEON_CRTC_EXT_CNTL); 2085 2086 /* 2087 * H_TOTAL_DISP 2088 */ 2089 v = ((mode->hdisplay / 8) - 1) << 16; 2090 v |= (mode->htotal / 8) - 1; 2091 PUT32(sc, htotaldisp, v); 2092 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2093 PUT32(sc, fphtotaldisp, v); 2094 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2095 2096 /* 2097 * H_SYNC_STRT_WID 2098 */ 2099 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2100 v |= mode->hsync_start; 2101 if (mode->flags & VID_NHSYNC) 2102 v |= RADEON_CRTC_H_SYNC_POL; 2103 PUT32(sc, hsyncstrt, v); 2104 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2105 PUT32(sc, fphsyncstrt, v); 2106 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2107 2108 /* 2109 * V_TOTAL_DISP 2110 */ 2111 v = ((mode->vdisplay - 1) << 16); 2112 v |= (mode->vtotal - 1); 2113 PUT32(sc, vtotaldisp, v); 2114 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2115 PUT32(sc, fpvtotaldisp, v); 2116 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2117 2118 /* 2119 * V_SYNC_STRT_WID 2120 */ 2121 v = ((mode->vsync_end - mode->vsync_start) << 16); 2122 v |= (mode->vsync_start - 1); 2123 if (mode->flags & VID_NVSYNC) 2124 v |= RADEON_CRTC_V_SYNC_POL; 2125 PUT32(sc, vsyncstrt, v); 2126 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2127 PUT32(sc, fpvsyncstrt, v); 2128 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2129 2130 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2131 2132 switch (crtc) { 2133 case 0: 2134 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2135 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2136 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2137 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2138 2139 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2140 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2141 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2142 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2143 PRINTREG(RADEON_CRTC_EXT_CNTL); 2144 PRINTREG(RADEON_CRTC_GEN_CNTL); 2145 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2146 break; 2147 2148 case 1: 2149 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2150 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2151 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2152 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2153 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2154 RADEON_CRTC2_VSYNC_DIS | 2155 RADEON_CRTC2_HSYNC_DIS | 2156 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2157 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2158 break; 2159 } 2160 } 2161 2162 int 2163 radeonfb_isblank(struct radeonfb_display *dp) 2164 { 2165 uint32_t reg, mask; 2166 2167 if (dp->rd_crtcs[0].rc_number) { 2168 reg = RADEON_CRTC2_GEN_CNTL; 2169 mask = RADEON_CRTC2_DISP_DIS; 2170 } else { 2171 reg = RADEON_CRTC_EXT_CNTL; 2172 mask = RADEON_CRTC_DISPLAY_DIS; 2173 } 2174 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2175 } 2176 2177 void 2178 radeonfb_blank(struct radeonfb_display *dp, int blank) 2179 { 2180 struct radeonfb_softc *sc = dp->rd_softc; 2181 uint32_t reg, mask; 2182 uint32_t fpreg, fpval; 2183 int i; 2184 2185 for (i = 0; i < dp->rd_ncrtcs; i++) { 2186 2187 if (dp->rd_crtcs[i].rc_number) { 2188 reg = RADEON_CRTC2_GEN_CNTL; 2189 mask = RADEON_CRTC2_DISP_DIS; 2190 fpreg = RADEON_FP2_GEN_CNTL; 2191 fpval = RADEON_FP2_ON; 2192 } else { 2193 reg = RADEON_CRTC_EXT_CNTL; 2194 mask = RADEON_CRTC_DISPLAY_DIS; 2195 fpreg = RADEON_FP_GEN_CNTL; 2196 fpval = RADEON_FP_FPON; 2197 } 2198 2199 if (blank) { 2200 SET32(sc, reg, mask); 2201 CLR32(sc, fpreg, fpval); 2202 } else { 2203 CLR32(sc, reg, mask); 2204 SET32(sc, fpreg, fpval); 2205 } 2206 } 2207 PRINTREG(RADEON_FP_GEN_CNTL); 2208 PRINTREG(RADEON_FP2_GEN_CNTL); 2209 } 2210 2211 void 2212 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2213 long *defattr) 2214 { 2215 struct radeonfb_display *dp = cookie; 2216 struct rasops_info *ri = &scr->scr_ri; 2217 2218 /* initialize font subsystem */ 2219 wsfont_init(); 2220 2221 DPRINTF(("init screen called, existing %d\n", existing)); 2222 2223 ri->ri_depth = dp->rd_bpp; 2224 ri->ri_width = dp->rd_virtx; 2225 ri->ri_height = dp->rd_virty; 2226 ri->ri_stride = dp->rd_stride; 2227 ri->ri_flg = RI_CENTER; 2228 if (ri->ri_depth == 32) { 2229 ri->ri_flg |= RI_ENABLE_ALPHA; 2230 } 2231 switch (ri->ri_depth) { 2232 case 8: 2233 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2234 break; 2235 case 32: 2236 /* we run radeons in RGB even on SPARC hardware */ 2237 ri->ri_rnum = 8; 2238 ri->ri_gnum = 8; 2239 ri->ri_bnum = 8; 2240 ri->ri_rpos = 16; 2241 ri->ri_gpos = 8; 2242 ri->ri_bpos = 0; 2243 break; 2244 } 2245 2246 ri->ri_bits = (void *)dp->rd_fbptr; 2247 2248 #ifdef VCONS_DRAW_INTR 2249 scr->scr_flags |= VCONS_DONT_READ; 2250 #endif 2251 2252 if (existing) { 2253 ri->ri_flg |= RI_CLEAR; 2254 2255 /* start a modeswitch now */ 2256 radeonfb_modeswitch(dp); 2257 } 2258 2259 /* 2260 * XXX: font selection should be based on properties, with some 2261 * normal/reasonable default. 2262 */ 2263 2264 /* initialize and look for an initial font */ 2265 rasops_init(ri, 0, 0); 2266 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2267 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2268 2269 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2270 dp->rd_virtx / ri->ri_font->fontwidth); 2271 2272 /* enable acceleration */ 2273 dp->rd_putchar = ri->ri_ops.putchar; 2274 ri->ri_ops.copyrows = radeonfb_copyrows; 2275 ri->ri_ops.copycols = radeonfb_copycols; 2276 ri->ri_ops.eraserows = radeonfb_eraserows; 2277 ri->ri_ops.erasecols = radeonfb_erasecols; 2278 /* pick a putchar method based on font and Radeon model */ 2279 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2280 /* got a bitmap font */ 2281 if (IS_R300(dp->rd_softc)) { 2282 /* 2283 * radeonfb_putchar() doesn't work right on some R3xx 2284 * so we use software drawing here, the wrapper just 2285 * makes sure the engine is idle before scribbling 2286 * into vram 2287 */ 2288 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2289 } else { 2290 ri->ri_ops.putchar = radeonfb_putchar; 2291 } 2292 } else { 2293 /* got an alpha font */ 2294 switch(ri->ri_depth) { 2295 case 32: 2296 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2297 break; 2298 case 8: 2299 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2300 break; 2301 default: 2302 /* XXX this should never happen */ 2303 panic("%s: depth is not 8 or 32 but we got an" \ 2304 " alpha font?!", __func__); 2305 } 2306 } 2307 ri->ri_ops.cursor = radeonfb_cursor; 2308 } 2309 2310 void 2311 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2312 { 2313 uint32_t gen, ext, gen2 = 0; 2314 uint32_t agploc, aperbase, apersize, mcfbloc; 2315 2316 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2317 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2318 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2319 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2320 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2321 2322 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2323 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2324 #if 0 2325 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2326 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2327 #endif 2328 2329 if (HAS_CRTC2(sc)) { 2330 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2331 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2332 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2333 } 2334 2335 delay(100000); 2336 2337 mcfbloc = (aperbase >> 16) | 2338 ((aperbase + (apersize - 1)) & 0xffff0000); 2339 2340 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2341 sc->sc_memsz = apersize; 2342 2343 if (((agploc & 0xffff) << 16) != 2344 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2345 agploc = mcfbloc & 0xffff0000U; 2346 agploc |= ((agploc + 0x10000) >> 16); 2347 } 2348 2349 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2350 2351 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2352 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2353 2354 DPRINTF(("aperbase = %u\n", aperbase)); 2355 PRINTREG(RADEON_MC_FB_LOCATION); 2356 PRINTREG(RADEON_MC_AGP_LOCATION); 2357 2358 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2359 2360 if (HAS_CRTC2(sc)) 2361 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2362 2363 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2364 2365 #if 0 2366 /* XXX: what is this AGP garbage? :-) */ 2367 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2368 #endif 2369 2370 delay(100000); 2371 2372 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2373 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2374 2375 if (HAS_CRTC2(sc)) 2376 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2377 } 2378 2379 void 2380 radeonfb_init_misc(struct radeonfb_softc *sc) 2381 { 2382 PUT32(sc, RADEON_BUS_CNTL, 2383 RADEON_BUS_MASTER_DIS | 2384 RADEON_BUS_PREFETCH_MODE_ACT | 2385 RADEON_BUS_PCI_READ_RETRY_EN | 2386 RADEON_BUS_PCI_WRT_RETRY_EN | 2387 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2388 RADEON_BUS_MSTR_RD_MULT | 2389 RADEON_BUS_MSTR_RD_LINE | 2390 RADEON_BUS_RD_DISCARD_EN | 2391 RADEON_BUS_MSTR_DISCONNECT_EN | 2392 RADEON_BUS_READ_BURST); 2393 2394 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2395 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2396 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2397 PUT32(sc, RADEON_RBBM_CNTL, 2398 (3 << RADEON_RB_SETTLE_SHIFT) | 2399 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2400 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2401 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2402 2403 /* XXX: figure out what these mean! */ 2404 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2405 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2406 #if 0 2407 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2408 #endif 2409 2410 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2411 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2412 } 2413 2414 /* 2415 * This loads a linear color map for true color. 2416 */ 2417 void 2418 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2419 { 2420 int i; 2421 uint32_t vclk; 2422 2423 #define DAC_WIDTH ((1 << 10) - 1) 2424 #define CLUT_WIDTH ((1 << 8) - 1) 2425 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2426 2427 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2428 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2429 2430 if (crtc) 2431 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2432 else 2433 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2434 2435 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2436 if (sc->sc_displays[crtc].rd_bpp == 0) 2437 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2438 2439 if (sc->sc_displays[crtc].rd_bpp == 8) { 2440 /* ANSI palette */ 2441 int j = 0; 2442 uint32_t tmp, r, g, b; 2443 2444 for (i = 0; i <= CLUT_WIDTH; ++i) { 2445 tmp = i & 0xe0; 2446 /* 2447 * replicate bits so 0xe0 maps to a red value of 0xff 2448 * in order to make white look actually white 2449 */ 2450 tmp |= (tmp >> 3) | (tmp >> 6); 2451 r = tmp; 2452 2453 tmp = (i & 0x1c) << 3; 2454 tmp |= (tmp >> 3) | (tmp >> 6); 2455 g = tmp; 2456 2457 tmp = (i & 0x03) << 6; 2458 tmp |= tmp >> 2; 2459 tmp |= tmp >> 4; 2460 b = tmp; 2461 PUT32(sc, RADEON_PALETTE_30_DATA, 2462 (r << 22) | 2463 (g << 12) | 2464 (b << 2)); 2465 j += 3; 2466 } 2467 } else { 2468 /* linear ramp */ 2469 for (i = 0; i <= CLUT_WIDTH; ++i) { 2470 PUT32(sc, RADEON_PALETTE_30_DATA, 2471 (CLUT_COLOR(i) << 10) | 2472 (CLUT_COLOR(i) << 20) | 2473 (CLUT_COLOR(i))); 2474 } 2475 } 2476 2477 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2478 PRINTREG(RADEON_DAC_CNTL2); 2479 2480 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2481 } 2482 2483 /* 2484 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2485 */ 2486 void 2487 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2488 { 2489 uint32_t tmp, save; 2490 2491 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2492 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2493 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2494 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2495 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2496 } 2497 2498 /* 2499 * Acceleration entry points. 2500 */ 2501 2502 /* this one draws characters using bitmap fonts */ 2503 static void 2504 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2505 { 2506 struct rasops_info *ri = cookie; 2507 struct vcons_screen *scr = ri->ri_hw; 2508 struct radeonfb_display *dp = scr->scr_cookie; 2509 struct radeonfb_softc *sc = dp->rd_softc; 2510 struct wsdisplay_font *font = PICK_FONT(ri, c); 2511 uint32_t w, h; 2512 int xd, yd, offset, i; 2513 uint32_t bg, fg, gmc; 2514 uint32_t reg; 2515 uint8_t *data8; 2516 uint16_t *data16; 2517 void *data; 2518 2519 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2520 return; 2521 2522 if (!CHAR_IN_FONT(c, font)) 2523 return; 2524 2525 w = font->fontwidth; 2526 h = font->fontheight; 2527 2528 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2529 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2530 2531 xd = ri->ri_xorigin + col * w; 2532 yd = ri->ri_yorigin + row * h; 2533 2534 if (c == 0x20) { 2535 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2536 return; 2537 } 2538 data = WSFONT_GLYPH(c, font); 2539 2540 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2541 2542 radeonfb_wait_fifo(sc, 9); 2543 2544 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2545 RADEON_GMC_BRUSH_NONE | 2546 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2547 RADEON_GMC_DST_CLIPPING | 2548 RADEON_ROP3_S | 2549 RADEON_DP_SRC_SOURCE_HOST_DATA | 2550 RADEON_GMC_CLR_CMP_CNTL_DIS | 2551 RADEON_GMC_WR_MSK_DIS | 2552 gmc); 2553 2554 PUT32(sc, RADEON_SC_LEFT, xd); 2555 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2556 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2557 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2558 PUT32(sc, RADEON_DP_CNTL, 2559 RADEON_DST_X_LEFT_TO_RIGHT | 2560 RADEON_DST_Y_TOP_TO_BOTTOM); 2561 2562 PUT32(sc, RADEON_SRC_X_Y, 0); 2563 offset = 32 - (font->stride << 3); 2564 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2565 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2566 2567 radeonfb_wait_fifo(sc, h); 2568 switch (font->stride) { 2569 case 1: { 2570 data8 = data; 2571 for (i = 0; i < h; i++) { 2572 reg = *data8; 2573 bus_space_write_stream_4(sc->sc_regt, 2574 sc->sc_regh, RADEON_HOST_DATA0, reg); 2575 data8++; 2576 } 2577 break; 2578 } 2579 case 2: { 2580 data16 = data; 2581 for (i = 0; i < h; i++) { 2582 reg = *data16; 2583 bus_space_write_stream_4(sc->sc_regt, 2584 sc->sc_regh, RADEON_HOST_DATA0, reg); 2585 data16++; 2586 } 2587 break; 2588 } 2589 } 2590 if (attr & 1) 2591 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2592 } 2593 2594 /* ... while this one is for anti-aliased ones */ 2595 static void 2596 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2597 { 2598 struct rasops_info *ri = cookie; 2599 struct vcons_screen *scr = ri->ri_hw; 2600 struct radeonfb_display *dp = scr->scr_cookie; 2601 struct radeonfb_softc *sc = dp->rd_softc; 2602 struct wsdisplay_font *font = PICK_FONT(ri, c); 2603 uint32_t bg, fg, gmc; 2604 uint8_t *data; 2605 int w, h, xd, yd; 2606 int i, r, g, b, aval; 2607 int rf, gf, bf, rb, gb, bb; 2608 uint32_t pixel; 2609 int rv; 2610 2611 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2612 return; 2613 2614 if (!CHAR_IN_FONT(c, font)) 2615 return; 2616 2617 w = font->fontwidth; 2618 h = font->fontheight; 2619 2620 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2621 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2622 2623 xd = ri->ri_xorigin + col * w; 2624 yd = ri->ri_yorigin + row * h; 2625 2626 if (c == 0x20) { 2627 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2628 if (attr & 1) 2629 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2630 return; 2631 } 2632 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2633 if (rv == GC_OK) 2634 return; 2635 2636 data = WSFONT_GLYPH(c, font); 2637 2638 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2639 2640 radeonfb_wait_fifo(sc, 5); 2641 2642 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2643 RADEON_GMC_BRUSH_NONE | 2644 RADEON_GMC_SRC_DATATYPE_COLOR | 2645 RADEON_ROP3_S | 2646 RADEON_DP_SRC_SOURCE_HOST_DATA | 2647 RADEON_GMC_CLR_CMP_CNTL_DIS | 2648 RADEON_GMC_WR_MSK_DIS | 2649 gmc); 2650 2651 PUT32(sc, RADEON_DP_CNTL, 2652 RADEON_DST_X_LEFT_TO_RIGHT | 2653 RADEON_DST_Y_TOP_TO_BOTTOM); 2654 2655 PUT32(sc, RADEON_SRC_X_Y, 0); 2656 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2657 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2658 2659 rf = (fg >> 16) & 0xff; 2660 rb = (bg >> 16) & 0xff; 2661 gf = (fg >> 8) & 0xff; 2662 gb = (bg >> 8) & 0xff; 2663 bf = fg & 0xff; 2664 bb = bg & 0xff; 2665 2666 /* 2667 * I doubt we can upload data faster than even the slowest Radeon 2668 * could process them, especially when doing the alpha blending stuff 2669 * along the way, so just make sure there's some room in the FIFO and 2670 * then hammer away 2671 * As it turns out we can, so make periodic stops to let the FIFO 2672 * drain. 2673 */ 2674 radeonfb_wait_fifo(sc, 20); 2675 for (i = 0; i < ri->ri_fontscale; i++) { 2676 aval = *data; 2677 data++; 2678 if (aval == 0) { 2679 pixel = bg; 2680 } else if (aval == 255) { 2681 pixel = fg; 2682 } else { 2683 r = aval * rf + (255 - aval) * rb; 2684 g = aval * gf + (255 - aval) * gb; 2685 b = aval * bf + (255 - aval) * bb; 2686 pixel = (r & 0xff00) << 8 | 2687 (g & 0xff00) | 2688 (b & 0xff00) >> 8; 2689 } 2690 if (i & 16) 2691 radeonfb_wait_fifo(sc, 20); 2692 PUT32(sc, RADEON_HOST_DATA0, pixel); 2693 } 2694 if (rv == GC_ADD) { 2695 glyphcache_add(&dp->rd_gc, c, xd, yd); 2696 } else 2697 if (attr & 1) 2698 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2699 2700 } 2701 2702 static void 2703 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2704 { 2705 struct rasops_info *ri = cookie; 2706 struct vcons_screen *scr = ri->ri_hw; 2707 struct radeonfb_display *dp = scr->scr_cookie; 2708 struct radeonfb_softc *sc = dp->rd_softc; 2709 struct wsdisplay_font *font = PICK_FONT(ri, c); 2710 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2711 int i, x, y, wi, he, r, g, b, aval; 2712 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2713 uint8_t *data8; 2714 int rv, cnt; 2715 2716 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2717 return; 2718 2719 if (!CHAR_IN_FONT(c, font)) 2720 return; 2721 2722 wi = font->fontwidth; 2723 he = font->fontheight; 2724 2725 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2726 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2727 2728 x = ri->ri_xorigin + col * wi; 2729 y = ri->ri_yorigin + row * he; 2730 2731 if (c == 0x20) { 2732 radeonfb_rectfill(dp, x, y, wi, he, bg); 2733 if (attr & 1) 2734 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2735 return; 2736 } 2737 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2738 if (rv == GC_OK) 2739 return; 2740 2741 data8 = WSFONT_GLYPH(c, font); 2742 2743 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2744 2745 radeonfb_wait_fifo(sc, 5); 2746 2747 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2748 RADEON_GMC_BRUSH_NONE | 2749 RADEON_GMC_SRC_DATATYPE_COLOR | 2750 RADEON_ROP3_S | 2751 RADEON_DP_SRC_SOURCE_HOST_DATA | 2752 RADEON_GMC_CLR_CMP_CNTL_DIS | 2753 RADEON_GMC_WR_MSK_DIS | 2754 gmc); 2755 2756 PUT32(sc, RADEON_DP_CNTL, 2757 RADEON_DST_X_LEFT_TO_RIGHT | 2758 RADEON_DST_Y_TOP_TO_BOTTOM); 2759 2760 PUT32(sc, RADEON_SRC_X_Y, 0); 2761 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2762 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2763 2764 /* 2765 * we need the RGB colours here, so get offsets into rasops_cmap 2766 */ 2767 fgo = ((attr >> 24) & 0xf) * 3; 2768 bgo = ((attr >> 16) & 0xf) * 3; 2769 2770 r0 = rasops_cmap[bgo]; 2771 r1 = rasops_cmap[fgo]; 2772 g0 = rasops_cmap[bgo + 1]; 2773 g1 = rasops_cmap[fgo + 1]; 2774 b0 = rasops_cmap[bgo + 2]; 2775 b1 = rasops_cmap[fgo + 2]; 2776 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2777 bg8 = R3G3B2(r0, g0, b0); 2778 fg8 = R3G3B2(r1, g1, b1); 2779 2780 radeonfb_wait_fifo(sc, 20); 2781 cnt = 0; 2782 for (i = 0; i < ri->ri_fontscale; i++) { 2783 aval = *data8; 2784 if (aval == 0) { 2785 pixel = bg8; 2786 } else if (aval == 255) { 2787 pixel = fg8; 2788 } else { 2789 r = aval * r1 + (255 - aval) * r0; 2790 g = aval * g1 + (255 - aval) * g0; 2791 b = aval * b1 + (255 - aval) * b0; 2792 pixel = ((r & 0xe000) >> 8) | 2793 ((g & 0xe000) >> 11) | 2794 ((b & 0xc000) >> 14); 2795 } 2796 latch = (latch << 8) | pixel; 2797 /* write in 32bit chunks */ 2798 if ((i & 3) == 3) { 2799 PUT32S(sc, RADEON_HOST_DATA0, latch); 2800 /* 2801 * not strictly necessary, old data should be shifted 2802 * out 2803 */ 2804 latch = 0; 2805 cnt++; 2806 if (cnt > 16) { 2807 cnt = 0; 2808 radeonfb_wait_fifo(sc, 20); 2809 } 2810 } 2811 data8++; 2812 } 2813 /* if we have pixels left in latch write them out */ 2814 if ((i & 3) != 0) { 2815 /* 2816 * radeon is weird - apparently leftover pixels are written 2817 * from the middle, not from the left as everything else 2818 */ 2819 PUT32(sc, RADEON_HOST_DATA0, latch); 2820 } 2821 2822 if (rv == GC_ADD) { 2823 glyphcache_add(&dp->rd_gc, c, x, y); 2824 } else 2825 if (attr & 1) 2826 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2827 2828 } 2829 2830 /* 2831 * wrapper for software character drawing 2832 * just sync the engine and call rasops*_putchar() 2833 */ 2834 2835 static void 2836 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2837 { 2838 struct rasops_info *ri = cookie; 2839 struct vcons_screen *scr = ri->ri_hw; 2840 struct radeonfb_display *dp = scr->scr_cookie; 2841 2842 radeonfb_engine_idle(dp->rd_softc); 2843 dp->rd_putchar(ri, row, col, c, attr); 2844 } 2845 2846 static void 2847 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2848 { 2849 struct rasops_info *ri = cookie; 2850 struct vcons_screen *scr = ri->ri_hw; 2851 struct radeonfb_display *dp = scr->scr_cookie; 2852 uint32_t x, y, w, h, fg, bg, ul; 2853 2854 /* XXX: check for full emulation mode? */ 2855 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2856 x = ri->ri_xorigin; 2857 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2858 w = ri->ri_emuwidth; 2859 h = ri->ri_font->fontheight * nrows; 2860 2861 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2862 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2863 } 2864 } 2865 2866 static void 2867 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2868 { 2869 struct rasops_info *ri = cookie; 2870 struct vcons_screen *scr = ri->ri_hw; 2871 struct radeonfb_display *dp = scr->scr_cookie; 2872 uint32_t x, ys, yd, w, h; 2873 2874 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2875 x = ri->ri_xorigin; 2876 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2877 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2878 w = ri->ri_emuwidth; 2879 h = ri->ri_font->fontheight * nrows; 2880 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2881 RADEON_ROP3_S); 2882 } 2883 } 2884 2885 static void 2886 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2887 { 2888 struct rasops_info *ri = cookie; 2889 struct vcons_screen *scr = ri->ri_hw; 2890 struct radeonfb_display *dp = scr->scr_cookie; 2891 uint32_t xs, xd, y, w, h; 2892 2893 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2894 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2895 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2896 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2897 w = ri->ri_font->fontwidth * ncols; 2898 h = ri->ri_font->fontheight; 2899 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2900 RADEON_ROP3_S); 2901 } 2902 } 2903 2904 static void 2905 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2906 long fillattr) 2907 { 2908 struct rasops_info *ri = cookie; 2909 struct vcons_screen *scr = ri->ri_hw; 2910 struct radeonfb_display *dp = scr->scr_cookie; 2911 uint32_t x, y, w, h, fg, bg, ul; 2912 2913 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2914 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2915 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2916 w = ri->ri_font->fontwidth * ncols; 2917 h = ri->ri_font->fontheight; 2918 2919 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2920 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2921 } 2922 } 2923 2924 static void 2925 radeonfb_cursor(void *cookie, int on, int row, int col) 2926 { 2927 struct rasops_info *ri = cookie; 2928 struct vcons_screen *scr = ri->ri_hw; 2929 struct radeonfb_display *dp = scr->scr_cookie; 2930 int x, y, wi, he; 2931 2932 wi = ri->ri_font->fontwidth; 2933 he = ri->ri_font->fontheight; 2934 2935 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2936 x = ri->ri_ccol * wi + ri->ri_xorigin; 2937 y = ri->ri_crow * he + ri->ri_yorigin; 2938 /* first turn off the old cursor */ 2939 if (ri->ri_flg & RI_CURSOR) { 2940 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2941 RADEON_ROP3_Dn); 2942 ri->ri_flg &= ~RI_CURSOR; 2943 } 2944 ri->ri_crow = row; 2945 ri->ri_ccol = col; 2946 /* then (possibly) turn on the new one */ 2947 if (on) { 2948 x = ri->ri_ccol * wi + ri->ri_xorigin; 2949 y = ri->ri_crow * he + ri->ri_yorigin; 2950 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2951 RADEON_ROP3_Dn); 2952 ri->ri_flg |= RI_CURSOR; 2953 } 2954 } else { 2955 scr->scr_ri.ri_crow = row; 2956 scr->scr_ri.ri_ccol = col; 2957 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2958 } 2959 } 2960 2961 /* 2962 * Underlying acceleration support. 2963 */ 2964 2965 static void 2966 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2967 int width, int height, uint32_t color) 2968 { 2969 struct radeonfb_softc *sc = dp->rd_softc; 2970 uint32_t gmc; 2971 2972 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2973 2974 radeonfb_wait_fifo(sc, 6); 2975 2976 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2977 RADEON_GMC_BRUSH_SOLID_COLOR | 2978 RADEON_GMC_SRC_DATATYPE_COLOR | 2979 RADEON_GMC_CLR_CMP_CNTL_DIS | 2980 RADEON_ROP3_P | gmc); 2981 2982 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2983 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2984 PUT32(sc, RADEON_DP_CNTL, 2985 RADEON_DST_X_LEFT_TO_RIGHT | 2986 RADEON_DST_Y_TOP_TO_BOTTOM); 2987 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2988 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2989 2990 } 2991 2992 static void 2993 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 2994 int width, int height, long attr) 2995 { 2996 struct radeonfb_display *dp = cookie; 2997 2998 radeonfb_rectfill(dp, dstx, dsty, width, height, 2999 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3000 } 3001 3002 static void 3003 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3004 int dstx, int dsty, int width, int height, int rop) 3005 { 3006 struct radeonfb_display *dp = cookie; 3007 struct radeonfb_softc *sc = dp->rd_softc; 3008 uint32_t gmc; 3009 uint32_t dir; 3010 3011 if (dsty < srcy) { 3012 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3013 } else { 3014 srcy += height - 1; 3015 dsty += height - 1; 3016 dir = 0; 3017 } 3018 if (dstx < srcx) { 3019 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3020 } else { 3021 srcx += width - 1; 3022 dstx += width - 1; 3023 } 3024 3025 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3026 3027 radeonfb_wait_fifo(sc, 6); 3028 3029 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3030 RADEON_GMC_BRUSH_SOLID_COLOR | 3031 RADEON_GMC_SRC_DATATYPE_COLOR | 3032 RADEON_GMC_CLR_CMP_CNTL_DIS | 3033 RADEON_DP_SRC_SOURCE_MEMORY | 3034 rop | gmc); 3035 3036 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3037 PUT32(sc, RADEON_DP_CNTL, dir); 3038 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3039 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3040 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3041 } 3042 3043 static void 3044 radeonfb_engine_idle(struct radeonfb_softc *sc) 3045 { 3046 3047 radeonfb_wait_fifo(sc, 64); 3048 while ((GET32(sc, RADEON_RBBM_STATUS) & 3049 RADEON_RBBM_ACTIVE) != 0); 3050 radeonfb_engine_flush(sc); 3051 } 3052 3053 static inline void 3054 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3055 { 3056 int i; 3057 3058 for (i = RADEON_TIMEOUT; i; i--) { 3059 if ((GET32(sc, RADEON_RBBM_STATUS) & 3060 RADEON_RBBM_FIFOCNT_MASK) >= n) 3061 return; 3062 } 3063 #ifdef DIAGNOSTIC 3064 if (!i) 3065 printf("%s: timed out waiting for fifo (%x)\n", 3066 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3067 #endif 3068 } 3069 3070 static void 3071 radeonfb_engine_flush(struct radeonfb_softc *sc) 3072 { 3073 int i = 0; 3074 3075 if (IS_R300(sc)) { 3076 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3077 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3078 i++; 3079 } 3080 } else { 3081 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3082 RADEON_RB2D_DC_FLUSH_ALL); 3083 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3084 RADEON_RB2D_DC_BUSY) { 3085 i++; 3086 } 3087 } 3088 #ifdef DIAGNOSTIC 3089 if (i > RADEON_TIMEOUT) 3090 printf("%s: engine flush timed out!\n", XNAME(sc)); 3091 #endif 3092 } 3093 3094 static inline void 3095 radeonfb_unclip(struct radeonfb_softc *sc) 3096 { 3097 3098 radeonfb_wait_fifo(sc, 2); 3099 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3100 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3101 } 3102 3103 static void 3104 radeonfb_engine_init(struct radeonfb_display *dp) 3105 { 3106 struct radeonfb_softc *sc = dp->rd_softc; 3107 uint32_t pitch; 3108 volatile uint32_t junk; 3109 3110 /* no 3D */ 3111 PUT32(sc, RADEON_RB3D_CNTL, 0); 3112 3113 radeonfb_engine_reset(sc); 3114 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3115 3116 radeonfb_wait_fifo(sc, 1); 3117 if (!IS_R300(sc)) 3118 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3119 3120 radeonfb_wait_fifo(sc, 3); 3121 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3122 (pitch << 22) | (sc->sc_aperbase >> 10)); 3123 3124 3125 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3126 (pitch << 22) | (sc->sc_aperbase >> 10)); 3127 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3128 (pitch << 22) | (sc->sc_aperbase >> 10)); 3129 3130 radeonfb_wait_fifo(sc, 1); 3131 #if _BYTE_ORDER == _BIG_ENDIAN 3132 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3133 #else 3134 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 3135 #endif 3136 junk = GET32(sc, RADEON_DP_DATATYPE); 3137 3138 /* default scissors -- no clipping */ 3139 radeonfb_wait_fifo(sc, 1); 3140 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3141 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3142 3143 radeonfb_wait_fifo(sc, 1); 3144 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3145 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3146 RADEON_GMC_CLR_CMP_CNTL_DIS | 3147 RADEON_GMC_BRUSH_SOLID_COLOR | 3148 RADEON_GMC_SRC_DATATYPE_COLOR); 3149 3150 radeonfb_wait_fifo(sc, 10); 3151 PUT32(sc, RADEON_DST_LINE_START, 0); 3152 PUT32(sc, RADEON_DST_LINE_END, 0); 3153 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3154 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3155 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3156 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3157 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3158 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3159 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3160 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3161 radeonfb_engine_idle(sc); 3162 } 3163 3164 static void 3165 radeonfb_engine_reset(struct radeonfb_softc *sc) 3166 { 3167 uint32_t hpc, rbbm, mclkcntl, clkindex; 3168 3169 radeonfb_engine_flush(sc); 3170 3171 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3172 if (HAS_R300CG(sc)) 3173 radeonfb_r300cg_workaround(sc); 3174 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3175 3176 /* 3177 * According to comments in XFree code, resetting the HDP via 3178 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3179 * So we use HOST_PATH_CNTL instead. 3180 */ 3181 3182 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3183 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3184 if (IS_R300(sc)) { 3185 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3186 RADEON_SOFT_RESET_CP | 3187 RADEON_SOFT_RESET_HI | 3188 RADEON_SOFT_RESET_E2); 3189 GET32(sc, RADEON_RBBM_SOFT_RESET); 3190 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3191 /* 3192 * XXX: this bit is not defined in any ATI docs I have, 3193 * nor in the XFree code, but XFree does it. Why? 3194 */ 3195 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3196 } else { 3197 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3198 RADEON_SOFT_RESET_CP | 3199 RADEON_SOFT_RESET_SE | 3200 RADEON_SOFT_RESET_RE | 3201 RADEON_SOFT_RESET_PP | 3202 RADEON_SOFT_RESET_E2 | 3203 RADEON_SOFT_RESET_RB); 3204 GET32(sc, RADEON_RBBM_SOFT_RESET); 3205 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3206 ~(RADEON_SOFT_RESET_CP | 3207 RADEON_SOFT_RESET_SE | 3208 RADEON_SOFT_RESET_RE | 3209 RADEON_SOFT_RESET_PP | 3210 RADEON_SOFT_RESET_E2 | 3211 RADEON_SOFT_RESET_RB)); 3212 GET32(sc, RADEON_RBBM_SOFT_RESET); 3213 } 3214 3215 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3216 GET32(sc, RADEON_HOST_PATH_CNTL); 3217 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3218 3219 if (IS_R300(sc)) 3220 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3221 3222 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3223 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3224 3225 if (HAS_R300CG(sc)) 3226 radeonfb_r300cg_workaround(sc); 3227 } 3228 3229 static int 3230 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3231 { 3232 int x, y; 3233 3234 x = pos->x; 3235 y = pos->y; 3236 3237 /* 3238 * This doesn't let a cursor move off the screen. I'm not 3239 * sure if this will have negative effects for e.g. Xinerama. 3240 * I'd guess Xinerama handles it by changing the cursor shape, 3241 * but that needs verification. 3242 */ 3243 if (x >= dp->rd_virtx) 3244 x = dp->rd_virtx - 1; 3245 if (x < 0) 3246 x = 0; 3247 if (y >= dp->rd_virty) 3248 y = dp->rd_virty - 1; 3249 if (y < 0) 3250 y = 0; 3251 3252 dp->rd_cursor.rc_pos.x = x; 3253 dp->rd_cursor.rc_pos.y = y; 3254 3255 radeonfb_cursor_position(dp); 3256 return 0; 3257 } 3258 3259 static int 3260 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3261 { 3262 unsigned flags; 3263 3264 uint8_t r[2], g[2], b[2]; 3265 unsigned index, count; 3266 int i, err; 3267 int pitch, size; 3268 struct radeonfb_cursor nc; 3269 3270 flags = wc->which; 3271 3272 /* copy old values */ 3273 nc = dp->rd_cursor; 3274 3275 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3276 index = wc->cmap.index; 3277 count = wc->cmap.count; 3278 3279 if (index >= 2 || (index + count) > 2) 3280 return EINVAL; 3281 3282 err = copyin(wc->cmap.red, &r[index], count); 3283 if (err) 3284 return err; 3285 err = copyin(wc->cmap.green, &g[index], count); 3286 if (err) 3287 return err; 3288 err = copyin(wc->cmap.blue, &b[index], count); 3289 if (err) 3290 return err; 3291 3292 for (i = index; i < index + count; i++) { 3293 nc.rc_cmap[i] = 3294 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3295 } 3296 } 3297 3298 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3299 if ((wc->size.x > RADEON_CURSORMAXX) || 3300 (wc->size.y > RADEON_CURSORMAXY)) 3301 return EINVAL; 3302 3303 /* figure bytes per line */ 3304 pitch = (wc->size.x + 7) / 8; 3305 size = pitch * wc->size.y; 3306 3307 /* clear the old cursor and mask */ 3308 memset(nc.rc_image, 0, 512); 3309 memset(nc.rc_mask, 0, 512); 3310 3311 nc.rc_size = wc->size; 3312 3313 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3314 return err; 3315 3316 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3317 return err; 3318 } 3319 3320 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3321 nc.rc_hot = wc->hot; 3322 if (nc.rc_hot.x >= nc.rc_size.x) 3323 nc.rc_hot.x = nc.rc_size.x - 1; 3324 if (nc.rc_hot.y >= nc.rc_size.y) 3325 nc.rc_hot.y = nc.rc_size.y - 1; 3326 } 3327 3328 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3329 nc.rc_pos = wc->pos; 3330 if (nc.rc_pos.x >= dp->rd_virtx) 3331 nc.rc_pos.x = dp->rd_virtx - 1; 3332 #if 0 3333 if (nc.rc_pos.x < 0) 3334 nc.rc_pos.x = 0; 3335 #endif 3336 if (nc.rc_pos.y >= dp->rd_virty) 3337 nc.rc_pos.y = dp->rd_virty - 1; 3338 #if 0 3339 if (nc.rc_pos.y < 0) 3340 nc.rc_pos.y = 0; 3341 #endif 3342 } 3343 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3344 nc.rc_visible = wc->enable; 3345 } 3346 3347 dp->rd_cursor = nc; 3348 radeonfb_cursor_update(dp, wc->which); 3349 3350 return 0; 3351 } 3352 3353 /* 3354 * Change the cursor shape. Call this with the cursor locked to avoid 3355 * flickering/tearing. 3356 */ 3357 static void 3358 radeonfb_cursor_shape(struct radeonfb_display *dp) 3359 { 3360 uint8_t and[512], xor[512]; 3361 int i, j, src, dst, pitch; 3362 const uint8_t *msk = dp->rd_cursor.rc_mask; 3363 const uint8_t *img = dp->rd_cursor.rc_image; 3364 3365 /* 3366 * Radeon cursor data interleaves one line of AND data followed 3367 * by a line of XOR data. (Each line corresponds to a whole hardware 3368 * pitch - i.e. 64 pixels or 8 bytes.) 3369 * 3370 * The cursor is displayed using the following table: 3371 * 3372 * AND XOR Result 3373 * ---------------------- 3374 * 0 0 Cursor color 0 3375 * 0 1 Cursor color 1 3376 * 1 0 Transparent 3377 * 1 1 Complement of background 3378 * 3379 * Our masks are therefore different from what we were passed. 3380 * Passed in, I'm assuming the data represents either color 0 or 1, 3381 * and a mask, so the passed in table looks like: 3382 * 3383 * IMG Mask Result 3384 * ----------------------- 3385 * 0 0 Transparent 3386 * 0 1 Cursor color 0 3387 * 1 0 Transparent 3388 * 1 1 Cursor color 1 3389 * 3390 * IF mask bit == 1, AND = 0, XOR = color. 3391 * IF mask bit == 0, AND = 1, XOR = 0. 3392 * 3393 * hence: AND = ~(mask); XOR = color & ~(mask); 3394 */ 3395 3396 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3397 3398 /* start by assuming all bits are transparent */ 3399 memset(and, 0xff, 512); 3400 memset(xor, 0x00, 512); 3401 3402 src = 0; 3403 dst = 0; 3404 for (i = 0; i < 64; i++) { 3405 for (j = 0; j < 64; j += 8) { 3406 if ((i < dp->rd_cursor.rc_size.y) && 3407 (j < dp->rd_cursor.rc_size.x)) { 3408 3409 /* take care to leave odd bits alone */ 3410 and[dst] &= ~(msk[src]); 3411 xor[dst] = img[src] & msk[src]; 3412 src++; 3413 } 3414 dst++; 3415 } 3416 } 3417 3418 /* copy the image into place */ 3419 for (i = 0; i < 64; i++) { 3420 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3421 &and[i * 8], 8); 3422 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3423 &xor[i * 8], 8); 3424 } 3425 } 3426 3427 static void 3428 radeonfb_cursor_position(struct radeonfb_display *dp) 3429 { 3430 struct radeonfb_softc *sc = dp->rd_softc; 3431 uint32_t offset, hvoff, hvpos; /* registers */ 3432 uint32_t coff; /* cursor offset */ 3433 int i, x, y, xoff, yoff, crtcoff; 3434 3435 /* 3436 * XXX: this also needs to handle pan/scan 3437 */ 3438 for (i = 0; i < dp->rd_ncrtcs; i++) { 3439 3440 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3441 3442 if (rcp->rc_number) { 3443 offset = RADEON_CUR2_OFFSET; 3444 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3445 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3446 crtcoff = RADEON_CRTC2_OFFSET; 3447 } else { 3448 offset = RADEON_CUR_OFFSET; 3449 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3450 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3451 crtcoff = RADEON_CRTC_OFFSET; 3452 } 3453 3454 x = dp->rd_cursor.rc_pos.x; 3455 y = dp->rd_cursor.rc_pos.y; 3456 3457 while (y < rcp->rc_yoffset) { 3458 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3459 } 3460 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3461 rcp->rc_yoffset += RADEON_PANINCREMENT; 3462 } 3463 while (x < rcp->rc_xoffset) { 3464 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3465 } 3466 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3467 rcp->rc_xoffset += RADEON_PANINCREMENT; 3468 } 3469 3470 /* adjust for the cursor's hotspot */ 3471 x -= dp->rd_cursor.rc_hot.x; 3472 y -= dp->rd_cursor.rc_hot.y; 3473 xoff = yoff = 0; 3474 3475 if (x >= dp->rd_virtx) 3476 x = dp->rd_virtx - 1; 3477 if (y >= dp->rd_virty) 3478 y = dp->rd_virty - 1; 3479 3480 /* now adjust cursor so it is relative to viewport */ 3481 x -= rcp->rc_xoffset; 3482 y -= rcp->rc_yoffset; 3483 3484 /* 3485 * no need to check for fall off, because we should 3486 * never move off the screen entirely! 3487 */ 3488 coff = 0; 3489 if (x < 0) { 3490 xoff = -x; 3491 x = 0; 3492 } 3493 if (y < 0) { 3494 yoff = -y; 3495 y = 0; 3496 coff = (yoff * 2) * 8; 3497 } 3498 3499 /* pan the display */ 3500 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3501 rcp->rc_xoffset); 3502 3503 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3504 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3505 /* NB: this unlocks the cursor */ 3506 PUT32(sc, hvpos, (x << 16) | y); 3507 } 3508 } 3509 3510 static void 3511 radeonfb_cursor_visible(struct radeonfb_display *dp) 3512 { 3513 int i; 3514 uint32_t gencntl, bit; 3515 3516 for (i = 0; i < dp->rd_ncrtcs; i++) { 3517 if (dp->rd_crtcs[i].rc_number) { 3518 gencntl = RADEON_CRTC2_GEN_CNTL; 3519 bit = RADEON_CRTC2_CUR_EN; 3520 } else { 3521 gencntl = RADEON_CRTC_GEN_CNTL; 3522 bit = RADEON_CRTC_CUR_EN; 3523 } 3524 3525 if (dp->rd_cursor.rc_visible) 3526 SET32(dp->rd_softc, gencntl, bit); 3527 else 3528 CLR32(dp->rd_softc, gencntl, bit); 3529 } 3530 } 3531 3532 static void 3533 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3534 { 3535 int i; 3536 uint32_t c0reg, c1reg; 3537 struct radeonfb_softc *sc = dp->rd_softc; 3538 3539 for (i = 0; i < dp->rd_ncrtcs; i++) { 3540 if (dp->rd_crtcs[i].rc_number) { 3541 c0reg = RADEON_CUR2_CLR0; 3542 c1reg = RADEON_CUR2_CLR1; 3543 } else { 3544 c0reg = RADEON_CUR_CLR0; 3545 c1reg = RADEON_CUR_CLR1; 3546 } 3547 3548 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3549 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3550 } 3551 } 3552 3553 static void 3554 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3555 { 3556 struct radeonfb_softc *sc; 3557 int i; 3558 3559 sc = dp->rd_softc; 3560 for (i = 0; i < dp->rd_ncrtcs; i++) { 3561 if (dp->rd_crtcs[i].rc_number) { 3562 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3563 } else { 3564 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3565 } 3566 } 3567 3568 if (which & WSDISPLAY_CURSOR_DOCMAP) 3569 radeonfb_cursor_cmap(dp); 3570 3571 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3572 radeonfb_cursor_shape(dp); 3573 3574 if (which & WSDISPLAY_CURSOR_DOCUR) 3575 radeonfb_cursor_visible(dp); 3576 3577 /* this one is unconditional, because it updates other stuff */ 3578 radeonfb_cursor_position(dp); 3579 } 3580 3581 static struct videomode * 3582 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3583 { 3584 int r1, r2; 3585 3586 /* otherwise pick the higher refresh rate */ 3587 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3588 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3589 3590 return (r1 < r2 ? m2 : m1); 3591 } 3592 3593 static const struct videomode * 3594 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3595 int x, int y) 3596 { 3597 struct edid_info *ep = &rp->rp_edid; 3598 struct videomode *vmp = NULL; 3599 int i; 3600 3601 if (!rp->rp_edid_valid) { 3602 /* fallback to safe mode */ 3603 return radeonfb_modelookup(sc->sc_defaultmode); 3604 } 3605 3606 /* always choose the preferred mode first! */ 3607 if (ep->edid_preferred_mode) { 3608 3609 /* XXX: add auto-stretching support for native mode */ 3610 3611 /* this may want panning to occur, btw */ 3612 if ((ep->edid_preferred_mode->hdisplay <= x) && 3613 (ep->edid_preferred_mode->vdisplay <= y)) 3614 return ep->edid_preferred_mode; 3615 } 3616 3617 for (i = 0; i < ep->edid_nmodes; i++) { 3618 /* 3619 * We elect to pick a resolution that is too large for 3620 * the monitor than one that is too small. This means 3621 * that we will prefer to pan rather than to try to 3622 * center a smaller display on a larger screen. In 3623 * practice, this shouldn't matter because if a 3624 * monitor can support a larger resolution, it can 3625 * probably also support the smaller. A specific 3626 * exception is fixed format panels, but hopefully 3627 * they are properly dealt with by the "autostretch" 3628 * logic above. 3629 */ 3630 if ((ep->edid_modes[i].hdisplay > x) || 3631 (ep->edid_modes[i].vdisplay > y)) { 3632 continue; 3633 } 3634 3635 /* 3636 * at this point, the display mode is no larger than 3637 * what we've requested. 3638 */ 3639 if (vmp == NULL) 3640 vmp = &ep->edid_modes[i]; 3641 3642 /* eliminate smaller modes */ 3643 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3644 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3645 continue; 3646 3647 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3648 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3649 vmp = &ep->edid_modes[i]; 3650 continue; 3651 } 3652 3653 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3654 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3655 3656 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3657 } 3658 3659 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3660 } 3661 3662 static int 3663 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3664 { 3665 int i; 3666 3667 for (i = 0; i < nlist; i++) { 3668 if ((x == list[i].hdisplay) && 3669 (y == list[i].vdisplay)) { 3670 return 1; 3671 } 3672 } 3673 return 0; 3674 } 3675 3676 static void 3677 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3678 int pan) 3679 { 3680 struct radeonfb_port *rp; 3681 struct edid_info *ep; 3682 int i, j; 3683 3684 *x = 0; 3685 *y = 0; 3686 3687 if (pan) { 3688 for (i = 0; i < dp->rd_ncrtcs; i++) { 3689 rp = dp->rd_crtcs[i].rc_port; 3690 ep = &rp->rp_edid; 3691 if (!rp->rp_edid_valid) { 3692 /* monitor not present */ 3693 continue; 3694 } 3695 3696 /* 3697 * For now we are ignoring "conflict" that 3698 * could occur when mixing some modes like 3699 * 1280x1024 and 1400x800. It isn't clear 3700 * which is better, so the first one wins. 3701 */ 3702 for (j = 0; j < ep->edid_nmodes; j++) { 3703 /* 3704 * ignore resolutions that are too big for 3705 * the radeon 3706 */ 3707 if (ep->edid_modes[j].hdisplay > 3708 dp->rd_softc->sc_maxx) 3709 continue; 3710 if (ep->edid_modes[j].vdisplay > 3711 dp->rd_softc->sc_maxy) 3712 continue; 3713 3714 /* 3715 * pick largest resolution, the 3716 * smaller monitor will pan 3717 */ 3718 if ((ep->edid_modes[j].hdisplay >= *x) && 3719 (ep->edid_modes[j].vdisplay >= *y)) { 3720 *x = ep->edid_modes[j].hdisplay; 3721 *y = ep->edid_modes[j].vdisplay; 3722 } 3723 } 3724 } 3725 3726 } else { 3727 struct videomode modes[64]; 3728 int nmodes = 0; 3729 int valid = 0; 3730 3731 for (i = 0; i < dp->rd_ncrtcs; i++) { 3732 /* 3733 * pick the largest resolution in common. 3734 */ 3735 rp = dp->rd_crtcs[i].rc_port; 3736 ep = &rp->rp_edid; 3737 3738 if (!rp->rp_edid_valid) 3739 continue; 3740 3741 if (!valid) { 3742 /* 3743 * Pick the preferred mode for this port 3744 * if available. 3745 */ 3746 if (ep->edid_preferred_mode) { 3747 struct videomode *vmp = 3748 ep->edid_preferred_mode; 3749 3750 if ((vmp->hdisplay <= 3751 dp->rd_softc->sc_maxx) && 3752 (vmp->vdisplay <= 3753 dp->rd_softc->sc_maxy)) 3754 modes[nmodes++] = *vmp; 3755 } else { 3756 3757 /* initialize starting list */ 3758 for (j = 0; j < ep->edid_nmodes; j++) { 3759 /* 3760 * ignore resolutions that are 3761 * too big for the radeon 3762 */ 3763 if (ep->edid_modes[j].hdisplay > 3764 dp->rd_softc->sc_maxx) 3765 continue; 3766 if (ep->edid_modes[j].vdisplay > 3767 dp->rd_softc->sc_maxy) 3768 continue; 3769 3770 modes[nmodes] = 3771 ep->edid_modes[j]; 3772 nmodes++; 3773 } 3774 } 3775 valid = 1; 3776 } else { 3777 /* merge into preexisting list */ 3778 for (j = 0; j < nmodes; j++) { 3779 if (!radeonfb_hasres(ep->edid_modes, 3780 ep->edid_nmodes, 3781 modes[j].hdisplay, 3782 modes[j].vdisplay)) { 3783 modes[j] = modes[nmodes]; 3784 j--; 3785 nmodes--; 3786 } 3787 } 3788 } 3789 } 3790 3791 /* now we have to pick from the merged list */ 3792 for (i = 0; i < nmodes; i++) { 3793 if ((modes[i].hdisplay >= *x) && 3794 (modes[i].vdisplay >= *y)) { 3795 *x = modes[i].hdisplay; 3796 *y = modes[i].vdisplay; 3797 } 3798 } 3799 } 3800 3801 if ((*x == 0) || (*y == 0)) { 3802 /* fallback to safe mode */ 3803 *x = 640; 3804 *y = 480; 3805 } 3806 } 3807 3808 /* 3809 * backlight levels are linear on: 3810 * - RV200, RV250, RV280, RV350 3811 * - but NOT on PowerBook4,3 6,3 6,5 3812 * according to Linux' radeonfb 3813 */ 3814 3815 /* Get the current backlight level for the display. */ 3816 3817 static int 3818 radeonfb_get_backlight(struct radeonfb_display *dp) 3819 { 3820 int s; 3821 uint32_t level; 3822 3823 s = spltty(); 3824 3825 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3826 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3827 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3828 3829 /* 3830 * On some chips, we should negate the backlight level. 3831 * XXX Find out on which chips. 3832 */ 3833 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3834 level = RADEONFB_BACKLIGHT_MAX - level; 3835 3836 splx(s); 3837 3838 return level; 3839 } 3840 3841 /* Set the backlight to the given level for the display. */ 3842 static void 3843 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3844 { 3845 if (dp->rd_bl_on == on) 3846 return; 3847 dp->rd_bl_on = on; 3848 radeonfb_set_backlight(dp, dp->rd_bl_level); 3849 } 3850 3851 static int 3852 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3853 { 3854 struct radeonfb_softc *sc; 3855 int rlevel, s; 3856 uint32_t lvds; 3857 3858 s = spltty(); 3859 3860 dp->rd_bl_level = level; 3861 if (dp->rd_bl_on == 0) 3862 level = 0; 3863 3864 if (level < 0) 3865 level = 0; 3866 else if (level >= RADEONFB_BACKLIGHT_MAX) 3867 level = RADEONFB_BACKLIGHT_MAX; 3868 3869 sc = dp->rd_softc; 3870 3871 /* On some chips, we should negate the backlight level. */ 3872 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3873 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3874 } else 3875 rlevel = level; 3876 3877 callout_stop(&dp->rd_bl_lvds_co); 3878 radeonfb_engine_idle(sc); 3879 3880 /* 3881 * Turn off the display if the backlight is set to 0, since the 3882 * display is useless without backlight anyway. 3883 */ 3884 if (level == 0) 3885 radeonfb_blank(dp, 1); 3886 else if (radeonfb_get_backlight(dp) == 0) 3887 radeonfb_blank(dp, 0); 3888 3889 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3890 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3891 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3892 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3893 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3894 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3895 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3896 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3897 lvds |= RADEON_LVDS_ON; 3898 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3899 } else { 3900 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3901 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3902 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3903 } 3904 3905 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3906 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3907 /* XXX What is the correct delay? */ 3908 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3909 3910 splx(s); 3911 3912 return 0; 3913 } 3914 3915 /* 3916 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3917 * Set the delayed bits in the register, and clear the stored delayed 3918 * value. 3919 */ 3920 3921 static void radeonfb_lvds_callout(void *arg) 3922 { 3923 struct radeonfb_display *dp = arg; 3924 int s; 3925 3926 s = splhigh(); 3927 3928 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3929 dp->rd_bl_lvds_val); 3930 dp->rd_bl_lvds_val = 0; 3931 3932 splx(s); 3933 } 3934 3935 static void 3936 radeonfb_brightness_up(device_t dev) 3937 { 3938 struct radeonfb_softc *sc = device_private(dev); 3939 struct radeonfb_display *dp = &sc->sc_displays[0]; 3940 int level; 3941 3942 /* we assume the main display is the first one - need a better way */ 3943 if (sc->sc_ndisplays < 1) return; 3944 /* make sure pushing the hotkeys always has an effect */ 3945 dp->rd_bl_on = 1; 3946 level = dp->rd_bl_level; 3947 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3948 radeonfb_set_backlight(dp, level); 3949 } 3950 3951 static void 3952 radeonfb_brightness_down(device_t dev) 3953 { 3954 struct radeonfb_softc *sc = device_private(dev); 3955 struct radeonfb_display *dp = &sc->sc_displays[0]; 3956 int level; 3957 3958 /* we assume the main display is the first one - need a better way */ 3959 if (sc->sc_ndisplays < 1) return; 3960 /* make sure pushing the hotkeys always has an effect */ 3961 dp->rd_bl_on = 1; 3962 level = dp->rd_bl_level; 3963 level = max(0, level - 5); 3964 radeonfb_set_backlight(dp, level); 3965 } 3966
Indexes created Tue Sep 23 23:09:58 GMT 2025