radeonfb.c revision 1.67
1 /* $NetBSD: radeonfb.c,v 1.67 2012/12/20 02:58:32 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.67 2012/12/20 02:58:32 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 1, 0 }, 384 { 2, 1 }, 385 { 3, 4 }, 386 { 4, 2 }, 387 { 6, 6 }, 388 { 8, 3 }, 389 { 12, 7 }, 390 { 0, 0 } 391 }; 392 393 /* 394 * This table taken from X11. 395 */ 396 static const struct { 397 int family; 398 struct radeon_tmds_pll plls[4]; 399 } radeonfb_tmds_pll[] = { 400 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RS100, {{0, 0}}}, 403 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 407 { RADEON_RS300, {{0, 0}}}, 408 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 409 { RADEON_R300, {{-1, 0xb01cb}}}, 410 { RADEON_R350, {{-1, 0xb01cb}}}, 411 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 412 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_R420, {{-1, 0xb01cb}}}, 414 }; 415 416 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 417 418 419 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 420 radeonfb_match, radeonfb_attach, NULL, NULL); 421 422 static int 423 radeonfb_match(device_t parent, cfdata_t match, void *aux) 424 { 425 const struct pci_attach_args *pa = aux; 426 int i; 427 428 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 429 return 0; 430 431 for (i = 0; radeonfb_devices[i].devid; i++) { 432 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 433 return 100; /* high to defeat VGA/VESA */ 434 } 435 436 return 0; 437 } 438 439 static void 440 radeonfb_attach(device_t parent, device_t dev, void *aux) 441 { 442 struct radeonfb_softc *sc = device_private(dev); 443 const struct pci_attach_args *pa = aux; 444 const char *mptr; 445 bus_size_t bsz; 446 pcireg_t screg; 447 int i, j, fg, bg, ul, flags; 448 uint32_t v; 449 450 sc->sc_dev = dev; 451 sc->sc_id = pa->pa_id; 452 for (i = 0; radeonfb_devices[i].devid; i++) { 453 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 454 break; 455 } 456 457 pci_aprint_devinfo(pa, NULL); 458 459 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 460 461 KASSERT(radeonfb_devices[i].devid != 0); 462 sc->sc_pt = pa->pa_tag; 463 sc->sc_iot = pa->pa_iot; 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_family = radeonfb_devices[i].family; 466 sc->sc_flags = radeonfb_devices[i].flags; 467 468 /* enable memory and IO access */ 469 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 470 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 472 473 /* 474 * Some flags are general to entire chip families, and rather 475 * than clutter up the table with them, we go ahead and set 476 * them here. 477 */ 478 switch (sc->sc_family) { 479 case RADEON_RS100: 480 case RADEON_RS200: 481 sc->sc_flags |= RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_RV100: 485 case RADEON_RV200: 486 case RADEON_RV250: 487 case RADEON_RV280: 488 sc->sc_flags |= RFB_RV100; 489 break; 490 491 case RADEON_RS300: 492 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_R300: 496 case RADEON_RV350: 497 case RADEON_R350: 498 case RADEON_RV380: 499 case RADEON_R420: 500 /* newer chips */ 501 sc->sc_flags |= RFB_R300; 502 break; 503 504 case RADEON_R100: 505 sc->sc_flags |= RFB_NCRTC2; 506 break; 507 } 508 509 if ((sc->sc_family == RADEON_RV200) || 510 (sc->sc_family == RADEON_RV250) || 511 (sc->sc_family == RADEON_RV280) || 512 (sc->sc_family == RADEON_RV350)) { 513 bool inverted = 0; 514 /* backlight level is linear */ 515 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 516 prop_dictionary_get_bool(device_properties(sc->sc_dev), 517 "backlight_level_reverted", &inverted); 518 if (inverted) { 519 DPRINTF(("nope, it's inverted\n")); 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 } 522 } else 523 sc->sc_flags |= RFB_INV_BLIGHT; 524 525 /* 526 * XXX: to support true multihead, this must change. 527 */ 528 sc->sc_ndisplays = 1; 529 530 /* XXX: */ 531 if (!HAS_CRTC2(sc)) { 532 sc->sc_ndisplays = 1; 533 } 534 535 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 536 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 537 &sc->sc_regsz) != 0) { 538 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 539 goto error; 540 } 541 542 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 543 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 544 { 545 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 546 goto error; 547 } 548 sc->sc_romt = sc->sc_memt; 549 550 /* scratch register test... */ 551 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 552 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 553 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 554 goto error; 555 } 556 557 PRINTREG(RADEON_CRTC_EXT_CNTL); 558 PRINTREG(RADEON_CRTC_GEN_CNTL); 559 PRINTREG(RADEON_CRTC2_GEN_CNTL); 560 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 561 PRINTREG(RADEON_DAC_CNTL2); 562 563 PRINTREG(RADEON_BIOS_4_SCRATCH); 564 PRINTREG(RADEON_FP_GEN_CNTL); 565 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 566 PRINTREG(RADEON_FP2_GEN_CNTL); 567 PRINTREG(RADEON_TMDS_CNTL); 568 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 569 PRINTREG(RADEON_TMDS_PLL_CNTL); 570 PRINTREG(RADEON_LVDS_GEN_CNTL); 571 PRINTREG(RADEON_FP_HORZ_STRETCH); 572 PRINTREG(RADEON_FP_VERT_STRETCH); 573 574 /* XXX: RV100 specific */ 575 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 576 577 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 578 RADEON_TMDS_TRANSMITTER_PLLEN, 579 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 580 581 radeonfb_i2c_init(sc); 582 583 radeonfb_loadbios(sc, pa); 584 585 #ifdef RADEONFB_BIOS_INIT 586 if (radeonfb_bios_init(sc)) { 587 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 588 } 589 #endif 590 591 if (radeonfb_getclocks(sc)) { 592 aprint_error("%s: Unable to get reference clocks from BIOS\n", 593 XNAME(sc)); 594 goto error; 595 } 596 597 if (radeonfb_gettmds(sc)) { 598 aprint_error("%s: Unable to identify TMDS PLL settings\n", 599 XNAME(sc)); 600 goto error; 601 } 602 603 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 604 "minpll = %d, maxpll = %d\n", XNAME(sc), 605 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 606 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 607 608 radeonfb_getconnectors(sc); 609 610 radeonfb_set_fbloc(sc); 611 612 for (i = 0; radeonfb_limits[i].size; i++) { 613 if (sc->sc_memsz >= radeonfb_limits[i].size) { 614 sc->sc_maxx = radeonfb_limits[i].maxx; 615 sc->sc_maxy = radeonfb_limits[i].maxy; 616 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 617 /* framebuffer offset, start at a 4K page */ 618 sc->sc_fboffset = sc->sc_memsz / 619 radeonfb_limits[i].maxdisp; 620 /* 621 * we use the fbsize to figure out where we can store 622 * things like cursor data. 623 */ 624 sc->sc_fbsize = 625 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 626 RADEON_STRIDEALIGN) * sc->sc_maxy, 627 4096); 628 break; 629 } 630 } 631 632 633 radeonfb_init_misc(sc); 634 radeonfb_init_palette(sc, 0); 635 if (HAS_CRTC2(sc)) 636 radeonfb_init_palette(sc, 1); 637 638 /* program the DAC wirings */ 639 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 640 switch (sc->sc_ports[i].rp_dac_type) { 641 case RADEON_DAC_PRIMARY: 642 PATCH32(sc, RADEON_DAC_CNTL2, 643 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 644 ~RADEON_DAC2_DAC_CLK_SEL); 645 break; 646 case RADEON_DAC_TVDAC: 647 /* we always use the TVDAC to drive a secondary analog 648 * CRT for now. if we ever support TV-out this will 649 * have to change. 650 */ 651 SET32(sc, RADEON_DAC_CNTL2, 652 RADEON_DAC2_DAC2_CLK_SEL); 653 PATCH32(sc, RADEON_DISP_HW_DEBUG, 654 i ? 0 : RADEON_CRT2_DISP1_SEL, 655 ~RADEON_CRT2_DISP1_SEL); 656 break; 657 } 658 } 659 PRINTREG(RADEON_DAC_CNTL2); 660 PRINTREG(RADEON_DISP_HW_DEBUG); 661 662 /* other DAC programming */ 663 v = GET32(sc, RADEON_DAC_CNTL); 664 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 665 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 666 PUT32(sc, RADEON_DAC_CNTL, v); 667 PRINTREG(RADEON_DAC_CNTL); 668 669 /* XXX: this may need more investigation */ 670 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 671 PRINTREG(RADEON_TV_DAC_CNTL); 672 673 /* enable TMDS */ 674 SET32(sc, RADEON_FP_GEN_CNTL, 675 RADEON_FP_TMDS_EN | 676 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 677 RADEON_FP_CRTC_DONT_SHADOW_HEND); 678 /* 679 * XXX 680 * no idea why this is necessary - if I do not clear this bit on my 681 * iBook G4 the screen remains black, even though it's already clear. 682 * It needs to be set on my Sun XVR-100 for the DVI port to work 683 */ 684 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 685 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 686 } else 687 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 688 689 if (HAS_CRTC2(sc)) 690 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 691 692 /* 693 * we use bus_space_map instead of pci_mapreg, because we don't 694 * need the full aperature space. no point in wasting virtual 695 * address space we don't intend to use, right? 696 */ 697 if ((sc->sc_memsz < (4096 * 1024)) || 698 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 699 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 700 (bsz < sc->sc_memsz)) { 701 sc->sc_memsz = 0; 702 aprint_error("%s: Bad frame buffer configuration\n", 703 XNAME(sc)); 704 goto error; 705 } 706 707 /* 64 MB should be enough -- more just wastes map entries */ 708 if (sc->sc_memsz > (64 << 20)) 709 sc->sc_memsz = (64 << 20); 710 711 sc->sc_memt = pa->pa_memt; 712 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 713 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 714 sc->sc_memsz = 0; 715 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 716 goto error; 717 } 718 719 aprint_normal("%s: %d MB aperture at 0x%08x, " 720 "%d KB registers at 0x%08x\n", XNAME(sc), 721 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 722 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 723 724 /* setup default video mode from devprop (allows PROM override) */ 725 sc->sc_defaultmode = radeonfb_default_mode; 726 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 727 "videomode", &mptr)) { 728 729 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 730 sc->sc_defaultmode = sc->sc_modebuf; 731 } 732 733 /* initialize some basic display parameters */ 734 for (i = 0; i < sc->sc_ndisplays; i++) { 735 struct radeonfb_display *dp = &sc->sc_displays[i]; 736 struct rasops_info *ri; 737 long defattr; 738 struct wsemuldisplaydev_attach_args aa; 739 740 /* 741 * Figure out how many "displays" (desktops) we are going to 742 * support. If more than one, then each CRTC gets its own 743 * programming. 744 * 745 * XXX: this code needs to change to support mergedfb. 746 * XXX: would be nice to allow this to be overridden 747 */ 748 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 749 DPRINTF(("dual crtcs!\n")); 750 dp->rd_ncrtcs = 2; 751 dp->rd_crtcs[0].rc_number = 0; 752 dp->rd_crtcs[1].rc_number = 1; 753 } else { 754 dp->rd_ncrtcs = 1; 755 dp->rd_crtcs[0].rc_number = i; 756 } 757 758 /* set up port pointer */ 759 for (j = 0; j < dp->rd_ncrtcs; j++) { 760 dp->rd_crtcs[j].rc_port = 761 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 762 } 763 764 dp->rd_softc = sc; 765 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 766 dp->rd_bg = WS_DEFAULT_BG; 767 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 768 769 /* for text mode, we pick a resolution that won't 770 * require panning */ 771 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 772 773 aprint_normal("%s: display %d: " 774 "initial virtual resolution %dx%d at %d bpp\n", 775 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 776 777 /* now select the *video mode* that we will use */ 778 for (j = 0; j < dp->rd_ncrtcs; j++) { 779 const struct videomode *vmp; 780 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 781 dp->rd_virtx, dp->rd_virty); 782 783 /* 784 * virtual resolution should be at least as high as 785 * physical 786 */ 787 if (dp->rd_virtx < vmp->hdisplay || 788 dp->rd_virty < vmp->vdisplay) { 789 dp->rd_virtx = vmp->hdisplay; 790 dp->rd_virty = vmp->vdisplay; 791 } 792 793 dp->rd_crtcs[j].rc_videomode = *vmp; 794 printf("%s: port %d: physical %dx%d %dHz\n", 795 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 796 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 797 vmp->htotal), vmp->vtotal)); 798 } 799 800 /* N.B.: radeon wants 64-byte aligned stride */ 801 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 802 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 803 DPRINTF(("stride: %d\n", dp->rd_stride)); 804 805 dp->rd_offset = sc->sc_fboffset * i; 806 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 807 sc->sc_memh) + dp->rd_offset; 808 dp->rd_curoff = sc->sc_fbsize; 809 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 810 811 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 812 813 switch (dp->rd_bpp) { 814 case 8: 815 dp->rd_format = 2; 816 break; 817 case 32: 818 dp->rd_format = 6; 819 break; 820 default: 821 aprint_error("%s: bad depth %d\n", XNAME(sc), 822 dp->rd_bpp); 823 goto error; 824 } 825 826 DPRINTF(("init engine\n")); 827 /* XXX: this seems suspicious - per display engine 828 initialization? */ 829 radeonfb_engine_init(dp); 830 831 /* copy the template into place */ 832 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 833 dp->rd_wsscreens = dp->rd_wsscreens_storage; 834 835 /* and make up the list */ 836 dp->rd_wsscreenlist.nscreens = 1; 837 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 838 839 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 840 &radeonfb_accessops); 841 842 dp->rd_vd.init_screen = radeonfb_init_screen; 843 844 #ifdef RADEONFB_DEBUG 845 dp->rd_virty -= 200; 846 #endif 847 848 dp->rd_console = 0; 849 prop_dictionary_get_bool(device_properties(sc->sc_dev), 850 "is_console", &dp->rd_console); 851 852 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 853 854 855 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 856 dp->rd_console, &defattr); 857 858 ri = &dp->rd_vscreen.scr_ri; 859 860 /* clear the screen */ 861 rasops_unpack_attr(defattr, &fg, &bg, &ul); 862 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 863 ri->ri_devcmap[bg & 0xf]); 864 865 dp->rd_wsscreens->textops = &ri->ri_ops; 866 dp->rd_wsscreens->capabilities = ri->ri_caps; 867 dp->rd_wsscreens->nrows = ri->ri_rows; 868 dp->rd_wsscreens->ncols = ri->ri_cols; 869 870 #ifdef SPLASHSCREEN 871 dp->rd_splash.si_depth = ri->ri_depth; 872 dp->rd_splash.si_bits = ri->ri_bits; 873 dp->rd_splash.si_hwbits = ri->ri_hwbits; 874 dp->rd_splash.si_width = ri->ri_width; 875 dp->rd_splash.si_height = ri->ri_height; 876 dp->rd_splash.si_stride = ri->ri_stride; 877 dp->rd_splash.si_fillrect = NULL; 878 #endif 879 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 880 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 881 dp->rd_gc.gc_rop = RADEON_ROP3_S; 882 dp->rd_gc.gc_blitcookie = dp; 883 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 884 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 885 dp->rd_virtx, 886 ri->ri_font->fontwidth, 887 ri->ri_font->fontheight, 888 defattr); 889 if (dp->rd_console) { 890 891 radeonfb_modeswitch(dp); 892 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 893 defattr); 894 #ifdef SPLASHSCREEN 895 if (splash_render(&dp->rd_splash, 896 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 897 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 898 else 899 #endif 900 vcons_replay_msgbuf(&dp->rd_vscreen); 901 } else { 902 903 /* 904 * since we're not the console we can postpone 905 * the rest until someone actually allocates a 906 * screen for us. but we do clear the screen 907 * at least. 908 */ 909 memset(ri->ri_bits, 0, 1024); 910 911 radeonfb_modeswitch(dp); 912 #ifdef SPLASHSCREEN 913 if (splash_render(&dp->rd_splash, 914 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 915 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 916 #endif 917 } 918 919 aa.console = dp->rd_console; 920 aa.scrdata = &dp->rd_wsscreenlist; 921 aa.accessops = &radeonfb_accessops; 922 aa.accesscookie = &dp->rd_vd; 923 924 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 925 926 radeonfb_blank(dp, 0); 927 928 /* Initialise delayed lvds operations for backlight. */ 929 callout_init(&dp->rd_bl_lvds_co, 0); 930 callout_setfunc(&dp->rd_bl_lvds_co, 931 radeonfb_lvds_callout, dp); 932 dp->rd_bl_on = 1; 933 dp->rd_bl_level = radeonfb_get_backlight(dp); 934 radeonfb_set_backlight(dp, dp->rd_bl_level); 935 } 936 937 /* 938 * if we have console output via firmware like on sparc64 it may 939 * interfere with DAC programming so program the palette again 940 * here after we took over 941 */ 942 radeonfb_init_palette(sc, 0); 943 if (HAS_CRTC2(sc)) { 944 radeonfb_init_palette(sc, 1); 945 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 946 } 947 948 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 949 radeonfb_brightness_up, TRUE); 950 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 951 radeonfb_brightness_down, TRUE); 952 953 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 954 955 PRINTREG(RADEON_CRTC_EXT_CNTL); 956 PRINTREG(RADEON_CRTC_GEN_CNTL); 957 PRINTREG(RADEON_CRTC2_GEN_CNTL); 958 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 959 PRINTREG(RADEON_DAC_CNTL2); 960 961 return; 962 963 error: 964 if (sc->sc_biossz) 965 free(sc->sc_bios, M_DEVBUF); 966 967 if (sc->sc_regsz) 968 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 969 970 if (sc->sc_memsz) 971 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 972 } 973 974 static void 975 radeonfb_map(struct radeonfb_softc *sc) 976 { 977 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 978 &sc->sc_regh) != 0) { 979 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 980 return; 981 } 982 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 983 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 984 sc->sc_memsz = 0; 985 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 986 return; 987 } 988 } 989 990 static void 991 radeonfb_unmap(struct radeonfb_softc *sc) 992 { 993 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 994 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 995 } 996 997 static int 998 radeonfb_drm_print(void *aux, const char *pnp) 999 { 1000 if (pnp) 1001 aprint_normal("drm at %s", pnp); 1002 return (UNCONF); 1003 } 1004 1005 int 1006 radeonfb_ioctl(void *v, void *vs, 1007 unsigned long cmd, void *d, int flag, struct lwp *l) 1008 { 1009 struct vcons_data *vd; 1010 struct radeonfb_display *dp; 1011 struct radeonfb_softc *sc; 1012 struct wsdisplay_param *param; 1013 1014 vd = (struct vcons_data *)v; 1015 dp = (struct radeonfb_display *)vd->cookie; 1016 sc = dp->rd_softc; 1017 1018 switch (cmd) { 1019 case WSDISPLAYIO_GTYPE: 1020 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1021 return 0; 1022 1023 case WSDISPLAYIO_GINFO: 1024 if (vd->active != NULL) { 1025 struct wsdisplay_fbinfo *fb; 1026 fb = (struct wsdisplay_fbinfo *)d; 1027 fb->width = dp->rd_virtx; 1028 fb->height = dp->rd_virty; 1029 fb->depth = dp->rd_bpp; 1030 fb->cmsize = 256; 1031 return 0; 1032 } else 1033 return ENODEV; 1034 case WSDISPLAYIO_GVIDEO: 1035 if (radeonfb_isblank(dp)) 1036 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1037 else 1038 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1039 return 0; 1040 1041 case WSDISPLAYIO_SVIDEO: 1042 radeonfb_blank(dp, 1043 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1044 return 0; 1045 1046 case WSDISPLAYIO_GETCMAP: 1047 #if 0 1048 if (dp->rd_bpp == 8) 1049 return radeonfb_getcmap(sc, 1050 (struct wsdisplay_cmap *)d); 1051 #endif 1052 return EINVAL; 1053 1054 case WSDISPLAYIO_PUTCMAP: 1055 #if 0 1056 if (dp->rd_bpp == 8) 1057 return radeonfb_putcmap(sc, 1058 (struct wsdisplay_cmap *)d); 1059 #endif 1060 return EINVAL; 1061 1062 case WSDISPLAYIO_LINEBYTES: 1063 *(unsigned *)d = dp->rd_stride; 1064 return 0; 1065 1066 case WSDISPLAYIO_SMODE: 1067 if (*(int *)d != dp->rd_wsmode) { 1068 dp->rd_wsmode = *(int *)d; 1069 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1070 (dp->rd_vd.active)) { 1071 radeonfb_map(sc); 1072 radeonfb_engine_init(dp); 1073 glyphcache_wipe(&dp->rd_gc); 1074 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1075 radeonfb_modeswitch(dp); 1076 vcons_redraw_screen(dp->rd_vd.active); 1077 } else { 1078 radeonfb_unmap(sc); 1079 } 1080 } 1081 return 0; 1082 1083 case WSDISPLAYIO_GCURMAX: 1084 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1085 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1086 return 0; 1087 1088 case WSDISPLAYIO_SCURSOR: 1089 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1090 1091 case WSDISPLAYIO_GCURSOR: 1092 return EPASSTHROUGH; 1093 1094 case WSDISPLAYIO_GCURPOS: 1095 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1096 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1097 return 0; 1098 1099 case WSDISPLAYIO_SCURPOS: 1100 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1101 1102 case WSDISPLAYIO_SSPLASH: 1103 #if defined(SPLASHSCREEN) 1104 if (*(int *)d == 1) { 1105 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1106 splash_render(&dp->rd_splash, 1107 SPLASH_F_CENTER|SPLASH_F_FILL); 1108 } else 1109 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1110 return 0; 1111 #else 1112 return ENODEV; 1113 #endif 1114 case WSDISPLAYIO_GETPARAM: 1115 param = (struct wsdisplay_param *)d; 1116 switch (param->param) { 1117 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1118 param->min = 0; 1119 param->max = 255; 1120 param->curval = dp->rd_bl_level; 1121 return 0; 1122 case WSDISPLAYIO_PARAM_BACKLIGHT: 1123 param->min = 0; 1124 param->max = RADEONFB_BACKLIGHT_MAX; 1125 param->curval = dp->rd_bl_on; 1126 return 0; 1127 } 1128 return EPASSTHROUGH; 1129 1130 case WSDISPLAYIO_SETPARAM: 1131 param = (struct wsdisplay_param *)d; 1132 switch (param->param) { 1133 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1134 radeonfb_set_backlight(dp, param->curval); 1135 return 0; 1136 case WSDISPLAYIO_PARAM_BACKLIGHT: 1137 radeonfb_switch_backlight(dp, param->curval); 1138 return 0; 1139 } 1140 return EPASSTHROUGH; 1141 1142 /* PCI config read/write passthrough. */ 1143 case PCI_IOC_CFGREAD: 1144 case PCI_IOC_CFGWRITE: 1145 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1146 1147 case WSDISPLAYIO_GET_BUSID: 1148 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1149 sc->sc_pt, d); 1150 1151 case WSDISPLAYIO_GET_EDID: { 1152 struct wsdisplayio_edid_info *ei = d; 1153 return wsdisplayio_get_edid(sc->sc_dev, ei); 1154 } 1155 1156 default: 1157 return EPASSTHROUGH; 1158 } 1159 } 1160 1161 paddr_t 1162 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1163 { 1164 struct vcons_data *vd; 1165 struct radeonfb_display *dp; 1166 struct radeonfb_softc *sc; 1167 paddr_t pa; 1168 1169 vd = (struct vcons_data *)v; 1170 dp = (struct radeonfb_display *)vd->cookie; 1171 sc = dp->rd_softc; 1172 1173 /* XXX: note that we don't allow mapping of registers right now */ 1174 /* XXX: this means that the XFree86 radeon driver won't work */ 1175 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1176 pa = bus_space_mmap(sc->sc_memt, 1177 sc->sc_memaddr + dp->rd_offset + offset, 0, 1178 prot, BUS_SPACE_MAP_LINEAR); 1179 return pa; 1180 } 1181 1182 #ifdef RADEONFB_MMAP_BARS 1183 /* 1184 * restrict all other mappings to processes with superuser privileges 1185 * or the kernel itself 1186 */ 1187 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1188 NULL, NULL, NULL, NULL) != 0) { 1189 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1190 return -1; 1191 } 1192 1193 if ((offset >= sc->sc_regaddr) && 1194 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1195 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1196 BUS_SPACE_MAP_LINEAR); 1197 } 1198 1199 if ((offset >= sc->sc_memaddr) && 1200 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1201 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1202 BUS_SPACE_MAP_LINEAR); 1203 } 1204 1205 if ((offset >= sc->sc_romaddr) && 1206 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1207 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1208 BUS_SPACE_MAP_LINEAR); 1209 } 1210 1211 #ifdef PCI_MAGIC_IO_RANGE 1212 /* allow mapping of IO space */ 1213 if ((offset >= PCI_MAGIC_IO_RANGE) && 1214 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1215 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1216 0, prot, 0); 1217 return pa; 1218 } 1219 #endif /* PCI_MAGIC_IO_RANGE */ 1220 1221 #endif /* RADEONFB_MMAP_BARS */ 1222 1223 return -1; 1224 } 1225 1226 static void 1227 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1228 { 1229 bus_space_tag_t romt; 1230 bus_space_handle_t romh, biosh; 1231 bus_size_t romsz; 1232 bus_addr_t ptr; 1233 1234 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1235 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1236 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1237 return; 1238 } 1239 1240 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1241 &sc->sc_biossz); 1242 if (sc->sc_biossz == 0) { 1243 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1244 return; 1245 } 1246 1247 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1248 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1249 1250 /* unmap the PCI expansion rom */ 1251 bus_space_unmap(romt, romh, romsz); 1252 1253 /* turn off rom decoder now */ 1254 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1255 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1256 ~PCI_MAPREG_ROM_ENABLE); 1257 1258 ptr = GETBIOS16(sc, 0x48); 1259 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1260 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1261 sc->sc_flags |= RFB_ATOM; 1262 } 1263 1264 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1265 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1266 } 1267 1268 1269 uint32_t 1270 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1271 { 1272 1273 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1274 } 1275 1276 void 1277 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1278 { 1279 1280 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1281 } 1282 1283 void 1284 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1285 { 1286 1287 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1288 } 1289 1290 void 1291 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1292 uint32_t andmask, uint32_t ormask) 1293 { 1294 int s; 1295 uint32_t val; 1296 1297 s = splhigh(); 1298 val = radeonfb_get32(sc, reg); 1299 val = (val & andmask) | ormask; 1300 radeonfb_put32(sc, reg, val); 1301 splx(s); 1302 } 1303 1304 uint32_t 1305 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1306 { 1307 int s; 1308 uint32_t val; 1309 1310 s = splhigh(); 1311 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1312 val = radeonfb_get32(sc, RADEON_MM_DATA); 1313 splx(s); 1314 1315 return (val); 1316 } 1317 1318 void 1319 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1320 { 1321 int s; 1322 1323 s = splhigh(); 1324 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1325 radeonfb_put32(sc, RADEON_MM_DATA, val); 1326 splx(s); 1327 } 1328 1329 void 1330 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1331 uint32_t andmask, uint32_t ormask) 1332 { 1333 int s; 1334 uint32_t val; 1335 1336 s = splhigh(); 1337 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1338 val = radeonfb_get32(sc, RADEON_MM_DATA); 1339 val = (val & andmask) | ormask; 1340 radeonfb_put32(sc, RADEON_MM_DATA, val); 1341 splx(s); 1342 } 1343 1344 uint32_t 1345 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1346 { 1347 int s; 1348 uint32_t val; 1349 1350 s = splhigh(); 1351 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1352 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1353 if (HAS_R300CG(sc)) 1354 radeonfb_r300cg_workaround(sc); 1355 splx(s); 1356 1357 return (val); 1358 } 1359 1360 void 1361 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1362 { 1363 int s; 1364 1365 s = splhigh(); 1366 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1367 RADEON_PLL_WR_EN); 1368 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1369 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1370 splx(s); 1371 } 1372 1373 void 1374 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1375 uint32_t andmask, uint32_t ormask) 1376 { 1377 int s; 1378 uint32_t val; 1379 1380 s = splhigh(); 1381 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1382 RADEON_PLL_WR_EN); 1383 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1384 val = (val & andmask) | ormask; 1385 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1386 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1387 splx(s); 1388 } 1389 1390 int 1391 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1392 { 1393 uint32_t saved; 1394 1395 saved = GET32(sc, reg); 1396 PUT32(sc, reg, v); 1397 if (GET32(sc, reg) != v) { 1398 return -1; 1399 } 1400 PUT32(sc, reg, saved); 1401 return 0; 1402 } 1403 1404 uintmax_t 1405 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1406 uintmax_t defval) 1407 { 1408 prop_number_t pn; 1409 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1410 if (pn == NULL) { 1411 return defval; 1412 } 1413 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1414 return (prop_number_integer_value(pn)); 1415 } 1416 1417 int 1418 radeonfb_getclocks(struct radeonfb_softc *sc) 1419 { 1420 bus_addr_t ptr; 1421 int refclk = 0; 1422 int refdiv = 0; 1423 int minpll = 0; 1424 int maxpll = 0; 1425 1426 /* load initial property values if port/board provides them */ 1427 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1428 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1429 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1430 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1431 1432 if (refclk && refdiv && minpll && maxpll) 1433 goto dontprobe; 1434 1435 if (!sc->sc_biossz) { 1436 /* no BIOS */ 1437 aprint_verbose("%s: No video BIOS, using default clocks\n", 1438 XNAME(sc)); 1439 if (IS_IGP(sc)) 1440 refclk = refclk ? refclk : 1432; 1441 else 1442 refclk = refclk ? refclk : 2700; 1443 refdiv = refdiv ? refdiv : 12; 1444 minpll = minpll ? minpll : 12500; 1445 maxpll = maxpll ? maxpll : 35000; 1446 } else if (IS_ATOM(sc)) { 1447 /* ATOM BIOS */ 1448 ptr = GETBIOS16(sc, 0x48); 1449 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1450 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1451 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1452 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1453 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1454 /* 1455 * ATOM BIOS doesn't supply a reference divider, so we 1456 * have to probe for it. 1457 */ 1458 if (refdiv < 2) 1459 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1460 RADEON_PPLL_REF_DIV_MASK; 1461 /* 1462 * if probe is zero, just assume one that should work 1463 * for most parts 1464 */ 1465 if (refdiv < 2) 1466 refdiv = 12; 1467 1468 } else { 1469 /* Legacy BIOS */ 1470 ptr = GETBIOS16(sc, 0x48); 1471 ptr = GETBIOS16(sc, ptr + 0x30); 1472 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1473 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1474 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1475 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1476 } 1477 1478 1479 dontprobe: 1480 sc->sc_refclk = refclk * 10; 1481 sc->sc_refdiv = refdiv; 1482 sc->sc_minpll = minpll * 10; 1483 sc->sc_maxpll = maxpll * 10; 1484 return 0; 1485 } 1486 1487 int 1488 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1489 uint32_t *postdivbit, uint32_t *feedbackdiv) 1490 { 1491 int i; 1492 uint32_t outfreq; 1493 int div; 1494 1495 DPRINTF(("dot clock: %u\n", dotclock)); 1496 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1497 outfreq = div * dotclock; 1498 if ((outfreq >= sc->sc_minpll) && 1499 (outfreq <= sc->sc_maxpll)) { 1500 DPRINTF(("outfreq: %u\n", outfreq)); 1501 *postdivbit = 1502 ((uint32_t)radeonfb_dividers[i].mask << 16); 1503 DPRINTF(("post divider: %d (mask %x)\n", div, 1504 *postdivbit)); 1505 break; 1506 } 1507 } 1508 1509 if (div == 0) 1510 return 1; 1511 1512 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1513 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1514 return 0; 1515 } 1516 1517 #if 0 1518 #ifdef RADEONFB_DEBUG 1519 static void 1520 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1521 { 1522 char asc[17]; 1523 unsigned ptr = (unsigned)buffer; 1524 char *start = (char *)(ptr & ~0xf); 1525 char *end = (char *)(ptr + size); 1526 1527 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1528 1529 if (pfx == NULL) { 1530 pfx = ""; 1531 } 1532 1533 while (start < end) { 1534 unsigned offset = (unsigned)start & 0xf; 1535 if (offset == 0) { 1536 printf("%s%x: ", pfx, (unsigned)start); 1537 } 1538 if (((unsigned)start < ptr) || 1539 ((unsigned)start >= (ptr + size))) { 1540 printf(" "); 1541 asc[offset] = ' '; 1542 } else { 1543 printf("%02x", *(unsigned char *)start); 1544 if ((*start >= ' ') && (*start <= '~')) { 1545 asc[offset] = *start; 1546 } else { 1547 asc[offset] = '.'; 1548 } 1549 } 1550 asc[offset + 1] = 0; 1551 if (offset % 2) { 1552 printf(" "); 1553 } 1554 if (offset == 15) { 1555 printf(" %s\n", asc); 1556 } 1557 start++; 1558 } 1559 } 1560 #endif 1561 #endif 1562 1563 int 1564 radeonfb_getconnectors(struct radeonfb_softc *sc) 1565 { 1566 int i; 1567 int found = 0; 1568 1569 for (i = 0; i < 2; i++) { 1570 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1571 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1572 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1573 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1574 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1575 } 1576 1577 /* 1578 * This logic is borrowed from Xorg's radeon driver. 1579 */ 1580 if (!sc->sc_biossz) 1581 goto nobios; 1582 1583 if (IS_ATOM(sc)) { 1584 /* not done yet */ 1585 } else { 1586 uint16_t ptr; 1587 int port = 0; 1588 1589 ptr = GETBIOS16(sc, 0x48); 1590 ptr = GETBIOS16(sc, ptr + 0x50); 1591 for (i = 1; i < 4; i++) { 1592 uint16_t entry; 1593 uint8_t conn, ddc, dac, tmds; 1594 1595 /* 1596 * Parse the connector table. From reading the code, 1597 * it appears to made up of 16-bit entries for each 1598 * connector. The 16-bits are defined as: 1599 * 1600 * bits 12-15 - connector type (0 == end of table) 1601 * bits 8-11 - DDC type 1602 * bits 5-7 - ??? 1603 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1604 * bits 1-3 - ??? 1605 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1606 */ 1607 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1608 break; 1609 entry = GETBIOS16(sc, ptr + i * 2); 1610 1611 conn = (entry >> 12) & 0xf; 1612 ddc = (entry >> 8) & 0xf; 1613 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1614 RADEON_DAC_PRIMARY; 1615 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1616 RADEON_TMDS_INT; 1617 1618 if (conn == RADEON_CONN_NONE) 1619 continue; /* no connector */ 1620 1621 if ((found > 0) && 1622 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1623 /* duplicate entry for same connector */ 1624 continue; 1625 } 1626 1627 /* internal DDC_DVI port gets priority */ 1628 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1629 port = 0; 1630 else 1631 port = 1; 1632 1633 sc->sc_ports[port].rp_ddc_type = 1634 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1635 sc->sc_ports[port].rp_dac_type = dac; 1636 sc->sc_ports[port].rp_conn_type = 1637 min(conn, RADEON_CONN_UNSUPPORTED) ; 1638 1639 sc->sc_ports[port].rp_tmds_type = tmds; 1640 1641 if ((conn != RADEON_CONN_DVI_I) && 1642 (conn != RADEON_CONN_DVI_D) && 1643 (tmds == RADEON_TMDS_INT)) 1644 sc->sc_ports[port].rp_tmds_type = 1645 RADEON_TMDS_UNKNOWN; 1646 1647 found += (port + 1); 1648 } 1649 } 1650 1651 nobios: 1652 if (!found) { 1653 DPRINTF(("No connector info in BIOS!\n")); 1654 /* default, port 0 = internal TMDS, port 1 = CRT */ 1655 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1656 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1657 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1658 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1659 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1660 1661 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1662 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1663 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1664 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1665 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1666 } 1667 1668 /* 1669 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1670 * these chips should use TVDAC for the VGA port. 1671 */ 1672 if (HAS_SDAC(sc)) { 1673 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1674 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1675 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1676 } else { 1677 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1678 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1679 } 1680 } else if (!HAS_CRTC2(sc)) { 1681 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1682 } 1683 1684 for (i = 0; i < 2; i++) { 1685 char edid[128]; 1686 uint8_t ddc; 1687 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1688 prop_data_t edid_data; 1689 1690 DPRINTF(("Port #%d:\n", i)); 1691 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1692 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1693 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1694 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1695 1696 sc->sc_ports[i].rp_edid_valid = 0; 1697 /* first look for static EDID data */ 1698 if ((edid_data = prop_dictionary_get(device_properties( 1699 sc->sc_dev), "EDID")) != NULL) { 1700 1701 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1702 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1703 if (edid_parse(edid, eip) == 0) { 1704 1705 sc->sc_ports[i].rp_edid_valid = 1; 1706 } 1707 } 1708 /* if we didn't find any we'll try to talk to the monitor */ 1709 if (sc->sc_ports[i].rp_edid_valid != 1) { 1710 1711 ddc = sc->sc_ports[i].rp_ddc_type; 1712 if (ddc != RADEON_DDC_NONE) { 1713 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1714 == 0) && (edid_parse(edid, eip) == 0)) { 1715 1716 sc->sc_ports[i].rp_edid_valid = 1; 1717 #ifdef RADEONFB_DEBUG 1718 edid_print(eip); 1719 #endif 1720 } 1721 } 1722 } 1723 } 1724 1725 return found; 1726 } 1727 1728 int 1729 radeonfb_gettmds(struct radeonfb_softc *sc) 1730 { 1731 int i; 1732 1733 if (!sc->sc_biossz) { 1734 goto nobios; 1735 } 1736 1737 if (IS_ATOM(sc)) { 1738 /* XXX: not done yet */ 1739 } else { 1740 uint16_t ptr; 1741 int n; 1742 1743 ptr = GETBIOS16(sc, 0x48); 1744 ptr = GETBIOS16(sc, ptr + 0x34); 1745 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1746 if (GETBIOS8(sc, ptr) == 3) { 1747 /* revision three table */ 1748 n = GETBIOS8(sc, ptr + 5) + 1; 1749 n = min(n, 4); 1750 1751 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1752 for (i = 0; i < n; i++) { 1753 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1754 ptr + i * 10 + 8); 1755 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1756 ptr + i * 10 + 0x10); 1757 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1758 sc->sc_tmds_pll[i].rtp_freq, 1759 sc->sc_tmds_pll[i].rtp_pll)); 1760 } 1761 return 0; 1762 } 1763 } 1764 1765 nobios: 1766 DPRINTF(("no suitable DFP table present\n")); 1767 for (i = 0; 1768 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1769 i++) { 1770 int j; 1771 1772 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1773 continue; 1774 1775 for (j = 0; j < 4; j++) { 1776 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1777 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1778 sc->sc_tmds_pll[j].rtp_freq, 1779 sc->sc_tmds_pll[j].rtp_pll)); 1780 } 1781 return 0; 1782 } 1783 1784 return -1; 1785 } 1786 1787 const struct videomode * 1788 radeonfb_modelookup(const char *name) 1789 { 1790 int i; 1791 1792 for (i = 0; i < videomode_count; i++) 1793 if (!strcmp(name, videomode_list[i].name)) 1794 return &videomode_list[i]; 1795 1796 return NULL; 1797 } 1798 1799 void 1800 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1801 { 1802 if (crtc) { 1803 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1804 RADEON_P2PLL_ATOMIC_UPDATE_R); 1805 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1806 } else { 1807 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1808 RADEON_PPLL_ATOMIC_UPDATE_R); 1809 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1810 } 1811 } 1812 1813 void 1814 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1815 { 1816 int i; 1817 1818 for (i = 10000; i; i--) { 1819 if (crtc) { 1820 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1821 RADEON_P2PLL_ATOMIC_UPDATE_R) 1822 break; 1823 } else { 1824 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1825 RADEON_PPLL_ATOMIC_UPDATE_R) 1826 break; 1827 } 1828 } 1829 } 1830 1831 void 1832 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1833 { 1834 uint32_t pbit = 0; 1835 uint32_t feed = 0; 1836 uint32_t data; 1837 #if 1 1838 int i; 1839 #endif 1840 1841 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1842 1843 if (crtc == 0) { 1844 1845 /* XXXX: mobility workaround missing */ 1846 /* XXXX: R300 stuff missing */ 1847 1848 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1849 RADEON_VCLK_SRC_SEL_CPUCLK, 1850 ~RADEON_VCLK_SRC_SEL_MASK); 1851 1852 /* put vclk into reset, use atomic updates */ 1853 SETPLL(sc, RADEON_PPLL_CNTL, 1854 RADEON_PPLL_REFCLK_SEL | 1855 RADEON_PPLL_FBCLK_SEL | 1856 RADEON_PPLL_RESET | 1857 RADEON_PPLL_ATOMIC_UPDATE_EN | 1858 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1859 1860 /* select clock 3 */ 1861 #if 0 1862 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1863 ~RADEON_PLL_DIV_SEL); 1864 #else 1865 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1866 ~RADEON_PLL_DIV_SEL); 1867 #endif 1868 1869 /* XXX: R300 family -- program divider differently? */ 1870 1871 /* program reference divider */ 1872 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1873 ~RADEON_PPLL_REF_DIV_MASK); 1874 PRINTPLL(RADEON_PPLL_REF_DIV); 1875 1876 #if 0 1877 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1878 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1879 RADEON_PPLL_POST3_DIV_MASK); 1880 data |= pbit; 1881 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1882 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1883 #else 1884 for (i = 0; i < 4; i++) { 1885 } 1886 #endif 1887 1888 /* use the atomic update */ 1889 radeonfb_pllwriteupdate(sc, crtc); 1890 1891 /* and wait for it to complete */ 1892 radeonfb_pllwaitatomicread(sc, crtc); 1893 1894 /* program HTOTAL (why?) */ 1895 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1896 1897 /* drop reset */ 1898 CLRPLL(sc, RADEON_PPLL_CNTL, 1899 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1900 RADEON_PPLL_ATOMIC_UPDATE_EN | 1901 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1902 1903 PRINTPLL(RADEON_PPLL_CNTL); 1904 1905 /* give clock time to lock */ 1906 delay(50000); 1907 1908 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1909 RADEON_VCLK_SRC_SEL_PPLLCLK, 1910 ~RADEON_VCLK_SRC_SEL_MASK); 1911 1912 } else { 1913 1914 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1915 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1916 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1917 1918 /* put vclk into reset, use atomic updates */ 1919 SETPLL(sc, RADEON_P2PLL_CNTL, 1920 RADEON_P2PLL_RESET | 1921 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1922 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1923 1924 /* XXX: R300 family -- program divider differently? */ 1925 1926 /* program reference divider */ 1927 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1928 ~RADEON_P2PLL_REF_DIV_MASK); 1929 1930 /* program feedback and post dividers */ 1931 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1932 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1933 RADEON_P2PLL_POST0_DIV_MASK); 1934 data |= pbit; 1935 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1936 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1937 1938 /* use the atomic update */ 1939 radeonfb_pllwriteupdate(sc, crtc); 1940 1941 /* and wait for it to complete */ 1942 radeonfb_pllwaitatomicread(sc, crtc); 1943 1944 /* program HTOTAL (why?) */ 1945 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1946 1947 /* drop reset */ 1948 CLRPLL(sc, RADEON_P2PLL_CNTL, 1949 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1950 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1951 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1952 1953 /* allow time for clock to lock */ 1954 delay(50000); 1955 1956 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1957 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1958 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1959 } 1960 PRINTREG(RADEON_CRTC_MORE_CNTL); 1961 } 1962 1963 void 1964 radeonfb_modeswitch(struct radeonfb_display *dp) 1965 { 1966 struct radeonfb_softc *sc = dp->rd_softc; 1967 int i; 1968 1969 /* blank the display while we switch modes */ 1970 radeonfb_blank(dp, 1); 1971 1972 #if 0 1973 SET32(sc, RADEON_CRTC_EXT_CNTL, 1974 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1975 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1976 #endif 1977 1978 /* these registers might get in the way... */ 1979 PUT32(sc, RADEON_OVR_CLR, 0); 1980 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1981 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1982 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1983 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1984 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1985 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1986 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1987 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1988 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1989 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1990 1991 for (i = 0; i < dp->rd_ncrtcs; i++) 1992 radeonfb_setcrtc(dp, i); 1993 1994 /* activate the display */ 1995 radeonfb_blank(dp, 0); 1996 } 1997 1998 void 1999 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2000 { 2001 int crtc; 2002 struct videomode *mode; 2003 struct radeonfb_softc *sc; 2004 struct radeonfb_crtc *cp; 2005 uint32_t v; 2006 uint32_t gencntl; 2007 uint32_t htotaldisp; 2008 uint32_t hsyncstrt; 2009 uint32_t vtotaldisp; 2010 uint32_t vsyncstrt; 2011 uint32_t fphsyncstrt; 2012 uint32_t fpvsyncstrt; 2013 uint32_t fphtotaldisp; 2014 uint32_t fpvtotaldisp; 2015 uint32_t pitch; 2016 2017 sc = dp->rd_softc; 2018 cp = &dp->rd_crtcs[index]; 2019 crtc = cp->rc_number; 2020 mode = &cp->rc_videomode; 2021 2022 #if 1 2023 pitch = dp->rd_stride / dp->rd_bpp; 2024 #else 2025 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2026 (sc->sc_maxbpp * 8)); 2027 #endif 2028 switch (crtc) { 2029 case 0: 2030 gencntl = RADEON_CRTC_GEN_CNTL; 2031 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2032 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2033 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2034 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2035 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2036 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2037 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2038 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2039 break; 2040 case 1: 2041 gencntl = RADEON_CRTC2_GEN_CNTL; 2042 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2043 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2044 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2045 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2046 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2047 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2048 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2049 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2050 break; 2051 default: 2052 panic("Bad CRTC!"); 2053 break; 2054 } 2055 2056 /* 2057 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2058 */ 2059 /* only bother with 32bpp and 8bpp */ 2060 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2061 2062 if (crtc == 1) { 2063 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2064 } else { 2065 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2066 } 2067 2068 if (mode->flags & VID_DBLSCAN) 2069 v |= RADEON_CRTC2_DBL_SCAN_EN; 2070 2071 if (mode->flags & VID_INTERLACE) 2072 v |= RADEON_CRTC2_INTERLACE_EN; 2073 2074 if (mode->flags & VID_CSYNC) { 2075 v |= RADEON_CRTC2_CSYNC_EN; 2076 if (crtc == 1) 2077 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2078 } 2079 2080 PUT32(sc, gencntl, v); 2081 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2082 2083 /* 2084 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2085 */ 2086 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2087 if (crtc == 0) { 2088 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2089 RADEON_CRTC_DISPLAY_DIS); 2090 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2091 if (mode->flags & VID_CSYNC) 2092 v |= RADEON_CRTC_VSYNC_TRISTAT; 2093 } 2094 /* unconditional turn on CRT, in case first CRTC is DFP */ 2095 v |= RADEON_CRTC_CRT_ON; 2096 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2097 PRINTREG(RADEON_CRTC_EXT_CNTL); 2098 2099 /* 2100 * H_TOTAL_DISP 2101 */ 2102 v = ((mode->hdisplay / 8) - 1) << 16; 2103 v |= (mode->htotal / 8) - 1; 2104 PUT32(sc, htotaldisp, v); 2105 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2106 PUT32(sc, fphtotaldisp, v); 2107 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2108 2109 /* 2110 * H_SYNC_STRT_WID 2111 */ 2112 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2113 v |= mode->hsync_start; 2114 if (mode->flags & VID_NHSYNC) 2115 v |= RADEON_CRTC_H_SYNC_POL; 2116 PUT32(sc, hsyncstrt, v); 2117 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2118 PUT32(sc, fphsyncstrt, v); 2119 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2120 2121 /* 2122 * V_TOTAL_DISP 2123 */ 2124 v = ((mode->vdisplay - 1) << 16); 2125 v |= (mode->vtotal - 1); 2126 PUT32(sc, vtotaldisp, v); 2127 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2128 PUT32(sc, fpvtotaldisp, v); 2129 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2130 2131 /* 2132 * V_SYNC_STRT_WID 2133 */ 2134 v = ((mode->vsync_end - mode->vsync_start) << 16); 2135 v |= (mode->vsync_start - 1); 2136 if (mode->flags & VID_NVSYNC) 2137 v |= RADEON_CRTC_V_SYNC_POL; 2138 PUT32(sc, vsyncstrt, v); 2139 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2140 PUT32(sc, fpvsyncstrt, v); 2141 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2142 2143 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2144 2145 switch (crtc) { 2146 case 0: 2147 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2148 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2149 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2150 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2151 2152 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2153 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2154 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2155 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2156 PRINTREG(RADEON_CRTC_EXT_CNTL); 2157 PRINTREG(RADEON_CRTC_GEN_CNTL); 2158 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2159 break; 2160 2161 case 1: 2162 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2163 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2164 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2165 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2166 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2167 RADEON_CRTC2_VSYNC_DIS | 2168 RADEON_CRTC2_HSYNC_DIS | 2169 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2170 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2171 break; 2172 } 2173 } 2174 2175 int 2176 radeonfb_isblank(struct radeonfb_display *dp) 2177 { 2178 uint32_t reg, mask; 2179 2180 if (dp->rd_crtcs[0].rc_number) { 2181 reg = RADEON_CRTC2_GEN_CNTL; 2182 mask = RADEON_CRTC2_DISP_DIS; 2183 } else { 2184 reg = RADEON_CRTC_EXT_CNTL; 2185 mask = RADEON_CRTC_DISPLAY_DIS; 2186 } 2187 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2188 } 2189 2190 void 2191 radeonfb_blank(struct radeonfb_display *dp, int blank) 2192 { 2193 struct radeonfb_softc *sc = dp->rd_softc; 2194 uint32_t reg, mask; 2195 uint32_t fpreg, fpval; 2196 int i; 2197 2198 for (i = 0; i < dp->rd_ncrtcs; i++) { 2199 2200 if (dp->rd_crtcs[i].rc_number) { 2201 reg = RADEON_CRTC2_GEN_CNTL; 2202 mask = RADEON_CRTC2_DISP_DIS; 2203 fpreg = RADEON_FP2_GEN_CNTL; 2204 fpval = RADEON_FP2_ON; 2205 } else { 2206 reg = RADEON_CRTC_EXT_CNTL; 2207 mask = RADEON_CRTC_DISPLAY_DIS; 2208 fpreg = RADEON_FP_GEN_CNTL; 2209 fpval = RADEON_FP_FPON; 2210 } 2211 2212 if (blank) { 2213 SET32(sc, reg, mask); 2214 CLR32(sc, fpreg, fpval); 2215 } else { 2216 CLR32(sc, reg, mask); 2217 SET32(sc, fpreg, fpval); 2218 } 2219 } 2220 PRINTREG(RADEON_FP_GEN_CNTL); 2221 PRINTREG(RADEON_FP2_GEN_CNTL); 2222 } 2223 2224 void 2225 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2226 long *defattr) 2227 { 2228 struct radeonfb_display *dp = cookie; 2229 struct rasops_info *ri = &scr->scr_ri; 2230 2231 /* initialize font subsystem */ 2232 wsfont_init(); 2233 2234 DPRINTF(("init screen called, existing %d\n", existing)); 2235 2236 ri->ri_depth = dp->rd_bpp; 2237 ri->ri_width = dp->rd_virtx; 2238 ri->ri_height = dp->rd_virty; 2239 ri->ri_stride = dp->rd_stride; 2240 ri->ri_flg = RI_CENTER; 2241 switch (ri->ri_depth) { 2242 case 8: 2243 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2244 break; 2245 case 32: 2246 ri->ri_flg |= RI_ENABLE_ALPHA; 2247 /* we run radeons in RGB even on SPARC hardware */ 2248 ri->ri_rnum = 8; 2249 ri->ri_gnum = 8; 2250 ri->ri_bnum = 8; 2251 ri->ri_rpos = 16; 2252 ri->ri_gpos = 8; 2253 ri->ri_bpos = 0; 2254 break; 2255 } 2256 2257 ri->ri_bits = (void *)dp->rd_fbptr; 2258 2259 #ifdef VCONS_DRAW_INTR 2260 scr->scr_flags |= VCONS_DONT_READ; 2261 #endif 2262 2263 if (existing) { 2264 ri->ri_flg |= RI_CLEAR; 2265 2266 /* start a modeswitch now */ 2267 radeonfb_modeswitch(dp); 2268 } 2269 2270 /* 2271 * XXX: font selection should be based on properties, with some 2272 * normal/reasonable default. 2273 */ 2274 2275 /* initialize and look for an initial font */ 2276 rasops_init(ri, 0, 0); 2277 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2278 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2279 2280 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2281 dp->rd_virtx / ri->ri_font->fontwidth); 2282 2283 /* enable acceleration */ 2284 dp->rd_putchar = ri->ri_ops.putchar; 2285 ri->ri_ops.copyrows = radeonfb_copyrows; 2286 ri->ri_ops.copycols = radeonfb_copycols; 2287 ri->ri_ops.eraserows = radeonfb_eraserows; 2288 ri->ri_ops.erasecols = radeonfb_erasecols; 2289 /* pick a putchar method based on font and Radeon model */ 2290 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2291 /* got a bitmap font */ 2292 if (IS_R300(dp->rd_softc)) { 2293 /* 2294 * radeonfb_putchar() doesn't work right on some R3xx 2295 * so we use software drawing here, the wrapper just 2296 * makes sure the engine is idle before scribbling 2297 * into vram 2298 */ 2299 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2300 } else { 2301 ri->ri_ops.putchar = radeonfb_putchar; 2302 } 2303 } else { 2304 /* got an alpha font */ 2305 switch(ri->ri_depth) { 2306 case 32: 2307 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2308 break; 2309 case 8: 2310 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2311 break; 2312 default: 2313 /* XXX this should never happen */ 2314 panic("%s: depth is not 8 or 32 but we got an" \ 2315 " alpha font?!", __func__); 2316 } 2317 } 2318 ri->ri_ops.cursor = radeonfb_cursor; 2319 } 2320 2321 void 2322 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2323 { 2324 uint32_t gen, ext, gen2 = 0; 2325 uint32_t agploc, aperbase, apersize, mcfbloc; 2326 2327 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2328 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2329 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2330 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2331 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2332 2333 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2334 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2335 #if 0 2336 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2337 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2338 #endif 2339 2340 if (HAS_CRTC2(sc)) { 2341 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2342 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2343 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2344 } 2345 2346 delay(100000); 2347 2348 mcfbloc = (aperbase >> 16) | 2349 ((aperbase + (apersize - 1)) & 0xffff0000); 2350 2351 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2352 sc->sc_memsz = apersize; 2353 2354 if (((agploc & 0xffff) << 16) != 2355 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2356 agploc = mcfbloc & 0xffff0000U; 2357 agploc |= ((agploc + 0x10000) >> 16); 2358 } 2359 2360 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2361 2362 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2363 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2364 2365 DPRINTF(("aperbase = %u\n", aperbase)); 2366 PRINTREG(RADEON_MC_FB_LOCATION); 2367 PRINTREG(RADEON_MC_AGP_LOCATION); 2368 2369 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2370 2371 if (HAS_CRTC2(sc)) 2372 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2373 2374 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2375 2376 #if 0 2377 /* XXX: what is this AGP garbage? :-) */ 2378 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2379 #endif 2380 2381 delay(100000); 2382 2383 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2384 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2385 2386 if (HAS_CRTC2(sc)) 2387 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2388 } 2389 2390 void 2391 radeonfb_init_misc(struct radeonfb_softc *sc) 2392 { 2393 PUT32(sc, RADEON_BUS_CNTL, 2394 RADEON_BUS_MASTER_DIS | 2395 RADEON_BUS_PREFETCH_MODE_ACT | 2396 RADEON_BUS_PCI_READ_RETRY_EN | 2397 RADEON_BUS_PCI_WRT_RETRY_EN | 2398 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2399 RADEON_BUS_MSTR_RD_MULT | 2400 RADEON_BUS_MSTR_RD_LINE | 2401 RADEON_BUS_RD_DISCARD_EN | 2402 RADEON_BUS_MSTR_DISCONNECT_EN | 2403 RADEON_BUS_READ_BURST); 2404 2405 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2406 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2407 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2408 PUT32(sc, RADEON_RBBM_CNTL, 2409 (3 << RADEON_RB_SETTLE_SHIFT) | 2410 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2411 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2412 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2413 2414 /* XXX: figure out what these mean! */ 2415 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2416 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2417 #if 0 2418 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2419 #endif 2420 2421 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2422 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2423 } 2424 2425 /* 2426 * This loads a linear color map for true color. 2427 */ 2428 void 2429 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2430 { 2431 int i; 2432 uint32_t vclk; 2433 2434 #define DAC_WIDTH ((1 << 10) - 1) 2435 #define CLUT_WIDTH ((1 << 8) - 1) 2436 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2437 2438 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2439 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2440 2441 if (crtc) 2442 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2443 else 2444 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2445 2446 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2447 if (sc->sc_displays[crtc].rd_bpp == 0) 2448 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2449 2450 if (sc->sc_displays[crtc].rd_bpp == 8) { 2451 /* ANSI palette */ 2452 int j = 0; 2453 uint32_t tmp, r, g, b; 2454 2455 for (i = 0; i <= CLUT_WIDTH; ++i) { 2456 tmp = i & 0xe0; 2457 /* 2458 * replicate bits so 0xe0 maps to a red value of 0xff 2459 * in order to make white look actually white 2460 */ 2461 tmp |= (tmp >> 3) | (tmp >> 6); 2462 r = tmp; 2463 2464 tmp = (i & 0x1c) << 3; 2465 tmp |= (tmp >> 3) | (tmp >> 6); 2466 g = tmp; 2467 2468 tmp = (i & 0x03) << 6; 2469 tmp |= tmp >> 2; 2470 tmp |= tmp >> 4; 2471 b = tmp; 2472 PUT32(sc, RADEON_PALETTE_30_DATA, 2473 (r << 22) | 2474 (g << 12) | 2475 (b << 2)); 2476 j += 3; 2477 } 2478 } else { 2479 /* linear ramp */ 2480 for (i = 0; i <= CLUT_WIDTH; ++i) { 2481 PUT32(sc, RADEON_PALETTE_30_DATA, 2482 (CLUT_COLOR(i) << 10) | 2483 (CLUT_COLOR(i) << 20) | 2484 (CLUT_COLOR(i))); 2485 } 2486 } 2487 2488 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2489 PRINTREG(RADEON_DAC_CNTL2); 2490 2491 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2492 } 2493 2494 /* 2495 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2496 */ 2497 void 2498 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2499 { 2500 uint32_t tmp, save; 2501 2502 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2503 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2504 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2505 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2506 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2507 } 2508 2509 /* 2510 * Acceleration entry points. 2511 */ 2512 2513 /* this one draws characters using bitmap fonts */ 2514 static void 2515 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2516 { 2517 struct rasops_info *ri = cookie; 2518 struct vcons_screen *scr = ri->ri_hw; 2519 struct radeonfb_display *dp = scr->scr_cookie; 2520 struct radeonfb_softc *sc = dp->rd_softc; 2521 struct wsdisplay_font *font = PICK_FONT(ri, c); 2522 uint32_t w, h; 2523 int xd, yd, offset, i; 2524 uint32_t bg, fg, gmc; 2525 uint32_t reg; 2526 uint8_t *data8; 2527 uint16_t *data16; 2528 void *data; 2529 2530 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2531 return; 2532 2533 if (!CHAR_IN_FONT(c, font)) 2534 return; 2535 2536 w = font->fontwidth; 2537 h = font->fontheight; 2538 2539 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2540 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2541 2542 xd = ri->ri_xorigin + col * w; 2543 yd = ri->ri_yorigin + row * h; 2544 2545 if (c == 0x20) { 2546 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2547 return; 2548 } 2549 data = WSFONT_GLYPH(c, font); 2550 2551 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2552 2553 radeonfb_wait_fifo(sc, 9); 2554 2555 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2556 RADEON_GMC_BRUSH_NONE | 2557 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2558 RADEON_GMC_DST_CLIPPING | 2559 RADEON_ROP3_S | 2560 RADEON_DP_SRC_SOURCE_HOST_DATA | 2561 RADEON_GMC_CLR_CMP_CNTL_DIS | 2562 RADEON_GMC_WR_MSK_DIS | 2563 gmc); 2564 2565 PUT32(sc, RADEON_SC_LEFT, xd); 2566 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2567 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2568 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2569 PUT32(sc, RADEON_DP_CNTL, 2570 RADEON_DST_X_LEFT_TO_RIGHT | 2571 RADEON_DST_Y_TOP_TO_BOTTOM); 2572 2573 PUT32(sc, RADEON_SRC_X_Y, 0); 2574 offset = 32 - (font->stride << 3); 2575 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2576 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2577 2578 radeonfb_wait_fifo(sc, h); 2579 switch (font->stride) { 2580 case 1: { 2581 data8 = data; 2582 for (i = 0; i < h; i++) { 2583 reg = *data8; 2584 #if BYTE_ORDER == LITTLE_ENDIAN 2585 reg = reg << 24; 2586 #endif 2587 bus_space_write_stream_4(sc->sc_regt, 2588 sc->sc_regh, RADEON_HOST_DATA0, reg); 2589 data8++; 2590 } 2591 break; 2592 } 2593 case 2: { 2594 data16 = data; 2595 for (i = 0; i < h; i++) { 2596 reg = *data16; 2597 #if BYTE_ORDER == LITTLE_ENDIAN 2598 reg = reg << 16; 2599 #endif 2600 bus_space_write_stream_4(sc->sc_regt, 2601 sc->sc_regh, RADEON_HOST_DATA0, reg); 2602 data16++; 2603 } 2604 break; 2605 } 2606 } 2607 if (attr & 1) 2608 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2609 } 2610 2611 /* ... while this one is for anti-aliased ones */ 2612 static void 2613 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2614 { 2615 struct rasops_info *ri = cookie; 2616 struct vcons_screen *scr = ri->ri_hw; 2617 struct radeonfb_display *dp = scr->scr_cookie; 2618 struct radeonfb_softc *sc = dp->rd_softc; 2619 struct wsdisplay_font *font = PICK_FONT(ri, c); 2620 uint32_t bg, fg, gmc; 2621 uint8_t *data; 2622 int w, h, xd, yd; 2623 int i, r, g, b, aval; 2624 int rf, gf, bf, rb, gb, bb; 2625 uint32_t pixel; 2626 int rv; 2627 2628 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2629 return; 2630 2631 if (!CHAR_IN_FONT(c, font)) 2632 return; 2633 2634 w = font->fontwidth; 2635 h = font->fontheight; 2636 2637 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2638 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2639 2640 xd = ri->ri_xorigin + col * w; 2641 yd = ri->ri_yorigin + row * h; 2642 2643 if (c == 0x20) { 2644 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2645 if (attr & 1) 2646 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2647 return; 2648 } 2649 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2650 if (rv == GC_OK) 2651 return; 2652 2653 data = WSFONT_GLYPH(c, font); 2654 2655 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2656 2657 radeonfb_wait_fifo(sc, 5); 2658 2659 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2660 RADEON_GMC_BRUSH_NONE | 2661 RADEON_GMC_SRC_DATATYPE_COLOR | 2662 RADEON_ROP3_S | 2663 RADEON_DP_SRC_SOURCE_HOST_DATA | 2664 RADEON_GMC_CLR_CMP_CNTL_DIS | 2665 RADEON_GMC_WR_MSK_DIS | 2666 gmc); 2667 2668 PUT32(sc, RADEON_DP_CNTL, 2669 RADEON_DST_X_LEFT_TO_RIGHT | 2670 RADEON_DST_Y_TOP_TO_BOTTOM); 2671 2672 PUT32(sc, RADEON_SRC_X_Y, 0); 2673 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2674 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2675 2676 rf = (fg >> 16) & 0xff; 2677 rb = (bg >> 16) & 0xff; 2678 gf = (fg >> 8) & 0xff; 2679 gb = (bg >> 8) & 0xff; 2680 bf = fg & 0xff; 2681 bb = bg & 0xff; 2682 2683 /* 2684 * I doubt we can upload data faster than even the slowest Radeon 2685 * could process them, especially when doing the alpha blending stuff 2686 * along the way, so just make sure there's some room in the FIFO and 2687 * then hammer away 2688 * As it turns out we can, so make periodic stops to let the FIFO 2689 * drain. 2690 */ 2691 radeonfb_wait_fifo(sc, 20); 2692 for (i = 0; i < ri->ri_fontscale; i++) { 2693 aval = *data; 2694 data++; 2695 if (aval == 0) { 2696 pixel = bg; 2697 } else if (aval == 255) { 2698 pixel = fg; 2699 } else { 2700 r = aval * rf + (255 - aval) * rb; 2701 g = aval * gf + (255 - aval) * gb; 2702 b = aval * bf + (255 - aval) * bb; 2703 pixel = (r & 0xff00) << 8 | 2704 (g & 0xff00) | 2705 (b & 0xff00) >> 8; 2706 } 2707 if (i & 16) 2708 radeonfb_wait_fifo(sc, 20); 2709 PUT32(sc, RADEON_HOST_DATA0, pixel); 2710 } 2711 if (rv == GC_ADD) { 2712 glyphcache_add(&dp->rd_gc, c, xd, yd); 2713 } else 2714 if (attr & 1) 2715 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2716 2717 } 2718 2719 static void 2720 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2721 { 2722 struct rasops_info *ri = cookie; 2723 struct vcons_screen *scr = ri->ri_hw; 2724 struct radeonfb_display *dp = scr->scr_cookie; 2725 struct radeonfb_softc *sc = dp->rd_softc; 2726 struct wsdisplay_font *font = PICK_FONT(ri, c); 2727 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2728 int i, x, y, wi, he, r, g, b, aval; 2729 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2730 uint8_t *data8; 2731 int rv, cnt; 2732 2733 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2734 return; 2735 2736 if (!CHAR_IN_FONT(c, font)) 2737 return; 2738 2739 wi = font->fontwidth; 2740 he = font->fontheight; 2741 2742 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2743 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2744 2745 x = ri->ri_xorigin + col * wi; 2746 y = ri->ri_yorigin + row * he; 2747 2748 if (c == 0x20) { 2749 radeonfb_rectfill(dp, x, y, wi, he, bg); 2750 if (attr & 1) 2751 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2752 return; 2753 } 2754 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2755 if (rv == GC_OK) 2756 return; 2757 2758 data8 = WSFONT_GLYPH(c, font); 2759 2760 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2761 2762 radeonfb_wait_fifo(sc, 5); 2763 2764 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2765 RADEON_GMC_BRUSH_NONE | 2766 RADEON_GMC_SRC_DATATYPE_COLOR | 2767 RADEON_ROP3_S | 2768 RADEON_DP_SRC_SOURCE_HOST_DATA | 2769 RADEON_GMC_CLR_CMP_CNTL_DIS | 2770 RADEON_GMC_WR_MSK_DIS | 2771 gmc); 2772 2773 PUT32(sc, RADEON_DP_CNTL, 2774 RADEON_DST_X_LEFT_TO_RIGHT | 2775 RADEON_DST_Y_TOP_TO_BOTTOM); 2776 2777 PUT32(sc, RADEON_SRC_X_Y, 0); 2778 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2779 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2780 2781 /* 2782 * we need the RGB colours here, so get offsets into rasops_cmap 2783 */ 2784 fgo = ((attr >> 24) & 0xf) * 3; 2785 bgo = ((attr >> 16) & 0xf) * 3; 2786 2787 r0 = rasops_cmap[bgo]; 2788 r1 = rasops_cmap[fgo]; 2789 g0 = rasops_cmap[bgo + 1]; 2790 g1 = rasops_cmap[fgo + 1]; 2791 b0 = rasops_cmap[bgo + 2]; 2792 b1 = rasops_cmap[fgo + 2]; 2793 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2794 bg8 = R3G3B2(r0, g0, b0); 2795 fg8 = R3G3B2(r1, g1, b1); 2796 2797 radeonfb_wait_fifo(sc, 20); 2798 cnt = 0; 2799 for (i = 0; i < ri->ri_fontscale; i++) { 2800 aval = *data8; 2801 if (aval == 0) { 2802 pixel = bg8; 2803 } else if (aval == 255) { 2804 pixel = fg8; 2805 } else { 2806 r = aval * r1 + (255 - aval) * r0; 2807 g = aval * g1 + (255 - aval) * g0; 2808 b = aval * b1 + (255 - aval) * b0; 2809 pixel = ((r & 0xe000) >> 8) | 2810 ((g & 0xe000) >> 11) | 2811 ((b & 0xc000) >> 14); 2812 } 2813 latch |= pixel << (8 * (i & 3)); 2814 /* write in 32bit chunks */ 2815 if ((i & 3) == 3) { 2816 PUT32(sc, RADEON_HOST_DATA0, latch); 2817 /* 2818 * not strictly necessary, old data should be shifted 2819 * out 2820 */ 2821 latch = 0; 2822 cnt++; 2823 if (cnt > 16) { 2824 cnt = 0; 2825 radeonfb_wait_fifo(sc, 20); 2826 } 2827 } 2828 data8++; 2829 } 2830 /* if we have pixels left in latch write them out */ 2831 if ((i & 3) != 0) { 2832 /* 2833 * radeon is weird - apparently leftover pixels are written 2834 * from the middle, not from the left as everything else 2835 */ 2836 PUT32(sc, RADEON_HOST_DATA0, latch); 2837 } 2838 2839 if (rv == GC_ADD) { 2840 glyphcache_add(&dp->rd_gc, c, x, y); 2841 } else 2842 if (attr & 1) 2843 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2844 2845 } 2846 2847 /* 2848 * wrapper for software character drawing 2849 * just sync the engine and call rasops*_putchar() 2850 */ 2851 2852 static void 2853 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2854 { 2855 struct rasops_info *ri = cookie; 2856 struct vcons_screen *scr = ri->ri_hw; 2857 struct radeonfb_display *dp = scr->scr_cookie; 2858 2859 radeonfb_engine_idle(dp->rd_softc); 2860 dp->rd_putchar(ri, row, col, c, attr); 2861 } 2862 2863 static void 2864 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2865 { 2866 struct rasops_info *ri = cookie; 2867 struct vcons_screen *scr = ri->ri_hw; 2868 struct radeonfb_display *dp = scr->scr_cookie; 2869 uint32_t x, y, w, h, fg, bg, ul; 2870 2871 /* XXX: check for full emulation mode? */ 2872 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2873 x = ri->ri_xorigin; 2874 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2875 w = ri->ri_emuwidth; 2876 h = ri->ri_font->fontheight * nrows; 2877 2878 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2879 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2880 } 2881 } 2882 2883 static void 2884 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2885 { 2886 struct rasops_info *ri = cookie; 2887 struct vcons_screen *scr = ri->ri_hw; 2888 struct radeonfb_display *dp = scr->scr_cookie; 2889 uint32_t x, ys, yd, w, h; 2890 2891 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2892 x = ri->ri_xorigin; 2893 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2894 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2895 w = ri->ri_emuwidth; 2896 h = ri->ri_font->fontheight * nrows; 2897 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2898 RADEON_ROP3_S); 2899 } 2900 } 2901 2902 static void 2903 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2904 { 2905 struct rasops_info *ri = cookie; 2906 struct vcons_screen *scr = ri->ri_hw; 2907 struct radeonfb_display *dp = scr->scr_cookie; 2908 uint32_t xs, xd, y, w, h; 2909 2910 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2911 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2912 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2913 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2914 w = ri->ri_font->fontwidth * ncols; 2915 h = ri->ri_font->fontheight; 2916 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2917 RADEON_ROP3_S); 2918 } 2919 } 2920 2921 static void 2922 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2923 long fillattr) 2924 { 2925 struct rasops_info *ri = cookie; 2926 struct vcons_screen *scr = ri->ri_hw; 2927 struct radeonfb_display *dp = scr->scr_cookie; 2928 uint32_t x, y, w, h, fg, bg, ul; 2929 2930 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2931 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2932 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2933 w = ri->ri_font->fontwidth * ncols; 2934 h = ri->ri_font->fontheight; 2935 2936 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2937 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2938 } 2939 } 2940 2941 static void 2942 radeonfb_cursor(void *cookie, int on, int row, int col) 2943 { 2944 struct rasops_info *ri = cookie; 2945 struct vcons_screen *scr = ri->ri_hw; 2946 struct radeonfb_display *dp = scr->scr_cookie; 2947 int x, y, wi, he; 2948 2949 wi = ri->ri_font->fontwidth; 2950 he = ri->ri_font->fontheight; 2951 2952 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2953 x = ri->ri_ccol * wi + ri->ri_xorigin; 2954 y = ri->ri_crow * he + ri->ri_yorigin; 2955 /* first turn off the old cursor */ 2956 if (ri->ri_flg & RI_CURSOR) { 2957 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2958 RADEON_ROP3_Dn); 2959 ri->ri_flg &= ~RI_CURSOR; 2960 } 2961 ri->ri_crow = row; 2962 ri->ri_ccol = col; 2963 /* then (possibly) turn on the new one */ 2964 if (on) { 2965 x = ri->ri_ccol * wi + ri->ri_xorigin; 2966 y = ri->ri_crow * he + ri->ri_yorigin; 2967 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2968 RADEON_ROP3_Dn); 2969 ri->ri_flg |= RI_CURSOR; 2970 } 2971 } else { 2972 scr->scr_ri.ri_crow = row; 2973 scr->scr_ri.ri_ccol = col; 2974 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2975 } 2976 } 2977 2978 /* 2979 * Underlying acceleration support. 2980 */ 2981 2982 static void 2983 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2984 int width, int height, uint32_t color) 2985 { 2986 struct radeonfb_softc *sc = dp->rd_softc; 2987 uint32_t gmc; 2988 2989 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2990 2991 radeonfb_wait_fifo(sc, 6); 2992 2993 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2994 RADEON_GMC_BRUSH_SOLID_COLOR | 2995 RADEON_GMC_SRC_DATATYPE_COLOR | 2996 RADEON_GMC_CLR_CMP_CNTL_DIS | 2997 RADEON_ROP3_P | gmc); 2998 2999 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3000 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3001 PUT32(sc, RADEON_DP_CNTL, 3002 RADEON_DST_X_LEFT_TO_RIGHT | 3003 RADEON_DST_Y_TOP_TO_BOTTOM); 3004 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3005 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3006 3007 } 3008 3009 static void 3010 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3011 int width, int height, long attr) 3012 { 3013 struct radeonfb_display *dp = cookie; 3014 3015 radeonfb_rectfill(dp, dstx, dsty, width, height, 3016 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3017 } 3018 3019 static void 3020 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3021 int dstx, int dsty, int width, int height, int rop) 3022 { 3023 struct radeonfb_display *dp = cookie; 3024 struct radeonfb_softc *sc = dp->rd_softc; 3025 uint32_t gmc; 3026 uint32_t dir; 3027 3028 if (dsty < srcy) { 3029 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3030 } else { 3031 srcy += height - 1; 3032 dsty += height - 1; 3033 dir = 0; 3034 } 3035 if (dstx < srcx) { 3036 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3037 } else { 3038 srcx += width - 1; 3039 dstx += width - 1; 3040 } 3041 3042 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3043 3044 radeonfb_wait_fifo(sc, 6); 3045 3046 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3047 RADEON_GMC_BRUSH_SOLID_COLOR | 3048 RADEON_GMC_SRC_DATATYPE_COLOR | 3049 RADEON_GMC_CLR_CMP_CNTL_DIS | 3050 RADEON_DP_SRC_SOURCE_MEMORY | 3051 rop | gmc); 3052 3053 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3054 PUT32(sc, RADEON_DP_CNTL, dir); 3055 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3056 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3057 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3058 } 3059 3060 static void 3061 radeonfb_engine_idle(struct radeonfb_softc *sc) 3062 { 3063 3064 radeonfb_wait_fifo(sc, 64); 3065 while ((GET32(sc, RADEON_RBBM_STATUS) & 3066 RADEON_RBBM_ACTIVE) != 0); 3067 radeonfb_engine_flush(sc); 3068 } 3069 3070 static inline void 3071 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3072 { 3073 int i; 3074 3075 for (i = RADEON_TIMEOUT; i; i--) { 3076 if ((GET32(sc, RADEON_RBBM_STATUS) & 3077 RADEON_RBBM_FIFOCNT_MASK) >= n) 3078 return; 3079 } 3080 #ifdef DIAGNOSTIC 3081 if (!i) 3082 printf("%s: timed out waiting for fifo (%x)\n", 3083 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3084 #endif 3085 } 3086 3087 static void 3088 radeonfb_engine_flush(struct radeonfb_softc *sc) 3089 { 3090 int i = 0; 3091 3092 if (IS_R300(sc)) { 3093 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3094 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3095 i++; 3096 } 3097 } else { 3098 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3099 RADEON_RB2D_DC_FLUSH_ALL); 3100 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3101 RADEON_RB2D_DC_BUSY) { 3102 i++; 3103 } 3104 } 3105 #ifdef DIAGNOSTIC 3106 if (i > RADEON_TIMEOUT) 3107 printf("%s: engine flush timed out!\n", XNAME(sc)); 3108 #endif 3109 } 3110 3111 static inline void 3112 radeonfb_unclip(struct radeonfb_softc *sc) 3113 { 3114 3115 radeonfb_wait_fifo(sc, 2); 3116 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3117 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3118 } 3119 3120 static void 3121 radeonfb_engine_init(struct radeonfb_display *dp) 3122 { 3123 struct radeonfb_softc *sc = dp->rd_softc; 3124 uint32_t pitch; 3125 volatile uint32_t junk; 3126 3127 /* no 3D */ 3128 PUT32(sc, RADEON_RB3D_CNTL, 0); 3129 3130 radeonfb_engine_reset(sc); 3131 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3132 3133 radeonfb_wait_fifo(sc, 1); 3134 if (!IS_R300(sc)) 3135 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3136 3137 radeonfb_wait_fifo(sc, 3); 3138 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3139 (pitch << 22) | (sc->sc_aperbase >> 10)); 3140 3141 3142 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3143 (pitch << 22) | (sc->sc_aperbase >> 10)); 3144 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3145 (pitch << 22) | (sc->sc_aperbase >> 10)); 3146 3147 junk = GET32(sc, RADEON_DP_DATATYPE); 3148 3149 /* default scissors -- no clipping */ 3150 radeonfb_wait_fifo(sc, 1); 3151 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3152 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3153 3154 radeonfb_wait_fifo(sc, 1); 3155 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3156 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3157 RADEON_GMC_CLR_CMP_CNTL_DIS | 3158 RADEON_GMC_BRUSH_SOLID_COLOR | 3159 RADEON_GMC_SRC_DATATYPE_COLOR); 3160 3161 radeonfb_wait_fifo(sc, 10); 3162 PUT32(sc, RADEON_DST_LINE_START, 0); 3163 PUT32(sc, RADEON_DST_LINE_END, 0); 3164 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3165 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3166 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3167 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3168 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3169 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3170 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3171 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3172 radeonfb_engine_idle(sc); 3173 } 3174 3175 static void 3176 radeonfb_engine_reset(struct radeonfb_softc *sc) 3177 { 3178 uint32_t hpc, rbbm, mclkcntl, clkindex; 3179 3180 radeonfb_engine_flush(sc); 3181 3182 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3183 if (HAS_R300CG(sc)) 3184 radeonfb_r300cg_workaround(sc); 3185 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3186 3187 /* 3188 * According to comments in XFree code, resetting the HDP via 3189 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3190 * So we use HOST_PATH_CNTL instead. 3191 */ 3192 3193 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3194 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3195 if (IS_R300(sc)) { 3196 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3197 RADEON_SOFT_RESET_CP | 3198 RADEON_SOFT_RESET_HI | 3199 RADEON_SOFT_RESET_E2); 3200 GET32(sc, RADEON_RBBM_SOFT_RESET); 3201 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3202 /* 3203 * XXX: this bit is not defined in any ATI docs I have, 3204 * nor in the XFree code, but XFree does it. Why? 3205 */ 3206 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3207 } else { 3208 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3209 RADEON_SOFT_RESET_CP | 3210 RADEON_SOFT_RESET_SE | 3211 RADEON_SOFT_RESET_RE | 3212 RADEON_SOFT_RESET_PP | 3213 RADEON_SOFT_RESET_E2 | 3214 RADEON_SOFT_RESET_RB); 3215 GET32(sc, RADEON_RBBM_SOFT_RESET); 3216 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3217 ~(RADEON_SOFT_RESET_CP | 3218 RADEON_SOFT_RESET_SE | 3219 RADEON_SOFT_RESET_RE | 3220 RADEON_SOFT_RESET_PP | 3221 RADEON_SOFT_RESET_E2 | 3222 RADEON_SOFT_RESET_RB)); 3223 GET32(sc, RADEON_RBBM_SOFT_RESET); 3224 } 3225 3226 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3227 GET32(sc, RADEON_HOST_PATH_CNTL); 3228 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3229 3230 if (IS_R300(sc)) 3231 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3232 3233 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3234 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3235 3236 if (HAS_R300CG(sc)) 3237 radeonfb_r300cg_workaround(sc); 3238 } 3239 3240 static int 3241 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3242 { 3243 int x, y; 3244 3245 x = pos->x; 3246 y = pos->y; 3247 3248 /* 3249 * This doesn't let a cursor move off the screen. I'm not 3250 * sure if this will have negative effects for e.g. Xinerama. 3251 * I'd guess Xinerama handles it by changing the cursor shape, 3252 * but that needs verification. 3253 */ 3254 if (x >= dp->rd_virtx) 3255 x = dp->rd_virtx - 1; 3256 if (x < 0) 3257 x = 0; 3258 if (y >= dp->rd_virty) 3259 y = dp->rd_virty - 1; 3260 if (y < 0) 3261 y = 0; 3262 3263 dp->rd_cursor.rc_pos.x = x; 3264 dp->rd_cursor.rc_pos.y = y; 3265 3266 radeonfb_cursor_position(dp); 3267 return 0; 3268 } 3269 3270 static int 3271 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3272 { 3273 unsigned flags; 3274 3275 uint8_t r[2], g[2], b[2]; 3276 unsigned index, count; 3277 int i, err; 3278 int pitch, size; 3279 struct radeonfb_cursor nc; 3280 3281 flags = wc->which; 3282 3283 /* copy old values */ 3284 nc = dp->rd_cursor; 3285 3286 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3287 index = wc->cmap.index; 3288 count = wc->cmap.count; 3289 3290 if (index >= 2 || (index + count) > 2) 3291 return EINVAL; 3292 3293 err = copyin(wc->cmap.red, &r[index], count); 3294 if (err) 3295 return err; 3296 err = copyin(wc->cmap.green, &g[index], count); 3297 if (err) 3298 return err; 3299 err = copyin(wc->cmap.blue, &b[index], count); 3300 if (err) 3301 return err; 3302 3303 for (i = index; i < index + count; i++) { 3304 nc.rc_cmap[i] = 3305 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3306 } 3307 } 3308 3309 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3310 if ((wc->size.x > RADEON_CURSORMAXX) || 3311 (wc->size.y > RADEON_CURSORMAXY)) 3312 return EINVAL; 3313 3314 /* figure bytes per line */ 3315 pitch = (wc->size.x + 7) / 8; 3316 size = pitch * wc->size.y; 3317 3318 /* clear the old cursor and mask */ 3319 memset(nc.rc_image, 0, 512); 3320 memset(nc.rc_mask, 0, 512); 3321 3322 nc.rc_size = wc->size; 3323 3324 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3325 return err; 3326 3327 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3328 return err; 3329 } 3330 3331 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3332 nc.rc_hot = wc->hot; 3333 if (nc.rc_hot.x >= nc.rc_size.x) 3334 nc.rc_hot.x = nc.rc_size.x - 1; 3335 if (nc.rc_hot.y >= nc.rc_size.y) 3336 nc.rc_hot.y = nc.rc_size.y - 1; 3337 } 3338 3339 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3340 nc.rc_pos = wc->pos; 3341 if (nc.rc_pos.x >= dp->rd_virtx) 3342 nc.rc_pos.x = dp->rd_virtx - 1; 3343 #if 0 3344 if (nc.rc_pos.x < 0) 3345 nc.rc_pos.x = 0; 3346 #endif 3347 if (nc.rc_pos.y >= dp->rd_virty) 3348 nc.rc_pos.y = dp->rd_virty - 1; 3349 #if 0 3350 if (nc.rc_pos.y < 0) 3351 nc.rc_pos.y = 0; 3352 #endif 3353 } 3354 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3355 nc.rc_visible = wc->enable; 3356 } 3357 3358 dp->rd_cursor = nc; 3359 radeonfb_cursor_update(dp, wc->which); 3360 3361 return 0; 3362 } 3363 3364 /* 3365 * Change the cursor shape. Call this with the cursor locked to avoid 3366 * flickering/tearing. 3367 */ 3368 static void 3369 radeonfb_cursor_shape(struct radeonfb_display *dp) 3370 { 3371 uint8_t and[512], xor[512]; 3372 int i, j, src, dst, pitch; 3373 const uint8_t *msk = dp->rd_cursor.rc_mask; 3374 const uint8_t *img = dp->rd_cursor.rc_image; 3375 3376 /* 3377 * Radeon cursor data interleaves one line of AND data followed 3378 * by a line of XOR data. (Each line corresponds to a whole hardware 3379 * pitch - i.e. 64 pixels or 8 bytes.) 3380 * 3381 * The cursor is displayed using the following table: 3382 * 3383 * AND XOR Result 3384 * ---------------------- 3385 * 0 0 Cursor color 0 3386 * 0 1 Cursor color 1 3387 * 1 0 Transparent 3388 * 1 1 Complement of background 3389 * 3390 * Our masks are therefore different from what we were passed. 3391 * Passed in, I'm assuming the data represents either color 0 or 1, 3392 * and a mask, so the passed in table looks like: 3393 * 3394 * IMG Mask Result 3395 * ----------------------- 3396 * 0 0 Transparent 3397 * 0 1 Cursor color 0 3398 * 1 0 Transparent 3399 * 1 1 Cursor color 1 3400 * 3401 * IF mask bit == 1, AND = 0, XOR = color. 3402 * IF mask bit == 0, AND = 1, XOR = 0. 3403 * 3404 * hence: AND = ~(mask); XOR = color & ~(mask); 3405 */ 3406 3407 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3408 3409 /* start by assuming all bits are transparent */ 3410 memset(and, 0xff, 512); 3411 memset(xor, 0x00, 512); 3412 3413 src = 0; 3414 dst = 0; 3415 for (i = 0; i < 64; i++) { 3416 for (j = 0; j < 64; j += 8) { 3417 if ((i < dp->rd_cursor.rc_size.y) && 3418 (j < dp->rd_cursor.rc_size.x)) { 3419 3420 /* take care to leave odd bits alone */ 3421 and[dst] &= ~(msk[src]); 3422 xor[dst] = img[src] & msk[src]; 3423 src++; 3424 } 3425 dst++; 3426 } 3427 } 3428 3429 /* copy the image into place */ 3430 for (i = 0; i < 64; i++) { 3431 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3432 &and[i * 8], 8); 3433 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3434 &xor[i * 8], 8); 3435 } 3436 } 3437 3438 static void 3439 radeonfb_cursor_position(struct radeonfb_display *dp) 3440 { 3441 struct radeonfb_softc *sc = dp->rd_softc; 3442 uint32_t offset, hvoff, hvpos; /* registers */ 3443 uint32_t coff; /* cursor offset */ 3444 int i, x, y, xoff, yoff, crtcoff; 3445 3446 /* 3447 * XXX: this also needs to handle pan/scan 3448 */ 3449 for (i = 0; i < dp->rd_ncrtcs; i++) { 3450 3451 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3452 3453 if (rcp->rc_number) { 3454 offset = RADEON_CUR2_OFFSET; 3455 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3456 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3457 crtcoff = RADEON_CRTC2_OFFSET; 3458 } else { 3459 offset = RADEON_CUR_OFFSET; 3460 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3461 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3462 crtcoff = RADEON_CRTC_OFFSET; 3463 } 3464 3465 x = dp->rd_cursor.rc_pos.x; 3466 y = dp->rd_cursor.rc_pos.y; 3467 3468 while (y < rcp->rc_yoffset) { 3469 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3470 } 3471 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3472 rcp->rc_yoffset += RADEON_PANINCREMENT; 3473 } 3474 while (x < rcp->rc_xoffset) { 3475 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3476 } 3477 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3478 rcp->rc_xoffset += RADEON_PANINCREMENT; 3479 } 3480 3481 /* adjust for the cursor's hotspot */ 3482 x -= dp->rd_cursor.rc_hot.x; 3483 y -= dp->rd_cursor.rc_hot.y; 3484 xoff = yoff = 0; 3485 3486 if (x >= dp->rd_virtx) 3487 x = dp->rd_virtx - 1; 3488 if (y >= dp->rd_virty) 3489 y = dp->rd_virty - 1; 3490 3491 /* now adjust cursor so it is relative to viewport */ 3492 x -= rcp->rc_xoffset; 3493 y -= rcp->rc_yoffset; 3494 3495 /* 3496 * no need to check for fall off, because we should 3497 * never move off the screen entirely! 3498 */ 3499 coff = 0; 3500 if (x < 0) { 3501 xoff = -x; 3502 x = 0; 3503 } 3504 if (y < 0) { 3505 yoff = -y; 3506 y = 0; 3507 coff = (yoff * 2) * 8; 3508 } 3509 3510 /* pan the display */ 3511 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3512 rcp->rc_xoffset); 3513 3514 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3515 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3516 /* NB: this unlocks the cursor */ 3517 PUT32(sc, hvpos, (x << 16) | y); 3518 } 3519 } 3520 3521 static void 3522 radeonfb_cursor_visible(struct radeonfb_display *dp) 3523 { 3524 int i; 3525 uint32_t gencntl, bit; 3526 3527 for (i = 0; i < dp->rd_ncrtcs; i++) { 3528 if (dp->rd_crtcs[i].rc_number) { 3529 gencntl = RADEON_CRTC2_GEN_CNTL; 3530 bit = RADEON_CRTC2_CUR_EN; 3531 } else { 3532 gencntl = RADEON_CRTC_GEN_CNTL; 3533 bit = RADEON_CRTC_CUR_EN; 3534 } 3535 3536 if (dp->rd_cursor.rc_visible) 3537 SET32(dp->rd_softc, gencntl, bit); 3538 else 3539 CLR32(dp->rd_softc, gencntl, bit); 3540 } 3541 } 3542 3543 static void 3544 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3545 { 3546 int i; 3547 uint32_t c0reg, c1reg; 3548 struct radeonfb_softc *sc = dp->rd_softc; 3549 3550 for (i = 0; i < dp->rd_ncrtcs; i++) { 3551 if (dp->rd_crtcs[i].rc_number) { 3552 c0reg = RADEON_CUR2_CLR0; 3553 c1reg = RADEON_CUR2_CLR1; 3554 } else { 3555 c0reg = RADEON_CUR_CLR0; 3556 c1reg = RADEON_CUR_CLR1; 3557 } 3558 3559 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3560 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3561 } 3562 } 3563 3564 static void 3565 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3566 { 3567 struct radeonfb_softc *sc; 3568 int i; 3569 3570 sc = dp->rd_softc; 3571 for (i = 0; i < dp->rd_ncrtcs; i++) { 3572 if (dp->rd_crtcs[i].rc_number) { 3573 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3574 } else { 3575 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3576 } 3577 } 3578 3579 if (which & WSDISPLAY_CURSOR_DOCMAP) 3580 radeonfb_cursor_cmap(dp); 3581 3582 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3583 radeonfb_cursor_shape(dp); 3584 3585 if (which & WSDISPLAY_CURSOR_DOCUR) 3586 radeonfb_cursor_visible(dp); 3587 3588 /* this one is unconditional, because it updates other stuff */ 3589 radeonfb_cursor_position(dp); 3590 } 3591 3592 static struct videomode * 3593 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3594 { 3595 int r1, r2; 3596 3597 /* otherwise pick the higher refresh rate */ 3598 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3599 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3600 3601 return (r1 < r2 ? m2 : m1); 3602 } 3603 3604 static const struct videomode * 3605 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3606 int x, int y) 3607 { 3608 struct edid_info *ep = &rp->rp_edid; 3609 struct videomode *vmp = NULL; 3610 int i; 3611 3612 if (!rp->rp_edid_valid) { 3613 /* fallback to safe mode */ 3614 return radeonfb_modelookup(sc->sc_defaultmode); 3615 } 3616 3617 /* always choose the preferred mode first! */ 3618 if (ep->edid_preferred_mode) { 3619 3620 /* XXX: add auto-stretching support for native mode */ 3621 3622 /* this may want panning to occur, btw */ 3623 if ((ep->edid_preferred_mode->hdisplay <= x) && 3624 (ep->edid_preferred_mode->vdisplay <= y)) 3625 return ep->edid_preferred_mode; 3626 } 3627 3628 for (i = 0; i < ep->edid_nmodes; i++) { 3629 /* 3630 * We elect to pick a resolution that is too large for 3631 * the monitor than one that is too small. This means 3632 * that we will prefer to pan rather than to try to 3633 * center a smaller display on a larger screen. In 3634 * practice, this shouldn't matter because if a 3635 * monitor can support a larger resolution, it can 3636 * probably also support the smaller. A specific 3637 * exception is fixed format panels, but hopefully 3638 * they are properly dealt with by the "autostretch" 3639 * logic above. 3640 */ 3641 if ((ep->edid_modes[i].hdisplay > x) || 3642 (ep->edid_modes[i].vdisplay > y)) { 3643 continue; 3644 } 3645 3646 /* 3647 * at this point, the display mode is no larger than 3648 * what we've requested. 3649 */ 3650 if (vmp == NULL) 3651 vmp = &ep->edid_modes[i]; 3652 3653 /* eliminate smaller modes */ 3654 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3655 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3656 continue; 3657 3658 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3659 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3660 vmp = &ep->edid_modes[i]; 3661 continue; 3662 } 3663 3664 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3665 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3666 3667 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3668 } 3669 3670 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3671 } 3672 3673 static int 3674 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3675 { 3676 int i; 3677 3678 for (i = 0; i < nlist; i++) { 3679 if ((x == list[i].hdisplay) && 3680 (y == list[i].vdisplay)) { 3681 return 1; 3682 } 3683 } 3684 return 0; 3685 } 3686 3687 static void 3688 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3689 int pan) 3690 { 3691 struct radeonfb_port *rp; 3692 struct edid_info *ep; 3693 int i, j; 3694 3695 *x = 0; 3696 *y = 0; 3697 3698 if (pan) { 3699 for (i = 0; i < dp->rd_ncrtcs; i++) { 3700 rp = dp->rd_crtcs[i].rc_port; 3701 ep = &rp->rp_edid; 3702 if (!rp->rp_edid_valid) { 3703 /* monitor not present */ 3704 continue; 3705 } 3706 3707 /* 3708 * For now we are ignoring "conflict" that 3709 * could occur when mixing some modes like 3710 * 1280x1024 and 1400x800. It isn't clear 3711 * which is better, so the first one wins. 3712 */ 3713 for (j = 0; j < ep->edid_nmodes; j++) { 3714 /* 3715 * ignore resolutions that are too big for 3716 * the radeon 3717 */ 3718 if (ep->edid_modes[j].hdisplay > 3719 dp->rd_softc->sc_maxx) 3720 continue; 3721 if (ep->edid_modes[j].vdisplay > 3722 dp->rd_softc->sc_maxy) 3723 continue; 3724 3725 /* 3726 * pick largest resolution, the 3727 * smaller monitor will pan 3728 */ 3729 if ((ep->edid_modes[j].hdisplay >= *x) && 3730 (ep->edid_modes[j].vdisplay >= *y)) { 3731 *x = ep->edid_modes[j].hdisplay; 3732 *y = ep->edid_modes[j].vdisplay; 3733 } 3734 } 3735 } 3736 3737 } else { 3738 struct videomode modes[64]; 3739 int nmodes = 0; 3740 int valid = 0; 3741 3742 for (i = 0; i < dp->rd_ncrtcs; i++) { 3743 /* 3744 * pick the largest resolution in common. 3745 */ 3746 rp = dp->rd_crtcs[i].rc_port; 3747 ep = &rp->rp_edid; 3748 3749 if (!rp->rp_edid_valid) 3750 continue; 3751 3752 if (!valid) { 3753 /* 3754 * Pick the preferred mode for this port 3755 * if available. 3756 */ 3757 if (ep->edid_preferred_mode) { 3758 struct videomode *vmp = 3759 ep->edid_preferred_mode; 3760 3761 if ((vmp->hdisplay <= 3762 dp->rd_softc->sc_maxx) && 3763 (vmp->vdisplay <= 3764 dp->rd_softc->sc_maxy)) 3765 modes[nmodes++] = *vmp; 3766 } else { 3767 3768 /* initialize starting list */ 3769 for (j = 0; j < ep->edid_nmodes; j++) { 3770 /* 3771 * ignore resolutions that are 3772 * too big for the radeon 3773 */ 3774 if (ep->edid_modes[j].hdisplay > 3775 dp->rd_softc->sc_maxx) 3776 continue; 3777 if (ep->edid_modes[j].vdisplay > 3778 dp->rd_softc->sc_maxy) 3779 continue; 3780 3781 modes[nmodes] = 3782 ep->edid_modes[j]; 3783 nmodes++; 3784 } 3785 } 3786 valid = 1; 3787 } else { 3788 /* merge into preexisting list */ 3789 for (j = 0; j < nmodes; j++) { 3790 if (!radeonfb_hasres(ep->edid_modes, 3791 ep->edid_nmodes, 3792 modes[j].hdisplay, 3793 modes[j].vdisplay)) { 3794 modes[j] = modes[nmodes]; 3795 j--; 3796 nmodes--; 3797 } 3798 } 3799 } 3800 } 3801 3802 /* now we have to pick from the merged list */ 3803 for (i = 0; i < nmodes; i++) { 3804 if ((modes[i].hdisplay >= *x) && 3805 (modes[i].vdisplay >= *y)) { 3806 *x = modes[i].hdisplay; 3807 *y = modes[i].vdisplay; 3808 } 3809 } 3810 } 3811 3812 if ((*x == 0) || (*y == 0)) { 3813 /* fallback to safe mode */ 3814 *x = 640; 3815 *y = 480; 3816 } 3817 } 3818 3819 /* 3820 * backlight levels are linear on: 3821 * - RV200, RV250, RV280, RV350 3822 * - but NOT on PowerBook4,3 6,3 6,5 3823 * according to Linux' radeonfb 3824 */ 3825 3826 /* Get the current backlight level for the display. */ 3827 3828 static int 3829 radeonfb_get_backlight(struct radeonfb_display *dp) 3830 { 3831 int s; 3832 uint32_t level; 3833 3834 s = spltty(); 3835 3836 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3837 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3838 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3839 3840 /* 3841 * On some chips, we should negate the backlight level. 3842 * XXX Find out on which chips. 3843 */ 3844 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3845 level = RADEONFB_BACKLIGHT_MAX - level; 3846 3847 splx(s); 3848 3849 return level; 3850 } 3851 3852 /* Set the backlight to the given level for the display. */ 3853 static void 3854 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3855 { 3856 if (dp->rd_bl_on == on) 3857 return; 3858 dp->rd_bl_on = on; 3859 radeonfb_set_backlight(dp, dp->rd_bl_level); 3860 } 3861 3862 static int 3863 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3864 { 3865 struct radeonfb_softc *sc; 3866 int rlevel, s; 3867 uint32_t lvds; 3868 3869 s = spltty(); 3870 3871 dp->rd_bl_level = level; 3872 if (dp->rd_bl_on == 0) 3873 level = 0; 3874 3875 if (level < 0) 3876 level = 0; 3877 else if (level >= RADEONFB_BACKLIGHT_MAX) 3878 level = RADEONFB_BACKLIGHT_MAX; 3879 3880 sc = dp->rd_softc; 3881 3882 /* On some chips, we should negate the backlight level. */ 3883 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3884 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3885 } else 3886 rlevel = level; 3887 3888 callout_stop(&dp->rd_bl_lvds_co); 3889 radeonfb_engine_idle(sc); 3890 3891 /* 3892 * Turn off the display if the backlight is set to 0, since the 3893 * display is useless without backlight anyway. 3894 */ 3895 if (level == 0) 3896 radeonfb_blank(dp, 1); 3897 else if (radeonfb_get_backlight(dp) == 0) 3898 radeonfb_blank(dp, 0); 3899 3900 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3901 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3902 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3903 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3904 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3905 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3906 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3907 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3908 lvds |= RADEON_LVDS_ON; 3909 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3910 } else { 3911 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3912 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3913 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3914 } 3915 3916 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3917 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3918 /* XXX What is the correct delay? */ 3919 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3920 3921 splx(s); 3922 3923 return 0; 3924 } 3925 3926 /* 3927 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3928 * Set the delayed bits in the register, and clear the stored delayed 3929 * value. 3930 */ 3931 3932 static void radeonfb_lvds_callout(void *arg) 3933 { 3934 struct radeonfb_display *dp = arg; 3935 int s; 3936 3937 s = splhigh(); 3938 3939 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3940 dp->rd_bl_lvds_val); 3941 dp->rd_bl_lvds_val = 0; 3942 3943 splx(s); 3944 } 3945 3946 static void 3947 radeonfb_brightness_up(device_t dev) 3948 { 3949 struct radeonfb_softc *sc = device_private(dev); 3950 struct radeonfb_display *dp = &sc->sc_displays[0]; 3951 int level; 3952 3953 /* we assume the main display is the first one - need a better way */ 3954 if (sc->sc_ndisplays < 1) return; 3955 /* make sure pushing the hotkeys always has an effect */ 3956 dp->rd_bl_on = 1; 3957 level = dp->rd_bl_level; 3958 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3959 radeonfb_set_backlight(dp, level); 3960 } 3961 3962 static void 3963 radeonfb_brightness_down(device_t dev) 3964 { 3965 struct radeonfb_softc *sc = device_private(dev); 3966 struct radeonfb_display *dp = &sc->sc_displays[0]; 3967 int level; 3968 3969 /* we assume the main display is the first one - need a better way */ 3970 if (sc->sc_ndisplays < 1) return; 3971 /* make sure pushing the hotkeys always has an effect */ 3972 dp->rd_bl_on = 1; 3973 level = dp->rd_bl_level; 3974 level = max(0, level - 5); 3975 radeonfb_set_backlight(dp, level); 3976 } 3977
Indexes created Fri Sep 26 08:10:20 GMT 2025