radeonfb.c revision 1.68
1 /* $NetBSD: radeonfb.c,v 1.68 2012/12/20 03:08:39 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.68 2012/12/20 03:08:39 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 1, 0 }, 384 { 2, 1 }, 385 { 3, 4 }, 386 { 4, 2 }, 387 { 6, 6 }, 388 { 8, 3 }, 389 { 12, 7 }, 390 { 0, 0 } 391 }; 392 393 /* 394 * This table taken from X11. 395 */ 396 static const struct { 397 int family; 398 struct radeon_tmds_pll plls[4]; 399 } radeonfb_tmds_pll[] = { 400 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 401 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RS100, {{0, 0}}}, 403 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 407 { RADEON_RS300, {{0, 0}}}, 408 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 409 { RADEON_R300, {{-1, 0xb01cb}}}, 410 { RADEON_R350, {{-1, 0xb01cb}}}, 411 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 412 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_R420, {{-1, 0xb01cb}}}, 414 }; 415 416 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 417 418 419 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 420 radeonfb_match, radeonfb_attach, NULL, NULL); 421 422 static int 423 radeonfb_match(device_t parent, cfdata_t match, void *aux) 424 { 425 const struct pci_attach_args *pa = aux; 426 int i; 427 428 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 429 return 0; 430 431 for (i = 0; radeonfb_devices[i].devid; i++) { 432 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 433 return 100; /* high to defeat VGA/VESA */ 434 } 435 436 return 0; 437 } 438 439 static void 440 radeonfb_attach(device_t parent, device_t dev, void *aux) 441 { 442 struct radeonfb_softc *sc = device_private(dev); 443 const struct pci_attach_args *pa = aux; 444 const char *mptr; 445 bus_size_t bsz; 446 pcireg_t screg; 447 int i, j, fg, bg, ul, flags; 448 uint32_t v; 449 450 sc->sc_dev = dev; 451 sc->sc_id = pa->pa_id; 452 for (i = 0; radeonfb_devices[i].devid; i++) { 453 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 454 break; 455 } 456 457 pci_aprint_devinfo(pa, NULL); 458 459 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 460 461 KASSERT(radeonfb_devices[i].devid != 0); 462 sc->sc_pt = pa->pa_tag; 463 sc->sc_iot = pa->pa_iot; 464 sc->sc_pc = pa->pa_pc; 465 sc->sc_family = radeonfb_devices[i].family; 466 sc->sc_flags = radeonfb_devices[i].flags; 467 468 /* enable memory and IO access */ 469 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 470 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 471 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 472 473 /* 474 * Some flags are general to entire chip families, and rather 475 * than clutter up the table with them, we go ahead and set 476 * them here. 477 */ 478 switch (sc->sc_family) { 479 case RADEON_RS100: 480 case RADEON_RS200: 481 sc->sc_flags |= RFB_IGP | RFB_RV100; 482 break; 483 484 case RADEON_RV100: 485 case RADEON_RV200: 486 case RADEON_RV250: 487 case RADEON_RV280: 488 sc->sc_flags |= RFB_RV100; 489 break; 490 491 case RADEON_RS300: 492 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_R300: 496 case RADEON_RV350: 497 case RADEON_R350: 498 case RADEON_RV380: 499 case RADEON_R420: 500 /* newer chips */ 501 sc->sc_flags |= RFB_R300; 502 break; 503 504 case RADEON_R100: 505 sc->sc_flags |= RFB_NCRTC2; 506 break; 507 } 508 509 if ((sc->sc_family == RADEON_RV200) || 510 (sc->sc_family == RADEON_RV250) || 511 (sc->sc_family == RADEON_RV280) || 512 (sc->sc_family == RADEON_RV350)) { 513 bool inverted = 0; 514 /* backlight level is linear */ 515 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 516 prop_dictionary_get_bool(device_properties(sc->sc_dev), 517 "backlight_level_reverted", &inverted); 518 if (inverted) { 519 DPRINTF(("nope, it's inverted\n")); 520 sc->sc_flags |= RFB_INV_BLIGHT; 521 } 522 } else 523 sc->sc_flags |= RFB_INV_BLIGHT; 524 525 /* 526 * XXX: to support true multihead, this must change. 527 */ 528 sc->sc_ndisplays = 1; 529 530 /* XXX: */ 531 if (!HAS_CRTC2(sc)) { 532 sc->sc_ndisplays = 1; 533 } 534 535 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 536 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 537 &sc->sc_regsz) != 0) { 538 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 539 goto error; 540 } 541 542 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 543 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 544 { 545 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 546 goto error; 547 } 548 sc->sc_romt = sc->sc_memt; 549 550 sc->sc_mapped = TRUE; 551 552 /* scratch register test... */ 553 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 554 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 555 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 556 goto error; 557 } 558 559 PRINTREG(RADEON_CRTC_EXT_CNTL); 560 PRINTREG(RADEON_CRTC_GEN_CNTL); 561 PRINTREG(RADEON_CRTC2_GEN_CNTL); 562 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 563 PRINTREG(RADEON_DAC_CNTL2); 564 565 PRINTREG(RADEON_BIOS_4_SCRATCH); 566 PRINTREG(RADEON_FP_GEN_CNTL); 567 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 568 PRINTREG(RADEON_FP2_GEN_CNTL); 569 PRINTREG(RADEON_TMDS_CNTL); 570 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 571 PRINTREG(RADEON_TMDS_PLL_CNTL); 572 PRINTREG(RADEON_LVDS_GEN_CNTL); 573 PRINTREG(RADEON_FP_HORZ_STRETCH); 574 PRINTREG(RADEON_FP_VERT_STRETCH); 575 576 /* XXX: RV100 specific */ 577 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 578 579 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 580 RADEON_TMDS_TRANSMITTER_PLLEN, 581 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 582 583 radeonfb_i2c_init(sc); 584 585 radeonfb_loadbios(sc, pa); 586 587 #ifdef RADEONFB_BIOS_INIT 588 if (radeonfb_bios_init(sc)) { 589 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 590 } 591 #endif 592 593 if (radeonfb_getclocks(sc)) { 594 aprint_error("%s: Unable to get reference clocks from BIOS\n", 595 XNAME(sc)); 596 goto error; 597 } 598 599 if (radeonfb_gettmds(sc)) { 600 aprint_error("%s: Unable to identify TMDS PLL settings\n", 601 XNAME(sc)); 602 goto error; 603 } 604 605 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 606 "minpll = %d, maxpll = %d\n", XNAME(sc), 607 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 608 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 609 610 radeonfb_getconnectors(sc); 611 612 radeonfb_set_fbloc(sc); 613 614 for (i = 0; radeonfb_limits[i].size; i++) { 615 if (sc->sc_memsz >= radeonfb_limits[i].size) { 616 sc->sc_maxx = radeonfb_limits[i].maxx; 617 sc->sc_maxy = radeonfb_limits[i].maxy; 618 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 619 /* framebuffer offset, start at a 4K page */ 620 sc->sc_fboffset = sc->sc_memsz / 621 radeonfb_limits[i].maxdisp; 622 /* 623 * we use the fbsize to figure out where we can store 624 * things like cursor data. 625 */ 626 sc->sc_fbsize = 627 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 628 RADEON_STRIDEALIGN) * sc->sc_maxy, 629 4096); 630 break; 631 } 632 } 633 634 635 radeonfb_init_misc(sc); 636 radeonfb_init_palette(sc, 0); 637 if (HAS_CRTC2(sc)) 638 radeonfb_init_palette(sc, 1); 639 640 /* program the DAC wirings */ 641 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 642 switch (sc->sc_ports[i].rp_dac_type) { 643 case RADEON_DAC_PRIMARY: 644 PATCH32(sc, RADEON_DAC_CNTL2, 645 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 646 ~RADEON_DAC2_DAC_CLK_SEL); 647 break; 648 case RADEON_DAC_TVDAC: 649 /* we always use the TVDAC to drive a secondary analog 650 * CRT for now. if we ever support TV-out this will 651 * have to change. 652 */ 653 SET32(sc, RADEON_DAC_CNTL2, 654 RADEON_DAC2_DAC2_CLK_SEL); 655 PATCH32(sc, RADEON_DISP_HW_DEBUG, 656 i ? 0 : RADEON_CRT2_DISP1_SEL, 657 ~RADEON_CRT2_DISP1_SEL); 658 break; 659 } 660 } 661 PRINTREG(RADEON_DAC_CNTL2); 662 PRINTREG(RADEON_DISP_HW_DEBUG); 663 664 /* other DAC programming */ 665 v = GET32(sc, RADEON_DAC_CNTL); 666 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 667 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 668 PUT32(sc, RADEON_DAC_CNTL, v); 669 PRINTREG(RADEON_DAC_CNTL); 670 671 /* XXX: this may need more investigation */ 672 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 673 PRINTREG(RADEON_TV_DAC_CNTL); 674 675 /* enable TMDS */ 676 SET32(sc, RADEON_FP_GEN_CNTL, 677 RADEON_FP_TMDS_EN | 678 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 679 RADEON_FP_CRTC_DONT_SHADOW_HEND); 680 /* 681 * XXX 682 * no idea why this is necessary - if I do not clear this bit on my 683 * iBook G4 the screen remains black, even though it's already clear. 684 * It needs to be set on my Sun XVR-100 for the DVI port to work 685 */ 686 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 687 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 688 } else 689 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 690 691 if (HAS_CRTC2(sc)) 692 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 693 694 /* 695 * we use bus_space_map instead of pci_mapreg, because we don't 696 * need the full aperature space. no point in wasting virtual 697 * address space we don't intend to use, right? 698 */ 699 if ((sc->sc_memsz < (4096 * 1024)) || 700 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 701 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 702 (bsz < sc->sc_memsz)) { 703 sc->sc_memsz = 0; 704 aprint_error("%s: Bad frame buffer configuration\n", 705 XNAME(sc)); 706 goto error; 707 } 708 709 /* 64 MB should be enough -- more just wastes map entries */ 710 if (sc->sc_memsz > (64 << 20)) 711 sc->sc_memsz = (64 << 20); 712 713 sc->sc_memt = pa->pa_memt; 714 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 715 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 716 sc->sc_memsz = 0; 717 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 718 goto error; 719 } 720 721 aprint_normal("%s: %d MB aperture at 0x%08x, " 722 "%d KB registers at 0x%08x\n", XNAME(sc), 723 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 724 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 725 726 /* setup default video mode from devprop (allows PROM override) */ 727 sc->sc_defaultmode = radeonfb_default_mode; 728 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 729 "videomode", &mptr)) { 730 731 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 732 sc->sc_defaultmode = sc->sc_modebuf; 733 } 734 735 /* initialize some basic display parameters */ 736 for (i = 0; i < sc->sc_ndisplays; i++) { 737 struct radeonfb_display *dp = &sc->sc_displays[i]; 738 struct rasops_info *ri; 739 long defattr; 740 struct wsemuldisplaydev_attach_args aa; 741 742 /* 743 * Figure out how many "displays" (desktops) we are going to 744 * support. If more than one, then each CRTC gets its own 745 * programming. 746 * 747 * XXX: this code needs to change to support mergedfb. 748 * XXX: would be nice to allow this to be overridden 749 */ 750 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 751 DPRINTF(("dual crtcs!\n")); 752 dp->rd_ncrtcs = 2; 753 dp->rd_crtcs[0].rc_number = 0; 754 dp->rd_crtcs[1].rc_number = 1; 755 } else { 756 dp->rd_ncrtcs = 1; 757 dp->rd_crtcs[0].rc_number = i; 758 } 759 760 /* set up port pointer */ 761 for (j = 0; j < dp->rd_ncrtcs; j++) { 762 dp->rd_crtcs[j].rc_port = 763 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 764 } 765 766 dp->rd_softc = sc; 767 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 768 dp->rd_bg = WS_DEFAULT_BG; 769 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 770 771 /* for text mode, we pick a resolution that won't 772 * require panning */ 773 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 774 775 aprint_normal("%s: display %d: " 776 "initial virtual resolution %dx%d at %d bpp\n", 777 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 778 779 /* now select the *video mode* that we will use */ 780 for (j = 0; j < dp->rd_ncrtcs; j++) { 781 const struct videomode *vmp; 782 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 783 dp->rd_virtx, dp->rd_virty); 784 785 /* 786 * virtual resolution should be at least as high as 787 * physical 788 */ 789 if (dp->rd_virtx < vmp->hdisplay || 790 dp->rd_virty < vmp->vdisplay) { 791 dp->rd_virtx = vmp->hdisplay; 792 dp->rd_virty = vmp->vdisplay; 793 } 794 795 dp->rd_crtcs[j].rc_videomode = *vmp; 796 printf("%s: port %d: physical %dx%d %dHz\n", 797 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 798 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 799 vmp->htotal), vmp->vtotal)); 800 } 801 802 /* N.B.: radeon wants 64-byte aligned stride */ 803 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 804 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 805 DPRINTF(("stride: %d\n", dp->rd_stride)); 806 807 dp->rd_offset = sc->sc_fboffset * i; 808 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 809 sc->sc_memh) + dp->rd_offset; 810 dp->rd_curoff = sc->sc_fbsize; 811 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 812 813 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 814 815 switch (dp->rd_bpp) { 816 case 8: 817 dp->rd_format = 2; 818 break; 819 case 32: 820 dp->rd_format = 6; 821 break; 822 default: 823 aprint_error("%s: bad depth %d\n", XNAME(sc), 824 dp->rd_bpp); 825 goto error; 826 } 827 828 DPRINTF(("init engine\n")); 829 /* XXX: this seems suspicious - per display engine 830 initialization? */ 831 radeonfb_engine_init(dp); 832 833 /* copy the template into place */ 834 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 835 dp->rd_wsscreens = dp->rd_wsscreens_storage; 836 837 /* and make up the list */ 838 dp->rd_wsscreenlist.nscreens = 1; 839 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 840 841 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 842 &radeonfb_accessops); 843 844 dp->rd_vd.init_screen = radeonfb_init_screen; 845 846 #ifdef RADEONFB_DEBUG 847 dp->rd_virty -= 200; 848 #endif 849 850 dp->rd_console = 0; 851 prop_dictionary_get_bool(device_properties(sc->sc_dev), 852 "is_console", &dp->rd_console); 853 854 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 855 856 857 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 858 dp->rd_console, &defattr); 859 860 ri = &dp->rd_vscreen.scr_ri; 861 862 /* clear the screen */ 863 rasops_unpack_attr(defattr, &fg, &bg, &ul); 864 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 865 ri->ri_devcmap[bg & 0xf]); 866 867 dp->rd_wsscreens->textops = &ri->ri_ops; 868 dp->rd_wsscreens->capabilities = ri->ri_caps; 869 dp->rd_wsscreens->nrows = ri->ri_rows; 870 dp->rd_wsscreens->ncols = ri->ri_cols; 871 872 #ifdef SPLASHSCREEN 873 dp->rd_splash.si_depth = ri->ri_depth; 874 dp->rd_splash.si_bits = ri->ri_bits; 875 dp->rd_splash.si_hwbits = ri->ri_hwbits; 876 dp->rd_splash.si_width = ri->ri_width; 877 dp->rd_splash.si_height = ri->ri_height; 878 dp->rd_splash.si_stride = ri->ri_stride; 879 dp->rd_splash.si_fillrect = NULL; 880 #endif 881 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 882 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 883 dp->rd_gc.gc_rop = RADEON_ROP3_S; 884 dp->rd_gc.gc_blitcookie = dp; 885 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 886 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 887 dp->rd_virtx, 888 ri->ri_font->fontwidth, 889 ri->ri_font->fontheight, 890 defattr); 891 if (dp->rd_console) { 892 893 radeonfb_modeswitch(dp); 894 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 895 defattr); 896 #ifdef SPLASHSCREEN 897 if (splash_render(&dp->rd_splash, 898 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 899 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 900 else 901 #endif 902 vcons_replay_msgbuf(&dp->rd_vscreen); 903 } else { 904 905 /* 906 * since we're not the console we can postpone 907 * the rest until someone actually allocates a 908 * screen for us. but we do clear the screen 909 * at least. 910 */ 911 memset(ri->ri_bits, 0, 1024); 912 913 radeonfb_modeswitch(dp); 914 #ifdef SPLASHSCREEN 915 if (splash_render(&dp->rd_splash, 916 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 917 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 918 #endif 919 } 920 921 aa.console = dp->rd_console; 922 aa.scrdata = &dp->rd_wsscreenlist; 923 aa.accessops = &radeonfb_accessops; 924 aa.accesscookie = &dp->rd_vd; 925 926 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 927 928 radeonfb_blank(dp, 0); 929 930 /* Initialise delayed lvds operations for backlight. */ 931 callout_init(&dp->rd_bl_lvds_co, 0); 932 callout_setfunc(&dp->rd_bl_lvds_co, 933 radeonfb_lvds_callout, dp); 934 dp->rd_bl_on = 1; 935 dp->rd_bl_level = radeonfb_get_backlight(dp); 936 radeonfb_set_backlight(dp, dp->rd_bl_level); 937 } 938 939 /* 940 * if we have console output via firmware like on sparc64 it may 941 * interfere with DAC programming so program the palette again 942 * here after we took over 943 */ 944 radeonfb_init_palette(sc, 0); 945 if (HAS_CRTC2(sc)) { 946 radeonfb_init_palette(sc, 1); 947 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 948 } 949 950 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 951 radeonfb_brightness_up, TRUE); 952 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 953 radeonfb_brightness_down, TRUE); 954 955 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 956 957 PRINTREG(RADEON_CRTC_EXT_CNTL); 958 PRINTREG(RADEON_CRTC_GEN_CNTL); 959 PRINTREG(RADEON_CRTC2_GEN_CNTL); 960 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 961 PRINTREG(RADEON_DAC_CNTL2); 962 963 return; 964 965 error: 966 if (sc->sc_biossz) 967 free(sc->sc_bios, M_DEVBUF); 968 969 if (sc->sc_regsz) 970 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 971 972 if (sc->sc_memsz) 973 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 974 } 975 976 static void 977 radeonfb_map(struct radeonfb_softc *sc) 978 { 979 if (!sc->sc_mapped) { 980 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 981 &sc->sc_regh) != 0) { 982 aprint_error_dev(sc->sc_dev, 983 "unable to map registers!\n"); 984 return; 985 } 986 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 987 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 988 sc->sc_memsz = 0; 989 aprint_error_dev(sc->sc_dev, 990 "Unable to map frame buffer\n"); 991 return; 992 } 993 sc->sc_mapped = TRUE; 994 } 995 } 996 997 static void 998 radeonfb_unmap(struct radeonfb_softc *sc) 999 { 1000 if (sc->sc_mapped) { 1001 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1002 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1003 sc->sc_mapped = FALSE; 1004 } 1005 } 1006 1007 static int 1008 radeonfb_drm_print(void *aux, const char *pnp) 1009 { 1010 if (pnp) 1011 aprint_normal("drm at %s", pnp); 1012 return (UNCONF); 1013 } 1014 1015 int 1016 radeonfb_ioctl(void *v, void *vs, 1017 unsigned long cmd, void *d, int flag, struct lwp *l) 1018 { 1019 struct vcons_data *vd; 1020 struct radeonfb_display *dp; 1021 struct radeonfb_softc *sc; 1022 struct wsdisplay_param *param; 1023 1024 vd = (struct vcons_data *)v; 1025 dp = (struct radeonfb_display *)vd->cookie; 1026 sc = dp->rd_softc; 1027 1028 switch (cmd) { 1029 case WSDISPLAYIO_GTYPE: 1030 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1031 return 0; 1032 1033 case WSDISPLAYIO_GINFO: 1034 if (vd->active != NULL) { 1035 struct wsdisplay_fbinfo *fb; 1036 fb = (struct wsdisplay_fbinfo *)d; 1037 fb->width = dp->rd_virtx; 1038 fb->height = dp->rd_virty; 1039 fb->depth = dp->rd_bpp; 1040 fb->cmsize = 256; 1041 return 0; 1042 } else 1043 return ENODEV; 1044 case WSDISPLAYIO_GVIDEO: 1045 if (radeonfb_isblank(dp)) 1046 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1047 else 1048 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1049 return 0; 1050 1051 case WSDISPLAYIO_SVIDEO: 1052 radeonfb_blank(dp, 1053 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1054 return 0; 1055 1056 case WSDISPLAYIO_GETCMAP: 1057 #if 0 1058 if (dp->rd_bpp == 8) 1059 return radeonfb_getcmap(sc, 1060 (struct wsdisplay_cmap *)d); 1061 #endif 1062 return EINVAL; 1063 1064 case WSDISPLAYIO_PUTCMAP: 1065 #if 0 1066 if (dp->rd_bpp == 8) 1067 return radeonfb_putcmap(sc, 1068 (struct wsdisplay_cmap *)d); 1069 #endif 1070 return EINVAL; 1071 1072 case WSDISPLAYIO_LINEBYTES: 1073 *(unsigned *)d = dp->rd_stride; 1074 return 0; 1075 1076 case WSDISPLAYIO_SMODE: 1077 if (*(int *)d != dp->rd_wsmode) { 1078 dp->rd_wsmode = *(int *)d; 1079 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1080 (dp->rd_vd.active)) { 1081 radeonfb_map(sc); 1082 radeonfb_engine_init(dp); 1083 glyphcache_wipe(&dp->rd_gc); 1084 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1085 radeonfb_modeswitch(dp); 1086 vcons_redraw_screen(dp->rd_vd.active); 1087 } else { 1088 radeonfb_unmap(sc); 1089 } 1090 } 1091 return 0; 1092 1093 case WSDISPLAYIO_GCURMAX: 1094 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1095 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1096 return 0; 1097 1098 case WSDISPLAYIO_SCURSOR: 1099 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1100 1101 case WSDISPLAYIO_GCURSOR: 1102 return EPASSTHROUGH; 1103 1104 case WSDISPLAYIO_GCURPOS: 1105 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1106 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1107 return 0; 1108 1109 case WSDISPLAYIO_SCURPOS: 1110 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1111 1112 case WSDISPLAYIO_SSPLASH: 1113 #if defined(SPLASHSCREEN) 1114 if (*(int *)d == 1) { 1115 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1116 splash_render(&dp->rd_splash, 1117 SPLASH_F_CENTER|SPLASH_F_FILL); 1118 } else 1119 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1120 return 0; 1121 #else 1122 return ENODEV; 1123 #endif 1124 case WSDISPLAYIO_GETPARAM: 1125 param = (struct wsdisplay_param *)d; 1126 switch (param->param) { 1127 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1128 param->min = 0; 1129 param->max = 255; 1130 param->curval = dp->rd_bl_level; 1131 return 0; 1132 case WSDISPLAYIO_PARAM_BACKLIGHT: 1133 param->min = 0; 1134 param->max = RADEONFB_BACKLIGHT_MAX; 1135 param->curval = dp->rd_bl_on; 1136 return 0; 1137 } 1138 return EPASSTHROUGH; 1139 1140 case WSDISPLAYIO_SETPARAM: 1141 param = (struct wsdisplay_param *)d; 1142 switch (param->param) { 1143 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1144 radeonfb_set_backlight(dp, param->curval); 1145 return 0; 1146 case WSDISPLAYIO_PARAM_BACKLIGHT: 1147 radeonfb_switch_backlight(dp, param->curval); 1148 return 0; 1149 } 1150 return EPASSTHROUGH; 1151 1152 /* PCI config read/write passthrough. */ 1153 case PCI_IOC_CFGREAD: 1154 case PCI_IOC_CFGWRITE: 1155 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1156 1157 case WSDISPLAYIO_GET_BUSID: 1158 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1159 sc->sc_pt, d); 1160 1161 case WSDISPLAYIO_GET_EDID: { 1162 struct wsdisplayio_edid_info *ei = d; 1163 return wsdisplayio_get_edid(sc->sc_dev, ei); 1164 } 1165 1166 default: 1167 return EPASSTHROUGH; 1168 } 1169 } 1170 1171 paddr_t 1172 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1173 { 1174 struct vcons_data *vd; 1175 struct radeonfb_display *dp; 1176 struct radeonfb_softc *sc; 1177 paddr_t pa; 1178 1179 vd = (struct vcons_data *)v; 1180 dp = (struct radeonfb_display *)vd->cookie; 1181 sc = dp->rd_softc; 1182 1183 /* XXX: note that we don't allow mapping of registers right now */ 1184 /* XXX: this means that the XFree86 radeon driver won't work */ 1185 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1186 pa = bus_space_mmap(sc->sc_memt, 1187 sc->sc_memaddr + dp->rd_offset + offset, 0, 1188 prot, BUS_SPACE_MAP_LINEAR); 1189 return pa; 1190 } 1191 1192 #ifdef RADEONFB_MMAP_BARS 1193 /* 1194 * restrict all other mappings to processes with superuser privileges 1195 * or the kernel itself 1196 */ 1197 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1198 NULL, NULL, NULL, NULL) != 0) { 1199 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1200 return -1; 1201 } 1202 1203 if ((offset >= sc->sc_regaddr) && 1204 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1205 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1206 BUS_SPACE_MAP_LINEAR); 1207 } 1208 1209 if ((offset >= sc->sc_memaddr) && 1210 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1211 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1212 BUS_SPACE_MAP_LINEAR); 1213 } 1214 1215 if ((offset >= sc->sc_romaddr) && 1216 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1217 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1218 BUS_SPACE_MAP_LINEAR); 1219 } 1220 1221 #ifdef PCI_MAGIC_IO_RANGE 1222 /* allow mapping of IO space */ 1223 if ((offset >= PCI_MAGIC_IO_RANGE) && 1224 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1225 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1226 0, prot, 0); 1227 return pa; 1228 } 1229 #endif /* PCI_MAGIC_IO_RANGE */ 1230 1231 #endif /* RADEONFB_MMAP_BARS */ 1232 1233 return -1; 1234 } 1235 1236 static void 1237 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1238 { 1239 bus_space_tag_t romt; 1240 bus_space_handle_t romh, biosh; 1241 bus_size_t romsz; 1242 bus_addr_t ptr; 1243 1244 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1245 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1246 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1247 return; 1248 } 1249 1250 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1251 &sc->sc_biossz); 1252 if (sc->sc_biossz == 0) { 1253 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1254 return; 1255 } 1256 1257 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1258 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1259 1260 /* unmap the PCI expansion rom */ 1261 bus_space_unmap(romt, romh, romsz); 1262 1263 /* turn off rom decoder now */ 1264 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1265 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1266 ~PCI_MAPREG_ROM_ENABLE); 1267 1268 ptr = GETBIOS16(sc, 0x48); 1269 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1270 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1271 sc->sc_flags |= RFB_ATOM; 1272 } 1273 1274 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1275 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1276 } 1277 1278 1279 uint32_t 1280 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1281 { 1282 1283 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1284 } 1285 1286 void 1287 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1288 { 1289 1290 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1291 } 1292 1293 void 1294 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1295 { 1296 1297 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1298 } 1299 1300 void 1301 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1302 uint32_t andmask, uint32_t ormask) 1303 { 1304 int s; 1305 uint32_t val; 1306 1307 s = splhigh(); 1308 val = radeonfb_get32(sc, reg); 1309 val = (val & andmask) | ormask; 1310 radeonfb_put32(sc, reg, val); 1311 splx(s); 1312 } 1313 1314 uint32_t 1315 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1316 { 1317 int s; 1318 uint32_t val; 1319 1320 s = splhigh(); 1321 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1322 val = radeonfb_get32(sc, RADEON_MM_DATA); 1323 splx(s); 1324 1325 return (val); 1326 } 1327 1328 void 1329 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1330 { 1331 int s; 1332 1333 s = splhigh(); 1334 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1335 radeonfb_put32(sc, RADEON_MM_DATA, val); 1336 splx(s); 1337 } 1338 1339 void 1340 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1341 uint32_t andmask, uint32_t ormask) 1342 { 1343 int s; 1344 uint32_t val; 1345 1346 s = splhigh(); 1347 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1348 val = radeonfb_get32(sc, RADEON_MM_DATA); 1349 val = (val & andmask) | ormask; 1350 radeonfb_put32(sc, RADEON_MM_DATA, val); 1351 splx(s); 1352 } 1353 1354 uint32_t 1355 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1356 { 1357 int s; 1358 uint32_t val; 1359 1360 s = splhigh(); 1361 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1362 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1363 if (HAS_R300CG(sc)) 1364 radeonfb_r300cg_workaround(sc); 1365 splx(s); 1366 1367 return (val); 1368 } 1369 1370 void 1371 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1372 { 1373 int s; 1374 1375 s = splhigh(); 1376 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1377 RADEON_PLL_WR_EN); 1378 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1379 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1380 splx(s); 1381 } 1382 1383 void 1384 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1385 uint32_t andmask, uint32_t ormask) 1386 { 1387 int s; 1388 uint32_t val; 1389 1390 s = splhigh(); 1391 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1392 RADEON_PLL_WR_EN); 1393 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1394 val = (val & andmask) | ormask; 1395 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1396 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1397 splx(s); 1398 } 1399 1400 int 1401 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1402 { 1403 uint32_t saved; 1404 1405 saved = GET32(sc, reg); 1406 PUT32(sc, reg, v); 1407 if (GET32(sc, reg) != v) { 1408 return -1; 1409 } 1410 PUT32(sc, reg, saved); 1411 return 0; 1412 } 1413 1414 uintmax_t 1415 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1416 uintmax_t defval) 1417 { 1418 prop_number_t pn; 1419 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1420 if (pn == NULL) { 1421 return defval; 1422 } 1423 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1424 return (prop_number_integer_value(pn)); 1425 } 1426 1427 int 1428 radeonfb_getclocks(struct radeonfb_softc *sc) 1429 { 1430 bus_addr_t ptr; 1431 int refclk = 0; 1432 int refdiv = 0; 1433 int minpll = 0; 1434 int maxpll = 0; 1435 1436 /* load initial property values if port/board provides them */ 1437 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1438 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1439 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1440 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1441 1442 if (refclk && refdiv && minpll && maxpll) 1443 goto dontprobe; 1444 1445 if (!sc->sc_biossz) { 1446 /* no BIOS */ 1447 aprint_verbose("%s: No video BIOS, using default clocks\n", 1448 XNAME(sc)); 1449 if (IS_IGP(sc)) 1450 refclk = refclk ? refclk : 1432; 1451 else 1452 refclk = refclk ? refclk : 2700; 1453 refdiv = refdiv ? refdiv : 12; 1454 minpll = minpll ? minpll : 12500; 1455 maxpll = maxpll ? maxpll : 35000; 1456 } else if (IS_ATOM(sc)) { 1457 /* ATOM BIOS */ 1458 ptr = GETBIOS16(sc, 0x48); 1459 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1460 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1461 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1462 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1463 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1464 /* 1465 * ATOM BIOS doesn't supply a reference divider, so we 1466 * have to probe for it. 1467 */ 1468 if (refdiv < 2) 1469 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1470 RADEON_PPLL_REF_DIV_MASK; 1471 /* 1472 * if probe is zero, just assume one that should work 1473 * for most parts 1474 */ 1475 if (refdiv < 2) 1476 refdiv = 12; 1477 1478 } else { 1479 /* Legacy BIOS */ 1480 ptr = GETBIOS16(sc, 0x48); 1481 ptr = GETBIOS16(sc, ptr + 0x30); 1482 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1483 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1484 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1485 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1486 } 1487 1488 1489 dontprobe: 1490 sc->sc_refclk = refclk * 10; 1491 sc->sc_refdiv = refdiv; 1492 sc->sc_minpll = minpll * 10; 1493 sc->sc_maxpll = maxpll * 10; 1494 return 0; 1495 } 1496 1497 int 1498 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1499 uint32_t *postdivbit, uint32_t *feedbackdiv) 1500 { 1501 int i; 1502 uint32_t outfreq; 1503 int div; 1504 1505 DPRINTF(("dot clock: %u\n", dotclock)); 1506 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1507 outfreq = div * dotclock; 1508 if ((outfreq >= sc->sc_minpll) && 1509 (outfreq <= sc->sc_maxpll)) { 1510 DPRINTF(("outfreq: %u\n", outfreq)); 1511 *postdivbit = 1512 ((uint32_t)radeonfb_dividers[i].mask << 16); 1513 DPRINTF(("post divider: %d (mask %x)\n", div, 1514 *postdivbit)); 1515 break; 1516 } 1517 } 1518 1519 if (div == 0) 1520 return 1; 1521 1522 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1523 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1524 return 0; 1525 } 1526 1527 #if 0 1528 #ifdef RADEONFB_DEBUG 1529 static void 1530 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1531 { 1532 char asc[17]; 1533 unsigned ptr = (unsigned)buffer; 1534 char *start = (char *)(ptr & ~0xf); 1535 char *end = (char *)(ptr + size); 1536 1537 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1538 1539 if (pfx == NULL) { 1540 pfx = ""; 1541 } 1542 1543 while (start < end) { 1544 unsigned offset = (unsigned)start & 0xf; 1545 if (offset == 0) { 1546 printf("%s%x: ", pfx, (unsigned)start); 1547 } 1548 if (((unsigned)start < ptr) || 1549 ((unsigned)start >= (ptr + size))) { 1550 printf(" "); 1551 asc[offset] = ' '; 1552 } else { 1553 printf("%02x", *(unsigned char *)start); 1554 if ((*start >= ' ') && (*start <= '~')) { 1555 asc[offset] = *start; 1556 } else { 1557 asc[offset] = '.'; 1558 } 1559 } 1560 asc[offset + 1] = 0; 1561 if (offset % 2) { 1562 printf(" "); 1563 } 1564 if (offset == 15) { 1565 printf(" %s\n", asc); 1566 } 1567 start++; 1568 } 1569 } 1570 #endif 1571 #endif 1572 1573 int 1574 radeonfb_getconnectors(struct radeonfb_softc *sc) 1575 { 1576 int i; 1577 int found = 0; 1578 1579 for (i = 0; i < 2; i++) { 1580 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1581 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1582 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1583 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1584 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1585 } 1586 1587 /* 1588 * This logic is borrowed from Xorg's radeon driver. 1589 */ 1590 if (!sc->sc_biossz) 1591 goto nobios; 1592 1593 if (IS_ATOM(sc)) { 1594 /* not done yet */ 1595 } else { 1596 uint16_t ptr; 1597 int port = 0; 1598 1599 ptr = GETBIOS16(sc, 0x48); 1600 ptr = GETBIOS16(sc, ptr + 0x50); 1601 for (i = 1; i < 4; i++) { 1602 uint16_t entry; 1603 uint8_t conn, ddc, dac, tmds; 1604 1605 /* 1606 * Parse the connector table. From reading the code, 1607 * it appears to made up of 16-bit entries for each 1608 * connector. The 16-bits are defined as: 1609 * 1610 * bits 12-15 - connector type (0 == end of table) 1611 * bits 8-11 - DDC type 1612 * bits 5-7 - ??? 1613 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1614 * bits 1-3 - ??? 1615 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1616 */ 1617 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1618 break; 1619 entry = GETBIOS16(sc, ptr + i * 2); 1620 1621 conn = (entry >> 12) & 0xf; 1622 ddc = (entry >> 8) & 0xf; 1623 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1624 RADEON_DAC_PRIMARY; 1625 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1626 RADEON_TMDS_INT; 1627 1628 if (conn == RADEON_CONN_NONE) 1629 continue; /* no connector */ 1630 1631 if ((found > 0) && 1632 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1633 /* duplicate entry for same connector */ 1634 continue; 1635 } 1636 1637 /* internal DDC_DVI port gets priority */ 1638 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1639 port = 0; 1640 else 1641 port = 1; 1642 1643 sc->sc_ports[port].rp_ddc_type = 1644 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1645 sc->sc_ports[port].rp_dac_type = dac; 1646 sc->sc_ports[port].rp_conn_type = 1647 min(conn, RADEON_CONN_UNSUPPORTED) ; 1648 1649 sc->sc_ports[port].rp_tmds_type = tmds; 1650 1651 if ((conn != RADEON_CONN_DVI_I) && 1652 (conn != RADEON_CONN_DVI_D) && 1653 (tmds == RADEON_TMDS_INT)) 1654 sc->sc_ports[port].rp_tmds_type = 1655 RADEON_TMDS_UNKNOWN; 1656 1657 found += (port + 1); 1658 } 1659 } 1660 1661 nobios: 1662 if (!found) { 1663 DPRINTF(("No connector info in BIOS!\n")); 1664 /* default, port 0 = internal TMDS, port 1 = CRT */ 1665 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1666 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1667 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1668 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1669 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1670 1671 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1672 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1673 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1674 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1675 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1676 } 1677 1678 /* 1679 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1680 * these chips should use TVDAC for the VGA port. 1681 */ 1682 if (HAS_SDAC(sc)) { 1683 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1684 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1685 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1686 } else { 1687 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1688 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1689 } 1690 } else if (!HAS_CRTC2(sc)) { 1691 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1692 } 1693 1694 for (i = 0; i < 2; i++) { 1695 char edid[128]; 1696 uint8_t ddc; 1697 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1698 prop_data_t edid_data; 1699 1700 DPRINTF(("Port #%d:\n", i)); 1701 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1702 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1703 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1704 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1705 1706 sc->sc_ports[i].rp_edid_valid = 0; 1707 /* first look for static EDID data */ 1708 if ((edid_data = prop_dictionary_get(device_properties( 1709 sc->sc_dev), "EDID")) != NULL) { 1710 1711 aprint_normal_dev(sc->sc_dev, "using static EDID\n"); 1712 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1713 if (edid_parse(edid, eip) == 0) { 1714 1715 sc->sc_ports[i].rp_edid_valid = 1; 1716 } 1717 } 1718 /* if we didn't find any we'll try to talk to the monitor */ 1719 if (sc->sc_ports[i].rp_edid_valid != 1) { 1720 1721 ddc = sc->sc_ports[i].rp_ddc_type; 1722 if (ddc != RADEON_DDC_NONE) { 1723 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1724 == 0) && (edid_parse(edid, eip) == 0)) { 1725 1726 sc->sc_ports[i].rp_edid_valid = 1; 1727 #ifdef RADEONFB_DEBUG 1728 edid_print(eip); 1729 #endif 1730 } 1731 } 1732 } 1733 } 1734 1735 return found; 1736 } 1737 1738 int 1739 radeonfb_gettmds(struct radeonfb_softc *sc) 1740 { 1741 int i; 1742 1743 if (!sc->sc_biossz) { 1744 goto nobios; 1745 } 1746 1747 if (IS_ATOM(sc)) { 1748 /* XXX: not done yet */ 1749 } else { 1750 uint16_t ptr; 1751 int n; 1752 1753 ptr = GETBIOS16(sc, 0x48); 1754 ptr = GETBIOS16(sc, ptr + 0x34); 1755 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1756 if (GETBIOS8(sc, ptr) == 3) { 1757 /* revision three table */ 1758 n = GETBIOS8(sc, ptr + 5) + 1; 1759 n = min(n, 4); 1760 1761 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1762 for (i = 0; i < n; i++) { 1763 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1764 ptr + i * 10 + 8); 1765 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1766 ptr + i * 10 + 0x10); 1767 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1768 sc->sc_tmds_pll[i].rtp_freq, 1769 sc->sc_tmds_pll[i].rtp_pll)); 1770 } 1771 return 0; 1772 } 1773 } 1774 1775 nobios: 1776 DPRINTF(("no suitable DFP table present\n")); 1777 for (i = 0; 1778 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1779 i++) { 1780 int j; 1781 1782 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1783 continue; 1784 1785 for (j = 0; j < 4; j++) { 1786 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1787 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1788 sc->sc_tmds_pll[j].rtp_freq, 1789 sc->sc_tmds_pll[j].rtp_pll)); 1790 } 1791 return 0; 1792 } 1793 1794 return -1; 1795 } 1796 1797 const struct videomode * 1798 radeonfb_modelookup(const char *name) 1799 { 1800 int i; 1801 1802 for (i = 0; i < videomode_count; i++) 1803 if (!strcmp(name, videomode_list[i].name)) 1804 return &videomode_list[i]; 1805 1806 return NULL; 1807 } 1808 1809 void 1810 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1811 { 1812 if (crtc) { 1813 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1814 RADEON_P2PLL_ATOMIC_UPDATE_R); 1815 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1816 } else { 1817 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1818 RADEON_PPLL_ATOMIC_UPDATE_R); 1819 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1820 } 1821 } 1822 1823 void 1824 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1825 { 1826 int i; 1827 1828 for (i = 10000; i; i--) { 1829 if (crtc) { 1830 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1831 RADEON_P2PLL_ATOMIC_UPDATE_R) 1832 break; 1833 } else { 1834 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1835 RADEON_PPLL_ATOMIC_UPDATE_R) 1836 break; 1837 } 1838 } 1839 } 1840 1841 void 1842 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1843 { 1844 uint32_t pbit = 0; 1845 uint32_t feed = 0; 1846 uint32_t data; 1847 #if 1 1848 int i; 1849 #endif 1850 1851 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1852 1853 if (crtc == 0) { 1854 1855 /* XXXX: mobility workaround missing */ 1856 /* XXXX: R300 stuff missing */ 1857 1858 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1859 RADEON_VCLK_SRC_SEL_CPUCLK, 1860 ~RADEON_VCLK_SRC_SEL_MASK); 1861 1862 /* put vclk into reset, use atomic updates */ 1863 SETPLL(sc, RADEON_PPLL_CNTL, 1864 RADEON_PPLL_REFCLK_SEL | 1865 RADEON_PPLL_FBCLK_SEL | 1866 RADEON_PPLL_RESET | 1867 RADEON_PPLL_ATOMIC_UPDATE_EN | 1868 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1869 1870 /* select clock 3 */ 1871 #if 0 1872 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1873 ~RADEON_PLL_DIV_SEL); 1874 #else 1875 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1876 ~RADEON_PLL_DIV_SEL); 1877 #endif 1878 1879 /* XXX: R300 family -- program divider differently? */ 1880 1881 /* program reference divider */ 1882 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1883 ~RADEON_PPLL_REF_DIV_MASK); 1884 PRINTPLL(RADEON_PPLL_REF_DIV); 1885 1886 #if 0 1887 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1888 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1889 RADEON_PPLL_POST3_DIV_MASK); 1890 data |= pbit; 1891 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1892 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1893 #else 1894 for (i = 0; i < 4; i++) { 1895 } 1896 #endif 1897 1898 /* use the atomic update */ 1899 radeonfb_pllwriteupdate(sc, crtc); 1900 1901 /* and wait for it to complete */ 1902 radeonfb_pllwaitatomicread(sc, crtc); 1903 1904 /* program HTOTAL (why?) */ 1905 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1906 1907 /* drop reset */ 1908 CLRPLL(sc, RADEON_PPLL_CNTL, 1909 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1910 RADEON_PPLL_ATOMIC_UPDATE_EN | 1911 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1912 1913 PRINTPLL(RADEON_PPLL_CNTL); 1914 1915 /* give clock time to lock */ 1916 delay(50000); 1917 1918 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1919 RADEON_VCLK_SRC_SEL_PPLLCLK, 1920 ~RADEON_VCLK_SRC_SEL_MASK); 1921 1922 } else { 1923 1924 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1925 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1926 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1927 1928 /* put vclk into reset, use atomic updates */ 1929 SETPLL(sc, RADEON_P2PLL_CNTL, 1930 RADEON_P2PLL_RESET | 1931 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1932 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1933 1934 /* XXX: R300 family -- program divider differently? */ 1935 1936 /* program reference divider */ 1937 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1938 ~RADEON_P2PLL_REF_DIV_MASK); 1939 1940 /* program feedback and post dividers */ 1941 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1942 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1943 RADEON_P2PLL_POST0_DIV_MASK); 1944 data |= pbit; 1945 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1946 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1947 1948 /* use the atomic update */ 1949 radeonfb_pllwriteupdate(sc, crtc); 1950 1951 /* and wait for it to complete */ 1952 radeonfb_pllwaitatomicread(sc, crtc); 1953 1954 /* program HTOTAL (why?) */ 1955 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1956 1957 /* drop reset */ 1958 CLRPLL(sc, RADEON_P2PLL_CNTL, 1959 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1960 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1961 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1962 1963 /* allow time for clock to lock */ 1964 delay(50000); 1965 1966 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1967 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1968 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1969 } 1970 PRINTREG(RADEON_CRTC_MORE_CNTL); 1971 } 1972 1973 void 1974 radeonfb_modeswitch(struct radeonfb_display *dp) 1975 { 1976 struct radeonfb_softc *sc = dp->rd_softc; 1977 int i; 1978 1979 /* blank the display while we switch modes */ 1980 radeonfb_blank(dp, 1); 1981 1982 #if 0 1983 SET32(sc, RADEON_CRTC_EXT_CNTL, 1984 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1985 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1986 #endif 1987 1988 /* these registers might get in the way... */ 1989 PUT32(sc, RADEON_OVR_CLR, 0); 1990 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1991 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1992 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1993 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1994 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1995 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1996 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1997 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1998 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1999 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2000 2001 for (i = 0; i < dp->rd_ncrtcs; i++) 2002 radeonfb_setcrtc(dp, i); 2003 2004 /* activate the display */ 2005 radeonfb_blank(dp, 0); 2006 } 2007 2008 void 2009 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2010 { 2011 int crtc; 2012 struct videomode *mode; 2013 struct radeonfb_softc *sc; 2014 struct radeonfb_crtc *cp; 2015 uint32_t v; 2016 uint32_t gencntl; 2017 uint32_t htotaldisp; 2018 uint32_t hsyncstrt; 2019 uint32_t vtotaldisp; 2020 uint32_t vsyncstrt; 2021 uint32_t fphsyncstrt; 2022 uint32_t fpvsyncstrt; 2023 uint32_t fphtotaldisp; 2024 uint32_t fpvtotaldisp; 2025 uint32_t pitch; 2026 2027 sc = dp->rd_softc; 2028 cp = &dp->rd_crtcs[index]; 2029 crtc = cp->rc_number; 2030 mode = &cp->rc_videomode; 2031 2032 #if 1 2033 pitch = dp->rd_stride / dp->rd_bpp; 2034 #else 2035 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2036 (sc->sc_maxbpp * 8)); 2037 #endif 2038 switch (crtc) { 2039 case 0: 2040 gencntl = RADEON_CRTC_GEN_CNTL; 2041 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2042 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2043 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2044 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2045 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2046 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2047 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2048 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2049 break; 2050 case 1: 2051 gencntl = RADEON_CRTC2_GEN_CNTL; 2052 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2053 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2054 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2055 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2056 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2057 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2058 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2059 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2060 break; 2061 default: 2062 panic("Bad CRTC!"); 2063 break; 2064 } 2065 2066 /* 2067 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2068 */ 2069 /* only bother with 32bpp and 8bpp */ 2070 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2071 2072 if (crtc == 1) { 2073 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2074 } else { 2075 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2076 } 2077 2078 if (mode->flags & VID_DBLSCAN) 2079 v |= RADEON_CRTC2_DBL_SCAN_EN; 2080 2081 if (mode->flags & VID_INTERLACE) 2082 v |= RADEON_CRTC2_INTERLACE_EN; 2083 2084 if (mode->flags & VID_CSYNC) { 2085 v |= RADEON_CRTC2_CSYNC_EN; 2086 if (crtc == 1) 2087 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2088 } 2089 2090 PUT32(sc, gencntl, v); 2091 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2092 2093 /* 2094 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2095 */ 2096 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2097 if (crtc == 0) { 2098 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2099 RADEON_CRTC_DISPLAY_DIS); 2100 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2101 if (mode->flags & VID_CSYNC) 2102 v |= RADEON_CRTC_VSYNC_TRISTAT; 2103 } 2104 /* unconditional turn on CRT, in case first CRTC is DFP */ 2105 v |= RADEON_CRTC_CRT_ON; 2106 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2107 PRINTREG(RADEON_CRTC_EXT_CNTL); 2108 2109 /* 2110 * H_TOTAL_DISP 2111 */ 2112 v = ((mode->hdisplay / 8) - 1) << 16; 2113 v |= (mode->htotal / 8) - 1; 2114 PUT32(sc, htotaldisp, v); 2115 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2116 PUT32(sc, fphtotaldisp, v); 2117 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2118 2119 /* 2120 * H_SYNC_STRT_WID 2121 */ 2122 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2123 v |= mode->hsync_start; 2124 if (mode->flags & VID_NHSYNC) 2125 v |= RADEON_CRTC_H_SYNC_POL; 2126 PUT32(sc, hsyncstrt, v); 2127 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2128 PUT32(sc, fphsyncstrt, v); 2129 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2130 2131 /* 2132 * V_TOTAL_DISP 2133 */ 2134 v = ((mode->vdisplay - 1) << 16); 2135 v |= (mode->vtotal - 1); 2136 PUT32(sc, vtotaldisp, v); 2137 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2138 PUT32(sc, fpvtotaldisp, v); 2139 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2140 2141 /* 2142 * V_SYNC_STRT_WID 2143 */ 2144 v = ((mode->vsync_end - mode->vsync_start) << 16); 2145 v |= (mode->vsync_start - 1); 2146 if (mode->flags & VID_NVSYNC) 2147 v |= RADEON_CRTC_V_SYNC_POL; 2148 PUT32(sc, vsyncstrt, v); 2149 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2150 PUT32(sc, fpvsyncstrt, v); 2151 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2152 2153 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2154 2155 switch (crtc) { 2156 case 0: 2157 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2158 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2159 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2160 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2161 2162 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2163 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2164 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2165 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2166 PRINTREG(RADEON_CRTC_EXT_CNTL); 2167 PRINTREG(RADEON_CRTC_GEN_CNTL); 2168 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2169 break; 2170 2171 case 1: 2172 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2173 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2174 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2175 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2176 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2177 RADEON_CRTC2_VSYNC_DIS | 2178 RADEON_CRTC2_HSYNC_DIS | 2179 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2180 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2181 break; 2182 } 2183 } 2184 2185 int 2186 radeonfb_isblank(struct radeonfb_display *dp) 2187 { 2188 uint32_t reg, mask; 2189 2190 if(!dp->rd_softc->sc_mapped) 2191 return 1; 2192 2193 if (dp->rd_crtcs[0].rc_number) { 2194 reg = RADEON_CRTC2_GEN_CNTL; 2195 mask = RADEON_CRTC2_DISP_DIS; 2196 } else { 2197 reg = RADEON_CRTC_EXT_CNTL; 2198 mask = RADEON_CRTC_DISPLAY_DIS; 2199 } 2200 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2201 } 2202 2203 void 2204 radeonfb_blank(struct radeonfb_display *dp, int blank) 2205 { 2206 struct radeonfb_softc *sc = dp->rd_softc; 2207 uint32_t reg, mask; 2208 uint32_t fpreg, fpval; 2209 int i; 2210 2211 if (!sc->sc_mapped) 2212 return; 2213 2214 for (i = 0; i < dp->rd_ncrtcs; i++) { 2215 2216 if (dp->rd_crtcs[i].rc_number) { 2217 reg = RADEON_CRTC2_GEN_CNTL; 2218 mask = RADEON_CRTC2_DISP_DIS; 2219 fpreg = RADEON_FP2_GEN_CNTL; 2220 fpval = RADEON_FP2_ON; 2221 } else { 2222 reg = RADEON_CRTC_EXT_CNTL; 2223 mask = RADEON_CRTC_DISPLAY_DIS; 2224 fpreg = RADEON_FP_GEN_CNTL; 2225 fpval = RADEON_FP_FPON; 2226 } 2227 2228 if (blank) { 2229 SET32(sc, reg, mask); 2230 CLR32(sc, fpreg, fpval); 2231 } else { 2232 CLR32(sc, reg, mask); 2233 SET32(sc, fpreg, fpval); 2234 } 2235 } 2236 PRINTREG(RADEON_FP_GEN_CNTL); 2237 PRINTREG(RADEON_FP2_GEN_CNTL); 2238 } 2239 2240 void 2241 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2242 long *defattr) 2243 { 2244 struct radeonfb_display *dp = cookie; 2245 struct rasops_info *ri = &scr->scr_ri; 2246 2247 /* initialize font subsystem */ 2248 wsfont_init(); 2249 2250 DPRINTF(("init screen called, existing %d\n", existing)); 2251 2252 ri->ri_depth = dp->rd_bpp; 2253 ri->ri_width = dp->rd_virtx; 2254 ri->ri_height = dp->rd_virty; 2255 ri->ri_stride = dp->rd_stride; 2256 ri->ri_flg = RI_CENTER; 2257 switch (ri->ri_depth) { 2258 case 8: 2259 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2260 break; 2261 case 32: 2262 ri->ri_flg |= RI_ENABLE_ALPHA; 2263 /* we run radeons in RGB even on SPARC hardware */ 2264 ri->ri_rnum = 8; 2265 ri->ri_gnum = 8; 2266 ri->ri_bnum = 8; 2267 ri->ri_rpos = 16; 2268 ri->ri_gpos = 8; 2269 ri->ri_bpos = 0; 2270 break; 2271 } 2272 2273 ri->ri_bits = (void *)dp->rd_fbptr; 2274 2275 #ifdef VCONS_DRAW_INTR 2276 scr->scr_flags |= VCONS_DONT_READ; 2277 #endif 2278 2279 if (existing) { 2280 ri->ri_flg |= RI_CLEAR; 2281 2282 /* start a modeswitch now */ 2283 radeonfb_modeswitch(dp); 2284 } 2285 2286 /* 2287 * XXX: font selection should be based on properties, with some 2288 * normal/reasonable default. 2289 */ 2290 2291 /* initialize and look for an initial font */ 2292 rasops_init(ri, 0, 0); 2293 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2294 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2295 2296 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2297 dp->rd_virtx / ri->ri_font->fontwidth); 2298 2299 /* enable acceleration */ 2300 dp->rd_putchar = ri->ri_ops.putchar; 2301 ri->ri_ops.copyrows = radeonfb_copyrows; 2302 ri->ri_ops.copycols = radeonfb_copycols; 2303 ri->ri_ops.eraserows = radeonfb_eraserows; 2304 ri->ri_ops.erasecols = radeonfb_erasecols; 2305 /* pick a putchar method based on font and Radeon model */ 2306 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2307 /* got a bitmap font */ 2308 if (IS_R300(dp->rd_softc)) { 2309 /* 2310 * radeonfb_putchar() doesn't work right on some R3xx 2311 * so we use software drawing here, the wrapper just 2312 * makes sure the engine is idle before scribbling 2313 * into vram 2314 */ 2315 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2316 } else { 2317 ri->ri_ops.putchar = radeonfb_putchar; 2318 } 2319 } else { 2320 /* got an alpha font */ 2321 switch(ri->ri_depth) { 2322 case 32: 2323 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2324 break; 2325 case 8: 2326 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2327 break; 2328 default: 2329 /* XXX this should never happen */ 2330 panic("%s: depth is not 8 or 32 but we got an" \ 2331 " alpha font?!", __func__); 2332 } 2333 } 2334 ri->ri_ops.cursor = radeonfb_cursor; 2335 } 2336 2337 void 2338 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2339 { 2340 uint32_t gen, ext, gen2 = 0; 2341 uint32_t agploc, aperbase, apersize, mcfbloc; 2342 2343 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2344 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2345 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2346 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2347 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2348 2349 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2350 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2351 #if 0 2352 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2353 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2354 #endif 2355 2356 if (HAS_CRTC2(sc)) { 2357 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2358 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2359 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2360 } 2361 2362 delay(100000); 2363 2364 mcfbloc = (aperbase >> 16) | 2365 ((aperbase + (apersize - 1)) & 0xffff0000); 2366 2367 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2368 sc->sc_memsz = apersize; 2369 2370 if (((agploc & 0xffff) << 16) != 2371 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2372 agploc = mcfbloc & 0xffff0000U; 2373 agploc |= ((agploc + 0x10000) >> 16); 2374 } 2375 2376 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2377 2378 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2379 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2380 2381 DPRINTF(("aperbase = %u\n", aperbase)); 2382 PRINTREG(RADEON_MC_FB_LOCATION); 2383 PRINTREG(RADEON_MC_AGP_LOCATION); 2384 2385 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2386 2387 if (HAS_CRTC2(sc)) 2388 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2389 2390 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2391 2392 #if 0 2393 /* XXX: what is this AGP garbage? :-) */ 2394 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2395 #endif 2396 2397 delay(100000); 2398 2399 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2400 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2401 2402 if (HAS_CRTC2(sc)) 2403 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2404 } 2405 2406 void 2407 radeonfb_init_misc(struct radeonfb_softc *sc) 2408 { 2409 PUT32(sc, RADEON_BUS_CNTL, 2410 RADEON_BUS_MASTER_DIS | 2411 RADEON_BUS_PREFETCH_MODE_ACT | 2412 RADEON_BUS_PCI_READ_RETRY_EN | 2413 RADEON_BUS_PCI_WRT_RETRY_EN | 2414 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2415 RADEON_BUS_MSTR_RD_MULT | 2416 RADEON_BUS_MSTR_RD_LINE | 2417 RADEON_BUS_RD_DISCARD_EN | 2418 RADEON_BUS_MSTR_DISCONNECT_EN | 2419 RADEON_BUS_READ_BURST); 2420 2421 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2422 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2423 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2424 PUT32(sc, RADEON_RBBM_CNTL, 2425 (3 << RADEON_RB_SETTLE_SHIFT) | 2426 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2427 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2428 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2429 2430 /* XXX: figure out what these mean! */ 2431 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2432 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2433 #if 0 2434 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2435 #endif 2436 2437 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2438 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2439 } 2440 2441 /* 2442 * This loads a linear color map for true color. 2443 */ 2444 void 2445 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2446 { 2447 int i; 2448 uint32_t vclk; 2449 2450 #define DAC_WIDTH ((1 << 10) - 1) 2451 #define CLUT_WIDTH ((1 << 8) - 1) 2452 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2453 2454 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2455 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2456 2457 if (crtc) 2458 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2459 else 2460 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2461 2462 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2463 if (sc->sc_displays[crtc].rd_bpp == 0) 2464 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2465 2466 if (sc->sc_displays[crtc].rd_bpp == 8) { 2467 /* ANSI palette */ 2468 int j = 0; 2469 uint32_t tmp, r, g, b; 2470 2471 for (i = 0; i <= CLUT_WIDTH; ++i) { 2472 tmp = i & 0xe0; 2473 /* 2474 * replicate bits so 0xe0 maps to a red value of 0xff 2475 * in order to make white look actually white 2476 */ 2477 tmp |= (tmp >> 3) | (tmp >> 6); 2478 r = tmp; 2479 2480 tmp = (i & 0x1c) << 3; 2481 tmp |= (tmp >> 3) | (tmp >> 6); 2482 g = tmp; 2483 2484 tmp = (i & 0x03) << 6; 2485 tmp |= tmp >> 2; 2486 tmp |= tmp >> 4; 2487 b = tmp; 2488 PUT32(sc, RADEON_PALETTE_30_DATA, 2489 (r << 22) | 2490 (g << 12) | 2491 (b << 2)); 2492 j += 3; 2493 } 2494 } else { 2495 /* linear ramp */ 2496 for (i = 0; i <= CLUT_WIDTH; ++i) { 2497 PUT32(sc, RADEON_PALETTE_30_DATA, 2498 (CLUT_COLOR(i) << 10) | 2499 (CLUT_COLOR(i) << 20) | 2500 (CLUT_COLOR(i))); 2501 } 2502 } 2503 2504 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2505 PRINTREG(RADEON_DAC_CNTL2); 2506 2507 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2508 } 2509 2510 /* 2511 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2512 */ 2513 void 2514 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2515 { 2516 uint32_t tmp, save; 2517 2518 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2519 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2520 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2521 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2522 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2523 } 2524 2525 /* 2526 * Acceleration entry points. 2527 */ 2528 2529 /* this one draws characters using bitmap fonts */ 2530 static void 2531 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2532 { 2533 struct rasops_info *ri = cookie; 2534 struct vcons_screen *scr = ri->ri_hw; 2535 struct radeonfb_display *dp = scr->scr_cookie; 2536 struct radeonfb_softc *sc = dp->rd_softc; 2537 struct wsdisplay_font *font = PICK_FONT(ri, c); 2538 uint32_t w, h; 2539 int xd, yd, offset, i; 2540 uint32_t bg, fg, gmc; 2541 uint32_t reg; 2542 uint8_t *data8; 2543 uint16_t *data16; 2544 void *data; 2545 2546 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2547 return; 2548 2549 if (!CHAR_IN_FONT(c, font)) 2550 return; 2551 2552 w = font->fontwidth; 2553 h = font->fontheight; 2554 2555 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2556 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2557 2558 xd = ri->ri_xorigin + col * w; 2559 yd = ri->ri_yorigin + row * h; 2560 2561 if (c == 0x20) { 2562 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2563 return; 2564 } 2565 data = WSFONT_GLYPH(c, font); 2566 2567 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2568 2569 radeonfb_wait_fifo(sc, 9); 2570 2571 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2572 RADEON_GMC_BRUSH_NONE | 2573 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2574 RADEON_GMC_DST_CLIPPING | 2575 RADEON_ROP3_S | 2576 RADEON_DP_SRC_SOURCE_HOST_DATA | 2577 RADEON_GMC_CLR_CMP_CNTL_DIS | 2578 RADEON_GMC_WR_MSK_DIS | 2579 gmc); 2580 2581 PUT32(sc, RADEON_SC_LEFT, xd); 2582 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2583 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2584 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2585 PUT32(sc, RADEON_DP_CNTL, 2586 RADEON_DST_X_LEFT_TO_RIGHT | 2587 RADEON_DST_Y_TOP_TO_BOTTOM); 2588 2589 PUT32(sc, RADEON_SRC_X_Y, 0); 2590 offset = 32 - (font->stride << 3); 2591 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2592 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2593 2594 radeonfb_wait_fifo(sc, h); 2595 switch (font->stride) { 2596 case 1: { 2597 data8 = data; 2598 for (i = 0; i < h; i++) { 2599 reg = *data8; 2600 #if BYTE_ORDER == LITTLE_ENDIAN 2601 reg = reg << 24; 2602 #endif 2603 bus_space_write_stream_4(sc->sc_regt, 2604 sc->sc_regh, RADEON_HOST_DATA0, reg); 2605 data8++; 2606 } 2607 break; 2608 } 2609 case 2: { 2610 data16 = data; 2611 for (i = 0; i < h; i++) { 2612 reg = *data16; 2613 #if BYTE_ORDER == LITTLE_ENDIAN 2614 reg = reg << 16; 2615 #endif 2616 bus_space_write_stream_4(sc->sc_regt, 2617 sc->sc_regh, RADEON_HOST_DATA0, reg); 2618 data16++; 2619 } 2620 break; 2621 } 2622 } 2623 if (attr & 1) 2624 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2625 } 2626 2627 /* ... while this one is for anti-aliased ones */ 2628 static void 2629 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2630 { 2631 struct rasops_info *ri = cookie; 2632 struct vcons_screen *scr = ri->ri_hw; 2633 struct radeonfb_display *dp = scr->scr_cookie; 2634 struct radeonfb_softc *sc = dp->rd_softc; 2635 struct wsdisplay_font *font = PICK_FONT(ri, c); 2636 uint32_t bg, fg, gmc; 2637 uint8_t *data; 2638 int w, h, xd, yd; 2639 int i, r, g, b, aval; 2640 int rf, gf, bf, rb, gb, bb; 2641 uint32_t pixel; 2642 int rv; 2643 2644 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2645 return; 2646 2647 if (!CHAR_IN_FONT(c, font)) 2648 return; 2649 2650 w = font->fontwidth; 2651 h = font->fontheight; 2652 2653 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2654 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2655 2656 xd = ri->ri_xorigin + col * w; 2657 yd = ri->ri_yorigin + row * h; 2658 2659 if (c == 0x20) { 2660 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2661 if (attr & 1) 2662 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2663 return; 2664 } 2665 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2666 if (rv == GC_OK) 2667 return; 2668 2669 data = WSFONT_GLYPH(c, font); 2670 2671 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2672 2673 radeonfb_wait_fifo(sc, 5); 2674 2675 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2676 RADEON_GMC_BRUSH_NONE | 2677 RADEON_GMC_SRC_DATATYPE_COLOR | 2678 RADEON_ROP3_S | 2679 RADEON_DP_SRC_SOURCE_HOST_DATA | 2680 RADEON_GMC_CLR_CMP_CNTL_DIS | 2681 RADEON_GMC_WR_MSK_DIS | 2682 gmc); 2683 2684 PUT32(sc, RADEON_DP_CNTL, 2685 RADEON_DST_X_LEFT_TO_RIGHT | 2686 RADEON_DST_Y_TOP_TO_BOTTOM); 2687 2688 PUT32(sc, RADEON_SRC_X_Y, 0); 2689 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2690 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2691 2692 rf = (fg >> 16) & 0xff; 2693 rb = (bg >> 16) & 0xff; 2694 gf = (fg >> 8) & 0xff; 2695 gb = (bg >> 8) & 0xff; 2696 bf = fg & 0xff; 2697 bb = bg & 0xff; 2698 2699 /* 2700 * I doubt we can upload data faster than even the slowest Radeon 2701 * could process them, especially when doing the alpha blending stuff 2702 * along the way, so just make sure there's some room in the FIFO and 2703 * then hammer away 2704 * As it turns out we can, so make periodic stops to let the FIFO 2705 * drain. 2706 */ 2707 radeonfb_wait_fifo(sc, 20); 2708 for (i = 0; i < ri->ri_fontscale; i++) { 2709 aval = *data; 2710 data++; 2711 if (aval == 0) { 2712 pixel = bg; 2713 } else if (aval == 255) { 2714 pixel = fg; 2715 } else { 2716 r = aval * rf + (255 - aval) * rb; 2717 g = aval * gf + (255 - aval) * gb; 2718 b = aval * bf + (255 - aval) * bb; 2719 pixel = (r & 0xff00) << 8 | 2720 (g & 0xff00) | 2721 (b & 0xff00) >> 8; 2722 } 2723 if (i & 16) 2724 radeonfb_wait_fifo(sc, 20); 2725 PUT32(sc, RADEON_HOST_DATA0, pixel); 2726 } 2727 if (rv == GC_ADD) { 2728 glyphcache_add(&dp->rd_gc, c, xd, yd); 2729 } else 2730 if (attr & 1) 2731 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2732 2733 } 2734 2735 static void 2736 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2737 { 2738 struct rasops_info *ri = cookie; 2739 struct vcons_screen *scr = ri->ri_hw; 2740 struct radeonfb_display *dp = scr->scr_cookie; 2741 struct radeonfb_softc *sc = dp->rd_softc; 2742 struct wsdisplay_font *font = PICK_FONT(ri, c); 2743 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2744 int i, x, y, wi, he, r, g, b, aval; 2745 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2746 uint8_t *data8; 2747 int rv, cnt; 2748 2749 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2750 return; 2751 2752 if (!CHAR_IN_FONT(c, font)) 2753 return; 2754 2755 wi = font->fontwidth; 2756 he = font->fontheight; 2757 2758 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2759 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2760 2761 x = ri->ri_xorigin + col * wi; 2762 y = ri->ri_yorigin + row * he; 2763 2764 if (c == 0x20) { 2765 radeonfb_rectfill(dp, x, y, wi, he, bg); 2766 if (attr & 1) 2767 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2768 return; 2769 } 2770 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2771 if (rv == GC_OK) 2772 return; 2773 2774 data8 = WSFONT_GLYPH(c, font); 2775 2776 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2777 2778 radeonfb_wait_fifo(sc, 5); 2779 2780 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2781 RADEON_GMC_BRUSH_NONE | 2782 RADEON_GMC_SRC_DATATYPE_COLOR | 2783 RADEON_ROP3_S | 2784 RADEON_DP_SRC_SOURCE_HOST_DATA | 2785 RADEON_GMC_CLR_CMP_CNTL_DIS | 2786 RADEON_GMC_WR_MSK_DIS | 2787 gmc); 2788 2789 PUT32(sc, RADEON_DP_CNTL, 2790 RADEON_DST_X_LEFT_TO_RIGHT | 2791 RADEON_DST_Y_TOP_TO_BOTTOM); 2792 2793 PUT32(sc, RADEON_SRC_X_Y, 0); 2794 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2795 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2796 2797 /* 2798 * we need the RGB colours here, so get offsets into rasops_cmap 2799 */ 2800 fgo = ((attr >> 24) & 0xf) * 3; 2801 bgo = ((attr >> 16) & 0xf) * 3; 2802 2803 r0 = rasops_cmap[bgo]; 2804 r1 = rasops_cmap[fgo]; 2805 g0 = rasops_cmap[bgo + 1]; 2806 g1 = rasops_cmap[fgo + 1]; 2807 b0 = rasops_cmap[bgo + 2]; 2808 b1 = rasops_cmap[fgo + 2]; 2809 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2810 bg8 = R3G3B2(r0, g0, b0); 2811 fg8 = R3G3B2(r1, g1, b1); 2812 2813 radeonfb_wait_fifo(sc, 20); 2814 cnt = 0; 2815 for (i = 0; i < ri->ri_fontscale; i++) { 2816 aval = *data8; 2817 if (aval == 0) { 2818 pixel = bg8; 2819 } else if (aval == 255) { 2820 pixel = fg8; 2821 } else { 2822 r = aval * r1 + (255 - aval) * r0; 2823 g = aval * g1 + (255 - aval) * g0; 2824 b = aval * b1 + (255 - aval) * b0; 2825 pixel = ((r & 0xe000) >> 8) | 2826 ((g & 0xe000) >> 11) | 2827 ((b & 0xc000) >> 14); 2828 } 2829 latch |= pixel << (8 * (i & 3)); 2830 /* write in 32bit chunks */ 2831 if ((i & 3) == 3) { 2832 PUT32(sc, RADEON_HOST_DATA0, latch); 2833 /* 2834 * not strictly necessary, old data should be shifted 2835 * out 2836 */ 2837 latch = 0; 2838 cnt++; 2839 if (cnt > 16) { 2840 cnt = 0; 2841 radeonfb_wait_fifo(sc, 20); 2842 } 2843 } 2844 data8++; 2845 } 2846 /* if we have pixels left in latch write them out */ 2847 if ((i & 3) != 0) { 2848 /* 2849 * radeon is weird - apparently leftover pixels are written 2850 * from the middle, not from the left as everything else 2851 */ 2852 PUT32(sc, RADEON_HOST_DATA0, latch); 2853 } 2854 2855 if (rv == GC_ADD) { 2856 glyphcache_add(&dp->rd_gc, c, x, y); 2857 } else 2858 if (attr & 1) 2859 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2860 2861 } 2862 2863 /* 2864 * wrapper for software character drawing 2865 * just sync the engine and call rasops*_putchar() 2866 */ 2867 2868 static void 2869 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2870 { 2871 struct rasops_info *ri = cookie; 2872 struct vcons_screen *scr = ri->ri_hw; 2873 struct radeonfb_display *dp = scr->scr_cookie; 2874 2875 radeonfb_engine_idle(dp->rd_softc); 2876 dp->rd_putchar(ri, row, col, c, attr); 2877 } 2878 2879 static void 2880 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2881 { 2882 struct rasops_info *ri = cookie; 2883 struct vcons_screen *scr = ri->ri_hw; 2884 struct radeonfb_display *dp = scr->scr_cookie; 2885 uint32_t x, y, w, h, fg, bg, ul; 2886 2887 /* XXX: check for full emulation mode? */ 2888 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2889 x = ri->ri_xorigin; 2890 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2891 w = ri->ri_emuwidth; 2892 h = ri->ri_font->fontheight * nrows; 2893 2894 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2895 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2896 } 2897 } 2898 2899 static void 2900 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2901 { 2902 struct rasops_info *ri = cookie; 2903 struct vcons_screen *scr = ri->ri_hw; 2904 struct radeonfb_display *dp = scr->scr_cookie; 2905 uint32_t x, ys, yd, w, h; 2906 2907 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2908 x = ri->ri_xorigin; 2909 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2910 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2911 w = ri->ri_emuwidth; 2912 h = ri->ri_font->fontheight * nrows; 2913 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2914 RADEON_ROP3_S); 2915 } 2916 } 2917 2918 static void 2919 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2920 { 2921 struct rasops_info *ri = cookie; 2922 struct vcons_screen *scr = ri->ri_hw; 2923 struct radeonfb_display *dp = scr->scr_cookie; 2924 uint32_t xs, xd, y, w, h; 2925 2926 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2927 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2928 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2929 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2930 w = ri->ri_font->fontwidth * ncols; 2931 h = ri->ri_font->fontheight; 2932 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2933 RADEON_ROP3_S); 2934 } 2935 } 2936 2937 static void 2938 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2939 long fillattr) 2940 { 2941 struct rasops_info *ri = cookie; 2942 struct vcons_screen *scr = ri->ri_hw; 2943 struct radeonfb_display *dp = scr->scr_cookie; 2944 uint32_t x, y, w, h, fg, bg, ul; 2945 2946 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2947 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2948 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2949 w = ri->ri_font->fontwidth * ncols; 2950 h = ri->ri_font->fontheight; 2951 2952 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2953 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2954 } 2955 } 2956 2957 static void 2958 radeonfb_cursor(void *cookie, int on, int row, int col) 2959 { 2960 struct rasops_info *ri = cookie; 2961 struct vcons_screen *scr = ri->ri_hw; 2962 struct radeonfb_display *dp = scr->scr_cookie; 2963 int x, y, wi, he; 2964 2965 wi = ri->ri_font->fontwidth; 2966 he = ri->ri_font->fontheight; 2967 2968 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2969 x = ri->ri_ccol * wi + ri->ri_xorigin; 2970 y = ri->ri_crow * he + ri->ri_yorigin; 2971 /* first turn off the old cursor */ 2972 if (ri->ri_flg & RI_CURSOR) { 2973 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2974 RADEON_ROP3_Dn); 2975 ri->ri_flg &= ~RI_CURSOR; 2976 } 2977 ri->ri_crow = row; 2978 ri->ri_ccol = col; 2979 /* then (possibly) turn on the new one */ 2980 if (on) { 2981 x = ri->ri_ccol * wi + ri->ri_xorigin; 2982 y = ri->ri_crow * he + ri->ri_yorigin; 2983 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2984 RADEON_ROP3_Dn); 2985 ri->ri_flg |= RI_CURSOR; 2986 } 2987 } else { 2988 scr->scr_ri.ri_crow = row; 2989 scr->scr_ri.ri_ccol = col; 2990 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2991 } 2992 } 2993 2994 /* 2995 * Underlying acceleration support. 2996 */ 2997 2998 static void 2999 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3000 int width, int height, uint32_t color) 3001 { 3002 struct radeonfb_softc *sc = dp->rd_softc; 3003 uint32_t gmc; 3004 3005 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3006 3007 radeonfb_wait_fifo(sc, 6); 3008 3009 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3010 RADEON_GMC_BRUSH_SOLID_COLOR | 3011 RADEON_GMC_SRC_DATATYPE_COLOR | 3012 RADEON_GMC_CLR_CMP_CNTL_DIS | 3013 RADEON_ROP3_P | gmc); 3014 3015 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3016 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3017 PUT32(sc, RADEON_DP_CNTL, 3018 RADEON_DST_X_LEFT_TO_RIGHT | 3019 RADEON_DST_Y_TOP_TO_BOTTOM); 3020 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3021 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3022 3023 } 3024 3025 static void 3026 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3027 int width, int height, long attr) 3028 { 3029 struct radeonfb_display *dp = cookie; 3030 3031 radeonfb_rectfill(dp, dstx, dsty, width, height, 3032 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3033 } 3034 3035 static void 3036 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3037 int dstx, int dsty, int width, int height, int rop) 3038 { 3039 struct radeonfb_display *dp = cookie; 3040 struct radeonfb_softc *sc = dp->rd_softc; 3041 uint32_t gmc; 3042 uint32_t dir; 3043 3044 if (dsty < srcy) { 3045 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3046 } else { 3047 srcy += height - 1; 3048 dsty += height - 1; 3049 dir = 0; 3050 } 3051 if (dstx < srcx) { 3052 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3053 } else { 3054 srcx += width - 1; 3055 dstx += width - 1; 3056 } 3057 3058 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3059 3060 radeonfb_wait_fifo(sc, 6); 3061 3062 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3063 RADEON_GMC_BRUSH_SOLID_COLOR | 3064 RADEON_GMC_SRC_DATATYPE_COLOR | 3065 RADEON_GMC_CLR_CMP_CNTL_DIS | 3066 RADEON_DP_SRC_SOURCE_MEMORY | 3067 rop | gmc); 3068 3069 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3070 PUT32(sc, RADEON_DP_CNTL, dir); 3071 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3072 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3073 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3074 } 3075 3076 static void 3077 radeonfb_engine_idle(struct radeonfb_softc *sc) 3078 { 3079 3080 radeonfb_wait_fifo(sc, 64); 3081 while ((GET32(sc, RADEON_RBBM_STATUS) & 3082 RADEON_RBBM_ACTIVE) != 0); 3083 radeonfb_engine_flush(sc); 3084 } 3085 3086 static inline void 3087 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3088 { 3089 int i; 3090 3091 for (i = RADEON_TIMEOUT; i; i--) { 3092 if ((GET32(sc, RADEON_RBBM_STATUS) & 3093 RADEON_RBBM_FIFOCNT_MASK) >= n) 3094 return; 3095 } 3096 #ifdef DIAGNOSTIC 3097 if (!i) 3098 printf("%s: timed out waiting for fifo (%x)\n", 3099 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3100 #endif 3101 } 3102 3103 static void 3104 radeonfb_engine_flush(struct radeonfb_softc *sc) 3105 { 3106 int i = 0; 3107 3108 if (IS_R300(sc)) { 3109 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3110 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3111 i++; 3112 } 3113 } else { 3114 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3115 RADEON_RB2D_DC_FLUSH_ALL); 3116 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3117 RADEON_RB2D_DC_BUSY) { 3118 i++; 3119 } 3120 } 3121 #ifdef DIAGNOSTIC 3122 if (i > RADEON_TIMEOUT) 3123 printf("%s: engine flush timed out!\n", XNAME(sc)); 3124 #endif 3125 } 3126 3127 static inline void 3128 radeonfb_unclip(struct radeonfb_softc *sc) 3129 { 3130 3131 radeonfb_wait_fifo(sc, 2); 3132 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3133 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3134 } 3135 3136 static void 3137 radeonfb_engine_init(struct radeonfb_display *dp) 3138 { 3139 struct radeonfb_softc *sc = dp->rd_softc; 3140 uint32_t pitch; 3141 volatile uint32_t junk; 3142 3143 /* no 3D */ 3144 PUT32(sc, RADEON_RB3D_CNTL, 0); 3145 3146 radeonfb_engine_reset(sc); 3147 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3148 3149 radeonfb_wait_fifo(sc, 1); 3150 if (!IS_R300(sc)) 3151 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3152 3153 radeonfb_wait_fifo(sc, 3); 3154 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3155 (pitch << 22) | (sc->sc_aperbase >> 10)); 3156 3157 3158 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3159 (pitch << 22) | (sc->sc_aperbase >> 10)); 3160 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3161 (pitch << 22) | (sc->sc_aperbase >> 10)); 3162 3163 junk = GET32(sc, RADEON_DP_DATATYPE); 3164 3165 /* default scissors -- no clipping */ 3166 radeonfb_wait_fifo(sc, 1); 3167 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3168 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3169 3170 radeonfb_wait_fifo(sc, 1); 3171 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3172 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3173 RADEON_GMC_CLR_CMP_CNTL_DIS | 3174 RADEON_GMC_BRUSH_SOLID_COLOR | 3175 RADEON_GMC_SRC_DATATYPE_COLOR); 3176 3177 radeonfb_wait_fifo(sc, 10); 3178 PUT32(sc, RADEON_DST_LINE_START, 0); 3179 PUT32(sc, RADEON_DST_LINE_END, 0); 3180 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3181 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3182 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3183 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3184 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3185 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3186 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3187 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3188 radeonfb_engine_idle(sc); 3189 } 3190 3191 static void 3192 radeonfb_engine_reset(struct radeonfb_softc *sc) 3193 { 3194 uint32_t hpc, rbbm, mclkcntl, clkindex; 3195 3196 radeonfb_engine_flush(sc); 3197 3198 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3199 if (HAS_R300CG(sc)) 3200 radeonfb_r300cg_workaround(sc); 3201 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3202 3203 /* 3204 * According to comments in XFree code, resetting the HDP via 3205 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3206 * So we use HOST_PATH_CNTL instead. 3207 */ 3208 3209 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3210 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3211 if (IS_R300(sc)) { 3212 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3213 RADEON_SOFT_RESET_CP | 3214 RADEON_SOFT_RESET_HI | 3215 RADEON_SOFT_RESET_E2); 3216 GET32(sc, RADEON_RBBM_SOFT_RESET); 3217 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3218 /* 3219 * XXX: this bit is not defined in any ATI docs I have, 3220 * nor in the XFree code, but XFree does it. Why? 3221 */ 3222 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3223 } else { 3224 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3225 RADEON_SOFT_RESET_CP | 3226 RADEON_SOFT_RESET_SE | 3227 RADEON_SOFT_RESET_RE | 3228 RADEON_SOFT_RESET_PP | 3229 RADEON_SOFT_RESET_E2 | 3230 RADEON_SOFT_RESET_RB); 3231 GET32(sc, RADEON_RBBM_SOFT_RESET); 3232 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3233 ~(RADEON_SOFT_RESET_CP | 3234 RADEON_SOFT_RESET_SE | 3235 RADEON_SOFT_RESET_RE | 3236 RADEON_SOFT_RESET_PP | 3237 RADEON_SOFT_RESET_E2 | 3238 RADEON_SOFT_RESET_RB)); 3239 GET32(sc, RADEON_RBBM_SOFT_RESET); 3240 } 3241 3242 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3243 GET32(sc, RADEON_HOST_PATH_CNTL); 3244 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3245 3246 if (IS_R300(sc)) 3247 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3248 3249 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3250 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3251 3252 if (HAS_R300CG(sc)) 3253 radeonfb_r300cg_workaround(sc); 3254 } 3255 3256 static int 3257 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3258 { 3259 int x, y; 3260 3261 x = pos->x; 3262 y = pos->y; 3263 3264 /* 3265 * This doesn't let a cursor move off the screen. I'm not 3266 * sure if this will have negative effects for e.g. Xinerama. 3267 * I'd guess Xinerama handles it by changing the cursor shape, 3268 * but that needs verification. 3269 */ 3270 if (x >= dp->rd_virtx) 3271 x = dp->rd_virtx - 1; 3272 if (x < 0) 3273 x = 0; 3274 if (y >= dp->rd_virty) 3275 y = dp->rd_virty - 1; 3276 if (y < 0) 3277 y = 0; 3278 3279 dp->rd_cursor.rc_pos.x = x; 3280 dp->rd_cursor.rc_pos.y = y; 3281 3282 radeonfb_cursor_position(dp); 3283 return 0; 3284 } 3285 3286 static int 3287 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3288 { 3289 unsigned flags; 3290 3291 uint8_t r[2], g[2], b[2]; 3292 unsigned index, count; 3293 int i, err; 3294 int pitch, size; 3295 struct radeonfb_cursor nc; 3296 3297 flags = wc->which; 3298 3299 /* copy old values */ 3300 nc = dp->rd_cursor; 3301 3302 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3303 index = wc->cmap.index; 3304 count = wc->cmap.count; 3305 3306 if (index >= 2 || (index + count) > 2) 3307 return EINVAL; 3308 3309 err = copyin(wc->cmap.red, &r[index], count); 3310 if (err) 3311 return err; 3312 err = copyin(wc->cmap.green, &g[index], count); 3313 if (err) 3314 return err; 3315 err = copyin(wc->cmap.blue, &b[index], count); 3316 if (err) 3317 return err; 3318 3319 for (i = index; i < index + count; i++) { 3320 nc.rc_cmap[i] = 3321 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3322 } 3323 } 3324 3325 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3326 if ((wc->size.x > RADEON_CURSORMAXX) || 3327 (wc->size.y > RADEON_CURSORMAXY)) 3328 return EINVAL; 3329 3330 /* figure bytes per line */ 3331 pitch = (wc->size.x + 7) / 8; 3332 size = pitch * wc->size.y; 3333 3334 /* clear the old cursor and mask */ 3335 memset(nc.rc_image, 0, 512); 3336 memset(nc.rc_mask, 0, 512); 3337 3338 nc.rc_size = wc->size; 3339 3340 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3341 return err; 3342 3343 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3344 return err; 3345 } 3346 3347 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3348 nc.rc_hot = wc->hot; 3349 if (nc.rc_hot.x >= nc.rc_size.x) 3350 nc.rc_hot.x = nc.rc_size.x - 1; 3351 if (nc.rc_hot.y >= nc.rc_size.y) 3352 nc.rc_hot.y = nc.rc_size.y - 1; 3353 } 3354 3355 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3356 nc.rc_pos = wc->pos; 3357 if (nc.rc_pos.x >= dp->rd_virtx) 3358 nc.rc_pos.x = dp->rd_virtx - 1; 3359 #if 0 3360 if (nc.rc_pos.x < 0) 3361 nc.rc_pos.x = 0; 3362 #endif 3363 if (nc.rc_pos.y >= dp->rd_virty) 3364 nc.rc_pos.y = dp->rd_virty - 1; 3365 #if 0 3366 if (nc.rc_pos.y < 0) 3367 nc.rc_pos.y = 0; 3368 #endif 3369 } 3370 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3371 nc.rc_visible = wc->enable; 3372 } 3373 3374 dp->rd_cursor = nc; 3375 radeonfb_cursor_update(dp, wc->which); 3376 3377 return 0; 3378 } 3379 3380 /* 3381 * Change the cursor shape. Call this with the cursor locked to avoid 3382 * flickering/tearing. 3383 */ 3384 static void 3385 radeonfb_cursor_shape(struct radeonfb_display *dp) 3386 { 3387 uint8_t and[512], xor[512]; 3388 int i, j, src, dst, pitch; 3389 const uint8_t *msk = dp->rd_cursor.rc_mask; 3390 const uint8_t *img = dp->rd_cursor.rc_image; 3391 3392 /* 3393 * Radeon cursor data interleaves one line of AND data followed 3394 * by a line of XOR data. (Each line corresponds to a whole hardware 3395 * pitch - i.e. 64 pixels or 8 bytes.) 3396 * 3397 * The cursor is displayed using the following table: 3398 * 3399 * AND XOR Result 3400 * ---------------------- 3401 * 0 0 Cursor color 0 3402 * 0 1 Cursor color 1 3403 * 1 0 Transparent 3404 * 1 1 Complement of background 3405 * 3406 * Our masks are therefore different from what we were passed. 3407 * Passed in, I'm assuming the data represents either color 0 or 1, 3408 * and a mask, so the passed in table looks like: 3409 * 3410 * IMG Mask Result 3411 * ----------------------- 3412 * 0 0 Transparent 3413 * 0 1 Cursor color 0 3414 * 1 0 Transparent 3415 * 1 1 Cursor color 1 3416 * 3417 * IF mask bit == 1, AND = 0, XOR = color. 3418 * IF mask bit == 0, AND = 1, XOR = 0. 3419 * 3420 * hence: AND = ~(mask); XOR = color & ~(mask); 3421 */ 3422 3423 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3424 3425 /* start by assuming all bits are transparent */ 3426 memset(and, 0xff, 512); 3427 memset(xor, 0x00, 512); 3428 3429 src = 0; 3430 dst = 0; 3431 for (i = 0; i < 64; i++) { 3432 for (j = 0; j < 64; j += 8) { 3433 if ((i < dp->rd_cursor.rc_size.y) && 3434 (j < dp->rd_cursor.rc_size.x)) { 3435 3436 /* take care to leave odd bits alone */ 3437 and[dst] &= ~(msk[src]); 3438 xor[dst] = img[src] & msk[src]; 3439 src++; 3440 } 3441 dst++; 3442 } 3443 } 3444 3445 /* copy the image into place */ 3446 for (i = 0; i < 64; i++) { 3447 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3448 &and[i * 8], 8); 3449 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3450 &xor[i * 8], 8); 3451 } 3452 } 3453 3454 static void 3455 radeonfb_cursor_position(struct radeonfb_display *dp) 3456 { 3457 struct radeonfb_softc *sc = dp->rd_softc; 3458 uint32_t offset, hvoff, hvpos; /* registers */ 3459 uint32_t coff; /* cursor offset */ 3460 int i, x, y, xoff, yoff, crtcoff; 3461 3462 /* 3463 * XXX: this also needs to handle pan/scan 3464 */ 3465 for (i = 0; i < dp->rd_ncrtcs; i++) { 3466 3467 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3468 3469 if (rcp->rc_number) { 3470 offset = RADEON_CUR2_OFFSET; 3471 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3472 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3473 crtcoff = RADEON_CRTC2_OFFSET; 3474 } else { 3475 offset = RADEON_CUR_OFFSET; 3476 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3477 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3478 crtcoff = RADEON_CRTC_OFFSET; 3479 } 3480 3481 x = dp->rd_cursor.rc_pos.x; 3482 y = dp->rd_cursor.rc_pos.y; 3483 3484 while (y < rcp->rc_yoffset) { 3485 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3486 } 3487 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3488 rcp->rc_yoffset += RADEON_PANINCREMENT; 3489 } 3490 while (x < rcp->rc_xoffset) { 3491 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3492 } 3493 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3494 rcp->rc_xoffset += RADEON_PANINCREMENT; 3495 } 3496 3497 /* adjust for the cursor's hotspot */ 3498 x -= dp->rd_cursor.rc_hot.x; 3499 y -= dp->rd_cursor.rc_hot.y; 3500 xoff = yoff = 0; 3501 3502 if (x >= dp->rd_virtx) 3503 x = dp->rd_virtx - 1; 3504 if (y >= dp->rd_virty) 3505 y = dp->rd_virty - 1; 3506 3507 /* now adjust cursor so it is relative to viewport */ 3508 x -= rcp->rc_xoffset; 3509 y -= rcp->rc_yoffset; 3510 3511 /* 3512 * no need to check for fall off, because we should 3513 * never move off the screen entirely! 3514 */ 3515 coff = 0; 3516 if (x < 0) { 3517 xoff = -x; 3518 x = 0; 3519 } 3520 if (y < 0) { 3521 yoff = -y; 3522 y = 0; 3523 coff = (yoff * 2) * 8; 3524 } 3525 3526 /* pan the display */ 3527 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3528 rcp->rc_xoffset); 3529 3530 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3531 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3532 /* NB: this unlocks the cursor */ 3533 PUT32(sc, hvpos, (x << 16) | y); 3534 } 3535 } 3536 3537 static void 3538 radeonfb_cursor_visible(struct radeonfb_display *dp) 3539 { 3540 int i; 3541 uint32_t gencntl, bit; 3542 3543 for (i = 0; i < dp->rd_ncrtcs; i++) { 3544 if (dp->rd_crtcs[i].rc_number) { 3545 gencntl = RADEON_CRTC2_GEN_CNTL; 3546 bit = RADEON_CRTC2_CUR_EN; 3547 } else { 3548 gencntl = RADEON_CRTC_GEN_CNTL; 3549 bit = RADEON_CRTC_CUR_EN; 3550 } 3551 3552 if (dp->rd_cursor.rc_visible) 3553 SET32(dp->rd_softc, gencntl, bit); 3554 else 3555 CLR32(dp->rd_softc, gencntl, bit); 3556 } 3557 } 3558 3559 static void 3560 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3561 { 3562 int i; 3563 uint32_t c0reg, c1reg; 3564 struct radeonfb_softc *sc = dp->rd_softc; 3565 3566 for (i = 0; i < dp->rd_ncrtcs; i++) { 3567 if (dp->rd_crtcs[i].rc_number) { 3568 c0reg = RADEON_CUR2_CLR0; 3569 c1reg = RADEON_CUR2_CLR1; 3570 } else { 3571 c0reg = RADEON_CUR_CLR0; 3572 c1reg = RADEON_CUR_CLR1; 3573 } 3574 3575 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3576 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3577 } 3578 } 3579 3580 static void 3581 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3582 { 3583 struct radeonfb_softc *sc; 3584 int i; 3585 3586 sc = dp->rd_softc; 3587 for (i = 0; i < dp->rd_ncrtcs; i++) { 3588 if (dp->rd_crtcs[i].rc_number) { 3589 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3590 } else { 3591 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3592 } 3593 } 3594 3595 if (which & WSDISPLAY_CURSOR_DOCMAP) 3596 radeonfb_cursor_cmap(dp); 3597 3598 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3599 radeonfb_cursor_shape(dp); 3600 3601 if (which & WSDISPLAY_CURSOR_DOCUR) 3602 radeonfb_cursor_visible(dp); 3603 3604 /* this one is unconditional, because it updates other stuff */ 3605 radeonfb_cursor_position(dp); 3606 } 3607 3608 static struct videomode * 3609 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3610 { 3611 int r1, r2; 3612 3613 /* otherwise pick the higher refresh rate */ 3614 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3615 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3616 3617 return (r1 < r2 ? m2 : m1); 3618 } 3619 3620 static const struct videomode * 3621 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3622 int x, int y) 3623 { 3624 struct edid_info *ep = &rp->rp_edid; 3625 struct videomode *vmp = NULL; 3626 int i; 3627 3628 if (!rp->rp_edid_valid) { 3629 /* fallback to safe mode */ 3630 return radeonfb_modelookup(sc->sc_defaultmode); 3631 } 3632 3633 /* always choose the preferred mode first! */ 3634 if (ep->edid_preferred_mode) { 3635 3636 /* XXX: add auto-stretching support for native mode */ 3637 3638 /* this may want panning to occur, btw */ 3639 if ((ep->edid_preferred_mode->hdisplay <= x) && 3640 (ep->edid_preferred_mode->vdisplay <= y)) 3641 return ep->edid_preferred_mode; 3642 } 3643 3644 for (i = 0; i < ep->edid_nmodes; i++) { 3645 /* 3646 * We elect to pick a resolution that is too large for 3647 * the monitor than one that is too small. This means 3648 * that we will prefer to pan rather than to try to 3649 * center a smaller display on a larger screen. In 3650 * practice, this shouldn't matter because if a 3651 * monitor can support a larger resolution, it can 3652 * probably also support the smaller. A specific 3653 * exception is fixed format panels, but hopefully 3654 * they are properly dealt with by the "autostretch" 3655 * logic above. 3656 */ 3657 if ((ep->edid_modes[i].hdisplay > x) || 3658 (ep->edid_modes[i].vdisplay > y)) { 3659 continue; 3660 } 3661 3662 /* 3663 * at this point, the display mode is no larger than 3664 * what we've requested. 3665 */ 3666 if (vmp == NULL) 3667 vmp = &ep->edid_modes[i]; 3668 3669 /* eliminate smaller modes */ 3670 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3671 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3672 continue; 3673 3674 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3675 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3676 vmp = &ep->edid_modes[i]; 3677 continue; 3678 } 3679 3680 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3681 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3682 3683 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3684 } 3685 3686 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3687 } 3688 3689 static int 3690 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3691 { 3692 int i; 3693 3694 for (i = 0; i < nlist; i++) { 3695 if ((x == list[i].hdisplay) && 3696 (y == list[i].vdisplay)) { 3697 return 1; 3698 } 3699 } 3700 return 0; 3701 } 3702 3703 static void 3704 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3705 int pan) 3706 { 3707 struct radeonfb_port *rp; 3708 struct edid_info *ep; 3709 int i, j; 3710 3711 *x = 0; 3712 *y = 0; 3713 3714 if (pan) { 3715 for (i = 0; i < dp->rd_ncrtcs; i++) { 3716 rp = dp->rd_crtcs[i].rc_port; 3717 ep = &rp->rp_edid; 3718 if (!rp->rp_edid_valid) { 3719 /* monitor not present */ 3720 continue; 3721 } 3722 3723 /* 3724 * For now we are ignoring "conflict" that 3725 * could occur when mixing some modes like 3726 * 1280x1024 and 1400x800. It isn't clear 3727 * which is better, so the first one wins. 3728 */ 3729 for (j = 0; j < ep->edid_nmodes; j++) { 3730 /* 3731 * ignore resolutions that are too big for 3732 * the radeon 3733 */ 3734 if (ep->edid_modes[j].hdisplay > 3735 dp->rd_softc->sc_maxx) 3736 continue; 3737 if (ep->edid_modes[j].vdisplay > 3738 dp->rd_softc->sc_maxy) 3739 continue; 3740 3741 /* 3742 * pick largest resolution, the 3743 * smaller monitor will pan 3744 */ 3745 if ((ep->edid_modes[j].hdisplay >= *x) && 3746 (ep->edid_modes[j].vdisplay >= *y)) { 3747 *x = ep->edid_modes[j].hdisplay; 3748 *y = ep->edid_modes[j].vdisplay; 3749 } 3750 } 3751 } 3752 3753 } else { 3754 struct videomode modes[64]; 3755 int nmodes = 0; 3756 int valid = 0; 3757 3758 for (i = 0; i < dp->rd_ncrtcs; i++) { 3759 /* 3760 * pick the largest resolution in common. 3761 */ 3762 rp = dp->rd_crtcs[i].rc_port; 3763 ep = &rp->rp_edid; 3764 3765 if (!rp->rp_edid_valid) 3766 continue; 3767 3768 if (!valid) { 3769 /* 3770 * Pick the preferred mode for this port 3771 * if available. 3772 */ 3773 if (ep->edid_preferred_mode) { 3774 struct videomode *vmp = 3775 ep->edid_preferred_mode; 3776 3777 if ((vmp->hdisplay <= 3778 dp->rd_softc->sc_maxx) && 3779 (vmp->vdisplay <= 3780 dp->rd_softc->sc_maxy)) 3781 modes[nmodes++] = *vmp; 3782 } else { 3783 3784 /* initialize starting list */ 3785 for (j = 0; j < ep->edid_nmodes; j++) { 3786 /* 3787 * ignore resolutions that are 3788 * too big for the radeon 3789 */ 3790 if (ep->edid_modes[j].hdisplay > 3791 dp->rd_softc->sc_maxx) 3792 continue; 3793 if (ep->edid_modes[j].vdisplay > 3794 dp->rd_softc->sc_maxy) 3795 continue; 3796 3797 modes[nmodes] = 3798 ep->edid_modes[j]; 3799 nmodes++; 3800 } 3801 } 3802 valid = 1; 3803 } else { 3804 /* merge into preexisting list */ 3805 for (j = 0; j < nmodes; j++) { 3806 if (!radeonfb_hasres(ep->edid_modes, 3807 ep->edid_nmodes, 3808 modes[j].hdisplay, 3809 modes[j].vdisplay)) { 3810 modes[j] = modes[nmodes]; 3811 j--; 3812 nmodes--; 3813 } 3814 } 3815 } 3816 } 3817 3818 /* now we have to pick from the merged list */ 3819 for (i = 0; i < nmodes; i++) { 3820 if ((modes[i].hdisplay >= *x) && 3821 (modes[i].vdisplay >= *y)) { 3822 *x = modes[i].hdisplay; 3823 *y = modes[i].vdisplay; 3824 } 3825 } 3826 } 3827 3828 if ((*x == 0) || (*y == 0)) { 3829 /* fallback to safe mode */ 3830 *x = 640; 3831 *y = 480; 3832 } 3833 } 3834 3835 /* 3836 * backlight levels are linear on: 3837 * - RV200, RV250, RV280, RV350 3838 * - but NOT on PowerBook4,3 6,3 6,5 3839 * according to Linux' radeonfb 3840 */ 3841 3842 /* Get the current backlight level for the display. */ 3843 3844 static int 3845 radeonfb_get_backlight(struct radeonfb_display *dp) 3846 { 3847 int s; 3848 uint32_t level; 3849 3850 s = spltty(); 3851 3852 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3853 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3854 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3855 3856 /* 3857 * On some chips, we should negate the backlight level. 3858 * XXX Find out on which chips. 3859 */ 3860 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3861 level = RADEONFB_BACKLIGHT_MAX - level; 3862 3863 splx(s); 3864 3865 return level; 3866 } 3867 3868 /* Set the backlight to the given level for the display. */ 3869 static void 3870 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3871 { 3872 if (dp->rd_bl_on == on) 3873 return; 3874 dp->rd_bl_on = on; 3875 radeonfb_set_backlight(dp, dp->rd_bl_level); 3876 } 3877 3878 static int 3879 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3880 { 3881 struct radeonfb_softc *sc; 3882 int rlevel, s; 3883 uint32_t lvds; 3884 3885 s = spltty(); 3886 3887 dp->rd_bl_level = level; 3888 if (dp->rd_bl_on == 0) 3889 level = 0; 3890 3891 if (level < 0) 3892 level = 0; 3893 else if (level >= RADEONFB_BACKLIGHT_MAX) 3894 level = RADEONFB_BACKLIGHT_MAX; 3895 3896 sc = dp->rd_softc; 3897 3898 /* On some chips, we should negate the backlight level. */ 3899 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3900 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3901 } else 3902 rlevel = level; 3903 3904 callout_stop(&dp->rd_bl_lvds_co); 3905 radeonfb_engine_idle(sc); 3906 3907 /* 3908 * Turn off the display if the backlight is set to 0, since the 3909 * display is useless without backlight anyway. 3910 */ 3911 if (level == 0) 3912 radeonfb_blank(dp, 1); 3913 else if (radeonfb_get_backlight(dp) == 0) 3914 radeonfb_blank(dp, 0); 3915 3916 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3917 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3918 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3919 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3920 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3921 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3922 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3923 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3924 lvds |= RADEON_LVDS_ON; 3925 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3926 } else { 3927 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3928 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3929 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3930 } 3931 3932 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3933 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3934 /* XXX What is the correct delay? */ 3935 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3936 3937 splx(s); 3938 3939 return 0; 3940 } 3941 3942 /* 3943 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3944 * Set the delayed bits in the register, and clear the stored delayed 3945 * value. 3946 */ 3947 3948 static void radeonfb_lvds_callout(void *arg) 3949 { 3950 struct radeonfb_display *dp = arg; 3951 int s; 3952 3953 s = splhigh(); 3954 3955 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3956 dp->rd_bl_lvds_val); 3957 dp->rd_bl_lvds_val = 0; 3958 3959 splx(s); 3960 } 3961 3962 static void 3963 radeonfb_brightness_up(device_t dev) 3964 { 3965 struct radeonfb_softc *sc = device_private(dev); 3966 struct radeonfb_display *dp = &sc->sc_displays[0]; 3967 int level; 3968 3969 /* we assume the main display is the first one - need a better way */ 3970 if (sc->sc_ndisplays < 1) return; 3971 /* make sure pushing the hotkeys always has an effect */ 3972 dp->rd_bl_on = 1; 3973 level = dp->rd_bl_level; 3974 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 3975 radeonfb_set_backlight(dp, level); 3976 } 3977 3978 static void 3979 radeonfb_brightness_down(device_t dev) 3980 { 3981 struct radeonfb_softc *sc = device_private(dev); 3982 struct radeonfb_display *dp = &sc->sc_displays[0]; 3983 int level; 3984 3985 /* we assume the main display is the first one - need a better way */ 3986 if (sc->sc_ndisplays < 1) return; 3987 /* make sure pushing the hotkeys always has an effect */ 3988 dp->rd_bl_on = 1; 3989 level = dp->rd_bl_level; 3990 level = max(0, level - 5); 3991 radeonfb_set_backlight(dp, level); 3992 } 3993
Indexes created Wed Sep 24 15:09:51 GMT 2025