radeonfb.c revision 1.69
1 /* $NetBSD: radeonfb.c,v 1.69 2012/12/30 09:45:05 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.69 2012/12/30 09:45:05 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_softc *, int); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 16, 5 }, 384 { 12, 7 }, 385 { 8, 3 }, 386 { 6, 6 }, 387 { 4, 2 }, 388 { 3, 4 }, 389 { 2, 1 }, 390 { 1, 0 }, 391 { 0, 0 } 392 }; 393 394 /* 395 * This table taken from X11. 396 */ 397 static const struct { 398 int family; 399 struct radeon_tmds_pll plls[4]; 400 } radeonfb_tmds_pll[] = { 401 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RS100, {{0, 0}}}, 404 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 408 { RADEON_RS300, {{0, 0}}}, 409 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 410 { RADEON_R300, {{-1, 0xb01cb}}}, 411 { RADEON_R350, {{-1, 0xb01cb}}}, 412 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 414 { RADEON_R420, {{-1, 0xb01cb}}}, 415 }; 416 417 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 418 419 420 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 421 radeonfb_match, radeonfb_attach, NULL, NULL); 422 423 static int 424 radeonfb_match(device_t parent, cfdata_t match, void *aux) 425 { 426 const struct pci_attach_args *pa = aux; 427 int i; 428 429 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 430 return 0; 431 432 for (i = 0; radeonfb_devices[i].devid; i++) { 433 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 434 return 100; /* high to defeat VGA/VESA */ 435 } 436 437 return 0; 438 } 439 440 static void 441 radeonfb_attach(device_t parent, device_t dev, void *aux) 442 { 443 struct radeonfb_softc *sc = device_private(dev); 444 const struct pci_attach_args *pa = aux; 445 const char *mptr; 446 bus_size_t bsz; 447 pcireg_t screg; 448 int i, j, fg, bg, ul, flags; 449 uint32_t v; 450 451 sc->sc_dev = dev; 452 sc->sc_id = pa->pa_id; 453 for (i = 0; radeonfb_devices[i].devid; i++) { 454 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 455 break; 456 } 457 458 pci_aprint_devinfo(pa, NULL); 459 460 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 461 462 KASSERT(radeonfb_devices[i].devid != 0); 463 sc->sc_pt = pa->pa_tag; 464 sc->sc_iot = pa->pa_iot; 465 sc->sc_pc = pa->pa_pc; 466 sc->sc_family = radeonfb_devices[i].family; 467 sc->sc_flags = radeonfb_devices[i].flags; 468 469 /* enable memory and IO access */ 470 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 471 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 472 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 473 474 /* 475 * Some flags are general to entire chip families, and rather 476 * than clutter up the table with them, we go ahead and set 477 * them here. 478 */ 479 switch (sc->sc_family) { 480 case RADEON_RS100: 481 case RADEON_RS200: 482 sc->sc_flags |= RFB_IGP | RFB_RV100; 483 break; 484 485 case RADEON_RV100: 486 case RADEON_RV200: 487 case RADEON_RV250: 488 case RADEON_RV280: 489 sc->sc_flags |= RFB_RV100; 490 break; 491 492 case RADEON_RS300: 493 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 494 break; 495 496 case RADEON_R300: 497 case RADEON_RV350: 498 case RADEON_R350: 499 case RADEON_RV380: 500 case RADEON_R420: 501 /* newer chips */ 502 sc->sc_flags |= RFB_R300; 503 break; 504 505 case RADEON_R100: 506 sc->sc_flags |= RFB_NCRTC2; 507 break; 508 } 509 510 if ((sc->sc_family == RADEON_RV200) || 511 (sc->sc_family == RADEON_RV250) || 512 (sc->sc_family == RADEON_RV280) || 513 (sc->sc_family == RADEON_RV350)) { 514 bool inverted = 0; 515 /* backlight level is linear */ 516 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 517 prop_dictionary_get_bool(device_properties(sc->sc_dev), 518 "backlight_level_reverted", &inverted); 519 if (inverted) { 520 DPRINTF(("nope, it's inverted\n")); 521 sc->sc_flags |= RFB_INV_BLIGHT; 522 } 523 } else 524 sc->sc_flags |= RFB_INV_BLIGHT; 525 526 /* 527 * XXX: to support true multihead, this must change. 528 */ 529 sc->sc_ndisplays = 1; 530 531 /* XXX: */ 532 if (!HAS_CRTC2(sc)) { 533 sc->sc_ndisplays = 1; 534 } 535 536 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 537 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 538 &sc->sc_regsz) != 0) { 539 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 540 goto error; 541 } 542 543 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 544 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 545 { 546 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 547 goto error; 548 } 549 sc->sc_romt = sc->sc_memt; 550 551 sc->sc_mapped = TRUE; 552 553 /* scratch register test... */ 554 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 555 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 556 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 557 goto error; 558 } 559 560 PRINTREG(RADEON_CRTC_EXT_CNTL); 561 PRINTREG(RADEON_CRTC_GEN_CNTL); 562 PRINTREG(RADEON_CRTC2_GEN_CNTL); 563 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 564 PRINTREG(RADEON_DAC_CNTL2); 565 PRINTREG(RADEON_FP_GEN_CNTL); 566 PRINTREG(RADEON_FP2_GEN_CNTL); 567 568 PRINTREG(RADEON_BIOS_4_SCRATCH); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 571 PRINTREG(RADEON_FP2_GEN_CNTL); 572 PRINTREG(RADEON_TMDS_CNTL); 573 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 574 PRINTREG(RADEON_TMDS_PLL_CNTL); 575 PRINTREG(RADEON_LVDS_GEN_CNTL); 576 PRINTREG(RADEON_FP_HORZ_STRETCH); 577 PRINTREG(RADEON_FP_VERT_STRETCH); 578 579 if (IS_RV100(sc)) 580 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 581 582 /* XXX 583 * according to xf86-video-radeon R3xx has this bit backwards 584 */ 585 if (IS_R300(sc)) { 586 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 587 0, 588 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 589 } else { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 RADEON_TMDS_TRANSMITTER_PLLEN, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } 594 595 radeonfb_i2c_init(sc); 596 597 radeonfb_loadbios(sc, pa); 598 599 #ifdef RADEONFB_BIOS_INIT 600 if (radeonfb_bios_init(sc)) { 601 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 602 } 603 #endif 604 605 if (radeonfb_getclocks(sc)) { 606 aprint_error("%s: Unable to get reference clocks from BIOS\n", 607 XNAME(sc)); 608 goto error; 609 } 610 611 if (radeonfb_gettmds(sc)) { 612 aprint_error("%s: Unable to identify TMDS PLL settings\n", 613 XNAME(sc)); 614 goto error; 615 } 616 617 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 618 "minpll = %d, maxpll = %d\n", XNAME(sc), 619 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 620 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 621 622 radeonfb_getconnectors(sc); 623 624 radeonfb_set_fbloc(sc); 625 626 for (i = 0; radeonfb_limits[i].size; i++) { 627 if (sc->sc_memsz >= radeonfb_limits[i].size) { 628 sc->sc_maxx = radeonfb_limits[i].maxx; 629 sc->sc_maxy = radeonfb_limits[i].maxy; 630 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 631 /* framebuffer offset, start at a 4K page */ 632 sc->sc_fboffset = sc->sc_memsz / 633 radeonfb_limits[i].maxdisp; 634 /* 635 * we use the fbsize to figure out where we can store 636 * things like cursor data. 637 */ 638 sc->sc_fbsize = 639 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 640 RADEON_STRIDEALIGN) * sc->sc_maxy, 641 4096); 642 break; 643 } 644 } 645 646 647 radeonfb_init_misc(sc); 648 radeonfb_init_palette(sc, 0); 649 if (HAS_CRTC2(sc)) 650 radeonfb_init_palette(sc, 1); 651 652 /* program the DAC wirings */ 653 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 654 switch (sc->sc_ports[i].rp_dac_type) { 655 case RADEON_DAC_PRIMARY: 656 PATCH32(sc, RADEON_DAC_CNTL2, 657 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 658 ~RADEON_DAC2_DAC_CLK_SEL); 659 break; 660 case RADEON_DAC_TVDAC: 661 /* we always use the TVDAC to drive a secondary analog 662 * CRT for now. if we ever support TV-out this will 663 * have to change. 664 */ 665 SET32(sc, RADEON_DAC_CNTL2, 666 RADEON_DAC2_DAC2_CLK_SEL); 667 PATCH32(sc, RADEON_DISP_HW_DEBUG, 668 i ? 0 : RADEON_CRT2_DISP1_SEL, 669 ~RADEON_CRT2_DISP1_SEL); 670 /* we're using CRTC2 for the 2nd port */ 671 if (sc->sc_ports[i].rp_number == 99) { 672 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 673 RADEON_DISP_DAC2_SOURCE_CRTC2, 674 ~RADEON_DISP_DAC2_SOURCE_MASK); 675 } 676 677 break; 678 } 679 switch (sc->sc_ports[i].rp_tmds_type) { 680 case RADEON_TMDS_INT: 681 /* point FP0 at the CRTC this port uses */ 682 if (IS_R300(sc)) { 683 PATCH32(sc, RADEON_FP_GEN_CNTL, 684 sc->sc_ports[i].rp_number ? 685 R200_FP_SOURCE_SEL_CRTC2 : 686 R200_FP_SOURCE_SEL_CRTC1, 687 ~R200_FP_SOURCE_SEL_MASK); 688 } else { 689 PATCH32(sc, RADEON_FP_GEN_CNTL, 690 sc->sc_ports[i].rp_number ? 691 RADEON_FP_SEL_CRTC2 : 692 RADEON_FP_SEL_CRTC1, 693 ~RADEON_FP_SEL_MASK); 694 } 695 } 696 } 697 PRINTREG(RADEON_DAC_CNTL2); 698 PRINTREG(RADEON_DISP_HW_DEBUG); 699 700 /* other DAC programming */ 701 v = GET32(sc, RADEON_DAC_CNTL); 702 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 703 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 704 PUT32(sc, RADEON_DAC_CNTL, v); 705 PRINTREG(RADEON_DAC_CNTL); 706 707 /* XXX: this may need more investigation */ 708 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 709 PRINTREG(RADEON_TV_DAC_CNTL); 710 711 /* enable TMDS */ 712 SET32(sc, RADEON_FP_GEN_CNTL, 713 RADEON_FP_TMDS_EN | 714 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 715 RADEON_FP_CRTC_DONT_SHADOW_HEND); 716 /* 717 * XXX 718 * no idea why this is necessary - if I do not clear this bit on my 719 * iBook G4 the screen remains black, even though it's already clear. 720 * It needs to be set on my Sun XVR-100 for the DVI port to work 721 * TODO: 722 * see if this is still necessary now that CRTCs, DACs and outputs are 723 * getting wired up in a halfway sane way 724 */ 725 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 726 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 727 } else { 728 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 729 } 730 731 /* 732 * we use bus_space_map instead of pci_mapreg, because we don't 733 * need the full aperature space. no point in wasting virtual 734 * address space we don't intend to use, right? 735 */ 736 if ((sc->sc_memsz < (4096 * 1024)) || 737 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 738 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 739 (bsz < sc->sc_memsz)) { 740 sc->sc_memsz = 0; 741 aprint_error("%s: Bad frame buffer configuration\n", 742 XNAME(sc)); 743 goto error; 744 } 745 746 /* 64 MB should be enough -- more just wastes map entries */ 747 if (sc->sc_memsz > (64 << 20)) 748 sc->sc_memsz = (64 << 20); 749 750 sc->sc_memt = pa->pa_memt; 751 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 752 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 753 sc->sc_memsz = 0; 754 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 755 goto error; 756 } 757 758 aprint_normal("%s: %d MB aperture at 0x%08x, " 759 "%d KB registers at 0x%08x\n", XNAME(sc), 760 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 761 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 762 763 /* setup default video mode from devprop (allows PROM override) */ 764 sc->sc_defaultmode = radeonfb_default_mode; 765 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 766 "videomode", &mptr)) { 767 768 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 769 sc->sc_defaultmode = sc->sc_modebuf; 770 } 771 772 /* initialize some basic display parameters */ 773 for (i = 0; i < sc->sc_ndisplays; i++) { 774 struct radeonfb_display *dp = &sc->sc_displays[i]; 775 struct rasops_info *ri; 776 long defattr; 777 struct wsemuldisplaydev_attach_args aa; 778 779 /* 780 * Figure out how many "displays" (desktops) we are going to 781 * support. If more than one, then each CRTC gets its own 782 * programming. 783 * 784 * XXX: this code needs to change to support mergedfb. 785 * XXX: would be nice to allow this to be overridden 786 */ 787 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 788 DPRINTF(("dual crtcs!\n")); 789 dp->rd_ncrtcs = 2; 790 dp->rd_crtcs[0].rc_port = 791 &sc->sc_ports[0]; 792 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 793 dp->rd_crtcs[1].rc_port = 794 &sc->sc_ports[1]; 795 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 796 } else { 797 dp->rd_ncrtcs = 1; 798 dp->rd_crtcs[0].rc_port = 799 &sc->sc_ports[i]; 800 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 801 } 802 803 dp->rd_softc = sc; 804 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 805 dp->rd_bg = WS_DEFAULT_BG; 806 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 807 808 /* for text mode, we pick a resolution that won't 809 * require panning */ 810 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 811 812 aprint_normal("%s: display %d: " 813 "initial virtual resolution %dx%d at %d bpp\n", 814 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 815 816 /* now select the *video mode* that we will use */ 817 for (j = 0; j < dp->rd_ncrtcs; j++) { 818 const struct videomode *vmp; 819 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 820 dp->rd_virtx, dp->rd_virty); 821 822 /* 823 * virtual resolution should be at least as high as 824 * physical 825 */ 826 if (dp->rd_virtx < vmp->hdisplay || 827 dp->rd_virty < vmp->vdisplay) { 828 dp->rd_virtx = vmp->hdisplay; 829 dp->rd_virty = vmp->vdisplay; 830 } 831 832 dp->rd_crtcs[j].rc_videomode = *vmp; 833 printf("%s: port %d: physical %dx%d %dHz\n", 834 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 835 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 836 vmp->htotal), vmp->vtotal)); 837 } 838 839 /* N.B.: radeon wants 64-byte aligned stride */ 840 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 841 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 842 DPRINTF(("stride: %d\n", dp->rd_stride)); 843 844 dp->rd_offset = sc->sc_fboffset * i; 845 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 846 sc->sc_memh) + dp->rd_offset; 847 dp->rd_curoff = sc->sc_fbsize; 848 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 849 850 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 851 852 switch (dp->rd_bpp) { 853 case 8: 854 dp->rd_format = 2; 855 break; 856 case 32: 857 dp->rd_format = 6; 858 break; 859 default: 860 aprint_error("%s: bad depth %d\n", XNAME(sc), 861 dp->rd_bpp); 862 goto error; 863 } 864 865 DPRINTF(("init engine\n")); 866 /* XXX: this seems suspicious - per display engine 867 initialization? */ 868 radeonfb_engine_init(dp); 869 870 /* copy the template into place */ 871 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 872 dp->rd_wsscreens = dp->rd_wsscreens_storage; 873 874 /* and make up the list */ 875 dp->rd_wsscreenlist.nscreens = 1; 876 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 877 878 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 879 &radeonfb_accessops); 880 881 dp->rd_vd.init_screen = radeonfb_init_screen; 882 883 #ifdef RADEONFB_DEBUG 884 dp->rd_virty -= 200; 885 #endif 886 887 dp->rd_console = 0; 888 prop_dictionary_get_bool(device_properties(sc->sc_dev), 889 "is_console", &dp->rd_console); 890 891 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 892 893 894 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 895 dp->rd_console, &defattr); 896 897 ri = &dp->rd_vscreen.scr_ri; 898 899 /* clear the screen */ 900 rasops_unpack_attr(defattr, &fg, &bg, &ul); 901 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 902 ri->ri_devcmap[bg & 0xf]); 903 904 dp->rd_wsscreens->textops = &ri->ri_ops; 905 dp->rd_wsscreens->capabilities = ri->ri_caps; 906 dp->rd_wsscreens->nrows = ri->ri_rows; 907 dp->rd_wsscreens->ncols = ri->ri_cols; 908 909 #ifdef SPLASHSCREEN 910 dp->rd_splash.si_depth = ri->ri_depth; 911 dp->rd_splash.si_bits = ri->ri_bits; 912 dp->rd_splash.si_hwbits = ri->ri_hwbits; 913 dp->rd_splash.si_width = ri->ri_width; 914 dp->rd_splash.si_height = ri->ri_height; 915 dp->rd_splash.si_stride = ri->ri_stride; 916 dp->rd_splash.si_fillrect = NULL; 917 #endif 918 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 919 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 920 dp->rd_gc.gc_rop = RADEON_ROP3_S; 921 dp->rd_gc.gc_blitcookie = dp; 922 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 923 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 924 dp->rd_virtx, 925 ri->ri_font->fontwidth, 926 ri->ri_font->fontheight, 927 defattr); 928 if (dp->rd_console) { 929 930 radeonfb_modeswitch(dp); 931 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 932 defattr); 933 #ifdef SPLASHSCREEN 934 if (splash_render(&dp->rd_splash, 935 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 936 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 937 else 938 #endif 939 vcons_replay_msgbuf(&dp->rd_vscreen); 940 } else { 941 942 /* 943 * since we're not the console we can postpone 944 * the rest until someone actually allocates a 945 * screen for us. but we do clear the screen 946 * at least. 947 */ 948 memset(ri->ri_bits, 0, 1024); 949 950 radeonfb_modeswitch(dp); 951 #ifdef SPLASHSCREEN 952 if (splash_render(&dp->rd_splash, 953 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 954 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 955 #endif 956 } 957 958 aa.console = dp->rd_console; 959 aa.scrdata = &dp->rd_wsscreenlist; 960 aa.accessops = &radeonfb_accessops; 961 aa.accesscookie = &dp->rd_vd; 962 963 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 964 965 radeonfb_blank(dp, 0); 966 967 /* Initialise delayed lvds operations for backlight. */ 968 callout_init(&dp->rd_bl_lvds_co, 0); 969 callout_setfunc(&dp->rd_bl_lvds_co, 970 radeonfb_lvds_callout, dp); 971 dp->rd_bl_on = 1; 972 dp->rd_bl_level = radeonfb_get_backlight(dp); 973 radeonfb_set_backlight(dp, dp->rd_bl_level); 974 } 975 976 /* 977 * if we have console output via firmware like on sparc64 it may 978 * interfere with DAC programming so program the palette again 979 * here after we took over 980 */ 981 radeonfb_init_palette(sc, 0); 982 if (HAS_CRTC2(sc)) { 983 radeonfb_init_palette(sc, 1); 984 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 985 } 986 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 987 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 988 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 989 radeonfb_brightness_up, TRUE); 990 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 991 radeonfb_brightness_down, TRUE); 992 993 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 994 995 PRINTREG(RADEON_CRTC_EXT_CNTL); 996 PRINTREG(RADEON_CRTC_GEN_CNTL); 997 PRINTREG(RADEON_CRTC2_GEN_CNTL); 998 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 999 PRINTREG(RADEON_DAC_CNTL2); 1000 PRINTREG(RADEON_FP_GEN_CNTL); 1001 PRINTREG(RADEON_FP2_GEN_CNTL); 1002 1003 return; 1004 1005 error: 1006 if (sc->sc_biossz) 1007 free(sc->sc_bios, M_DEVBUF); 1008 1009 if (sc->sc_regsz) 1010 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1011 1012 if (sc->sc_memsz) 1013 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1014 } 1015 1016 static void 1017 radeonfb_map(struct radeonfb_softc *sc) 1018 { 1019 if (!sc->sc_mapped) { 1020 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1021 &sc->sc_regh) != 0) { 1022 aprint_error_dev(sc->sc_dev, 1023 "unable to map registers!\n"); 1024 return; 1025 } 1026 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1027 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1028 sc->sc_memsz = 0; 1029 aprint_error_dev(sc->sc_dev, 1030 "Unable to map frame buffer\n"); 1031 return; 1032 } 1033 sc->sc_mapped = TRUE; 1034 } 1035 } 1036 1037 static void 1038 radeonfb_unmap(struct radeonfb_softc *sc) 1039 { 1040 if (sc->sc_mapped) { 1041 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1042 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1043 sc->sc_mapped = FALSE; 1044 } 1045 } 1046 1047 static int 1048 radeonfb_drm_print(void *aux, const char *pnp) 1049 { 1050 if (pnp) 1051 aprint_normal("drm at %s", pnp); 1052 return (UNCONF); 1053 } 1054 1055 int 1056 radeonfb_ioctl(void *v, void *vs, 1057 unsigned long cmd, void *d, int flag, struct lwp *l) 1058 { 1059 struct vcons_data *vd; 1060 struct radeonfb_display *dp; 1061 struct radeonfb_softc *sc; 1062 struct wsdisplay_param *param; 1063 1064 vd = (struct vcons_data *)v; 1065 dp = (struct radeonfb_display *)vd->cookie; 1066 sc = dp->rd_softc; 1067 1068 switch (cmd) { 1069 case WSDISPLAYIO_GTYPE: 1070 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1071 return 0; 1072 1073 case WSDISPLAYIO_GINFO: 1074 if (vd->active != NULL) { 1075 struct wsdisplay_fbinfo *fb; 1076 fb = (struct wsdisplay_fbinfo *)d; 1077 fb->width = dp->rd_virtx; 1078 fb->height = dp->rd_virty; 1079 fb->depth = dp->rd_bpp; 1080 fb->cmsize = 256; 1081 return 0; 1082 } else 1083 return ENODEV; 1084 case WSDISPLAYIO_GVIDEO: 1085 if (radeonfb_isblank(dp)) 1086 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1087 else 1088 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1089 return 0; 1090 1091 case WSDISPLAYIO_SVIDEO: 1092 radeonfb_blank(dp, 1093 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1094 return 0; 1095 1096 case WSDISPLAYIO_GETCMAP: 1097 #if 0 1098 if (dp->rd_bpp == 8) 1099 return radeonfb_getcmap(sc, 1100 (struct wsdisplay_cmap *)d); 1101 #endif 1102 return EINVAL; 1103 1104 case WSDISPLAYIO_PUTCMAP: 1105 #if 0 1106 if (dp->rd_bpp == 8) 1107 return radeonfb_putcmap(sc, 1108 (struct wsdisplay_cmap *)d); 1109 #endif 1110 return EINVAL; 1111 1112 case WSDISPLAYIO_LINEBYTES: 1113 *(unsigned *)d = dp->rd_stride; 1114 return 0; 1115 1116 case WSDISPLAYIO_SMODE: 1117 if (*(int *)d != dp->rd_wsmode) { 1118 dp->rd_wsmode = *(int *)d; 1119 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1120 (dp->rd_vd.active)) { 1121 radeonfb_map(sc); 1122 radeonfb_engine_init(dp); 1123 glyphcache_wipe(&dp->rd_gc); 1124 radeonfb_init_palette(sc, dp == &sc->sc_displays[0] ? 0 : 1); 1125 radeonfb_modeswitch(dp); 1126 vcons_redraw_screen(dp->rd_vd.active); 1127 } else { 1128 radeonfb_unmap(sc); 1129 } 1130 } 1131 return 0; 1132 1133 case WSDISPLAYIO_GCURMAX: 1134 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1135 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1136 return 0; 1137 1138 case WSDISPLAYIO_SCURSOR: 1139 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1140 1141 case WSDISPLAYIO_GCURSOR: 1142 return EPASSTHROUGH; 1143 1144 case WSDISPLAYIO_GCURPOS: 1145 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1146 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1147 return 0; 1148 1149 case WSDISPLAYIO_SCURPOS: 1150 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1151 1152 case WSDISPLAYIO_SSPLASH: 1153 #if defined(SPLASHSCREEN) 1154 if (*(int *)d == 1) { 1155 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1156 splash_render(&dp->rd_splash, 1157 SPLASH_F_CENTER|SPLASH_F_FILL); 1158 } else 1159 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1160 return 0; 1161 #else 1162 return ENODEV; 1163 #endif 1164 case WSDISPLAYIO_GETPARAM: 1165 param = (struct wsdisplay_param *)d; 1166 switch (param->param) { 1167 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1168 param->min = 0; 1169 param->max = 255; 1170 param->curval = dp->rd_bl_level; 1171 return 0; 1172 case WSDISPLAYIO_PARAM_BACKLIGHT: 1173 param->min = 0; 1174 param->max = RADEONFB_BACKLIGHT_MAX; 1175 param->curval = dp->rd_bl_on; 1176 return 0; 1177 } 1178 return EPASSTHROUGH; 1179 1180 case WSDISPLAYIO_SETPARAM: 1181 param = (struct wsdisplay_param *)d; 1182 switch (param->param) { 1183 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1184 radeonfb_set_backlight(dp, param->curval); 1185 return 0; 1186 case WSDISPLAYIO_PARAM_BACKLIGHT: 1187 radeonfb_switch_backlight(dp, param->curval); 1188 return 0; 1189 } 1190 return EPASSTHROUGH; 1191 1192 /* PCI config read/write passthrough. */ 1193 case PCI_IOC_CFGREAD: 1194 case PCI_IOC_CFGWRITE: 1195 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1196 1197 case WSDISPLAYIO_GET_BUSID: 1198 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1199 sc->sc_pt, d); 1200 1201 case WSDISPLAYIO_GET_EDID: { 1202 struct wsdisplayio_edid_info *ei = d; 1203 return wsdisplayio_get_edid(sc->sc_dev, ei); 1204 } 1205 1206 default: 1207 return EPASSTHROUGH; 1208 } 1209 } 1210 1211 paddr_t 1212 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1213 { 1214 struct vcons_data *vd; 1215 struct radeonfb_display *dp; 1216 struct radeonfb_softc *sc; 1217 paddr_t pa; 1218 1219 vd = (struct vcons_data *)v; 1220 dp = (struct radeonfb_display *)vd->cookie; 1221 sc = dp->rd_softc; 1222 1223 /* XXX: note that we don't allow mapping of registers right now */ 1224 /* XXX: this means that the XFree86 radeon driver won't work */ 1225 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1226 pa = bus_space_mmap(sc->sc_memt, 1227 sc->sc_memaddr + dp->rd_offset + offset, 0, 1228 prot, BUS_SPACE_MAP_LINEAR); 1229 return pa; 1230 } 1231 1232 #ifdef RADEONFB_MMAP_BARS 1233 /* 1234 * restrict all other mappings to processes with superuser privileges 1235 * or the kernel itself 1236 */ 1237 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1238 NULL, NULL, NULL, NULL) != 0) { 1239 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1240 return -1; 1241 } 1242 1243 if ((offset >= sc->sc_regaddr) && 1244 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1245 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1246 BUS_SPACE_MAP_LINEAR); 1247 } 1248 1249 if ((offset >= sc->sc_memaddr) && 1250 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1251 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1252 BUS_SPACE_MAP_LINEAR); 1253 } 1254 1255 if ((offset >= sc->sc_romaddr) && 1256 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1257 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1258 BUS_SPACE_MAP_LINEAR); 1259 } 1260 1261 #ifdef PCI_MAGIC_IO_RANGE 1262 /* allow mapping of IO space */ 1263 if ((offset >= PCI_MAGIC_IO_RANGE) && 1264 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1265 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1266 0, prot, 0); 1267 return pa; 1268 } 1269 #endif /* PCI_MAGIC_IO_RANGE */ 1270 1271 #endif /* RADEONFB_MMAP_BARS */ 1272 1273 return -1; 1274 } 1275 1276 static void 1277 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1278 { 1279 bus_space_tag_t romt; 1280 bus_space_handle_t romh, biosh; 1281 bus_size_t romsz; 1282 bus_addr_t ptr; 1283 1284 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1285 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1286 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1287 return; 1288 } 1289 1290 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1291 &sc->sc_biossz); 1292 if (sc->sc_biossz == 0) { 1293 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1294 return; 1295 } 1296 1297 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1298 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1299 1300 /* unmap the PCI expansion rom */ 1301 bus_space_unmap(romt, romh, romsz); 1302 1303 /* turn off rom decoder now */ 1304 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1305 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1306 ~PCI_MAPREG_ROM_ENABLE); 1307 1308 ptr = GETBIOS16(sc, 0x48); 1309 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1310 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1311 sc->sc_flags |= RFB_ATOM; 1312 } 1313 1314 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1315 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1316 } 1317 1318 1319 uint32_t 1320 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1321 { 1322 1323 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1324 } 1325 1326 void 1327 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1328 { 1329 1330 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1331 } 1332 1333 void 1334 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1335 { 1336 1337 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1338 } 1339 1340 void 1341 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1342 uint32_t andmask, uint32_t ormask) 1343 { 1344 int s; 1345 uint32_t val; 1346 1347 s = splhigh(); 1348 val = radeonfb_get32(sc, reg); 1349 val = (val & andmask) | ormask; 1350 radeonfb_put32(sc, reg, val); 1351 splx(s); 1352 } 1353 1354 uint32_t 1355 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1356 { 1357 int s; 1358 uint32_t val; 1359 1360 s = splhigh(); 1361 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1362 val = radeonfb_get32(sc, RADEON_MM_DATA); 1363 splx(s); 1364 1365 return (val); 1366 } 1367 1368 void 1369 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1370 { 1371 int s; 1372 1373 s = splhigh(); 1374 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1375 radeonfb_put32(sc, RADEON_MM_DATA, val); 1376 splx(s); 1377 } 1378 1379 void 1380 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1381 uint32_t andmask, uint32_t ormask) 1382 { 1383 int s; 1384 uint32_t val; 1385 1386 s = splhigh(); 1387 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1388 val = radeonfb_get32(sc, RADEON_MM_DATA); 1389 val = (val & andmask) | ormask; 1390 radeonfb_put32(sc, RADEON_MM_DATA, val); 1391 splx(s); 1392 } 1393 1394 uint32_t 1395 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1396 { 1397 int s; 1398 uint32_t val; 1399 1400 s = splhigh(); 1401 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1402 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1403 if (HAS_R300CG(sc)) 1404 radeonfb_r300cg_workaround(sc); 1405 splx(s); 1406 1407 return (val); 1408 } 1409 1410 void 1411 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1412 { 1413 int s; 1414 1415 s = splhigh(); 1416 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1417 RADEON_PLL_WR_EN); 1418 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1419 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1420 splx(s); 1421 } 1422 1423 void 1424 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1425 uint32_t andmask, uint32_t ormask) 1426 { 1427 int s; 1428 uint32_t val; 1429 1430 s = splhigh(); 1431 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1432 RADEON_PLL_WR_EN); 1433 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1434 val = (val & andmask) | ormask; 1435 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1436 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1437 splx(s); 1438 } 1439 1440 int 1441 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1442 { 1443 uint32_t saved; 1444 1445 saved = GET32(sc, reg); 1446 PUT32(sc, reg, v); 1447 if (GET32(sc, reg) != v) { 1448 return -1; 1449 } 1450 PUT32(sc, reg, saved); 1451 return 0; 1452 } 1453 1454 uintmax_t 1455 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1456 uintmax_t defval) 1457 { 1458 prop_number_t pn; 1459 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1460 if (pn == NULL) { 1461 return defval; 1462 } 1463 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1464 return (prop_number_integer_value(pn)); 1465 } 1466 1467 int 1468 radeonfb_getclocks(struct radeonfb_softc *sc) 1469 { 1470 bus_addr_t ptr; 1471 int refclk = 0; 1472 int refdiv = 0; 1473 int minpll = 0; 1474 int maxpll = 0; 1475 1476 /* load initial property values if port/board provides them */ 1477 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1478 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1479 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1480 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1481 1482 PRINTPLL(RADEON_PPLL_REF_DIV); 1483 PRINTPLL(RADEON_PPLL_DIV_0); 1484 PRINTPLL(RADEON_PPLL_DIV_1); 1485 PRINTPLL(RADEON_PPLL_DIV_2); 1486 PRINTPLL(RADEON_PPLL_DIV_3); 1487 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1488 PRINTPLL(RADEON_P2PLL_REF_DIV); 1489 PRINTPLL(RADEON_P2PLL_DIV_0); 1490 1491 if (refclk && refdiv && minpll && maxpll) 1492 goto dontprobe; 1493 1494 if (!sc->sc_biossz) { 1495 /* no BIOS */ 1496 aprint_verbose("%s: No video BIOS, using default clocks\n", 1497 XNAME(sc)); 1498 if (IS_IGP(sc)) 1499 refclk = refclk ? refclk : 1432; 1500 else 1501 refclk = refclk ? refclk : 2700; 1502 refdiv = refdiv ? refdiv : 12; 1503 minpll = minpll ? minpll : 12500; 1504 /* XXX 1505 * Need to check if the firmware or something programmed a 1506 * higher value than this, and if so, bump it. 1507 * The RV280 in my iBook is unhappy if the PLL input is less 1508 * than 360MHz 1509 */ 1510 maxpll = maxpll ? maxpll : 40000/*35000*/; 1511 } else if (IS_ATOM(sc)) { 1512 /* ATOM BIOS */ 1513 ptr = GETBIOS16(sc, 0x48); 1514 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1515 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1516 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1517 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1518 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1519 /* 1520 * ATOM BIOS doesn't supply a reference divider, so we 1521 * have to probe for it. 1522 */ 1523 if (refdiv < 2) 1524 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1525 RADEON_PPLL_REF_DIV_MASK; 1526 /* 1527 * if probe is zero, just assume one that should work 1528 * for most parts 1529 */ 1530 if (refdiv < 2) 1531 refdiv = 12; 1532 1533 } else { 1534 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1535 /* Legacy BIOS */ 1536 ptr = GETBIOS16(sc, 0x48); 1537 ptr = GETBIOS16(sc, ptr + 0x30); 1538 if (IS_R300(sc)) { 1539 refdiv = refdiv ? refdiv : 1540 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1541 R300_PPLL_REF_DIV_ACC_SHIFT; 1542 } else { 1543 refdiv = refdiv ? refdiv : 1544 tmp & RADEON_PPLL_REF_DIV_MASK; 1545 } 1546 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1547 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1548 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1549 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1550 } 1551 1552 1553 dontprobe: 1554 sc->sc_refclk = refclk * 10; 1555 sc->sc_refdiv = refdiv; 1556 sc->sc_minpll = minpll * 10; 1557 sc->sc_maxpll = maxpll * 10; 1558 return 0; 1559 } 1560 1561 int 1562 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1563 uint32_t *postdivbit, uint32_t *feedbackdiv) 1564 { 1565 int i; 1566 uint32_t outfreq; 1567 int div; 1568 1569 DPRINTF(("dot clock: %u\n", dotclock)); 1570 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1571 outfreq = div * dotclock; 1572 if ((outfreq >= sc->sc_minpll) && 1573 (outfreq <= sc->sc_maxpll)) { 1574 DPRINTF(("outfreq: %u\n", outfreq)); 1575 *postdivbit = 1576 ((uint32_t)radeonfb_dividers[i].mask << 16); 1577 DPRINTF(("post divider: %d (mask %x)\n", div, 1578 *postdivbit)); 1579 break; 1580 } 1581 } 1582 1583 if (div == 0) 1584 return 1; 1585 1586 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1587 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1588 return 0; 1589 } 1590 1591 #if 0 1592 #ifdef RADEONFB_DEBUG 1593 static void 1594 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1595 { 1596 char asc[17]; 1597 unsigned ptr = (unsigned)buffer; 1598 char *start = (char *)(ptr & ~0xf); 1599 char *end = (char *)(ptr + size); 1600 1601 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1602 1603 if (pfx == NULL) { 1604 pfx = ""; 1605 } 1606 1607 while (start < end) { 1608 unsigned offset = (unsigned)start & 0xf; 1609 if (offset == 0) { 1610 printf("%s%x: ", pfx, (unsigned)start); 1611 } 1612 if (((unsigned)start < ptr) || 1613 ((unsigned)start >= (ptr + size))) { 1614 printf(" "); 1615 asc[offset] = ' '; 1616 } else { 1617 printf("%02x", *(unsigned char *)start); 1618 if ((*start >= ' ') && (*start <= '~')) { 1619 asc[offset] = *start; 1620 } else { 1621 asc[offset] = '.'; 1622 } 1623 } 1624 asc[offset + 1] = 0; 1625 if (offset % 2) { 1626 printf(" "); 1627 } 1628 if (offset == 15) { 1629 printf(" %s\n", asc); 1630 } 1631 start++; 1632 } 1633 } 1634 #endif 1635 #endif 1636 1637 int 1638 radeonfb_getconnectors(struct radeonfb_softc *sc) 1639 { 1640 int i; 1641 int found = 0; 1642 1643 for (i = 0; i < 2; i++) { 1644 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1645 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1646 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1647 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1648 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1649 } 1650 1651 /* 1652 * This logic is borrowed from Xorg's radeon driver. 1653 */ 1654 if (!sc->sc_biossz) 1655 goto nobios; 1656 1657 if (IS_ATOM(sc)) { 1658 /* not done yet */ 1659 } else { 1660 uint16_t ptr; 1661 int port = 0; 1662 1663 ptr = GETBIOS16(sc, 0x48); 1664 ptr = GETBIOS16(sc, ptr + 0x50); 1665 for (i = 1; i < 4; i++) { 1666 uint16_t entry; 1667 uint8_t conn, ddc, dac, tmds; 1668 1669 /* 1670 * Parse the connector table. From reading the code, 1671 * it appears to made up of 16-bit entries for each 1672 * connector. The 16-bits are defined as: 1673 * 1674 * bits 12-15 - connector type (0 == end of table) 1675 * bits 8-11 - DDC type 1676 * bits 5-7 - ??? 1677 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1678 * bits 1-3 - ??? 1679 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1680 */ 1681 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1682 break; 1683 entry = GETBIOS16(sc, ptr + i * 2); 1684 1685 conn = (entry >> 12) & 0xf; 1686 ddc = (entry >> 8) & 0xf; 1687 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1688 RADEON_DAC_PRIMARY; 1689 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1690 RADEON_TMDS_INT; 1691 1692 if (conn == RADEON_CONN_NONE) 1693 continue; /* no connector */ 1694 1695 if ((found > 0) && 1696 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1697 /* duplicate entry for same connector */ 1698 continue; 1699 } 1700 1701 /* internal DDC_DVI port gets priority */ 1702 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1703 port = 0; 1704 else 1705 port = 1; 1706 1707 sc->sc_ports[port].rp_ddc_type = 1708 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1709 sc->sc_ports[port].rp_dac_type = dac; 1710 sc->sc_ports[port].rp_conn_type = 1711 min(conn, RADEON_CONN_UNSUPPORTED) ; 1712 1713 sc->sc_ports[port].rp_tmds_type = tmds; 1714 1715 if ((conn != RADEON_CONN_DVI_I) && 1716 (conn != RADEON_CONN_DVI_D) && 1717 (tmds == RADEON_TMDS_INT)) 1718 sc->sc_ports[port].rp_tmds_type = 1719 RADEON_TMDS_UNKNOWN; 1720 sc->sc_ports[port].rp_number = i - 1; 1721 1722 found += (port + 1); 1723 } 1724 } 1725 1726 nobios: 1727 if (!found) { 1728 DPRINTF(("No connector info in BIOS!\n")); 1729 if IS_MOBILITY(sc) { 1730 /* default, port 0 = internal TMDS, port 1 = CRT */ 1731 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1732 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1733 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1734 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1735 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1736 sc->sc_ports[0].rp_number = 0; 1737 1738 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1739 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1740 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1741 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1742 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1743 sc->sc_ports[1].rp_number = 1; 1744 } else { 1745 /* default, port 0 = DVI, port 1 = CRT */ 1746 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1747 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1748 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1749 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1750 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1751 sc->sc_ports[0].rp_number = 1; 1752 1753 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1754 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1755 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1756 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1757 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1758 sc->sc_ports[1].rp_number = 0; 1759 } 1760 } 1761 1762 /* 1763 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1764 * these chips should use TVDAC for the VGA port. 1765 */ 1766 if (HAS_SDAC(sc)) { 1767 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1768 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1769 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1770 } else { 1771 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1772 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1773 } 1774 } else if (!HAS_CRTC2(sc)) { 1775 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1776 } 1777 1778 for (i = 0; i < 2; i++) { 1779 char edid[128]; 1780 uint8_t ddc; 1781 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1782 prop_data_t edid_data; 1783 1784 DPRINTF(("Port #%d:\n", i)); 1785 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1786 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1787 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1788 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1789 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1790 1791 sc->sc_ports[i].rp_edid_valid = 0; 1792 /* first look for static EDID data */ 1793 if ((edid_data = prop_dictionary_get(device_properties( 1794 sc->sc_dev), "EDID")) != NULL) { 1795 1796 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1797 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1798 if (edid_parse(edid, eip) == 0) { 1799 1800 sc->sc_ports[i].rp_edid_valid = 1; 1801 } 1802 } 1803 /* if we didn't find any we'll try to talk to the monitor */ 1804 if (sc->sc_ports[i].rp_edid_valid != 1) { 1805 1806 ddc = sc->sc_ports[i].rp_ddc_type; 1807 if (ddc != RADEON_DDC_NONE) { 1808 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1809 == 0) && (edid_parse(edid, eip) == 0)) { 1810 1811 sc->sc_ports[i].rp_edid_valid = 1; 1812 #ifdef RADEONFB_DEBUG 1813 edid_print(eip); 1814 #endif 1815 } 1816 } 1817 } 1818 } 1819 1820 return found; 1821 } 1822 1823 int 1824 radeonfb_gettmds(struct radeonfb_softc *sc) 1825 { 1826 int i; 1827 1828 if (!sc->sc_biossz) { 1829 goto nobios; 1830 } 1831 1832 if (IS_ATOM(sc)) { 1833 /* XXX: not done yet */ 1834 } else { 1835 uint16_t ptr; 1836 int n; 1837 1838 ptr = GETBIOS16(sc, 0x48); 1839 ptr = GETBIOS16(sc, ptr + 0x34); 1840 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1841 if (GETBIOS8(sc, ptr) == 3) { 1842 /* revision three table */ 1843 n = GETBIOS8(sc, ptr + 5) + 1; 1844 n = min(n, 4); 1845 1846 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1847 for (i = 0; i < n; i++) { 1848 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1849 ptr + i * 10 + 8); 1850 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1851 ptr + i * 10 + 0x10); 1852 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1853 sc->sc_tmds_pll[i].rtp_freq, 1854 sc->sc_tmds_pll[i].rtp_pll)); 1855 } 1856 return 0; 1857 } 1858 } 1859 1860 nobios: 1861 DPRINTF(("no suitable DFP table present\n")); 1862 for (i = 0; 1863 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1864 i++) { 1865 int j; 1866 1867 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1868 continue; 1869 1870 for (j = 0; j < 4; j++) { 1871 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1872 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1873 sc->sc_tmds_pll[j].rtp_freq, 1874 sc->sc_tmds_pll[j].rtp_pll)); 1875 } 1876 return 0; 1877 } 1878 1879 return -1; 1880 } 1881 1882 const struct videomode * 1883 radeonfb_modelookup(const char *name) 1884 { 1885 int i; 1886 1887 for (i = 0; i < videomode_count; i++) 1888 if (!strcmp(name, videomode_list[i].name)) 1889 return &videomode_list[i]; 1890 1891 return NULL; 1892 } 1893 1894 void 1895 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1896 { 1897 if (crtc) { 1898 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1899 RADEON_P2PLL_ATOMIC_UPDATE_R); 1900 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1901 } else { 1902 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1903 RADEON_PPLL_ATOMIC_UPDATE_R); 1904 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1905 } 1906 } 1907 1908 void 1909 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1910 { 1911 int i; 1912 1913 for (i = 10000; i; i--) { 1914 if (crtc) { 1915 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1916 RADEON_P2PLL_ATOMIC_UPDATE_R) 1917 break; 1918 } else { 1919 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1920 RADEON_PPLL_ATOMIC_UPDATE_R) 1921 break; 1922 } 1923 } 1924 } 1925 1926 void 1927 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1928 { 1929 uint32_t pbit = 0; 1930 uint32_t feed = 0; 1931 uint32_t data, refdiv, div0; 1932 1933 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1934 1935 if (crtc == 0) { 1936 1937 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1938 if (IS_R300(sc)) { 1939 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1940 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1941 } else { 1942 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1943 sc->sc_refdiv; 1944 } 1945 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1946 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1947 RADEON_PPLL_POST3_DIV_MASK); 1948 div0 |= pbit; 1949 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1950 1951 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1952 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1953 /* 1954 * nothing to do here, the PLL is already where we 1955 * want it 1956 */ 1957 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1958 ~RADEON_PLL_DIV_SEL); 1959 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1960 return; 1961 } 1962 1963 /* alright, we do need to reprogram stuff */ 1964 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1965 RADEON_VCLK_SRC_SEL_CPUCLK, 1966 ~RADEON_VCLK_SRC_SEL_MASK); 1967 1968 /* put vclk into reset, use atomic updates */ 1969 SETPLL(sc, RADEON_PPLL_CNTL, 1970 RADEON_PPLL_REFCLK_SEL | 1971 RADEON_PPLL_FBCLK_SEL | 1972 RADEON_PPLL_RESET | 1973 RADEON_PPLL_ATOMIC_UPDATE_EN | 1974 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1975 1976 /* select clock 0 */ 1977 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1978 ~RADEON_PLL_DIV_SEL); 1979 1980 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1981 1982 /* xf86-video-radeon does this, not sure why */ 1983 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1984 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1985 1986 /* use the atomic update */ 1987 radeonfb_pllwriteupdate(sc, crtc); 1988 1989 /* and wait for it to complete */ 1990 radeonfb_pllwaitatomicread(sc, crtc); 1991 1992 /* program HTOTAL (why?) */ 1993 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1994 1995 /* drop reset */ 1996 CLRPLL(sc, RADEON_PPLL_CNTL, 1997 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1998 RADEON_PPLL_ATOMIC_UPDATE_EN | 1999 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2000 2001 PRINTPLL(RADEON_PPLL_CNTL); 2002 PRINTPLL(RADEON_PPLL_REF_DIV); 2003 PRINTPLL(RADEON_PPLL_DIV_3); 2004 2005 /* give clock time to lock */ 2006 delay(50000); 2007 2008 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2009 RADEON_VCLK_SRC_SEL_PPLLCLK, 2010 ~RADEON_VCLK_SRC_SEL_MASK); 2011 2012 } else { 2013 2014 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2015 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2016 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2017 2018 /* put vclk into reset, use atomic updates */ 2019 SETPLL(sc, RADEON_P2PLL_CNTL, 2020 RADEON_P2PLL_RESET | 2021 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2022 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2023 2024 /* program reference divider */ 2025 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2026 ~RADEON_P2PLL_REF_DIV_MASK); 2027 2028 /* program feedback and post dividers */ 2029 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2030 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2031 RADEON_P2PLL_POST0_DIV_MASK); 2032 data |= pbit; 2033 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2034 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2035 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2036 2037 PRINTPLL(RADEON_P2PLL_REF_DIV); 2038 PRINTPLL(RADEON_P2PLL_DIV_0); 2039 2040 /* use the atomic update */ 2041 radeonfb_pllwriteupdate(sc, crtc); 2042 2043 /* and wait for it to complete */ 2044 radeonfb_pllwaitatomicread(sc, crtc); 2045 2046 /* program HTOTAL (why?) */ 2047 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2048 2049 /* drop reset */ 2050 CLRPLL(sc, RADEON_P2PLL_CNTL, 2051 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2052 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2053 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2054 2055 /* allow time for clock to lock */ 2056 delay(50000); 2057 2058 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2059 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2060 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2061 } 2062 PRINTREG(RADEON_CRTC_MORE_CNTL); 2063 } 2064 2065 void 2066 radeonfb_modeswitch(struct radeonfb_display *dp) 2067 { 2068 struct radeonfb_softc *sc = dp->rd_softc; 2069 int i; 2070 2071 /* blank the display while we switch modes */ 2072 radeonfb_blank(dp, 1); 2073 2074 #if 0 2075 SET32(sc, RADEON_CRTC_EXT_CNTL, 2076 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2077 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2078 #endif 2079 2080 /* these registers might get in the way... */ 2081 PUT32(sc, RADEON_OVR_CLR, 0); 2082 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2083 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2084 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2085 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2086 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2087 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2088 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2089 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2090 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2091 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2092 2093 for (i = 0; i < dp->rd_ncrtcs; i++) 2094 radeonfb_setcrtc(dp, i); 2095 2096 /* activate the display */ 2097 radeonfb_blank(dp, 0); 2098 } 2099 2100 void 2101 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2102 { 2103 int crtc; 2104 struct videomode *mode; 2105 struct radeonfb_softc *sc; 2106 struct radeonfb_crtc *cp; 2107 uint32_t v; 2108 uint32_t gencntl; 2109 uint32_t htotaldisp; 2110 uint32_t hsyncstrt; 2111 uint32_t vtotaldisp; 2112 uint32_t vsyncstrt; 2113 uint32_t fphsyncstrt; 2114 uint32_t fpvsyncstrt; 2115 uint32_t fphtotaldisp; 2116 uint32_t fpvtotaldisp; 2117 uint32_t pitch; 2118 2119 sc = dp->rd_softc; 2120 cp = &dp->rd_crtcs[index]; 2121 crtc = cp->rc_number; 2122 mode = &cp->rc_videomode; 2123 2124 #if 1 2125 pitch = dp->rd_stride / dp->rd_bpp; 2126 #else 2127 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2128 (sc->sc_maxbpp * 8)); 2129 #endif 2130 switch (crtc) { 2131 case 0: 2132 gencntl = RADEON_CRTC_GEN_CNTL; 2133 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2134 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2135 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2136 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2137 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2138 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2139 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2140 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2141 break; 2142 case 1: 2143 gencntl = RADEON_CRTC2_GEN_CNTL; 2144 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2145 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2146 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2147 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2148 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2149 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2150 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2151 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2152 break; 2153 default: 2154 panic("Bad CRTC!"); 2155 break; 2156 } 2157 2158 /* 2159 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2160 */ 2161 /* only bother with 32bpp and 8bpp */ 2162 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2163 2164 if (crtc == 1) { 2165 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2166 } else { 2167 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2168 } 2169 2170 if (mode->flags & VID_DBLSCAN) 2171 v |= RADEON_CRTC2_DBL_SCAN_EN; 2172 2173 if (mode->flags & VID_INTERLACE) 2174 v |= RADEON_CRTC2_INTERLACE_EN; 2175 2176 if (mode->flags & VID_CSYNC) { 2177 v |= RADEON_CRTC2_CSYNC_EN; 2178 if (crtc == 1) 2179 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2180 } 2181 2182 PUT32(sc, gencntl, v); 2183 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2184 2185 /* 2186 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2187 */ 2188 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2189 if (crtc == 0) { 2190 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2191 RADEON_CRTC_DISPLAY_DIS); 2192 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2193 if (mode->flags & VID_CSYNC) 2194 v |= RADEON_CRTC_VSYNC_TRISTAT; 2195 } 2196 /* unconditional turn on CRT, in case first CRTC is DFP */ 2197 v |= RADEON_CRTC_CRT_ON; 2198 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2199 PRINTREG(RADEON_CRTC_EXT_CNTL); 2200 2201 /* 2202 * H_TOTAL_DISP 2203 */ 2204 v = ((mode->hdisplay / 8) - 1) << 16; 2205 v |= (mode->htotal / 8) - 1; 2206 PUT32(sc, htotaldisp, v); 2207 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2208 PUT32(sc, fphtotaldisp, v); 2209 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2210 2211 /* 2212 * H_SYNC_STRT_WID 2213 */ 2214 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2215 v |= mode->hsync_start; 2216 if (mode->flags & VID_NHSYNC) 2217 v |= RADEON_CRTC_H_SYNC_POL; 2218 PUT32(sc, hsyncstrt, v); 2219 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2220 PUT32(sc, fphsyncstrt, v); 2221 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2222 2223 /* 2224 * V_TOTAL_DISP 2225 */ 2226 v = ((mode->vdisplay - 1) << 16); 2227 v |= (mode->vtotal - 1); 2228 PUT32(sc, vtotaldisp, v); 2229 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2230 PUT32(sc, fpvtotaldisp, v); 2231 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2232 2233 /* 2234 * V_SYNC_STRT_WID 2235 */ 2236 v = ((mode->vsync_end - mode->vsync_start) << 16); 2237 v |= (mode->vsync_start - 1); 2238 if (mode->flags & VID_NVSYNC) 2239 v |= RADEON_CRTC_V_SYNC_POL; 2240 PUT32(sc, vsyncstrt, v); 2241 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2242 PUT32(sc, fpvsyncstrt, v); 2243 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2244 2245 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2246 2247 switch (crtc) { 2248 case 0: 2249 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2250 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2251 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2252 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2253 2254 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2255 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2256 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2257 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2258 PRINTREG(RADEON_CRTC_EXT_CNTL); 2259 PRINTREG(RADEON_CRTC_GEN_CNTL); 2260 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2261 break; 2262 2263 case 1: 2264 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2265 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2266 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2267 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2268 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2269 RADEON_CRTC2_VSYNC_DIS | 2270 RADEON_CRTC2_HSYNC_DIS | 2271 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2272 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2273 break; 2274 } 2275 } 2276 2277 int 2278 radeonfb_isblank(struct radeonfb_display *dp) 2279 { 2280 uint32_t reg, mask; 2281 2282 if(!dp->rd_softc->sc_mapped) 2283 return 1; 2284 2285 if (dp->rd_crtcs[0].rc_number) { 2286 reg = RADEON_CRTC2_GEN_CNTL; 2287 mask = RADEON_CRTC2_DISP_DIS; 2288 } else { 2289 reg = RADEON_CRTC_EXT_CNTL; 2290 mask = RADEON_CRTC_DISPLAY_DIS; 2291 } 2292 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2293 } 2294 2295 void 2296 radeonfb_blank(struct radeonfb_display *dp, int blank) 2297 { 2298 struct radeonfb_softc *sc = dp->rd_softc; 2299 uint32_t reg, mask; 2300 uint32_t fpreg, fpval; 2301 int i; 2302 2303 if (!sc->sc_mapped) 2304 return; 2305 2306 for (i = 0; i < dp->rd_ncrtcs; i++) { 2307 2308 if (dp->rd_crtcs[i].rc_number) { 2309 reg = RADEON_CRTC2_GEN_CNTL; 2310 mask = RADEON_CRTC2_DISP_DIS; 2311 fpreg = RADEON_FP2_GEN_CNTL; 2312 fpval = RADEON_FP2_ON; 2313 } else { 2314 reg = RADEON_CRTC_EXT_CNTL; 2315 mask = RADEON_CRTC_DISPLAY_DIS; 2316 fpreg = RADEON_FP_GEN_CNTL; 2317 fpval = RADEON_FP_FPON; 2318 } 2319 2320 if (blank) { 2321 SET32(sc, reg, mask); 2322 CLR32(sc, fpreg, fpval); 2323 } else { 2324 CLR32(sc, reg, mask); 2325 SET32(sc, fpreg, fpval); 2326 } 2327 } 2328 PRINTREG(RADEON_FP_GEN_CNTL); 2329 PRINTREG(RADEON_FP2_GEN_CNTL); 2330 } 2331 2332 void 2333 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2334 long *defattr) 2335 { 2336 struct radeonfb_display *dp = cookie; 2337 struct rasops_info *ri = &scr->scr_ri; 2338 2339 /* initialize font subsystem */ 2340 wsfont_init(); 2341 2342 DPRINTF(("init screen called, existing %d\n", existing)); 2343 2344 ri->ri_depth = dp->rd_bpp; 2345 ri->ri_width = dp->rd_virtx; 2346 ri->ri_height = dp->rd_virty; 2347 ri->ri_stride = dp->rd_stride; 2348 ri->ri_flg = RI_CENTER; 2349 switch (ri->ri_depth) { 2350 case 8: 2351 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2352 break; 2353 case 32: 2354 ri->ri_flg |= RI_ENABLE_ALPHA; 2355 /* we run radeons in RGB even on SPARC hardware */ 2356 ri->ri_rnum = 8; 2357 ri->ri_gnum = 8; 2358 ri->ri_bnum = 8; 2359 ri->ri_rpos = 16; 2360 ri->ri_gpos = 8; 2361 ri->ri_bpos = 0; 2362 break; 2363 } 2364 2365 ri->ri_bits = (void *)dp->rd_fbptr; 2366 2367 #ifdef VCONS_DRAW_INTR 2368 scr->scr_flags |= VCONS_DONT_READ; 2369 #endif 2370 2371 if (existing) { 2372 ri->ri_flg |= RI_CLEAR; 2373 2374 /* start a modeswitch now */ 2375 radeonfb_modeswitch(dp); 2376 } 2377 2378 /* 2379 * XXX: font selection should be based on properties, with some 2380 * normal/reasonable default. 2381 */ 2382 2383 /* initialize and look for an initial font */ 2384 rasops_init(ri, 0, 0); 2385 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2386 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2387 2388 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2389 dp->rd_virtx / ri->ri_font->fontwidth); 2390 2391 /* enable acceleration */ 2392 dp->rd_putchar = ri->ri_ops.putchar; 2393 ri->ri_ops.copyrows = radeonfb_copyrows; 2394 ri->ri_ops.copycols = radeonfb_copycols; 2395 ri->ri_ops.eraserows = radeonfb_eraserows; 2396 ri->ri_ops.erasecols = radeonfb_erasecols; 2397 /* pick a putchar method based on font and Radeon model */ 2398 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2399 /* got a bitmap font */ 2400 if (IS_R300(dp->rd_softc)) { 2401 /* 2402 * radeonfb_putchar() doesn't work right on some R3xx 2403 * so we use software drawing here, the wrapper just 2404 * makes sure the engine is idle before scribbling 2405 * into vram 2406 */ 2407 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2408 } else { 2409 ri->ri_ops.putchar = radeonfb_putchar; 2410 } 2411 } else { 2412 /* got an alpha font */ 2413 switch(ri->ri_depth) { 2414 case 32: 2415 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2416 break; 2417 case 8: 2418 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2419 break; 2420 default: 2421 /* XXX this should never happen */ 2422 panic("%s: depth is not 8 or 32 but we got an" \ 2423 " alpha font?!", __func__); 2424 } 2425 } 2426 ri->ri_ops.cursor = radeonfb_cursor; 2427 } 2428 2429 void 2430 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2431 { 2432 uint32_t gen, ext, gen2 = 0; 2433 uint32_t agploc, aperbase, apersize, mcfbloc; 2434 2435 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2436 /* XXX */ 2437 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2438 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2439 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2440 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2441 2442 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2443 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2444 #if 0 2445 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2446 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2447 #endif 2448 2449 if (HAS_CRTC2(sc)) { 2450 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2451 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2452 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2453 } 2454 2455 delay(100000); 2456 2457 mcfbloc = (aperbase >> 16) | 2458 ((aperbase + (apersize - 1)) & 0xffff0000); 2459 2460 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2461 sc->sc_memsz = apersize; 2462 2463 if (((agploc & 0xffff) << 16) != 2464 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2465 agploc = mcfbloc & 0xffff0000U; 2466 agploc |= ((agploc + 0x10000) >> 16); 2467 } 2468 2469 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2470 2471 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2472 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2473 2474 DPRINTF(("aperbase = %u\n", aperbase)); 2475 PRINTREG(RADEON_MC_FB_LOCATION); 2476 PRINTREG(RADEON_MC_AGP_LOCATION); 2477 2478 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2479 2480 if (HAS_CRTC2(sc)) 2481 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2482 2483 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2484 2485 #if 0 2486 /* XXX: what is this AGP garbage? :-) */ 2487 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2488 #endif 2489 2490 delay(100000); 2491 2492 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2493 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2494 2495 if (HAS_CRTC2(sc)) 2496 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2497 } 2498 2499 void 2500 radeonfb_init_misc(struct radeonfb_softc *sc) 2501 { 2502 PUT32(sc, RADEON_BUS_CNTL, 2503 RADEON_BUS_MASTER_DIS | 2504 RADEON_BUS_PREFETCH_MODE_ACT | 2505 RADEON_BUS_PCI_READ_RETRY_EN | 2506 RADEON_BUS_PCI_WRT_RETRY_EN | 2507 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2508 RADEON_BUS_MSTR_RD_MULT | 2509 RADEON_BUS_MSTR_RD_LINE | 2510 RADEON_BUS_RD_DISCARD_EN | 2511 RADEON_BUS_MSTR_DISCONNECT_EN | 2512 RADEON_BUS_READ_BURST); 2513 2514 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2515 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2516 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2517 PUT32(sc, RADEON_RBBM_CNTL, 2518 (3 << RADEON_RB_SETTLE_SHIFT) | 2519 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2520 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2521 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2522 2523 /* XXX: figure out what these mean! */ 2524 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2525 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2526 #if 0 2527 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2528 #endif 2529 2530 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2531 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2532 } 2533 2534 /* 2535 * This loads a linear color map for true color. 2536 */ 2537 void 2538 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2539 { 2540 int i; 2541 uint32_t vclk; 2542 2543 #define DAC_WIDTH ((1 << 10) - 1) 2544 #define CLUT_WIDTH ((1 << 8) - 1) 2545 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2546 2547 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2548 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2549 2550 if (crtc) 2551 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2552 else 2553 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2554 2555 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2556 if (sc->sc_displays[crtc].rd_bpp == 0) 2557 sc->sc_displays[crtc].rd_bpp = RADEONFB_DEFAULT_DEPTH; 2558 2559 if (sc->sc_displays[crtc].rd_bpp == 8) { 2560 /* ANSI palette */ 2561 int j = 0; 2562 uint32_t tmp, r, g, b; 2563 2564 for (i = 0; i <= CLUT_WIDTH; ++i) { 2565 tmp = i & 0xe0; 2566 /* 2567 * replicate bits so 0xe0 maps to a red value of 0xff 2568 * in order to make white look actually white 2569 */ 2570 tmp |= (tmp >> 3) | (tmp >> 6); 2571 r = tmp; 2572 2573 tmp = (i & 0x1c) << 3; 2574 tmp |= (tmp >> 3) | (tmp >> 6); 2575 g = tmp; 2576 2577 tmp = (i & 0x03) << 6; 2578 tmp |= tmp >> 2; 2579 tmp |= tmp >> 4; 2580 b = tmp; 2581 PUT32(sc, RADEON_PALETTE_30_DATA, 2582 (r << 22) | 2583 (g << 12) | 2584 (b << 2)); 2585 j += 3; 2586 } 2587 } else { 2588 /* linear ramp */ 2589 for (i = 0; i <= CLUT_WIDTH; ++i) { 2590 PUT32(sc, RADEON_PALETTE_30_DATA, 2591 (CLUT_COLOR(i) << 10) | 2592 (CLUT_COLOR(i) << 20) | 2593 (CLUT_COLOR(i))); 2594 } 2595 } 2596 2597 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2598 PRINTREG(RADEON_DAC_CNTL2); 2599 2600 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2601 } 2602 2603 /* 2604 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2605 */ 2606 void 2607 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2608 { 2609 uint32_t tmp, save; 2610 2611 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2612 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2613 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2614 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2615 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2616 } 2617 2618 /* 2619 * Acceleration entry points. 2620 */ 2621 2622 /* this one draws characters using bitmap fonts */ 2623 static void 2624 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2625 { 2626 struct rasops_info *ri = cookie; 2627 struct vcons_screen *scr = ri->ri_hw; 2628 struct radeonfb_display *dp = scr->scr_cookie; 2629 struct radeonfb_softc *sc = dp->rd_softc; 2630 struct wsdisplay_font *font = PICK_FONT(ri, c); 2631 uint32_t w, h; 2632 int xd, yd, offset, i; 2633 uint32_t bg, fg, gmc; 2634 uint32_t reg; 2635 uint8_t *data8; 2636 uint16_t *data16; 2637 void *data; 2638 2639 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2640 return; 2641 2642 if (!CHAR_IN_FONT(c, font)) 2643 return; 2644 2645 w = font->fontwidth; 2646 h = font->fontheight; 2647 2648 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2649 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2650 2651 xd = ri->ri_xorigin + col * w; 2652 yd = ri->ri_yorigin + row * h; 2653 2654 if (c == 0x20) { 2655 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2656 return; 2657 } 2658 data = WSFONT_GLYPH(c, font); 2659 2660 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2661 2662 radeonfb_wait_fifo(sc, 9); 2663 2664 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2665 RADEON_GMC_BRUSH_NONE | 2666 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2667 RADEON_GMC_DST_CLIPPING | 2668 RADEON_ROP3_S | 2669 RADEON_DP_SRC_SOURCE_HOST_DATA | 2670 RADEON_GMC_CLR_CMP_CNTL_DIS | 2671 RADEON_GMC_WR_MSK_DIS | 2672 gmc); 2673 2674 PUT32(sc, RADEON_SC_LEFT, xd); 2675 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2676 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2677 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2678 PUT32(sc, RADEON_DP_CNTL, 2679 RADEON_DST_X_LEFT_TO_RIGHT | 2680 RADEON_DST_Y_TOP_TO_BOTTOM); 2681 2682 PUT32(sc, RADEON_SRC_X_Y, 0); 2683 offset = 32 - (font->stride << 3); 2684 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2685 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2686 2687 radeonfb_wait_fifo(sc, h); 2688 switch (font->stride) { 2689 case 1: { 2690 data8 = data; 2691 for (i = 0; i < h; i++) { 2692 reg = *data8; 2693 #if BYTE_ORDER == LITTLE_ENDIAN 2694 reg = reg << 24; 2695 #endif 2696 bus_space_write_stream_4(sc->sc_regt, 2697 sc->sc_regh, RADEON_HOST_DATA0, reg); 2698 data8++; 2699 } 2700 break; 2701 } 2702 case 2: { 2703 data16 = data; 2704 for (i = 0; i < h; i++) { 2705 reg = *data16; 2706 #if BYTE_ORDER == LITTLE_ENDIAN 2707 reg = reg << 16; 2708 #endif 2709 bus_space_write_stream_4(sc->sc_regt, 2710 sc->sc_regh, RADEON_HOST_DATA0, reg); 2711 data16++; 2712 } 2713 break; 2714 } 2715 } 2716 if (attr & 1) 2717 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2718 } 2719 2720 /* ... while this one is for anti-aliased ones */ 2721 static void 2722 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2723 { 2724 struct rasops_info *ri = cookie; 2725 struct vcons_screen *scr = ri->ri_hw; 2726 struct radeonfb_display *dp = scr->scr_cookie; 2727 struct radeonfb_softc *sc = dp->rd_softc; 2728 struct wsdisplay_font *font = PICK_FONT(ri, c); 2729 uint32_t bg, fg, gmc; 2730 uint8_t *data; 2731 int w, h, xd, yd; 2732 int i, r, g, b, aval; 2733 int rf, gf, bf, rb, gb, bb; 2734 uint32_t pixel; 2735 int rv; 2736 2737 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2738 return; 2739 2740 if (!CHAR_IN_FONT(c, font)) 2741 return; 2742 2743 w = font->fontwidth; 2744 h = font->fontheight; 2745 2746 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2747 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2748 2749 xd = ri->ri_xorigin + col * w; 2750 yd = ri->ri_yorigin + row * h; 2751 2752 if (c == 0x20) { 2753 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2754 if (attr & 1) 2755 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2756 return; 2757 } 2758 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2759 if (rv == GC_OK) 2760 return; 2761 2762 data = WSFONT_GLYPH(c, font); 2763 2764 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2765 2766 radeonfb_wait_fifo(sc, 5); 2767 2768 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2769 RADEON_GMC_BRUSH_NONE | 2770 RADEON_GMC_SRC_DATATYPE_COLOR | 2771 RADEON_ROP3_S | 2772 RADEON_DP_SRC_SOURCE_HOST_DATA | 2773 RADEON_GMC_CLR_CMP_CNTL_DIS | 2774 RADEON_GMC_WR_MSK_DIS | 2775 gmc); 2776 2777 PUT32(sc, RADEON_DP_CNTL, 2778 RADEON_DST_X_LEFT_TO_RIGHT | 2779 RADEON_DST_Y_TOP_TO_BOTTOM); 2780 2781 PUT32(sc, RADEON_SRC_X_Y, 0); 2782 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2783 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2784 2785 rf = (fg >> 16) & 0xff; 2786 rb = (bg >> 16) & 0xff; 2787 gf = (fg >> 8) & 0xff; 2788 gb = (bg >> 8) & 0xff; 2789 bf = fg & 0xff; 2790 bb = bg & 0xff; 2791 2792 /* 2793 * I doubt we can upload data faster than even the slowest Radeon 2794 * could process them, especially when doing the alpha blending stuff 2795 * along the way, so just make sure there's some room in the FIFO and 2796 * then hammer away 2797 * As it turns out we can, so make periodic stops to let the FIFO 2798 * drain. 2799 */ 2800 radeonfb_wait_fifo(sc, 20); 2801 for (i = 0; i < ri->ri_fontscale; i++) { 2802 aval = *data; 2803 data++; 2804 if (aval == 0) { 2805 pixel = bg; 2806 } else if (aval == 255) { 2807 pixel = fg; 2808 } else { 2809 r = aval * rf + (255 - aval) * rb; 2810 g = aval * gf + (255 - aval) * gb; 2811 b = aval * bf + (255 - aval) * bb; 2812 pixel = (r & 0xff00) << 8 | 2813 (g & 0xff00) | 2814 (b & 0xff00) >> 8; 2815 } 2816 if (i & 16) 2817 radeonfb_wait_fifo(sc, 20); 2818 PUT32(sc, RADEON_HOST_DATA0, pixel); 2819 } 2820 if (rv == GC_ADD) { 2821 glyphcache_add(&dp->rd_gc, c, xd, yd); 2822 } else 2823 if (attr & 1) 2824 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2825 2826 } 2827 2828 static void 2829 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2830 { 2831 struct rasops_info *ri = cookie; 2832 struct vcons_screen *scr = ri->ri_hw; 2833 struct radeonfb_display *dp = scr->scr_cookie; 2834 struct radeonfb_softc *sc = dp->rd_softc; 2835 struct wsdisplay_font *font = PICK_FONT(ri, c); 2836 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2837 int i, x, y, wi, he, r, g, b, aval; 2838 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2839 uint8_t *data8; 2840 int rv, cnt; 2841 2842 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2843 return; 2844 2845 if (!CHAR_IN_FONT(c, font)) 2846 return; 2847 2848 wi = font->fontwidth; 2849 he = font->fontheight; 2850 2851 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2852 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2853 2854 x = ri->ri_xorigin + col * wi; 2855 y = ri->ri_yorigin + row * he; 2856 2857 if (c == 0x20) { 2858 radeonfb_rectfill(dp, x, y, wi, he, bg); 2859 if (attr & 1) 2860 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2861 return; 2862 } 2863 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2864 if (rv == GC_OK) 2865 return; 2866 2867 data8 = WSFONT_GLYPH(c, font); 2868 2869 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2870 2871 radeonfb_wait_fifo(sc, 5); 2872 2873 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2874 RADEON_GMC_BRUSH_NONE | 2875 RADEON_GMC_SRC_DATATYPE_COLOR | 2876 RADEON_ROP3_S | 2877 RADEON_DP_SRC_SOURCE_HOST_DATA | 2878 RADEON_GMC_CLR_CMP_CNTL_DIS | 2879 RADEON_GMC_WR_MSK_DIS | 2880 gmc); 2881 2882 PUT32(sc, RADEON_DP_CNTL, 2883 RADEON_DST_X_LEFT_TO_RIGHT | 2884 RADEON_DST_Y_TOP_TO_BOTTOM); 2885 2886 PUT32(sc, RADEON_SRC_X_Y, 0); 2887 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2888 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2889 2890 /* 2891 * we need the RGB colours here, so get offsets into rasops_cmap 2892 */ 2893 fgo = ((attr >> 24) & 0xf) * 3; 2894 bgo = ((attr >> 16) & 0xf) * 3; 2895 2896 r0 = rasops_cmap[bgo]; 2897 r1 = rasops_cmap[fgo]; 2898 g0 = rasops_cmap[bgo + 1]; 2899 g1 = rasops_cmap[fgo + 1]; 2900 b0 = rasops_cmap[bgo + 2]; 2901 b1 = rasops_cmap[fgo + 2]; 2902 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2903 bg8 = R3G3B2(r0, g0, b0); 2904 fg8 = R3G3B2(r1, g1, b1); 2905 2906 radeonfb_wait_fifo(sc, 20); 2907 cnt = 0; 2908 for (i = 0; i < ri->ri_fontscale; i++) { 2909 aval = *data8; 2910 if (aval == 0) { 2911 pixel = bg8; 2912 } else if (aval == 255) { 2913 pixel = fg8; 2914 } else { 2915 r = aval * r1 + (255 - aval) * r0; 2916 g = aval * g1 + (255 - aval) * g0; 2917 b = aval * b1 + (255 - aval) * b0; 2918 pixel = ((r & 0xe000) >> 8) | 2919 ((g & 0xe000) >> 11) | 2920 ((b & 0xc000) >> 14); 2921 } 2922 latch |= pixel << (8 * (i & 3)); 2923 /* write in 32bit chunks */ 2924 if ((i & 3) == 3) { 2925 PUT32(sc, RADEON_HOST_DATA0, latch); 2926 /* 2927 * not strictly necessary, old data should be shifted 2928 * out 2929 */ 2930 latch = 0; 2931 cnt++; 2932 if (cnt > 16) { 2933 cnt = 0; 2934 radeonfb_wait_fifo(sc, 20); 2935 } 2936 } 2937 data8++; 2938 } 2939 /* if we have pixels left in latch write them out */ 2940 if ((i & 3) != 0) { 2941 /* 2942 * radeon is weird - apparently leftover pixels are written 2943 * from the middle, not from the left as everything else 2944 */ 2945 PUT32(sc, RADEON_HOST_DATA0, latch); 2946 } 2947 2948 if (rv == GC_ADD) { 2949 glyphcache_add(&dp->rd_gc, c, x, y); 2950 } else 2951 if (attr & 1) 2952 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2953 2954 } 2955 2956 /* 2957 * wrapper for software character drawing 2958 * just sync the engine and call rasops*_putchar() 2959 */ 2960 2961 static void 2962 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2963 { 2964 struct rasops_info *ri = cookie; 2965 struct vcons_screen *scr = ri->ri_hw; 2966 struct radeonfb_display *dp = scr->scr_cookie; 2967 2968 radeonfb_engine_idle(dp->rd_softc); 2969 dp->rd_putchar(ri, row, col, c, attr); 2970 } 2971 2972 static void 2973 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2974 { 2975 struct rasops_info *ri = cookie; 2976 struct vcons_screen *scr = ri->ri_hw; 2977 struct radeonfb_display *dp = scr->scr_cookie; 2978 uint32_t x, y, w, h, fg, bg, ul; 2979 2980 /* XXX: check for full emulation mode? */ 2981 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2982 x = ri->ri_xorigin; 2983 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2984 w = ri->ri_emuwidth; 2985 h = ri->ri_font->fontheight * nrows; 2986 2987 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2988 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2989 } 2990 } 2991 2992 static void 2993 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2994 { 2995 struct rasops_info *ri = cookie; 2996 struct vcons_screen *scr = ri->ri_hw; 2997 struct radeonfb_display *dp = scr->scr_cookie; 2998 uint32_t x, ys, yd, w, h; 2999 3000 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3001 x = ri->ri_xorigin; 3002 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3003 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3004 w = ri->ri_emuwidth; 3005 h = ri->ri_font->fontheight * nrows; 3006 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3007 RADEON_ROP3_S); 3008 } 3009 } 3010 3011 static void 3012 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3013 { 3014 struct rasops_info *ri = cookie; 3015 struct vcons_screen *scr = ri->ri_hw; 3016 struct radeonfb_display *dp = scr->scr_cookie; 3017 uint32_t xs, xd, y, w, h; 3018 3019 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3020 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3021 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3022 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3023 w = ri->ri_font->fontwidth * ncols; 3024 h = ri->ri_font->fontheight; 3025 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3026 RADEON_ROP3_S); 3027 } 3028 } 3029 3030 static void 3031 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3032 long fillattr) 3033 { 3034 struct rasops_info *ri = cookie; 3035 struct vcons_screen *scr = ri->ri_hw; 3036 struct radeonfb_display *dp = scr->scr_cookie; 3037 uint32_t x, y, w, h, fg, bg, ul; 3038 3039 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3040 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3041 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3042 w = ri->ri_font->fontwidth * ncols; 3043 h = ri->ri_font->fontheight; 3044 3045 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3046 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3047 } 3048 } 3049 3050 static void 3051 radeonfb_cursor(void *cookie, int on, int row, int col) 3052 { 3053 struct rasops_info *ri = cookie; 3054 struct vcons_screen *scr = ri->ri_hw; 3055 struct radeonfb_display *dp = scr->scr_cookie; 3056 int x, y, wi, he; 3057 3058 wi = ri->ri_font->fontwidth; 3059 he = ri->ri_font->fontheight; 3060 3061 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3062 x = ri->ri_ccol * wi + ri->ri_xorigin; 3063 y = ri->ri_crow * he + ri->ri_yorigin; 3064 /* first turn off the old cursor */ 3065 if (ri->ri_flg & RI_CURSOR) { 3066 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3067 RADEON_ROP3_Dn); 3068 ri->ri_flg &= ~RI_CURSOR; 3069 } 3070 ri->ri_crow = row; 3071 ri->ri_ccol = col; 3072 /* then (possibly) turn on the new one */ 3073 if (on) { 3074 x = ri->ri_ccol * wi + ri->ri_xorigin; 3075 y = ri->ri_crow * he + ri->ri_yorigin; 3076 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3077 RADEON_ROP3_Dn); 3078 ri->ri_flg |= RI_CURSOR; 3079 } 3080 } else { 3081 scr->scr_ri.ri_crow = row; 3082 scr->scr_ri.ri_ccol = col; 3083 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3084 } 3085 } 3086 3087 /* 3088 * Underlying acceleration support. 3089 */ 3090 3091 static void 3092 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3093 int width, int height, uint32_t color) 3094 { 3095 struct radeonfb_softc *sc = dp->rd_softc; 3096 uint32_t gmc; 3097 3098 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3099 3100 radeonfb_wait_fifo(sc, 6); 3101 3102 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3103 RADEON_GMC_BRUSH_SOLID_COLOR | 3104 RADEON_GMC_SRC_DATATYPE_COLOR | 3105 RADEON_GMC_CLR_CMP_CNTL_DIS | 3106 RADEON_ROP3_P | gmc); 3107 3108 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3109 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3110 PUT32(sc, RADEON_DP_CNTL, 3111 RADEON_DST_X_LEFT_TO_RIGHT | 3112 RADEON_DST_Y_TOP_TO_BOTTOM); 3113 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3114 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3115 3116 } 3117 3118 static void 3119 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3120 int width, int height, long attr) 3121 { 3122 struct radeonfb_display *dp = cookie; 3123 3124 radeonfb_rectfill(dp, dstx, dsty, width, height, 3125 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3126 } 3127 3128 static void 3129 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3130 int dstx, int dsty, int width, int height, int rop) 3131 { 3132 struct radeonfb_display *dp = cookie; 3133 struct radeonfb_softc *sc = dp->rd_softc; 3134 uint32_t gmc; 3135 uint32_t dir; 3136 3137 if (dsty < srcy) { 3138 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3139 } else { 3140 srcy += height - 1; 3141 dsty += height - 1; 3142 dir = 0; 3143 } 3144 if (dstx < srcx) { 3145 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3146 } else { 3147 srcx += width - 1; 3148 dstx += width - 1; 3149 } 3150 3151 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3152 3153 radeonfb_wait_fifo(sc, 6); 3154 3155 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3156 RADEON_GMC_BRUSH_SOLID_COLOR | 3157 RADEON_GMC_SRC_DATATYPE_COLOR | 3158 RADEON_GMC_CLR_CMP_CNTL_DIS | 3159 RADEON_DP_SRC_SOURCE_MEMORY | 3160 rop | gmc); 3161 3162 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3163 PUT32(sc, RADEON_DP_CNTL, dir); 3164 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3165 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3166 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3167 } 3168 3169 static void 3170 radeonfb_engine_idle(struct radeonfb_softc *sc) 3171 { 3172 3173 radeonfb_wait_fifo(sc, 64); 3174 while ((GET32(sc, RADEON_RBBM_STATUS) & 3175 RADEON_RBBM_ACTIVE) != 0); 3176 radeonfb_engine_flush(sc); 3177 } 3178 3179 static inline void 3180 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3181 { 3182 int i; 3183 3184 for (i = RADEON_TIMEOUT; i; i--) { 3185 if ((GET32(sc, RADEON_RBBM_STATUS) & 3186 RADEON_RBBM_FIFOCNT_MASK) >= n) 3187 return; 3188 } 3189 #ifdef DIAGNOSTIC 3190 if (!i) 3191 printf("%s: timed out waiting for fifo (%x)\n", 3192 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3193 #endif 3194 } 3195 3196 static void 3197 radeonfb_engine_flush(struct radeonfb_softc *sc) 3198 { 3199 int i = 0; 3200 3201 if (IS_R300(sc)) { 3202 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3203 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3204 i++; 3205 } 3206 } else { 3207 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3208 RADEON_RB2D_DC_FLUSH_ALL); 3209 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3210 RADEON_RB2D_DC_BUSY) { 3211 i++; 3212 } 3213 } 3214 #ifdef DIAGNOSTIC 3215 if (i > RADEON_TIMEOUT) 3216 printf("%s: engine flush timed out!\n", XNAME(sc)); 3217 #endif 3218 } 3219 3220 static inline void 3221 radeonfb_unclip(struct radeonfb_softc *sc) 3222 { 3223 3224 radeonfb_wait_fifo(sc, 2); 3225 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3226 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3227 } 3228 3229 static void 3230 radeonfb_engine_init(struct radeonfb_display *dp) 3231 { 3232 struct radeonfb_softc *sc = dp->rd_softc; 3233 uint32_t pitch; 3234 volatile uint32_t junk; 3235 3236 /* no 3D */ 3237 PUT32(sc, RADEON_RB3D_CNTL, 0); 3238 3239 radeonfb_engine_reset(sc); 3240 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3241 3242 radeonfb_wait_fifo(sc, 1); 3243 if (!IS_R300(sc)) 3244 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3245 3246 radeonfb_wait_fifo(sc, 3); 3247 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3248 (pitch << 22) | (sc->sc_aperbase >> 10)); 3249 3250 3251 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3252 (pitch << 22) | (sc->sc_aperbase >> 10)); 3253 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3254 (pitch << 22) | (sc->sc_aperbase >> 10)); 3255 3256 junk = GET32(sc, RADEON_DP_DATATYPE); 3257 3258 /* default scissors -- no clipping */ 3259 radeonfb_wait_fifo(sc, 1); 3260 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3261 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3262 3263 radeonfb_wait_fifo(sc, 1); 3264 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3265 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3266 RADEON_GMC_CLR_CMP_CNTL_DIS | 3267 RADEON_GMC_BRUSH_SOLID_COLOR | 3268 RADEON_GMC_SRC_DATATYPE_COLOR); 3269 3270 radeonfb_wait_fifo(sc, 10); 3271 PUT32(sc, RADEON_DST_LINE_START, 0); 3272 PUT32(sc, RADEON_DST_LINE_END, 0); 3273 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3274 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3275 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3276 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3277 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3278 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3279 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3280 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3281 radeonfb_engine_idle(sc); 3282 } 3283 3284 static void 3285 radeonfb_engine_reset(struct radeonfb_softc *sc) 3286 { 3287 uint32_t hpc, rbbm, mclkcntl, clkindex; 3288 3289 radeonfb_engine_flush(sc); 3290 3291 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3292 if (HAS_R300CG(sc)) 3293 radeonfb_r300cg_workaround(sc); 3294 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3295 3296 /* 3297 * According to comments in XFree code, resetting the HDP via 3298 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3299 * So we use HOST_PATH_CNTL instead. 3300 */ 3301 3302 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3303 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3304 if (IS_R300(sc)) { 3305 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3306 RADEON_SOFT_RESET_CP | 3307 RADEON_SOFT_RESET_HI | 3308 RADEON_SOFT_RESET_E2); 3309 GET32(sc, RADEON_RBBM_SOFT_RESET); 3310 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3311 /* 3312 * XXX: this bit is not defined in any ATI docs I have, 3313 * nor in the XFree code, but XFree does it. Why? 3314 */ 3315 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3316 } else { 3317 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3318 RADEON_SOFT_RESET_CP | 3319 RADEON_SOFT_RESET_SE | 3320 RADEON_SOFT_RESET_RE | 3321 RADEON_SOFT_RESET_PP | 3322 RADEON_SOFT_RESET_E2 | 3323 RADEON_SOFT_RESET_RB); 3324 GET32(sc, RADEON_RBBM_SOFT_RESET); 3325 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3326 ~(RADEON_SOFT_RESET_CP | 3327 RADEON_SOFT_RESET_SE | 3328 RADEON_SOFT_RESET_RE | 3329 RADEON_SOFT_RESET_PP | 3330 RADEON_SOFT_RESET_E2 | 3331 RADEON_SOFT_RESET_RB)); 3332 GET32(sc, RADEON_RBBM_SOFT_RESET); 3333 } 3334 3335 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3336 GET32(sc, RADEON_HOST_PATH_CNTL); 3337 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3338 3339 if (IS_R300(sc)) 3340 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3341 3342 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3343 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3344 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3345 3346 if (HAS_R300CG(sc)) 3347 radeonfb_r300cg_workaround(sc); 3348 } 3349 3350 static int 3351 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3352 { 3353 int x, y; 3354 3355 x = pos->x; 3356 y = pos->y; 3357 3358 /* 3359 * This doesn't let a cursor move off the screen. I'm not 3360 * sure if this will have negative effects for e.g. Xinerama. 3361 * I'd guess Xinerama handles it by changing the cursor shape, 3362 * but that needs verification. 3363 */ 3364 if (x >= dp->rd_virtx) 3365 x = dp->rd_virtx - 1; 3366 if (x < 0) 3367 x = 0; 3368 if (y >= dp->rd_virty) 3369 y = dp->rd_virty - 1; 3370 if (y < 0) 3371 y = 0; 3372 3373 dp->rd_cursor.rc_pos.x = x; 3374 dp->rd_cursor.rc_pos.y = y; 3375 3376 radeonfb_cursor_position(dp); 3377 return 0; 3378 } 3379 3380 static int 3381 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3382 { 3383 unsigned flags; 3384 3385 uint8_t r[2], g[2], b[2]; 3386 unsigned index, count; 3387 int i, err; 3388 int pitch, size; 3389 struct radeonfb_cursor nc; 3390 3391 flags = wc->which; 3392 3393 /* copy old values */ 3394 nc = dp->rd_cursor; 3395 3396 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3397 index = wc->cmap.index; 3398 count = wc->cmap.count; 3399 3400 if (index >= 2 || (index + count) > 2) 3401 return EINVAL; 3402 3403 err = copyin(wc->cmap.red, &r[index], count); 3404 if (err) 3405 return err; 3406 err = copyin(wc->cmap.green, &g[index], count); 3407 if (err) 3408 return err; 3409 err = copyin(wc->cmap.blue, &b[index], count); 3410 if (err) 3411 return err; 3412 3413 for (i = index; i < index + count; i++) { 3414 nc.rc_cmap[i] = 3415 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3416 } 3417 } 3418 3419 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3420 if ((wc->size.x > RADEON_CURSORMAXX) || 3421 (wc->size.y > RADEON_CURSORMAXY)) 3422 return EINVAL; 3423 3424 /* figure bytes per line */ 3425 pitch = (wc->size.x + 7) / 8; 3426 size = pitch * wc->size.y; 3427 3428 /* clear the old cursor and mask */ 3429 memset(nc.rc_image, 0, 512); 3430 memset(nc.rc_mask, 0, 512); 3431 3432 nc.rc_size = wc->size; 3433 3434 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3435 return err; 3436 3437 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3438 return err; 3439 } 3440 3441 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3442 nc.rc_hot = wc->hot; 3443 if (nc.rc_hot.x >= nc.rc_size.x) 3444 nc.rc_hot.x = nc.rc_size.x - 1; 3445 if (nc.rc_hot.y >= nc.rc_size.y) 3446 nc.rc_hot.y = nc.rc_size.y - 1; 3447 } 3448 3449 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3450 nc.rc_pos = wc->pos; 3451 if (nc.rc_pos.x >= dp->rd_virtx) 3452 nc.rc_pos.x = dp->rd_virtx - 1; 3453 #if 0 3454 if (nc.rc_pos.x < 0) 3455 nc.rc_pos.x = 0; 3456 #endif 3457 if (nc.rc_pos.y >= dp->rd_virty) 3458 nc.rc_pos.y = dp->rd_virty - 1; 3459 #if 0 3460 if (nc.rc_pos.y < 0) 3461 nc.rc_pos.y = 0; 3462 #endif 3463 } 3464 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3465 nc.rc_visible = wc->enable; 3466 } 3467 3468 dp->rd_cursor = nc; 3469 radeonfb_cursor_update(dp, wc->which); 3470 3471 return 0; 3472 } 3473 3474 /* 3475 * Change the cursor shape. Call this with the cursor locked to avoid 3476 * flickering/tearing. 3477 */ 3478 static void 3479 radeonfb_cursor_shape(struct radeonfb_display *dp) 3480 { 3481 uint8_t and[512], xor[512]; 3482 int i, j, src, dst, pitch; 3483 const uint8_t *msk = dp->rd_cursor.rc_mask; 3484 const uint8_t *img = dp->rd_cursor.rc_image; 3485 3486 /* 3487 * Radeon cursor data interleaves one line of AND data followed 3488 * by a line of XOR data. (Each line corresponds to a whole hardware 3489 * pitch - i.e. 64 pixels or 8 bytes.) 3490 * 3491 * The cursor is displayed using the following table: 3492 * 3493 * AND XOR Result 3494 * ---------------------- 3495 * 0 0 Cursor color 0 3496 * 0 1 Cursor color 1 3497 * 1 0 Transparent 3498 * 1 1 Complement of background 3499 * 3500 * Our masks are therefore different from what we were passed. 3501 * Passed in, I'm assuming the data represents either color 0 or 1, 3502 * and a mask, so the passed in table looks like: 3503 * 3504 * IMG Mask Result 3505 * ----------------------- 3506 * 0 0 Transparent 3507 * 0 1 Cursor color 0 3508 * 1 0 Transparent 3509 * 1 1 Cursor color 1 3510 * 3511 * IF mask bit == 1, AND = 0, XOR = color. 3512 * IF mask bit == 0, AND = 1, XOR = 0. 3513 * 3514 * hence: AND = ~(mask); XOR = color & ~(mask); 3515 */ 3516 3517 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3518 3519 /* start by assuming all bits are transparent */ 3520 memset(and, 0xff, 512); 3521 memset(xor, 0x00, 512); 3522 3523 src = 0; 3524 dst = 0; 3525 for (i = 0; i < 64; i++) { 3526 for (j = 0; j < 64; j += 8) { 3527 if ((i < dp->rd_cursor.rc_size.y) && 3528 (j < dp->rd_cursor.rc_size.x)) { 3529 3530 /* take care to leave odd bits alone */ 3531 and[dst] &= ~(msk[src]); 3532 xor[dst] = img[src] & msk[src]; 3533 src++; 3534 } 3535 dst++; 3536 } 3537 } 3538 3539 /* copy the image into place */ 3540 for (i = 0; i < 64; i++) { 3541 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3542 &and[i * 8], 8); 3543 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3544 &xor[i * 8], 8); 3545 } 3546 } 3547 3548 static void 3549 radeonfb_cursor_position(struct radeonfb_display *dp) 3550 { 3551 struct radeonfb_softc *sc = dp->rd_softc; 3552 uint32_t offset, hvoff, hvpos; /* registers */ 3553 uint32_t coff; /* cursor offset */ 3554 int i, x, y, xoff, yoff, crtcoff; 3555 3556 /* 3557 * XXX: this also needs to handle pan/scan 3558 */ 3559 for (i = 0; i < dp->rd_ncrtcs; i++) { 3560 3561 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3562 3563 if (rcp->rc_number) { 3564 offset = RADEON_CUR2_OFFSET; 3565 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3566 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3567 crtcoff = RADEON_CRTC2_OFFSET; 3568 } else { 3569 offset = RADEON_CUR_OFFSET; 3570 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3571 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3572 crtcoff = RADEON_CRTC_OFFSET; 3573 } 3574 3575 x = dp->rd_cursor.rc_pos.x; 3576 y = dp->rd_cursor.rc_pos.y; 3577 3578 while (y < rcp->rc_yoffset) { 3579 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3580 } 3581 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3582 rcp->rc_yoffset += RADEON_PANINCREMENT; 3583 } 3584 while (x < rcp->rc_xoffset) { 3585 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3586 } 3587 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3588 rcp->rc_xoffset += RADEON_PANINCREMENT; 3589 } 3590 3591 /* adjust for the cursor's hotspot */ 3592 x -= dp->rd_cursor.rc_hot.x; 3593 y -= dp->rd_cursor.rc_hot.y; 3594 xoff = yoff = 0; 3595 3596 if (x >= dp->rd_virtx) 3597 x = dp->rd_virtx - 1; 3598 if (y >= dp->rd_virty) 3599 y = dp->rd_virty - 1; 3600 3601 /* now adjust cursor so it is relative to viewport */ 3602 x -= rcp->rc_xoffset; 3603 y -= rcp->rc_yoffset; 3604 3605 /* 3606 * no need to check for fall off, because we should 3607 * never move off the screen entirely! 3608 */ 3609 coff = 0; 3610 if (x < 0) { 3611 xoff = -x; 3612 x = 0; 3613 } 3614 if (y < 0) { 3615 yoff = -y; 3616 y = 0; 3617 coff = (yoff * 2) * 8; 3618 } 3619 3620 /* pan the display */ 3621 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3622 rcp->rc_xoffset); 3623 3624 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3625 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3626 /* NB: this unlocks the cursor */ 3627 PUT32(sc, hvpos, (x << 16) | y); 3628 } 3629 } 3630 3631 static void 3632 radeonfb_cursor_visible(struct radeonfb_display *dp) 3633 { 3634 int i; 3635 uint32_t gencntl, bit; 3636 3637 for (i = 0; i < dp->rd_ncrtcs; i++) { 3638 if (dp->rd_crtcs[i].rc_number) { 3639 gencntl = RADEON_CRTC2_GEN_CNTL; 3640 bit = RADEON_CRTC2_CUR_EN; 3641 } else { 3642 gencntl = RADEON_CRTC_GEN_CNTL; 3643 bit = RADEON_CRTC_CUR_EN; 3644 } 3645 3646 if (dp->rd_cursor.rc_visible) 3647 SET32(dp->rd_softc, gencntl, bit); 3648 else 3649 CLR32(dp->rd_softc, gencntl, bit); 3650 } 3651 } 3652 3653 static void 3654 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3655 { 3656 int i; 3657 uint32_t c0reg, c1reg; 3658 struct radeonfb_softc *sc = dp->rd_softc; 3659 3660 for (i = 0; i < dp->rd_ncrtcs; i++) { 3661 if (dp->rd_crtcs[i].rc_number) { 3662 c0reg = RADEON_CUR2_CLR0; 3663 c1reg = RADEON_CUR2_CLR1; 3664 } else { 3665 c0reg = RADEON_CUR_CLR0; 3666 c1reg = RADEON_CUR_CLR1; 3667 } 3668 3669 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3670 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3671 } 3672 } 3673 3674 static void 3675 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3676 { 3677 struct radeonfb_softc *sc; 3678 int i; 3679 3680 sc = dp->rd_softc; 3681 for (i = 0; i < dp->rd_ncrtcs; i++) { 3682 if (dp->rd_crtcs[i].rc_number) { 3683 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3684 } else { 3685 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3686 } 3687 } 3688 3689 if (which & WSDISPLAY_CURSOR_DOCMAP) 3690 radeonfb_cursor_cmap(dp); 3691 3692 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3693 radeonfb_cursor_shape(dp); 3694 3695 if (which & WSDISPLAY_CURSOR_DOCUR) 3696 radeonfb_cursor_visible(dp); 3697 3698 /* this one is unconditional, because it updates other stuff */ 3699 radeonfb_cursor_position(dp); 3700 } 3701 3702 static struct videomode * 3703 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3704 { 3705 int r1, r2; 3706 3707 /* otherwise pick the higher refresh rate */ 3708 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3709 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3710 3711 return (r1 < r2 ? m2 : m1); 3712 } 3713 3714 static const struct videomode * 3715 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3716 int x, int y) 3717 { 3718 struct edid_info *ep = &rp->rp_edid; 3719 struct videomode *vmp = NULL; 3720 int i; 3721 3722 if (!rp->rp_edid_valid) { 3723 /* fallback to safe mode */ 3724 return radeonfb_modelookup(sc->sc_defaultmode); 3725 } 3726 3727 /* always choose the preferred mode first! */ 3728 if (ep->edid_preferred_mode) { 3729 3730 /* XXX: add auto-stretching support for native mode */ 3731 3732 /* this may want panning to occur, btw */ 3733 if ((ep->edid_preferred_mode->hdisplay <= x) && 3734 (ep->edid_preferred_mode->vdisplay <= y)) 3735 return ep->edid_preferred_mode; 3736 } 3737 3738 for (i = 0; i < ep->edid_nmodes; i++) { 3739 /* 3740 * We elect to pick a resolution that is too large for 3741 * the monitor than one that is too small. This means 3742 * that we will prefer to pan rather than to try to 3743 * center a smaller display on a larger screen. In 3744 * practice, this shouldn't matter because if a 3745 * monitor can support a larger resolution, it can 3746 * probably also support the smaller. A specific 3747 * exception is fixed format panels, but hopefully 3748 * they are properly dealt with by the "autostretch" 3749 * logic above. 3750 */ 3751 if ((ep->edid_modes[i].hdisplay > x) || 3752 (ep->edid_modes[i].vdisplay > y)) { 3753 continue; 3754 } 3755 3756 /* 3757 * at this point, the display mode is no larger than 3758 * what we've requested. 3759 */ 3760 if (vmp == NULL) 3761 vmp = &ep->edid_modes[i]; 3762 3763 /* eliminate smaller modes */ 3764 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3765 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3766 continue; 3767 3768 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3769 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3770 vmp = &ep->edid_modes[i]; 3771 continue; 3772 } 3773 3774 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3775 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3776 3777 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3778 } 3779 3780 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3781 } 3782 3783 static int 3784 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3785 { 3786 int i; 3787 3788 for (i = 0; i < nlist; i++) { 3789 if ((x == list[i].hdisplay) && 3790 (y == list[i].vdisplay)) { 3791 return 1; 3792 } 3793 } 3794 return 0; 3795 } 3796 3797 static void 3798 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3799 int pan) 3800 { 3801 struct radeonfb_port *rp; 3802 struct edid_info *ep; 3803 int i, j; 3804 3805 *x = 0; 3806 *y = 0; 3807 3808 if (pan) { 3809 for (i = 0; i < dp->rd_ncrtcs; i++) { 3810 rp = dp->rd_crtcs[i].rc_port; 3811 ep = &rp->rp_edid; 3812 if (!rp->rp_edid_valid) { 3813 /* monitor not present */ 3814 continue; 3815 } 3816 3817 /* 3818 * For now we are ignoring "conflict" that 3819 * could occur when mixing some modes like 3820 * 1280x1024 and 1400x800. It isn't clear 3821 * which is better, so the first one wins. 3822 */ 3823 for (j = 0; j < ep->edid_nmodes; j++) { 3824 /* 3825 * ignore resolutions that are too big for 3826 * the radeon 3827 */ 3828 if (ep->edid_modes[j].hdisplay > 3829 dp->rd_softc->sc_maxx) 3830 continue; 3831 if (ep->edid_modes[j].vdisplay > 3832 dp->rd_softc->sc_maxy) 3833 continue; 3834 3835 /* 3836 * pick largest resolution, the 3837 * smaller monitor will pan 3838 */ 3839 if ((ep->edid_modes[j].hdisplay >= *x) && 3840 (ep->edid_modes[j].vdisplay >= *y)) { 3841 *x = ep->edid_modes[j].hdisplay; 3842 *y = ep->edid_modes[j].vdisplay; 3843 } 3844 } 3845 } 3846 3847 } else { 3848 struct videomode modes[64]; 3849 int nmodes = 0; 3850 int valid = 0; 3851 3852 for (i = 0; i < dp->rd_ncrtcs; i++) { 3853 /* 3854 * pick the largest resolution in common. 3855 */ 3856 rp = dp->rd_crtcs[i].rc_port; 3857 ep = &rp->rp_edid; 3858 3859 if (!rp->rp_edid_valid) 3860 continue; 3861 3862 if (!valid) { 3863 /* 3864 * Pick the preferred mode for this port 3865 * if available. 3866 */ 3867 if (ep->edid_preferred_mode) { 3868 struct videomode *vmp = 3869 ep->edid_preferred_mode; 3870 3871 if ((vmp->hdisplay <= 3872 dp->rd_softc->sc_maxx) && 3873 (vmp->vdisplay <= 3874 dp->rd_softc->sc_maxy)) 3875 modes[nmodes++] = *vmp; 3876 } else { 3877 3878 /* initialize starting list */ 3879 for (j = 0; j < ep->edid_nmodes; j++) { 3880 /* 3881 * ignore resolutions that are 3882 * too big for the radeon 3883 */ 3884 if (ep->edid_modes[j].hdisplay > 3885 dp->rd_softc->sc_maxx) 3886 continue; 3887 if (ep->edid_modes[j].vdisplay > 3888 dp->rd_softc->sc_maxy) 3889 continue; 3890 3891 modes[nmodes] = 3892 ep->edid_modes[j]; 3893 nmodes++; 3894 } 3895 } 3896 valid = 1; 3897 } else { 3898 /* merge into preexisting list */ 3899 for (j = 0; j < nmodes; j++) { 3900 if (!radeonfb_hasres(ep->edid_modes, 3901 ep->edid_nmodes, 3902 modes[j].hdisplay, 3903 modes[j].vdisplay)) { 3904 modes[j] = modes[nmodes]; 3905 j--; 3906 nmodes--; 3907 } 3908 } 3909 } 3910 } 3911 3912 /* now we have to pick from the merged list */ 3913 for (i = 0; i < nmodes; i++) { 3914 if ((modes[i].hdisplay >= *x) && 3915 (modes[i].vdisplay >= *y)) { 3916 *x = modes[i].hdisplay; 3917 *y = modes[i].vdisplay; 3918 } 3919 } 3920 } 3921 3922 if ((*x == 0) || (*y == 0)) { 3923 /* fallback to safe mode */ 3924 *x = 640; 3925 *y = 480; 3926 } 3927 } 3928 3929 /* 3930 * backlight levels are linear on: 3931 * - RV200, RV250, RV280, RV350 3932 * - but NOT on PowerBook4,3 6,3 6,5 3933 * according to Linux' radeonfb 3934 */ 3935 3936 /* Get the current backlight level for the display. */ 3937 3938 static int 3939 radeonfb_get_backlight(struct radeonfb_display *dp) 3940 { 3941 int s; 3942 uint32_t level; 3943 3944 s = spltty(); 3945 3946 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3947 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3948 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3949 3950 /* 3951 * On some chips, we should negate the backlight level. 3952 * XXX Find out on which chips. 3953 */ 3954 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3955 level = RADEONFB_BACKLIGHT_MAX - level; 3956 3957 splx(s); 3958 3959 return level; 3960 } 3961 3962 /* Set the backlight to the given level for the display. */ 3963 static void 3964 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3965 { 3966 if (dp->rd_bl_on == on) 3967 return; 3968 dp->rd_bl_on = on; 3969 radeonfb_set_backlight(dp, dp->rd_bl_level); 3970 } 3971 3972 static int 3973 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3974 { 3975 struct radeonfb_softc *sc; 3976 int rlevel, s; 3977 uint32_t lvds; 3978 3979 s = spltty(); 3980 3981 dp->rd_bl_level = level; 3982 if (dp->rd_bl_on == 0) 3983 level = 0; 3984 3985 if (level < 0) 3986 level = 0; 3987 else if (level >= RADEONFB_BACKLIGHT_MAX) 3988 level = RADEONFB_BACKLIGHT_MAX; 3989 3990 sc = dp->rd_softc; 3991 3992 /* On some chips, we should negate the backlight level. */ 3993 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3994 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3995 } else 3996 rlevel = level; 3997 3998 callout_stop(&dp->rd_bl_lvds_co); 3999 radeonfb_engine_idle(sc); 4000 4001 /* 4002 * Turn off the display if the backlight is set to 0, since the 4003 * display is useless without backlight anyway. 4004 */ 4005 if (level == 0) 4006 radeonfb_blank(dp, 1); 4007 else if (radeonfb_get_backlight(dp) == 0) 4008 radeonfb_blank(dp, 0); 4009 4010 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4011 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4012 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4013 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4014 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4015 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4016 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4017 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4018 lvds |= RADEON_LVDS_ON; 4019 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4020 } else { 4021 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4022 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4023 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4024 } 4025 4026 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4027 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4028 /* XXX What is the correct delay? */ 4029 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4030 4031 splx(s); 4032 4033 return 0; 4034 } 4035 4036 /* 4037 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4038 * Set the delayed bits in the register, and clear the stored delayed 4039 * value. 4040 */ 4041 4042 static void radeonfb_lvds_callout(void *arg) 4043 { 4044 struct radeonfb_display *dp = arg; 4045 int s; 4046 4047 s = splhigh(); 4048 4049 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4050 dp->rd_bl_lvds_val); 4051 dp->rd_bl_lvds_val = 0; 4052 4053 splx(s); 4054 } 4055 4056 static void 4057 radeonfb_brightness_up(device_t dev) 4058 { 4059 struct radeonfb_softc *sc = device_private(dev); 4060 struct radeonfb_display *dp = &sc->sc_displays[0]; 4061 int level; 4062 4063 /* we assume the main display is the first one - need a better way */ 4064 if (sc->sc_ndisplays < 1) return; 4065 /* make sure pushing the hotkeys always has an effect */ 4066 dp->rd_bl_on = 1; 4067 level = dp->rd_bl_level; 4068 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4069 radeonfb_set_backlight(dp, level); 4070 } 4071 4072 static void 4073 radeonfb_brightness_down(device_t dev) 4074 { 4075 struct radeonfb_softc *sc = device_private(dev); 4076 struct radeonfb_display *dp = &sc->sc_displays[0]; 4077 int level; 4078 4079 /* we assume the main display is the first one - need a better way */ 4080 if (sc->sc_ndisplays < 1) return; 4081 /* make sure pushing the hotkeys always has an effect */ 4082 dp->rd_bl_on = 1; 4083 level = dp->rd_bl_level; 4084 level = max(0, level - 5); 4085 radeonfb_set_backlight(dp, level); 4086 } 4087
Indexes created Sat Sep 27 14:09:57 GMT 2025