radeonfb.c revision 1.7
1 /* $NetBSD: radeonfb.c,v 1.7 2006/11/28 13:38:39 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.7 2006/11/28 13:38:39 christos Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static struct videomode *radeonfb_best_refresh(struct videomode *, 167 struct videomode *); 168 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 169 uint16_t *, int); 170 static const struct videomode *radeonfb_port_mode(struct radeonfb_port *, 171 int, int); 172 173 174 #define RADEON_DEBUG 175 #ifdef RADEON_DEBUG 176 int radeon_debug = 1; 177 #define DPRINTF(x) \ 178 if (radeon_debug) printf x 179 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 180 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 181 #else 182 #define DPRINTF(x) 183 #define PRINTREG(r) 184 #define PRINTPLL(r) 185 #endif 186 187 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 188 189 #ifndef RADEON_DEFAULT_MODE 190 /* any reasonably modern display should handle this */ 191 #define RADEON_DEFAULT_MODE "1024x768x60" 192 //#define RADEON_DEFAULT_MODE "1280x1024x60" 193 #endif 194 195 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 196 197 static struct { 198 int size; /* minimum memory size (MB) */ 199 int maxx; /* maximum x dimension */ 200 int maxy; /* maximum y dimension */ 201 int maxbpp; /* maximum bpp */ 202 int maxdisp; /* maximum logical display count */ 203 } radeonfb_limits[] = { 204 { 32, 2048, 1536, 32, 2 }, 205 { 16, 1600, 1200, 32, 2 }, 206 { 8, 1600, 1200, 32, 1 }, 207 { 0, 0, 0, 0, 0 }, 208 }; 209 210 static struct wsscreen_descr radeonfb_stdscreen = { 211 "fb", /* name */ 212 0, 0, /* ncols, nrows */ 213 NULL, /* textops */ 214 8, 16, /* fontwidth, fontheight */ 215 WSSCREEN_WSCOLORS, /* capabilities */ 216 0, /* modecookie */ 217 }; 218 219 struct wsdisplay_accessops radeonfb_accessops = { 220 radeonfb_ioctl, 221 radeonfb_mmap, 222 NULL, /* vcons_alloc_screen */ 223 NULL, /* vcons_free_screen */ 224 NULL, /* vcons_show_screen */ 225 NULL, /* load_font */ 226 NULL, /* pollc */ 227 NULL, /* scroll */ 228 }; 229 230 static struct { 231 uint16_t devid; 232 uint16_t family; 233 uint16_t flags; 234 } radeonfb_devices[] = 235 { 236 /* R100 family */ 237 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 238 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 239 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 240 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 241 242 /* RV100 family */ 243 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 244 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 245 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 246 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 247 248 /* RS100 family */ 249 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 251 252 /* RS200/RS250 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 254 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 257 258 /* R200 family */ 259 /* add more R200 products? , 5148 */ 260 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 265 266 /* RV200 family */ 267 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 269 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 271 272 /* RV250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 278 279 /* RS300 family */ 280 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 284 285 /* RV280 family */ 286 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 293 294 /* R300 family */ 295 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 303 304 /* RV350/RV360 family */ 305 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 317 318 /* R350/R360 family */ 319 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 327 328 /* RV380/RV370 family */ 329 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 338 339 /* R420/R423 family */ 340 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 356 357 { 0, 0, 0 } 358 }; 359 360 static struct { 361 int divider; 362 int mask; 363 } radeonfb_dividers[] = { 364 { 1, 0 }, 365 { 2, 1 }, 366 { 3, 4 }, 367 { 4, 2 }, 368 { 6, 6 }, 369 { 8, 3 }, 370 { 12, 7 }, 371 { 0, 0 } 372 }; 373 374 /* 375 * This table taken from X11. 376 */ 377 static const struct { 378 int family; 379 struct radeon_tmds_pll plls[4]; 380 } radeonfb_tmds_pll[] = { 381 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 382 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 383 { RADEON_RS100, {{0, 0}}}, 384 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 385 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 388 { RADEON_RS300, {{0, 0}}}, 389 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 390 { RADEON_R300, {{-1, 0xb01cb}}}, 391 { RADEON_R350, {{-1, 0xb01cb}}}, 392 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 393 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 394 { RADEON_R420, {{-1, 0xb01cb}}}, 395 }; 396 397 398 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 399 radeonfb_match, radeonfb_attach, NULL, NULL); 400 401 static int 402 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 403 { 404 struct pci_attach_args *pa = aux; 405 int i; 406 407 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 408 return 0; 409 410 for (i = 0; radeonfb_devices[i].devid; i++) { 411 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 412 return 100; /* high to defeat VGA/VESA */ 413 } 414 415 return 0; 416 } 417 418 static void 419 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 420 { 421 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 422 struct pci_attach_args *pa = aux; 423 bus_size_t bsz; 424 pcireg_t screg; 425 int i, j; 426 uint32_t v; 427 428 sc->sc_id = pa->pa_id; 429 for (i = 0; radeonfb_devices[i].devid; i++) { 430 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 431 break; 432 } 433 434 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 435 sizeof(sc->sc_devinfo)); 436 437 aprint_naive("\n"); 438 aprint_normal(": %s\n", sc->sc_devinfo); 439 440 KASSERT(radeonfb_devices[i].devid != 0); 441 sc->sc_pt = pa->pa_tag; 442 sc->sc_pc = pa->pa_pc; 443 sc->sc_family = radeonfb_devices[i].family; 444 sc->sc_flags = radeonfb_devices[i].flags; 445 446 /* enable memory and IO access */ 447 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 448 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 449 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 450 451 /* 452 * Some flags are general to entire chip families, and rather 453 * than clutter up the table with them, we go ahead and set 454 * them here. 455 */ 456 switch (sc->sc_family) { 457 case RADEON_RS100: 458 case RADEON_RS200: 459 sc->sc_flags |= RFB_IGP | RFB_RV100; 460 break; 461 462 case RADEON_RV100: 463 case RADEON_RV200: 464 case RADEON_RV250: 465 case RADEON_RV280: 466 sc->sc_flags |= RFB_RV100; 467 break; 468 469 case RADEON_RS300: 470 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 471 break; 472 473 case RADEON_R300: 474 case RADEON_RV350: 475 case RADEON_R350: 476 case RADEON_RV380: 477 case RADEON_R420: 478 /* newer chips */ 479 sc->sc_flags |= RFB_R300; 480 break; 481 482 case RADEON_R100: 483 sc->sc_flags |= RFB_NCRTC2; 484 break; 485 } 486 487 /* 488 * XXX: to support true multihead, this must change. 489 */ 490 sc->sc_ndisplays = 1; 491 492 /* XXX: */ 493 if (!HAS_CRTC2(sc)) { 494 sc->sc_ndisplays = 1; 495 } 496 497 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 498 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 499 &sc->sc_regsz) != 0) { 500 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 501 goto error; 502 } 503 504 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 505 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 506 &sc->sc_iosz) != 0) { 507 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 508 } 509 510 /* scratch register test... */ 511 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 512 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 513 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 514 goto error; 515 } 516 517 PRINTREG(RADEON_BIOS_4_SCRATCH); 518 PRINTREG(RADEON_FP_GEN_CNTL); 519 PRINTREG(RADEON_FP2_GEN_CNTL); 520 PRINTREG(RADEON_TMDS_CNTL); 521 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 522 PRINTREG(RADEON_TMDS_PLL_CNTL); 523 PRINTREG(RADEON_LVDS_GEN_CNTL); 524 PRINTREG(RADEON_FP_HORZ_STRETCH); 525 PRINTREG(RADEON_FP_VERT_STRETCH); 526 527 /* XXX: RV100 specific */ 528 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 529 530 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 531 RADEON_TMDS_TRANSMITTER_PLLEN, 532 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 533 534 radeonfb_i2c_init(sc); 535 536 radeonfb_loadbios(sc, pa); 537 538 #ifdef RADEON_BIOS_INIT 539 if (radeonfb_bios_init(sc)) { 540 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 541 goto error; 542 } 543 #endif 544 545 if (radeonfb_getclocks(sc)) { 546 aprint_error("%s: Unable to get reference clocks from BIOS\n", 547 XNAME(sc)); 548 goto error; 549 } 550 551 if (radeonfb_gettmds(sc)) { 552 aprint_error("%s: Unable to identify TMDS PLL settings\n", 553 XNAME(sc)); 554 goto error; 555 } 556 557 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 558 "minpll = %d, maxpll = %d\n", XNAME(sc), 559 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 560 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 561 562 radeonfb_getconnectors(sc); 563 564 radeonfb_set_fbloc(sc); 565 566 for (i = 0; radeonfb_limits[i].size; i++) { 567 if (sc->sc_memsz >= radeonfb_limits[i].size) { 568 sc->sc_maxx = radeonfb_limits[i].maxx; 569 sc->sc_maxy = radeonfb_limits[i].maxy; 570 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 571 /* framebuffer offset, start at a 4K page */ 572 sc->sc_fboffset = sc->sc_memsz / 573 radeonfb_limits[i].maxdisp; 574 /* 575 * we use the fbsize to figure out where we can store 576 * things like cursor data. 577 */ 578 sc->sc_fbsize = 579 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 580 RADEON_STRIDEALIGN) * sc->sc_maxy, 581 4096); 582 break; 583 } 584 } 585 586 587 radeonfb_init_misc(sc); 588 radeonfb_init_palette(sc, 0); 589 if (HAS_CRTC2(sc)) 590 radeonfb_init_palette(sc, 1); 591 592 /* program the DAC wirings */ 593 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 594 switch (sc->sc_ports[i].rp_dac_type) { 595 case RADEON_DAC_PRIMARY: 596 PATCH32(sc, RADEON_DAC_CNTL2, 597 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 598 ~RADEON_DAC2_DAC_CLK_SEL); 599 break; 600 case RADEON_DAC_TVDAC: 601 /* we always use the TVDAC to drive a secondary analog 602 * CRT for now. if we ever support TV-out this will 603 * have to change. 604 */ 605 SET32(sc, RADEON_DAC_CNTL2, 606 RADEON_DAC2_DAC2_CLK_SEL); 607 PATCH32(sc, RADEON_DISP_HW_DEBUG, 608 i ? 0 : RADEON_CRT2_DISP1_SEL, 609 ~RADEON_CRT2_DISP1_SEL); 610 break; 611 } 612 } 613 PRINTREG(RADEON_DAC_CNTL2); 614 PRINTREG(RADEON_DISP_HW_DEBUG); 615 616 /* other DAC programming */ 617 v = GET32(sc, RADEON_DAC_CNTL); 618 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 619 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 620 PUT32(sc, RADEON_DAC_CNTL, v); 621 PRINTREG(RADEON_DAC_CNTL); 622 623 /* XXX: this may need more investigation */ 624 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 625 PRINTREG(RADEON_TV_DAC_CNTL); 626 627 /* enable TMDS */ 628 SET32(sc, RADEON_FP_GEN_CNTL, 629 RADEON_FP_TMDS_EN | 630 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 631 RADEON_FP_CRTC_DONT_SHADOW_HEND); 632 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 633 if (HAS_CRTC2(sc)) 634 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 635 636 /* 637 * we use bus_space_map instead of pci_mapreg, because we don't 638 * need the full aperature space. no point in wasting virtual 639 * address space we don't intend to use, right? 640 */ 641 if ((sc->sc_memsz < (4096 * 1024)) || 642 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 643 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 644 (bsz < sc->sc_memsz)) { 645 sc->sc_memsz = 0; 646 aprint_error("%s: Bad frame buffer configuration\n", 647 XNAME(sc)); 648 goto error; 649 } 650 651 /* 64 MB should be enough -- more just wastes map entries */ 652 if (sc->sc_memsz > (64 << 20)) 653 sc->sc_memsz = (64 << 20); 654 655 sc->sc_memt = pa->pa_memt; 656 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 657 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 658 sc->sc_memsz = 0; 659 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 660 goto error; 661 } 662 663 aprint_normal("%s: %d MB aperture at 0x%08x, " 664 "%d KB registers at 0x%08x\n", XNAME(sc), 665 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 666 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 667 668 #if 0 669 /* setup default video mode from devprop (allows PROM override) */ 670 sc->sc_defaultmode = radeonfb_default_mode; 671 ps = prop_dictionary_get(device_properties(&sc->sc_dev), 672 "videomode"); 673 if (ps != NULL) { 674 sc->sc_modebuf = prop_string_cstring(ps); 675 if (sc->sc_modebuf) 676 sc->sc_defaultmode = sc->sc_modebuf; 677 } 678 #endif 679 680 /* initialize some basic display parameters */ 681 for (i = 0; i < sc->sc_ndisplays; i++) { 682 struct radeonfb_display *dp = &sc->sc_displays[i]; 683 struct rasops_info *ri; 684 long defattr; 685 struct wsemuldisplaydev_attach_args aa; 686 687 /* 688 * Figure out how many "displays" (desktops) we are going to 689 * support. If more than one, then each CRTC gets its own 690 * programming. 691 * 692 * XXX: this code needs to change to support mergedfb. 693 * XXX: would be nice to allow this to be overridden 694 */ 695 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 696 DPRINTF(("dual crtcs!\n")); 697 dp->rd_ncrtcs = 2; 698 dp->rd_crtcs[0].rc_number = 0; 699 dp->rd_crtcs[1].rc_number = 1; 700 } else { 701 dp->rd_ncrtcs = 1; 702 dp->rd_crtcs[0].rc_number = i; 703 } 704 705 /* set up port pointer */ 706 for (j = 0; j < dp->rd_ncrtcs; j++) { 707 dp->rd_crtcs[j].rc_port = 708 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 709 } 710 711 dp->rd_softc = sc; 712 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 713 dp->rd_bg = WS_DEFAULT_BG; 714 #if 0 715 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 716 #else 717 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 718 #endif 719 /* for text mode, we pick a resolution that won't 720 * require panning */ 721 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 722 723 aprint_normal("%s: display %d: " 724 "virtual resolution %dx%d at %d bpp\n", 725 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 726 727 /* now select the *video mode* that we will use */ 728 for (j = 0; j < dp->rd_ncrtcs; j++) { 729 const struct videomode *vmp; 730 vmp = radeonfb_port_mode(dp->rd_crtcs[j].rc_port, 731 dp->rd_virtx, dp->rd_virty); 732 dp->rd_crtcs[j].rc_videomode = *vmp; 733 printf("%s: port %d: physical %dx%d %dHz\n", 734 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 735 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 736 vmp->htotal), vmp->vtotal)); 737 } 738 739 /* N.B.: radeon wants 64-byte aligned stride */ 740 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 741 //dp->rd_stride = sc->sc_maxx * sc->sc_maxbpp / 8; 742 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 743 744 dp->rd_offset = sc->sc_fboffset * i; 745 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 746 sc->sc_memh) + dp->rd_offset; 747 dp->rd_curoff = sc->sc_fbsize; 748 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 749 750 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 751 752 switch (dp->rd_bpp) { 753 case 8: 754 dp->rd_format = 2; 755 break; 756 case 32: 757 dp->rd_format = 6; 758 break; 759 default: 760 aprint_error("%s: bad depth %d\n", XNAME(sc), 761 dp->rd_bpp); 762 goto error; 763 } 764 765 printf("init engine\n"); 766 /* XXX: this seems suspicious - per display engine 767 initialization? */ 768 radeonfb_engine_init(dp); 769 770 /* copy the template into place */ 771 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 772 dp->rd_wsscreens = dp->rd_wsscreens_storage; 773 774 /* and make up the list */ 775 dp->rd_wsscreenlist.nscreens = 1; 776 dp->rd_wsscreenlist.screens = 777 (const struct wsscreen_descr **)&dp->rd_wsscreens; 778 779 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 780 &radeonfb_accessops); 781 782 dp->rd_vd.init_screen = radeonfb_init_screen; 783 784 dp->rd_console = 1; 785 786 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 787 788 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 789 dp->rd_console, &defattr); 790 791 ri = &dp->rd_vscreen.scr_ri; 792 dp->rd_wsscreens->textops = &ri->ri_ops; 793 dp->rd_wsscreens->capabilities = ri->ri_caps; 794 dp->rd_wsscreens->nrows = ri->ri_rows; 795 dp->rd_wsscreens->ncols = ri->ri_cols; 796 797 #ifdef SPLASHSCREEN 798 dp->rd_splash.si_depth = ri->ri_depth; 799 dp->rd_splash.si_bits = ri->ri_bits; 800 dp->rd_splash.si_hwbits = ri->ri_hwbits; 801 dp->rd_splash.si_width = ri->ri_width; 802 dp->rd_splash.si_height = ri->ri_height; 803 dp->rd_splash.si_stride = ri->ri_stride; 804 dp->rd_splash.si_fillrect = NULL; 805 #endif 806 if (dp->rd_console) { 807 808 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 809 defattr); 810 #ifdef SPLASHSCREEN 811 splash_render(&dp->rd_splash, 812 SPLASH_F_CENTER|SPLASH_F_FILL); 813 #endif 814 815 #ifdef SPLASHSCREEN_PROGRESS 816 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 817 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 818 dp->rd_progress.sp_left = (dp->rd_virtx - 819 dp->rd_progress.sp_width) / 2; 820 dp->rd_progress.sp_height = 20; 821 dp->rd_progress.sp_state = -1; 822 dp->rd_progress.sp_si = &dp->rd_splash; 823 splash_progress_init(&dp->rd_progress); 824 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 825 #endif 826 827 } else { 828 829 /* 830 * since we're not the console we can postpone 831 * the rest until someone actually allocates a 832 * screen for us. but we do clear the screen 833 * at least. 834 */ 835 memset(ri->ri_bits, 0, 1024); 836 837 radeonfb_modeswitch(dp); 838 #ifdef SPLASHSCREEN 839 splash_render(&dp->rd_splash, 840 SPLASH_F_CENTER|SPLASH_F_FILL); 841 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 842 #endif 843 } 844 845 aa.console = dp->rd_console; 846 aa.scrdata = &dp->rd_wsscreenlist; 847 aa.accessops = &radeonfb_accessops; 848 aa.accesscookie = &dp->rd_vd; 849 850 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 851 radeonfb_blank(dp, 0); 852 } 853 854 return; 855 856 error: 857 if (sc->sc_biossz) 858 free(sc->sc_bios, M_DEVBUF); 859 860 if (sc->sc_regsz) 861 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 862 863 if (sc->sc_memsz) 864 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 865 } 866 867 int 868 radeonfb_ioctl(void *v, void *vs, 869 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 870 { 871 struct vcons_data *vd; 872 struct radeonfb_display *dp; 873 struct radeonfb_softc *sc; 874 875 vd = (struct vcons_data *)v; 876 dp = (struct radeonfb_display *)vd->cookie; 877 sc = dp->rd_softc; 878 879 switch (cmd) { 880 case WSDISPLAYIO_GTYPE: 881 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 882 return 0; 883 884 case WSDISPLAYIO_GINFO: 885 if (vd->active != NULL) { 886 struct wsdisplay_fbinfo *fb; 887 fb = (struct wsdisplay_fbinfo *)d; 888 fb->width = dp->rd_virtx; 889 fb->height = dp->rd_virty; 890 fb->depth = dp->rd_bpp; 891 fb->cmsize = 256; 892 return 0; 893 } else 894 return ENODEV; 895 case WSDISPLAYIO_GVIDEO: 896 if (radeonfb_isblank(dp)) 897 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 898 else 899 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 900 return 0; 901 902 case WSDISPLAYIO_SVIDEO: 903 radeonfb_blank(dp, 904 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 905 return 0; 906 907 case WSDISPLAYIO_GETCMAP: 908 #if 0 909 if (dp->rd_bpp == 8) 910 return radeonfb_getcmap(sc, 911 (struct wsdisplay_cmap *)d); 912 #endif 913 return EINVAL; 914 915 case WSDISPLAYIO_PUTCMAP: 916 #if 0 917 if (dp->rd_bpp == 8) 918 return radeonfb_putcmap(sc, 919 (struct wsdisplay_cmap *)d); 920 #endif 921 return EINVAL; 922 923 case WSDISPLAYIO_LINEBYTES: 924 *(unsigned *)d = dp->rd_stride; 925 return 0; 926 927 case WSDISPLAYIO_SMODE: 928 if (*(int *)d != dp->rd_wsmode) { 929 dp->rd_wsmode = *(int *)d; 930 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 931 (dp->rd_vd.active)) { 932 vcons_redraw_screen(dp->rd_vd.active); 933 } 934 } 935 return 0; 936 937 case WSDISPLAYIO_GCURMAX: 938 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 939 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 940 return 0; 941 942 case WSDISPLAYIO_SCURSOR: 943 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 944 945 case WSDISPLAYIO_GCURSOR: 946 return EPASSTHROUGH; 947 948 case WSDISPLAYIO_GCURPOS: 949 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 950 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 951 return 0; 952 953 case WSDISPLAYIO_SCURPOS: 954 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 955 956 case WSDISPLAYIO_SSPLASH: 957 #if defined(SPLASHSCREEN) 958 if (*(int *)d == 1) { 959 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 960 splash_render(&dp->rd_splash, 961 SPLASH_F_CENTER|SPLASH_F_FILL); 962 } else 963 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 964 return 0; 965 #else 966 return ENODEV; 967 #endif 968 case WSDISPLAYIO_SPROGRESS: 969 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 970 dp->rd_progress.sp_force = 1; 971 splash_progress_update(&dp->rd_progress); 972 dp->rd_progress.sp_force = 0; 973 return 0; 974 #else 975 return ENODEV; 976 #endif 977 978 default: 979 return EPASSTHROUGH; 980 } 981 } 982 983 paddr_t 984 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 985 { 986 struct vcons_data *vd; 987 struct radeonfb_display *dp; 988 struct radeonfb_softc *sc; 989 #ifdef RADEONFB_MMAP_BARS 990 struct lwp *me; 991 #endif 992 paddr_t pa; 993 994 vd = (struct vcons_data *)v; 995 dp = (struct radeonfb_display *)vd->cookie; 996 sc = dp->rd_softc; 997 998 /* XXX: note that we don't allow mapping of registers right now */ 999 /* XXX: this means that the XFree86 radeon driver won't work */ 1000 1001 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1002 pa = bus_space_mmap(sc->sc_memt, 1003 sc->sc_memaddr + dp->rd_offset + offset, 0, 1004 prot, BUS_SPACE_MAP_LINEAR); 1005 return pa; 1006 } 1007 1008 #ifdef RADEONFB_MMAP_BARS 1009 /* 1010 * restrict all other mappings to processes with superuser privileges 1011 * or the kernel itself 1012 */ 1013 me = curlwp; 1014 if (me != NULL) { 1015 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1016 NULL) != 0) { 1017 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1018 return -1; 1019 } 1020 } 1021 1022 if ((offset >= sc->sc_regaddr) && 1023 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1024 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1025 BUS_SPACE_MAP_LINEAR); 1026 } 1027 1028 if ((offset >= sc->sc_memaddr) && 1029 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1030 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1031 BUS_SPACE_MAP_LINEAR); 1032 } 1033 1034 #ifdef macppc 1035 /* allow mapping of IO space */ 1036 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1037 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1038 BUS_SPACE_MAP_LINEAR); 1039 return pa; 1040 } 1041 #endif /* macppc */ 1042 1043 #endif /* RADEONFB_MMAP_BARS */ 1044 1045 return -1; 1046 } 1047 1048 static void 1049 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1050 { 1051 bus_space_tag_t romt; 1052 bus_space_handle_t romh, biosh; 1053 bus_size_t romsz; 1054 bus_addr_t ptr; 1055 1056 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1057 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1058 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1059 return; 1060 } 1061 1062 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1063 &sc->sc_biossz); 1064 if (sc->sc_biossz == 0) { 1065 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1066 return; 1067 } 1068 1069 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1070 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1071 1072 /* unmap the PCI expansion rom */ 1073 bus_space_unmap(romt, romh, romsz); 1074 1075 /* turn off rom decoder now */ 1076 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1077 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1078 ~PCI_MAPREG_ROM_ENABLE); 1079 1080 ptr = GETBIOS16(sc, 0x48); 1081 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1082 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1083 sc->sc_flags |= RFB_ATOM; 1084 } 1085 1086 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1087 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1088 } 1089 1090 1091 uint32_t 1092 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1093 { 1094 1095 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1096 } 1097 1098 void 1099 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1100 { 1101 1102 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1103 } 1104 1105 void 1106 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1107 uint32_t andmask, uint32_t ormask) 1108 { 1109 int s; 1110 uint32_t val; 1111 1112 s = splhigh(); 1113 val = radeonfb_get32(sc, reg); 1114 val = (val & andmask) | ormask; 1115 radeonfb_put32(sc, reg, val); 1116 splx(s); 1117 } 1118 1119 uint32_t 1120 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1121 { 1122 int s; 1123 uint32_t val; 1124 1125 s = splhigh(); 1126 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1127 val = radeonfb_get32(sc, RADEON_MM_DATA); 1128 splx(s); 1129 1130 return (val); 1131 } 1132 1133 void 1134 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1135 { 1136 int s; 1137 1138 s = splhigh(); 1139 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1140 radeonfb_put32(sc, RADEON_MM_DATA, val); 1141 splx(s); 1142 } 1143 1144 void 1145 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1146 uint32_t andmask, uint32_t ormask) 1147 { 1148 int s; 1149 uint32_t val; 1150 1151 s = splhigh(); 1152 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1153 val = radeonfb_get32(sc, RADEON_MM_DATA); 1154 val = (val & andmask) | ormask; 1155 radeonfb_put32(sc, RADEON_MM_DATA, val); 1156 splx(s); 1157 } 1158 1159 uint32_t 1160 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1161 { 1162 int s; 1163 uint32_t val; 1164 1165 s = splhigh(); 1166 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1167 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1168 if (HAS_R300CG(sc)) 1169 radeonfb_r300cg_workaround(sc); 1170 splx(s); 1171 1172 return (val); 1173 } 1174 1175 void 1176 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1177 { 1178 int s; 1179 1180 s = splhigh(); 1181 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1182 RADEON_PLL_WR_EN); 1183 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1184 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1185 splx(s); 1186 } 1187 1188 void 1189 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1190 uint32_t andmask, uint32_t ormask) 1191 { 1192 int s; 1193 uint32_t val; 1194 1195 s = splhigh(); 1196 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1197 RADEON_PLL_WR_EN); 1198 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1199 val = (val & andmask) | ormask; 1200 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1201 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1202 splx(s); 1203 } 1204 1205 int 1206 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1207 { 1208 uint32_t saved; 1209 1210 saved = GET32(sc, reg); 1211 PUT32(sc, reg, v); 1212 if (GET32(sc, reg) != v) { 1213 return -1; 1214 } 1215 PUT32(sc, reg, saved); 1216 return 0; 1217 } 1218 1219 uintmax_t 1220 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1221 uintmax_t defval) 1222 { 1223 prop_number_t pn; 1224 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1225 if (pn == NULL) { 1226 return defval; 1227 } 1228 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1229 return (prop_number_integer_value(pn)); 1230 } 1231 1232 int 1233 radeonfb_getclocks(struct radeonfb_softc *sc) 1234 { 1235 bus_addr_t ptr; 1236 int refclk = 0; 1237 int refdiv = 0; 1238 int minpll = 0; 1239 int maxpll = 0; 1240 1241 /* load initial property values if port/board provides them */ 1242 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1243 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1244 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1245 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1246 1247 if (refclk && refdiv && minpll && maxpll) 1248 goto dontprobe; 1249 1250 if (!sc->sc_biossz) { 1251 /* no BIOS */ 1252 aprint_verbose("%s: No video BIOS, using default clocks\n", 1253 XNAME(sc)); 1254 if (IS_IGP(sc)) 1255 refclk = refclk ? refclk : 1432; 1256 else 1257 refclk = refclk ? refclk : 2700; 1258 refdiv = refdiv ? refdiv : 12; 1259 minpll = minpll ? minpll : 12500; 1260 maxpll = maxpll ? maxpll : 35000; 1261 } else if (IS_ATOM(sc)) { 1262 /* ATOM BIOS */ 1263 ptr = GETBIOS16(sc, 0x48); 1264 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1265 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1266 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1267 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1268 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1269 /* 1270 * ATOM BIOS doesn't supply a reference divider, so we 1271 * have to probe for it. 1272 */ 1273 if (refdiv < 2) 1274 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1275 RADEON_PPLL_REF_DIV_MASK; 1276 /* 1277 * if probe is zero, just assume one that should work 1278 * for most parts 1279 */ 1280 if (refdiv < 2) 1281 refdiv = 12; 1282 1283 } else { 1284 /* Legacy BIOS */ 1285 ptr = GETBIOS16(sc, 0x48); 1286 ptr = GETBIOS16(sc, ptr + 0x30); 1287 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1288 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1289 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1290 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1291 } 1292 1293 1294 dontprobe: 1295 sc->sc_refclk = refclk * 10; 1296 sc->sc_refdiv = refdiv; 1297 sc->sc_minpll = minpll * 10; 1298 sc->sc_maxpll = maxpll * 10; 1299 return 0; 1300 } 1301 1302 int 1303 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1304 uint32_t *postdivbit, uint32_t *feedbackdiv) 1305 { 1306 int i; 1307 uint32_t outfreq; 1308 int div; 1309 1310 DPRINTF(("dot clock: %u\n", dotclock)); 1311 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1312 outfreq = div * dotclock; 1313 if ((outfreq >= sc->sc_minpll) && 1314 (outfreq <= sc->sc_maxpll)) { 1315 DPRINTF(("outfreq: %u\n", outfreq)); 1316 *postdivbit = 1317 ((uint32_t)radeonfb_dividers[i].mask << 16); 1318 DPRINTF(("post divider: %d (mask %x)\n", div, 1319 *postdivbit)); 1320 break; 1321 } 1322 } 1323 1324 if (div == 0) 1325 return 1; 1326 1327 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1328 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1329 return 0; 1330 } 1331 1332 #if 0 1333 #ifdef RADEON_DEBUG 1334 static void 1335 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1336 { 1337 char asc[17]; 1338 unsigned ptr = (unsigned)buffer; 1339 char *start = (char *)(ptr & ~0xf); 1340 char *end = (char *)(ptr + size); 1341 1342 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1343 1344 if (pfx == NULL) { 1345 pfx = ""; 1346 } 1347 1348 while (start < end) { 1349 unsigned offset = (unsigned)start & 0xf; 1350 if (offset == 0) { 1351 printf("%s%x: ", pfx, (unsigned)start); 1352 } 1353 if (((unsigned)start < ptr) || 1354 ((unsigned)start >= (ptr + size))) { 1355 printf(" "); 1356 asc[offset] = ' '; 1357 } else { 1358 printf("%02x", *(unsigned char *)start); 1359 if ((*start >= ' ') && (*start <= '~')) { 1360 asc[offset] = *start; 1361 } else { 1362 asc[offset] = '.'; 1363 } 1364 } 1365 asc[offset + 1] = 0; 1366 if (offset % 2) { 1367 printf(" "); 1368 } 1369 if (offset == 15) { 1370 printf(" %s\n", asc); 1371 } 1372 start++; 1373 } 1374 } 1375 #endif 1376 #endif 1377 1378 int 1379 radeonfb_getconnectors(struct radeonfb_softc *sc) 1380 { 1381 int i; 1382 int found = 0; 1383 1384 for (i = 0; i < 2; i++) { 1385 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1386 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1387 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1388 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1389 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1390 } 1391 1392 /* 1393 * This logic is borrowed from Xorg's radeon driver. 1394 */ 1395 if (!sc->sc_biossz) 1396 goto nobios; 1397 1398 if (IS_ATOM(sc)) { 1399 /* not done yet */ 1400 } else { 1401 uint16_t ptr; 1402 int port = 0; 1403 1404 ptr = GETBIOS16(sc, 0x48); 1405 ptr = GETBIOS16(sc, ptr + 0x50); 1406 for (i = 1; i < 4; i++) { 1407 uint16_t entry; 1408 uint8_t conn, ddc, dac, tmds; 1409 1410 /* 1411 * Parse the connector table. From reading the code, 1412 * it appears to made up of 16-bit entries for each 1413 * connector. The 16-bits are defined as: 1414 * 1415 * bits 12-15 - connector type (0 == end of table) 1416 * bits 8-11 - DDC type 1417 * bits 5-7 - ??? 1418 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1419 * bits 1-3 - ??? 1420 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1421 */ 1422 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1423 break; 1424 entry = GETBIOS16(sc, ptr + i * 2); 1425 1426 conn = (entry >> 12) & 0xf; 1427 ddc = (entry >> 8) & 0xf; 1428 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1429 RADEON_DAC_PRIMARY; 1430 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1431 RADEON_TMDS_INT; 1432 1433 if (conn == RADEON_CONN_NONE) 1434 continue; /* no connector */ 1435 1436 if ((found > 0) && 1437 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1438 /* duplicate entry for same connector */ 1439 continue; 1440 } 1441 1442 /* internal DDC_DVI port gets priority */ 1443 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1444 port = 0; 1445 else 1446 port = 1; 1447 1448 sc->sc_ports[port].rp_ddc_type = 1449 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1450 sc->sc_ports[port].rp_dac_type = dac; 1451 sc->sc_ports[port].rp_conn_type = 1452 min(conn, RADEON_CONN_UNSUPPORTED) ; 1453 1454 sc->sc_ports[port].rp_tmds_type = tmds; 1455 1456 if ((conn != RADEON_CONN_DVI_I) && 1457 (conn != RADEON_CONN_DVI_D) && 1458 (tmds == RADEON_TMDS_INT)) 1459 sc->sc_ports[port].rp_tmds_type = 1460 RADEON_TMDS_UNKNOWN; 1461 1462 found += (port + 1); 1463 } 1464 } 1465 1466 nobios: 1467 if (!found) { 1468 DPRINTF(("No connector info in BIOS!\n")); 1469 /* default, port 0 = internal TMDS, port 1 = CRT */ 1470 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1471 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1472 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1473 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1474 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1475 1476 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1477 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1478 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1479 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1480 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1481 } 1482 1483 /* 1484 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1485 * these chips should use TVDAC for the VGA port. 1486 */ 1487 if (HAS_SDAC(sc)) { 1488 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1489 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1490 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1491 } else { 1492 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1493 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1494 } 1495 } else if (!HAS_CRTC2(sc)) { 1496 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1497 } 1498 1499 for (i = 0; i < 2; i++) { 1500 char edid[128]; 1501 uint8_t ddc; 1502 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1503 1504 DPRINTF(("Port #%d:\n", i)); 1505 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1506 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1507 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1508 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1509 1510 sc->sc_ports[i].rp_edid_valid = 0; 1511 ddc = sc->sc_ports[i].rp_ddc_type; 1512 if (ddc != RADEON_DDC_NONE) { 1513 if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1514 (edid_parse(edid, eip) == 0)) { 1515 sc->sc_ports[i].rp_edid_valid = 1; 1516 edid_print(eip); 1517 } 1518 } 1519 } 1520 1521 return found; 1522 } 1523 1524 int 1525 radeonfb_gettmds(struct radeonfb_softc *sc) 1526 { 1527 int i; 1528 1529 if (!sc->sc_biossz) { 1530 goto nobios; 1531 } 1532 1533 if (IS_ATOM(sc)) { 1534 /* XXX: not done yet */ 1535 } else { 1536 uint16_t ptr; 1537 int n; 1538 1539 ptr = GETBIOS16(sc, 0x48); 1540 ptr = GETBIOS16(sc, ptr + 0x34); 1541 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1542 if (GETBIOS8(sc, ptr) == 3) { 1543 /* revision three table */ 1544 n = GETBIOS8(sc, ptr + 5) + 1; 1545 n = min(n, 4); 1546 1547 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1548 for (i = 0; i < n; i++) { 1549 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1550 ptr + i * 10 + 8); 1551 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1552 ptr + i * 10 + 0x10); 1553 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1554 sc->sc_tmds_pll[i].rtp_freq, 1555 sc->sc_tmds_pll[i].rtp_pll)); 1556 } 1557 return 0; 1558 } 1559 } 1560 1561 nobios: 1562 DPRINTF(("no suitable DFP table present\n")); 1563 for (i = 0; 1564 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1565 i++) { 1566 int j; 1567 1568 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1569 continue; 1570 1571 for (j = 0; j < 4; j++) { 1572 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1573 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1574 sc->sc_tmds_pll[j].rtp_freq, 1575 sc->sc_tmds_pll[j].rtp_pll)); 1576 } 1577 return 0; 1578 } 1579 1580 return -1; 1581 } 1582 1583 const struct videomode * 1584 radeonfb_modelookup(const char *name) 1585 { 1586 int i; 1587 1588 for (i = 0; i < videomode_count; i++) 1589 if (!strcmp(name, videomode_list[i].name)) 1590 return &videomode_list[i]; 1591 1592 return NULL; 1593 } 1594 1595 void 1596 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1597 { 1598 if (crtc) { 1599 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1600 RADEON_P2PLL_ATOMIC_UPDATE_R); 1601 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1602 } else { 1603 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1604 RADEON_PPLL_ATOMIC_UPDATE_R); 1605 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1606 } 1607 } 1608 1609 void 1610 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1611 { 1612 int i; 1613 1614 for (i = 10000; i; i--) { 1615 if (crtc) { 1616 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1617 RADEON_P2PLL_ATOMIC_UPDATE_R) 1618 break; 1619 } else { 1620 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1621 RADEON_PPLL_ATOMIC_UPDATE_R) 1622 break; 1623 } 1624 } 1625 } 1626 1627 void 1628 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1629 { 1630 uint32_t pbit = 0; 1631 uint32_t feed = 0; 1632 uint32_t data; 1633 #if 1 1634 int i; 1635 #endif 1636 1637 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1638 1639 if (crtc == 0) { 1640 1641 /* XXXX: mobility workaround missing */ 1642 /* XXXX: R300 stuff missing */ 1643 1644 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1645 RADEON_VCLK_SRC_SEL_CPUCLK, 1646 ~RADEON_VCLK_SRC_SEL_MASK); 1647 1648 /* put vclk into reset, use atomic updates */ 1649 SETPLL(sc, RADEON_PPLL_CNTL, 1650 RADEON_PPLL_REFCLK_SEL | 1651 RADEON_PPLL_FBCLK_SEL | 1652 RADEON_PPLL_RESET | 1653 RADEON_PPLL_ATOMIC_UPDATE_EN | 1654 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1655 1656 /* select clock 3 */ 1657 #if 0 1658 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1659 ~RADEON_PLL_DIV_SEL); 1660 #else 1661 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1662 ~RADEON_PLL_DIV_SEL); 1663 #endif 1664 1665 /* XXX: R300 family -- program divider differently? */ 1666 1667 /* program reference divider */ 1668 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1669 ~RADEON_PPLL_REF_DIV_MASK); 1670 PRINTPLL(RADEON_PPLL_REF_DIV); 1671 1672 #if 0 1673 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1674 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1675 RADEON_PPLL_POST3_DIV_MASK); 1676 data |= pbit; 1677 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1678 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1679 #else 1680 for (i = 0; i < 4; i++) { 1681 } 1682 #endif 1683 1684 /* use the atomic update */ 1685 radeonfb_pllwriteupdate(sc, crtc); 1686 1687 /* and wait for it to complete */ 1688 radeonfb_pllwaitatomicread(sc, crtc); 1689 1690 /* program HTOTAL (why?) */ 1691 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1692 1693 /* drop reset */ 1694 CLRPLL(sc, RADEON_PPLL_CNTL, 1695 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1696 RADEON_PPLL_ATOMIC_UPDATE_EN | 1697 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1698 1699 PRINTPLL(RADEON_PPLL_CNTL); 1700 1701 /* give clock time to lock */ 1702 delay(50000); 1703 1704 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1705 RADEON_VCLK_SRC_SEL_PPLLCLK, 1706 ~RADEON_VCLK_SRC_SEL_MASK); 1707 1708 } else { 1709 1710 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1711 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1712 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1713 1714 /* put vclk into reset, use atomic updates */ 1715 SETPLL(sc, RADEON_P2PLL_CNTL, 1716 RADEON_P2PLL_RESET | 1717 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1718 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1719 1720 /* XXX: R300 family -- program divider differently? */ 1721 1722 /* program reference divider */ 1723 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1724 ~RADEON_P2PLL_REF_DIV_MASK); 1725 1726 /* program feedback and post dividers */ 1727 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1728 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1729 RADEON_P2PLL_POST0_DIV_MASK); 1730 data |= pbit; 1731 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1732 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1733 1734 /* use the atomic update */ 1735 radeonfb_pllwriteupdate(sc, crtc); 1736 1737 /* and wait for it to complete */ 1738 radeonfb_pllwaitatomicread(sc, crtc); 1739 1740 /* program HTOTAL (why?) */ 1741 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1742 1743 /* drop reset */ 1744 CLRPLL(sc, RADEON_P2PLL_CNTL, 1745 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1746 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1747 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1748 1749 /* allow time for clock to lock */ 1750 delay(50000); 1751 1752 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1753 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1754 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1755 } 1756 PRINTREG(RADEON_CRTC_MORE_CNTL); 1757 } 1758 1759 void 1760 radeonfb_modeswitch(struct radeonfb_display *dp) 1761 { 1762 struct radeonfb_softc *sc = dp->rd_softc; 1763 int i; 1764 1765 /* blank the display while we switch modes */ 1766 //radeonfb_blank(dp, 1); 1767 1768 #if 0 1769 SET32(sc, RADEON_CRTC_EXT_CNTL, 1770 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1771 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1772 #endif 1773 1774 /* these registers might get in the way... */ 1775 PUT32(sc, RADEON_OVR_CLR, 0); 1776 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1777 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1778 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1779 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1780 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1781 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1782 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1783 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1784 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1785 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1786 1787 for (i = 0; i < dp->rd_ncrtcs; i++) 1788 radeonfb_setcrtc(dp, i); 1789 1790 /* activate the display */ 1791 //radeonfb_blank(dp, 0); 1792 } 1793 1794 void 1795 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1796 { 1797 int crtc; 1798 struct videomode *mode; 1799 struct radeonfb_softc *sc; 1800 struct radeonfb_crtc *cp; 1801 uint32_t v; 1802 uint32_t gencntl; 1803 uint32_t htotaldisp; 1804 uint32_t hsyncstrt; 1805 uint32_t vtotaldisp; 1806 uint32_t vsyncstrt; 1807 uint32_t fphsyncstrt; 1808 uint32_t fpvsyncstrt; 1809 uint32_t fphtotaldisp; 1810 uint32_t fpvtotaldisp; 1811 uint32_t pitch; 1812 1813 sc = dp->rd_softc; 1814 cp = &dp->rd_crtcs[index]; 1815 crtc = cp->rc_number; 1816 mode = &cp->rc_videomode; 1817 1818 #if 1 1819 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1820 (dp->rd_bpp * 8)); 1821 #else 1822 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1823 (sc->sc_maxbpp * 8)); 1824 #endif 1825 //pitch = pitch | (pitch << 16); 1826 1827 switch (crtc) { 1828 case 0: 1829 gencntl = RADEON_CRTC_GEN_CNTL; 1830 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1831 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1832 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1833 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1834 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1835 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1836 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1837 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1838 break; 1839 case 1: 1840 gencntl = RADEON_CRTC2_GEN_CNTL; 1841 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1842 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1843 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1844 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1845 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1846 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1847 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1848 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1849 break; 1850 default: 1851 panic("Bad CRTC!"); 1852 break; 1853 } 1854 1855 /* 1856 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1857 */ 1858 /* only bother with 32bpp and 8bpp */ 1859 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1860 1861 if (crtc == 1) { 1862 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1863 } else { 1864 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1865 } 1866 1867 if (mode->flags & VID_DBLSCAN) 1868 v |= RADEON_CRTC2_DBL_SCAN_EN; 1869 1870 if (mode->flags & VID_INTERLACE) 1871 v |= RADEON_CRTC2_INTERLACE_EN; 1872 1873 if (mode->flags & VID_CSYNC) { 1874 v |= RADEON_CRTC2_CSYNC_EN; 1875 if (crtc == 1) 1876 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1877 } 1878 1879 PUT32(sc, gencntl, v); 1880 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1881 1882 /* 1883 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1884 */ 1885 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1886 if (crtc == 0) { 1887 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1888 RADEON_CRTC_DISPLAY_DIS); 1889 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1890 if (mode->flags & VID_CSYNC) 1891 v |= RADEON_CRTC_VSYNC_TRISTAT; 1892 } 1893 /* unconditional turn on CRT, in case first CRTC is DFP */ 1894 v |= RADEON_CRTC_CRT_ON; 1895 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1896 PRINTREG(RADEON_CRTC_EXT_CNTL); 1897 1898 /* 1899 * H_TOTAL_DISP 1900 */ 1901 v = ((mode->hdisplay / 8) - 1) << 16; 1902 v |= (mode->htotal / 8) - 1; 1903 PUT32(sc, htotaldisp, v); 1904 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1905 PUT32(sc, fphtotaldisp, v); 1906 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1907 1908 /* 1909 * H_SYNC_STRT_WID 1910 */ 1911 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1912 v |= mode->hsync_start; 1913 if (mode->flags & VID_NHSYNC) 1914 v |= RADEON_CRTC_H_SYNC_POL; 1915 PUT32(sc, hsyncstrt, v); 1916 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1917 PUT32(sc, fphsyncstrt, v); 1918 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1919 1920 /* 1921 * V_TOTAL_DISP 1922 */ 1923 v = ((mode->vdisplay - 1) << 16); 1924 v |= (mode->vtotal - 1); 1925 PUT32(sc, vtotaldisp, v); 1926 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1927 PUT32(sc, fpvtotaldisp, v); 1928 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1929 1930 /* 1931 * V_SYNC_STRT_WID 1932 */ 1933 v = ((mode->vsync_end - mode->vsync_start) << 16); 1934 v |= (mode->vsync_start - 1); 1935 if (mode->flags & VID_NVSYNC) 1936 v |= RADEON_CRTC_V_SYNC_POL; 1937 PUT32(sc, vsyncstrt, v); 1938 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1939 PUT32(sc, fpvsyncstrt, v); 1940 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1941 1942 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1943 1944 switch (crtc) { 1945 case 0: 1946 PUT32(sc, RADEON_CRTC_OFFSET, 0); 1947 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1948 PUT32(sc, RADEON_CRTC_PITCH, pitch); 1949 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1950 1951 CLR32(sc, RADEON_CRTC_EXT_CNTL, 1952 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1953 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1954 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1955 PRINTREG(RADEON_CRTC_EXT_CNTL); 1956 PRINTREG(RADEON_CRTC_GEN_CNTL); 1957 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1958 break; 1959 1960 case 1: 1961 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 1962 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 1963 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 1964 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 1965 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 1966 RADEON_CRTC2_VSYNC_DIS | 1967 RADEON_CRTC2_HSYNC_DIS | 1968 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 1969 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1970 break; 1971 } 1972 } 1973 1974 int 1975 radeonfb_isblank(struct radeonfb_display *dp) 1976 { 1977 uint32_t reg, mask; 1978 1979 if (dp->rd_crtcs[0].rc_number) { 1980 reg = RADEON_CRTC2_GEN_CNTL; 1981 mask = RADEON_CRTC2_DISP_DIS; 1982 } else { 1983 reg = RADEON_CRTC_EXT_CNTL; 1984 mask = RADEON_CRTC_DISPLAY_DIS; 1985 } 1986 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 1987 } 1988 1989 void 1990 radeonfb_blank(struct radeonfb_display *dp, int blank) 1991 { 1992 struct radeonfb_softc *sc = dp->rd_softc; 1993 uint32_t reg, mask; 1994 uint32_t fpreg, fpval; 1995 int i; 1996 1997 for (i = 0; i < dp->rd_ncrtcs; i++) { 1998 1999 if (dp->rd_crtcs[i].rc_number) { 2000 reg = RADEON_CRTC2_GEN_CNTL; 2001 mask = RADEON_CRTC2_DISP_DIS; 2002 fpreg = RADEON_FP2_GEN_CNTL; 2003 fpval = RADEON_FP2_ON; 2004 } else { 2005 reg = RADEON_CRTC_EXT_CNTL; 2006 mask = RADEON_CRTC_DISPLAY_DIS; 2007 fpreg = RADEON_FP_GEN_CNTL; 2008 fpval = RADEON_FP_FPON; 2009 } 2010 2011 if (blank) { 2012 SET32(sc, reg, mask); 2013 CLR32(sc, fpreg, fpval); 2014 } else { 2015 CLR32(sc, reg, mask); 2016 SET32(sc, fpreg, fpval); 2017 } 2018 } 2019 PRINTREG(RADEON_FP_GEN_CNTL); 2020 PRINTREG(RADEON_FP2_GEN_CNTL); 2021 } 2022 2023 void 2024 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2025 long *defattr) 2026 { 2027 struct radeonfb_display *dp = cookie; 2028 struct rasops_info *ri = &scr->scr_ri; 2029 2030 /* initialize font subsystem */ 2031 wsfont_init(); 2032 2033 DPRINTF(("init screen called, existing %d\n", existing)); 2034 2035 ri->ri_depth = dp->rd_bpp; 2036 ri->ri_width = dp->rd_virtx; 2037 ri->ri_height = dp->rd_virty; 2038 ri->ri_stride = dp->rd_stride; 2039 ri->ri_flg = RI_CENTER; 2040 ri->ri_bits = (void *)dp->rd_fbptr; 2041 2042 /* XXX: 32 bpp only */ 2043 /* this is rgb in "big-endian order..." */ 2044 ri->ri_rnum = 8; 2045 ri->ri_gnum = 8; 2046 ri->ri_bnum = 8; 2047 ri->ri_rpos = 16; 2048 ri->ri_gpos = 8; 2049 ri->ri_bpos = 0; 2050 2051 if (existing) { 2052 ri->ri_flg |= RI_CLEAR; 2053 2054 /* start a modeswitch now */ 2055 radeonfb_modeswitch(dp); 2056 } 2057 2058 /* 2059 * XXX: font selection should be based on properties, with some 2060 * normal/reasonable default. 2061 */ 2062 ri->ri_caps = WSSCREEN_WSCOLORS; 2063 2064 /* initialize and look for an initial font */ 2065 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2066 2067 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2068 dp->rd_virtx / ri->ri_font->fontwidth); 2069 2070 /* enable acceleration */ 2071 ri->ri_ops.copyrows = radeonfb_copyrows; 2072 ri->ri_ops.copycols = radeonfb_copycols; 2073 ri->ri_ops.eraserows = radeonfb_eraserows; 2074 ri->ri_ops.erasecols = radeonfb_erasecols; 2075 ri->ri_ops.allocattr = radeonfb_allocattr; 2076 ri->ri_ops.putchar = radeonfb_putchar; 2077 ri->ri_ops.cursor = radeonfb_cursor; 2078 } 2079 2080 void 2081 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2082 { 2083 uint32_t gen, ext, gen2 = 0; 2084 uint32_t agploc, aperbase, apersize, mcfbloc; 2085 2086 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2087 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2088 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2089 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2090 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2091 2092 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2093 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2094 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2095 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2096 2097 if (HAS_CRTC2(sc)) { 2098 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2099 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2100 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2101 } 2102 2103 delay(100000); 2104 2105 mcfbloc = (aperbase >> 16) | 2106 ((aperbase + (apersize - 1)) & 0xffff0000); 2107 2108 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2109 sc->sc_memsz = apersize; 2110 2111 if (((agploc & 0xffff) << 16) != 2112 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2113 agploc = mcfbloc & 0xffff0000U; 2114 agploc |= ((agploc + 0x10000) >> 16); 2115 } 2116 2117 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2118 2119 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2120 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2121 2122 DPRINTF(("aperbase = %u\n", aperbase)); 2123 PRINTREG(RADEON_MC_FB_LOCATION); 2124 PRINTREG(RADEON_MC_AGP_LOCATION); 2125 2126 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2127 2128 if (HAS_CRTC2(sc)) 2129 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2130 2131 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2132 2133 #if 0 2134 /* XXX: what is this AGP garbage? :-) */ 2135 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2136 #endif 2137 2138 delay(100000); 2139 2140 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2141 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2142 2143 if (HAS_CRTC2(sc)) 2144 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2145 } 2146 2147 void 2148 radeonfb_init_misc(struct radeonfb_softc *sc) 2149 { 2150 PUT32(sc, RADEON_BUS_CNTL, 2151 RADEON_BUS_MASTER_DIS | 2152 RADEON_BUS_PREFETCH_MODE_ACT | 2153 RADEON_BUS_PCI_READ_RETRY_EN | 2154 RADEON_BUS_PCI_WRT_RETRY_EN | 2155 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2156 RADEON_BUS_MSTR_RD_MULT | 2157 RADEON_BUS_MSTR_RD_LINE | 2158 RADEON_BUS_RD_DISCARD_EN | 2159 RADEON_BUS_MSTR_DISCONNECT_EN | 2160 RADEON_BUS_READ_BURST); 2161 2162 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2163 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2164 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2165 PUT32(sc, RADEON_RBBM_CNTL, 2166 (3 << RADEON_RB_SETTLE_SHIFT) | 2167 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2168 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2169 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2170 2171 /* XXX: figure out what these mean! */ 2172 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2173 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2174 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2175 2176 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2177 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2178 } 2179 2180 /* 2181 * This loads a linear color map for true color. 2182 */ 2183 void 2184 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2185 { 2186 int i; 2187 uint32_t vclk; 2188 2189 #define DAC_WIDTH ((1 << 10) - 1) 2190 #define CLUT_WIDTH ((1 << 8) - 1) 2191 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2192 2193 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2194 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2195 2196 if (crtc) 2197 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2198 else 2199 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2200 2201 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2202 for (i = 0; i <= CLUT_WIDTH; ++i) { 2203 PUT32(sc, RADEON_PALETTE_30_DATA, 2204 (CLUT_COLOR(i) << 10) | 2205 (CLUT_COLOR(i) << 20) | 2206 (CLUT_COLOR(i))); 2207 } 2208 2209 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2210 PRINTREG(RADEON_DAC_CNTL2); 2211 2212 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2213 } 2214 2215 /* 2216 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2217 */ 2218 void 2219 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2220 { 2221 uint32_t tmp, save; 2222 2223 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2224 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2225 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2226 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2227 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2228 } 2229 2230 /* 2231 * Acceleration entry points. 2232 */ 2233 static void 2234 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2235 { 2236 struct rasops_info *ri = cookie; 2237 struct vcons_screen *scr = ri->ri_hw; 2238 struct radeonfb_display *dp = scr->scr_cookie; 2239 uint32_t x, y, w, h; 2240 uint32_t bg, fg; 2241 uint8_t *data; 2242 2243 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2244 return; 2245 2246 if (!CHAR_IN_FONT(c, ri->ri_font)) 2247 return; 2248 2249 w = ri->ri_font->fontwidth; 2250 h = ri->ri_font->fontheight; 2251 2252 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2253 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2254 2255 x = ri->ri_xorigin + col * w; 2256 y = ri->ri_yorigin + row * h; 2257 2258 if (c == 0x20) { 2259 radeonfb_rectfill(dp, x, y, w, h, bg); 2260 } else { 2261 data = (uint8_t *)ri->ri_font->data + 2262 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2263 2264 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2265 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2266 } 2267 } 2268 2269 static void 2270 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2271 { 2272 struct rasops_info *ri = cookie; 2273 struct vcons_screen *scr = ri->ri_hw; 2274 struct radeonfb_display *dp = scr->scr_cookie; 2275 uint32_t x, y, w, h, fg, bg, ul; 2276 2277 /* XXX: check for full emulation mode? */ 2278 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2279 x = ri->ri_xorigin; 2280 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2281 w = ri->ri_emuwidth; 2282 h = ri->ri_font->fontheight * nrows; 2283 2284 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2285 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2286 } 2287 } 2288 2289 static void 2290 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2291 { 2292 struct rasops_info *ri = cookie; 2293 struct vcons_screen *scr = ri->ri_hw; 2294 struct radeonfb_display *dp = scr->scr_cookie; 2295 uint32_t x, ys, yd, w, h; 2296 2297 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2298 x = ri->ri_xorigin; 2299 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2300 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2301 w = ri->ri_emuwidth; 2302 h = ri->ri_font->fontheight * nrows; 2303 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2304 RADEON_ROP3_S, 0xffffffff); 2305 } 2306 } 2307 2308 static void 2309 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2310 { 2311 struct rasops_info *ri = cookie; 2312 struct vcons_screen *scr = ri->ri_hw; 2313 struct radeonfb_display *dp = scr->scr_cookie; 2314 uint32_t xs, xd, y, w, h; 2315 2316 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2317 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2318 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2319 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2320 w = ri->ri_font->fontwidth * ncols; 2321 h = ri->ri_font->fontheight; 2322 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2323 RADEON_ROP3_S, 0xffffffff); 2324 } 2325 } 2326 2327 static void 2328 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2329 long fillattr) 2330 { 2331 struct rasops_info *ri = cookie; 2332 struct vcons_screen *scr = ri->ri_hw; 2333 struct radeonfb_display *dp = scr->scr_cookie; 2334 uint32_t x, y, w, h, fg, bg, ul; 2335 2336 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2337 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2338 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2339 w = ri->ri_font->fontwidth * ncols; 2340 h = ri->ri_font->fontheight; 2341 2342 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2343 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2344 } 2345 } 2346 2347 static void 2348 radeonfb_cursor(void *cookie, int on, int row, int col) 2349 { 2350 struct rasops_info *ri = cookie; 2351 struct vcons_screen *scr = ri->ri_hw; 2352 struct radeonfb_display *dp = scr->scr_cookie; 2353 int x, y, wi, he; 2354 2355 wi = ri->ri_font->fontwidth; 2356 he = ri->ri_font->fontheight; 2357 2358 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2359 x = ri->ri_ccol * wi + ri->ri_xorigin; 2360 y = ri->ri_crow * he + ri->ri_yorigin; 2361 /* first turn off the old cursor */ 2362 if (ri->ri_flg & RI_CURSOR) { 2363 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2364 RADEON_ROP3_Dn, 0xffffffff); 2365 ri->ri_flg &= ~RI_CURSOR; 2366 } 2367 ri->ri_crow = row; 2368 ri->ri_ccol = col; 2369 /* then (possibly) turn on the new one */ 2370 if (on) { 2371 x = ri->ri_ccol * wi + ri->ri_xorigin; 2372 y = ri->ri_crow * he + ri->ri_yorigin; 2373 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2374 RADEON_ROP3_Dn, 0xffffffff); 2375 ri->ri_flg |= RI_CURSOR; 2376 } 2377 } else { 2378 scr->scr_ri.ri_crow = row; 2379 scr->scr_ri.ri_ccol = col; 2380 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2381 } 2382 } 2383 2384 static int 2385 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2386 { 2387 if ((fg == 0) && (bg == 0)) { 2388 fg = WS_DEFAULT_FG; 2389 bg = WS_DEFAULT_BG; 2390 } 2391 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2392 return 0; 2393 } 2394 2395 /* 2396 * Underlying acceleration support. 2397 */ 2398 static void 2399 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2400 int height, uint32_t fg, uint32_t bg) 2401 { 2402 struct radeonfb_softc *sc = dp->rd_softc; 2403 uint32_t gmc; 2404 uint32_t padded_width = (width+7) & 0xfff8; 2405 uint32_t topleft, bottomright; 2406 2407 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2408 2409 if (width != padded_width) { 2410 2411 radeonfb_wait_fifo(sc, 2); 2412 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2413 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2414 ((xd + width) & 0x1fff); 2415 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2416 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2417 } 2418 2419 radeonfb_wait_fifo(sc, 5); 2420 2421 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2422 RADEON_GMC_BRUSH_NONE | 2423 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2424 //RADEON_GMC_BYTE_LSB_TO_MSB | 2425 RADEON_GMC_DST_CLIPPING | 2426 RADEON_ROP3_S | 2427 RADEON_DP_SRC_SOURCE_HOST_DATA | 2428 RADEON_GMC_CLR_CMP_CNTL_DIS | 2429 RADEON_GMC_WR_MSK_DIS | 2430 gmc); 2431 2432 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2433 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2434 2435 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2436 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2437 2438 } 2439 2440 static void 2441 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2442 { 2443 struct radeonfb_softc *sc = dp->rd_softc; 2444 int i; 2445 uint32_t latch = 0; 2446 int shift = 0; 2447 2448 for (i = 0; i < count; i++) { 2449 latch |= (data[i] << shift); 2450 if (shift == 24) { 2451 radeonfb_wait_fifo(sc, 1); 2452 PUT32(sc, RADEON_HOST_DATA0, latch); 2453 latch = 0; 2454 shift = 0; 2455 } else 2456 shift += 8; 2457 } 2458 if (shift != 0) { 2459 radeonfb_wait_fifo(sc, 1); 2460 PUT32(sc, RADEON_HOST_DATA0, latch); 2461 } 2462 radeonfb_unclip(sc); 2463 } 2464 2465 static void 2466 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2467 int width, int height, uint32_t color) 2468 { 2469 struct radeonfb_softc *sc = dp->rd_softc; 2470 uint32_t gmc; 2471 2472 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2473 2474 radeonfb_wait_fifo(sc, 6); 2475 2476 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2477 RADEON_GMC_BRUSH_SOLID_COLOR | 2478 RADEON_GMC_SRC_DATATYPE_COLOR | 2479 RADEON_GMC_CLR_CMP_CNTL_DIS | 2480 RADEON_ROP3_P | gmc); 2481 2482 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2483 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2484 PUT32(sc, RADEON_DP_CNTL, 2485 RADEON_DST_X_LEFT_TO_RIGHT | 2486 RADEON_DST_Y_TOP_TO_BOTTOM); 2487 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2488 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2489 2490 /* 2491 * XXX: we don't wait for the fifo to empty -- that would slow 2492 * things down! The linux radeonfb driver waits, but xfree doesn't 2493 */ 2494 /* XXX: for now we do, to make it safe for direct drawing */ 2495 radeonfb_engine_idle(sc); 2496 } 2497 2498 static void 2499 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2500 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2501 { 2502 struct radeonfb_softc *sc = dp->rd_softc; 2503 uint32_t gmc; 2504 uint32_t dir; 2505 2506 if (dsty < srcy) { 2507 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2508 } else { 2509 srcy += height - 1; 2510 dsty += height - 1; 2511 dir = 0; 2512 } 2513 if (dstx < srcx) { 2514 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2515 } else { 2516 srcx += width - 1; 2517 dstx += width - 1; 2518 } 2519 2520 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2521 2522 radeonfb_wait_fifo(sc, 6); 2523 2524 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2525 //RADEON_GMC_SRC_CLIPPING | 2526 RADEON_GMC_BRUSH_SOLID_COLOR | 2527 RADEON_GMC_SRC_DATATYPE_COLOR | 2528 RADEON_GMC_CLR_CMP_CNTL_DIS | 2529 RADEON_DP_SRC_SOURCE_MEMORY | 2530 rop | gmc); 2531 2532 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2533 PUT32(sc, RADEON_DP_CNTL, dir); 2534 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2535 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2536 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2537 2538 /* 2539 * XXX: we don't wait for the fifo to empty -- that would slow 2540 * things down! The linux radeonfb driver waits, but xfree doesn't 2541 */ 2542 /* XXX: for now we do, to make it safe for direct drawing */ 2543 radeonfb_engine_idle(sc); 2544 } 2545 2546 static void 2547 radeonfb_engine_idle(struct radeonfb_softc *sc) 2548 { 2549 int i; 2550 2551 radeonfb_wait_fifo(sc, 64); 2552 for (i = RADEON_TIMEOUT; i; i--) { 2553 if ((GET32(sc, RADEON_RBBM_STATUS) & 2554 RADEON_RBBM_ACTIVE) == 0) { 2555 radeonfb_engine_flush(sc); 2556 break; 2557 } 2558 } 2559 } 2560 2561 static void 2562 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2563 { 2564 int i; 2565 2566 for (i = RADEON_TIMEOUT; i; i--) { 2567 if ((GET32(sc, RADEON_RBBM_STATUS) & 2568 RADEON_RBBM_FIFOCNT_MASK) >= n) 2569 return; 2570 } 2571 #ifdef DIAGNOSTIC 2572 if (!i) 2573 printf("%s: timed out waiting for fifo (%x)\n", 2574 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2575 #endif 2576 } 2577 2578 static void 2579 radeonfb_engine_flush(struct radeonfb_softc *sc) 2580 { 2581 int i; 2582 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2583 for (i = RADEON_TIMEOUT; i; i--) { 2584 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2585 RADEON_RB2D_DC_BUSY) == 0) 2586 break; 2587 } 2588 #ifdef DIAGNOSTIC 2589 if (!i) 2590 printf("%s: engine flush timed out!\n", XNAME(sc)); 2591 #endif 2592 } 2593 2594 static inline void 2595 radeonfb_unclip(struct radeonfb_softc *sc) 2596 { 2597 2598 radeonfb_wait_fifo(sc, 2); 2599 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2600 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2601 } 2602 2603 static void 2604 radeonfb_engine_init(struct radeonfb_display *dp) 2605 { 2606 struct radeonfb_softc *sc = dp->rd_softc; 2607 uint32_t pitch; 2608 2609 /* no 3D */ 2610 PUT32(sc, RADEON_RB3D_CNTL, 0); 2611 2612 radeonfb_engine_reset(sc); 2613 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2614 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2615 2616 radeonfb_wait_fifo(sc, 1); 2617 if (!IS_R300(sc)) 2618 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2619 2620 radeonfb_wait_fifo(sc, 3); 2621 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2622 (pitch << 22) | (sc->sc_aperbase >> 10)); 2623 2624 2625 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2626 (pitch << 22) | (sc->sc_aperbase >> 10)); 2627 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2628 (pitch << 22) | (sc->sc_aperbase >> 10)); 2629 2630 radeonfb_wait_fifo(sc, 1); 2631 #if _BYTE_ORDER == _BIG_ENDIAN 2632 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2633 #else 2634 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2635 #endif 2636 2637 /* default scissors -- no clipping */ 2638 radeonfb_wait_fifo(sc, 1); 2639 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2640 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2641 2642 radeonfb_wait_fifo(sc, 1); 2643 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2644 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2645 RADEON_GMC_CLR_CMP_CNTL_DIS | 2646 RADEON_GMC_BRUSH_SOLID_COLOR | 2647 RADEON_GMC_SRC_DATATYPE_COLOR); 2648 2649 radeonfb_wait_fifo(sc, 7); 2650 PUT32(sc, RADEON_DST_LINE_START, 0); 2651 PUT32(sc, RADEON_DST_LINE_END, 0); 2652 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2653 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2654 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2655 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2656 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2657 2658 radeonfb_engine_idle(sc); 2659 } 2660 2661 static void 2662 radeonfb_engine_reset(struct radeonfb_softc *sc) 2663 { 2664 uint32_t hpc, rbbm, mclkcntl, clkindex; 2665 2666 radeonfb_engine_flush(sc); 2667 2668 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2669 if (HAS_R300CG(sc)) 2670 radeonfb_r300cg_workaround(sc); 2671 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2672 2673 /* 2674 * According to comments in XFree code, resetting the HDP via 2675 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2676 * So we use HOST_PATH_CNTL instead. 2677 */ 2678 2679 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2680 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2681 if (IS_R300(sc)) { 2682 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2683 RADEON_SOFT_RESET_CP | 2684 RADEON_SOFT_RESET_HI | 2685 RADEON_SOFT_RESET_E2); 2686 GET32(sc, RADEON_RBBM_SOFT_RESET); 2687 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2688 /* 2689 * XXX: this bit is not defined in any ATI docs I have, 2690 * nor in the XFree code, but XFree does it. Why? 2691 */ 2692 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2693 } else { 2694 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2695 RADEON_SOFT_RESET_CP | 2696 RADEON_SOFT_RESET_SE | 2697 RADEON_SOFT_RESET_RE | 2698 RADEON_SOFT_RESET_PP | 2699 RADEON_SOFT_RESET_E2 | 2700 RADEON_SOFT_RESET_RB); 2701 GET32(sc, RADEON_RBBM_SOFT_RESET); 2702 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2703 ~(RADEON_SOFT_RESET_CP | 2704 RADEON_SOFT_RESET_SE | 2705 RADEON_SOFT_RESET_RE | 2706 RADEON_SOFT_RESET_PP | 2707 RADEON_SOFT_RESET_E2 | 2708 RADEON_SOFT_RESET_RB)); 2709 GET32(sc, RADEON_RBBM_SOFT_RESET); 2710 } 2711 2712 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2713 GET32(sc, RADEON_HOST_PATH_CNTL); 2714 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2715 2716 if (IS_R300(sc)) 2717 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2718 2719 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2720 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2721 2722 if (HAS_R300CG(sc)) 2723 radeonfb_r300cg_workaround(sc); 2724 } 2725 2726 static int 2727 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2728 { 2729 int x, y; 2730 2731 x = pos->x; 2732 y = pos->y; 2733 2734 /* 2735 * This doesn't let a cursor move off the screen. I'm not 2736 * sure if this will have negative effects for e.g. Xinerama. 2737 * I'd guess Xinerama handles it by changing the cursor shape, 2738 * but that needs verification. 2739 */ 2740 if (x >= dp->rd_virtx) 2741 x = dp->rd_virtx - 1; 2742 if (x < 0) 2743 x = 0; 2744 if (y >= dp->rd_virty) 2745 y = dp->rd_virty - 1; 2746 if (y < 0) 2747 y = 0; 2748 2749 dp->rd_cursor.rc_pos.x = x; 2750 dp->rd_cursor.rc_pos.y = y; 2751 2752 radeonfb_cursor_position(dp); 2753 return 0; 2754 } 2755 2756 static int 2757 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2758 { 2759 unsigned flags; 2760 2761 uint8_t r[2], g[2], b[2]; 2762 unsigned index, count; 2763 int i, err; 2764 int pitch, size; 2765 struct radeonfb_cursor nc; 2766 2767 flags = wc->which; 2768 2769 /* copy old values */ 2770 nc = dp->rd_cursor; 2771 2772 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2773 index = wc->cmap.index; 2774 count = wc->cmap.count; 2775 2776 if (index >= 2 || (index + count) > 2) 2777 return EINVAL; 2778 2779 err = copyin(wc->cmap.red, &r[index], count); 2780 if (err) 2781 return err; 2782 err = copyin(wc->cmap.green, &g[index], count); 2783 if (err) 2784 return err; 2785 err = copyin(wc->cmap.blue, &b[index], count); 2786 if (err) 2787 return err; 2788 2789 for (i = index; i < index + count; i++) { 2790 nc.rc_cmap[i] = 2791 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2792 } 2793 } 2794 2795 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2796 if ((wc->size.x > RADEON_CURSORMAXX) || 2797 (wc->size.y > RADEON_CURSORMAXY)) 2798 return EINVAL; 2799 2800 /* figure bytes per line */ 2801 pitch = (wc->size.x + 7) / 8; 2802 size = pitch * wc->size.y; 2803 2804 /* clear the old cursor and mask */ 2805 memset(nc.rc_image, 0, 512); 2806 memset(nc.rc_mask, 0, 512); 2807 2808 nc.rc_size = wc->size; 2809 2810 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2811 return err; 2812 2813 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2814 return err; 2815 } 2816 2817 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2818 nc.rc_hot = wc->hot; 2819 if (nc.rc_hot.x >= nc.rc_size.x) 2820 nc.rc_hot.x = nc.rc_size.x - 1; 2821 if (nc.rc_hot.y >= nc.rc_size.y) 2822 nc.rc_hot.y = nc.rc_size.y - 1; 2823 } 2824 2825 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2826 nc.rc_pos = wc->pos; 2827 if (nc.rc_pos.x >= dp->rd_virtx) 2828 nc.rc_pos.x = dp->rd_virtx - 1; 2829 #if 0 2830 if (nc.rc_pos.x < 0) 2831 nc.rc_pos.x = 0; 2832 #endif 2833 if (nc.rc_pos.y >= dp->rd_virty) 2834 nc.rc_pos.y = dp->rd_virty - 1; 2835 #if 0 2836 if (nc.rc_pos.y < 0) 2837 nc.rc_pos.y = 0; 2838 #endif 2839 } 2840 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2841 nc.rc_visible = wc->enable; 2842 } 2843 2844 dp->rd_cursor = nc; 2845 radeonfb_cursor_update(dp, wc->which); 2846 2847 return 0; 2848 } 2849 2850 /* 2851 * Change the cursor shape. Call this with the cursor locked to avoid 2852 * flickering/tearing. 2853 */ 2854 static void 2855 radeonfb_cursor_shape(struct radeonfb_display *dp) 2856 { 2857 uint8_t and[512], xor[512]; 2858 int i, j, src, dst, pitch; 2859 const uint8_t *msk = dp->rd_cursor.rc_mask; 2860 const uint8_t *img = dp->rd_cursor.rc_image; 2861 2862 /* 2863 * Radeon cursor data interleaves one line of AND data followed 2864 * by a line of XOR data. (Each line corresponds to a whole hardware 2865 * pitch - i.e. 64 pixels or 8 bytes.) 2866 * 2867 * The cursor is displayed using the following table: 2868 * 2869 * AND XOR Result 2870 * ---------------------- 2871 * 0 0 Cursor color 0 2872 * 0 1 Cursor color 1 2873 * 1 0 Transparent 2874 * 1 1 Complement of background 2875 * 2876 * Our masks are therefore different from what we were passed. 2877 * Passed in, I'm assuming the data represents either color 0 or 1, 2878 * and a mask, so the passed in table looks like: 2879 * 2880 * IMG Mask Result 2881 * ----------------------- 2882 * 0 0 Transparent 2883 * 0 1 Cursor color 0 2884 * 1 0 Transparent 2885 * 1 1 Cursor color 1 2886 * 2887 * IF mask bit == 1, AND = 0, XOR = color. 2888 * IF mask bit == 0, AND = 1, XOR = 0. 2889 * 2890 * hence: AND = ~(mask); XOR = color & ~(mask); 2891 */ 2892 2893 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2894 2895 /* start by assuming all bits are transparent */ 2896 memset(and, 0xff, 512); 2897 memset(xor, 0x00, 512); 2898 2899 src = 0; 2900 dst = 0; 2901 for (i = 0; i < 64; i++) { 2902 for (j = 0; j < 64; j += 8) { 2903 if ((i < dp->rd_cursor.rc_size.y) && 2904 (j < dp->rd_cursor.rc_size.x)) { 2905 2906 /* take care to leave odd bits alone */ 2907 and[dst] &= ~(msk[src]); 2908 xor[dst] = img[src] & msk[src]; 2909 src++; 2910 } 2911 dst++; 2912 } 2913 } 2914 2915 /* copy the image into place */ 2916 for (i = 0; i < 64; i++) { 2917 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2918 &and[i * 8], 8); 2919 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2920 &xor[i * 8], 8); 2921 } 2922 } 2923 2924 static void 2925 radeonfb_cursor_position(struct radeonfb_display *dp) 2926 { 2927 struct radeonfb_softc *sc = dp->rd_softc; 2928 uint32_t offset, hvoff, hvpos; /* registers */ 2929 uint32_t coff; /* cursor offset */ 2930 int i, x, y, xoff, yoff, crtcoff; 2931 2932 /* 2933 * XXX: this also needs to handle pan/scan 2934 */ 2935 for (i = 0; i < dp->rd_ncrtcs; i++) { 2936 2937 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2938 2939 if (rcp->rc_number) { 2940 offset = RADEON_CUR2_OFFSET; 2941 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2942 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2943 crtcoff = RADEON_CRTC2_OFFSET; 2944 } else { 2945 offset = RADEON_CUR_OFFSET; 2946 hvoff = RADEON_CUR_HORZ_VERT_OFF; 2947 hvpos = RADEON_CUR_HORZ_VERT_POSN; 2948 crtcoff = RADEON_CRTC_OFFSET; 2949 } 2950 2951 x = dp->rd_cursor.rc_pos.x; 2952 y = dp->rd_cursor.rc_pos.y; 2953 2954 while (y < rcp->rc_yoffset) { 2955 rcp->rc_yoffset -= RADEON_PANINCREMENT; 2956 } 2957 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 2958 rcp->rc_yoffset += RADEON_PANINCREMENT; 2959 } 2960 while (x < rcp->rc_xoffset) { 2961 rcp->rc_xoffset -= RADEON_PANINCREMENT; 2962 } 2963 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 2964 rcp->rc_xoffset += RADEON_PANINCREMENT; 2965 } 2966 2967 /* adjust for the cursor's hotspot */ 2968 x -= dp->rd_cursor.rc_hot.x; 2969 y -= dp->rd_cursor.rc_hot.y; 2970 xoff = yoff = 0; 2971 2972 if (x >= dp->rd_virtx) 2973 x = dp->rd_virtx - 1; 2974 if (y >= dp->rd_virty) 2975 y = dp->rd_virty - 1; 2976 2977 /* now adjust cursor so it is relative to viewport */ 2978 x -= rcp->rc_xoffset; 2979 y -= rcp->rc_yoffset; 2980 2981 /* 2982 * no need to check for fall off, because we should 2983 * never move off the screen entirely! 2984 */ 2985 coff = 0; 2986 if (x < 0) { 2987 xoff = -x; 2988 x = 0; 2989 } 2990 if (y < 0) { 2991 yoff = -y; 2992 y = 0; 2993 coff = (yoff * 2) * 8; 2994 } 2995 2996 /* pan the display */ 2997 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 2998 rcp->rc_xoffset); 2999 3000 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3001 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3002 /* NB: this unlocks the cursor */ 3003 PUT32(sc, hvpos, (x << 16) | y); 3004 } 3005 } 3006 3007 static void 3008 radeonfb_cursor_visible(struct radeonfb_display *dp) 3009 { 3010 int i; 3011 uint32_t gencntl, bit; 3012 3013 for (i = 0; i < dp->rd_ncrtcs; i++) { 3014 if (dp->rd_crtcs[i].rc_number) { 3015 gencntl = RADEON_CRTC2_GEN_CNTL; 3016 bit = RADEON_CRTC2_CUR_EN; 3017 } else { 3018 gencntl = RADEON_CRTC_GEN_CNTL; 3019 bit = RADEON_CRTC_CUR_EN; 3020 } 3021 3022 if (dp->rd_cursor.rc_visible) 3023 SET32(dp->rd_softc, gencntl, bit); 3024 else 3025 CLR32(dp->rd_softc, gencntl, bit); 3026 } 3027 } 3028 3029 static void 3030 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3031 { 3032 int i; 3033 uint32_t c0reg, c1reg; 3034 struct radeonfb_softc *sc = dp->rd_softc; 3035 3036 for (i = 0; i < dp->rd_ncrtcs; i++) { 3037 if (dp->rd_crtcs[i].rc_number) { 3038 c0reg = RADEON_CUR2_CLR0; 3039 c1reg = RADEON_CUR2_CLR1; 3040 } else { 3041 c0reg = RADEON_CUR_CLR0; 3042 c1reg = RADEON_CUR_CLR1; 3043 } 3044 3045 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3046 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3047 } 3048 } 3049 3050 static void 3051 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3052 { 3053 struct radeonfb_softc *sc; 3054 int i; 3055 3056 sc = dp->rd_softc; 3057 for (i = 0; i < dp->rd_ncrtcs; i++) { 3058 if (dp->rd_crtcs[i].rc_number) { 3059 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3060 } else { 3061 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3062 } 3063 } 3064 3065 if (which & WSDISPLAY_CURSOR_DOCMAP) 3066 radeonfb_cursor_cmap(dp); 3067 3068 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3069 radeonfb_cursor_shape(dp); 3070 3071 if (which & WSDISPLAY_CURSOR_DOCUR) 3072 radeonfb_cursor_visible(dp); 3073 3074 /* this one is unconditional, because it updates other stuff */ 3075 radeonfb_cursor_position(dp); 3076 } 3077 3078 static struct videomode * 3079 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3080 { 3081 int r1, r2; 3082 3083 /* otherwise pick the higher refresh rate */ 3084 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3085 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3086 3087 return (r1 < r2 ? m2 : m1); 3088 } 3089 3090 static const struct videomode * 3091 radeonfb_port_mode(struct radeonfb_port *rp, int x, int y) 3092 { 3093 struct edid_info *ep = &rp->rp_edid; 3094 struct videomode *vmp = NULL; 3095 int i; 3096 3097 if (!rp->rp_edid_valid) { 3098 /* fallback to safe mode */ 3099 return radeonfb_modelookup(RADEON_DEFAULT_MODE); 3100 } 3101 3102 /* always choose the preferred mode first! */ 3103 if (ep->edid_preferred_mode) { 3104 3105 /* XXX: add auto-stretching support for native mode */ 3106 3107 /* this may want panning to occur, btw */ 3108 if ((ep->edid_preferred_mode->hdisplay <= x) && 3109 (ep->edid_preferred_mode->vdisplay <= y)) 3110 return ep->edid_preferred_mode; 3111 } 3112 3113 for (i = 0; i < ep->edid_nmodes; i++) { 3114 /* 3115 * We elect to pick a resolution that is too large for 3116 * the monitor than one that is too small. This means 3117 * that we will prefer to pan rather than to try to 3118 * center a smaller display on a larger screen. In 3119 * practice, this shouldn't matter because if a 3120 * monitor can support a larger resolution, it can 3121 * probably also support the smaller. A specific 3122 * exception is fixed format panels, but hopefully 3123 * they are properly dealt with by the "autostretch" 3124 * logic above. 3125 */ 3126 if ((ep->edid_modes[i].hdisplay > x) || 3127 (ep->edid_modes[i].vdisplay > y)) { 3128 continue; 3129 } 3130 3131 /* 3132 * at this point, the display mode is no larger than 3133 * what we've requested. 3134 */ 3135 if (vmp == NULL) 3136 vmp = &ep->edid_modes[i]; 3137 3138 /* eliminate smaller modes */ 3139 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3140 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3141 continue; 3142 3143 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3144 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3145 vmp = &ep->edid_modes[i]; 3146 continue; 3147 } 3148 3149 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3150 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3151 3152 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3153 } 3154 3155 return (vmp ? vmp : radeonfb_modelookup(RADEON_DEFAULT_MODE)); 3156 } 3157 3158 static int 3159 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3160 { 3161 int i; 3162 3163 for (i = 0; i < nlist; i++) { 3164 if ((x == list[i].hdisplay) && 3165 (y == list[i].vdisplay)) { 3166 return 1; 3167 } 3168 } 3169 return 0; 3170 } 3171 3172 static void 3173 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3174 int pan) 3175 { 3176 struct radeonfb_port *rp; 3177 struct edid_info *ep; 3178 int i, j; 3179 3180 *x = 0; 3181 *y = 0; 3182 3183 if (pan) { 3184 for (i = 0; i < dp->rd_ncrtcs; i++) { 3185 rp = dp->rd_crtcs[i].rc_port; 3186 ep = &rp->rp_edid; 3187 if (!rp->rp_edid_valid) { 3188 /* monitor not present */ 3189 continue; 3190 } 3191 3192 /* 3193 * For now we are ignoring "conflict" that 3194 * could occur when mixing some modes like 3195 * 1280x1024 and 1400x800. It isn't clear 3196 * which is better, so the first one wins. 3197 */ 3198 for (j = 0; j < ep->edid_nmodes; j++) { 3199 /* 3200 * ignore resolutions that are too big for 3201 * the radeon 3202 */ 3203 if (ep->edid_modes[j].hdisplay > 3204 dp->rd_softc->sc_maxx) 3205 continue; 3206 if (ep->edid_modes[j].vdisplay > 3207 dp->rd_softc->sc_maxy) 3208 continue; 3209 3210 /* 3211 * pick largest resolution, the 3212 * smaller monitor will pan 3213 */ 3214 if ((ep->edid_modes[j].hdisplay >= *x) && 3215 (ep->edid_modes[j].vdisplay >= *y)) { 3216 *x = ep->edid_modes[j].hdisplay; 3217 *y = ep->edid_modes[j].vdisplay; 3218 } 3219 } 3220 } 3221 3222 } else { 3223 struct videomode modes[64]; 3224 int nmodes = 0; 3225 int valid = 0; 3226 3227 for (i = 0; i < dp->rd_ncrtcs; i++) { 3228 /* 3229 * pick the largest resolution in common. 3230 */ 3231 rp = dp->rd_crtcs[i].rc_port; 3232 ep = &rp->rp_edid; 3233 3234 if (!rp->rp_edid_valid) 3235 continue; 3236 3237 if (!valid) { 3238 /* initialize starting list */ 3239 for (j = 0; j < ep->edid_nmodes; j++) { 3240 /* 3241 * ignore resolutions that are 3242 * too big for the radeon 3243 */ 3244 if (ep->edid_modes[j].hdisplay > 3245 dp->rd_softc->sc_maxx) 3246 continue; 3247 if (ep->edid_modes[j].vdisplay > 3248 dp->rd_softc->sc_maxy) 3249 continue; 3250 3251 modes[nmodes] = ep->edid_modes[j]; 3252 nmodes++; 3253 } 3254 valid = 1; 3255 } else { 3256 /* merge into preexisting list */ 3257 for (j = 0; j < nmodes; j++) { 3258 if (!radeonfb_hasres(ep->edid_modes, 3259 ep->edid_nmodes, 3260 modes[j].hdisplay, 3261 modes[j].vdisplay)) { 3262 modes[j] = modes[nmodes]; 3263 j--; 3264 nmodes--; 3265 } 3266 } 3267 } 3268 } 3269 3270 /* now we have to pick from the merged list */ 3271 for (i = 0; i < nmodes; i++) { 3272 if ((modes[i].hdisplay >= *x) && 3273 (modes[i].vdisplay >= *y)) { 3274 *x = modes[i].hdisplay; 3275 *y = modes[i].vdisplay; 3276 } 3277 } 3278 } 3279 3280 if ((*x == 0) || (*y == 0)) { 3281 /* fallback to safe mode */ 3282 *x = 640; 3283 *y = 480; 3284 } 3285 } 3286
Indexes created Mon Sep 22 13:09:51 GMT 2025