radeonfb.c revision 1.7.2.1
1 /* $NetBSD: radeonfb.c,v 1.7.2.1 2007/03/04 12:25:14 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.7.2.1 2007/03/04 12:25:14 bouyer Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static int radeonfb_get_backlight(struct radeonfb_display *); 167 static int radeonfb_set_backlight(struct radeonfb_display *, int); 168 static void radeonfb_lvds_callout(void *); 169 170 static struct videomode *radeonfb_best_refresh(struct videomode *, 171 struct videomode *); 172 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 173 uint16_t *, int); 174 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 175 struct radeonfb_port *, int, int); 176 177 178 #define RADEON_DEBUG 179 #ifdef RADEON_DEBUG 180 int radeon_debug = 1; 181 #define DPRINTF(x) \ 182 if (radeon_debug) printf x 183 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 184 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 185 #else 186 #define DPRINTF(x) 187 #define PRINTREG(r) 188 #define PRINTPLL(r) 189 #endif 190 191 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 192 193 #ifndef RADEON_DEFAULT_MODE 194 /* any reasonably modern display should handle this */ 195 #define RADEON_DEFAULT_MODE "1024x768x60" 196 //#define RADEON_DEFAULT_MODE "1280x1024x60" 197 #endif 198 199 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 201 static struct { 202 int size; /* minimum memory size (MB) */ 203 int maxx; /* maximum x dimension */ 204 int maxy; /* maximum y dimension */ 205 int maxbpp; /* maximum bpp */ 206 int maxdisp; /* maximum logical display count */ 207 } radeonfb_limits[] = { 208 { 32, 2048, 1536, 32, 2 }, 209 { 16, 1600, 1200, 32, 2 }, 210 { 8, 1600, 1200, 32, 1 }, 211 { 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct wsscreen_descr radeonfb_stdscreen = { 215 "fb", /* name */ 216 0, 0, /* ncols, nrows */ 217 NULL, /* textops */ 218 8, 16, /* fontwidth, fontheight */ 219 WSSCREEN_WSCOLORS, /* capabilities */ 220 0, /* modecookie */ 221 }; 222 223 struct wsdisplay_accessops radeonfb_accessops = { 224 radeonfb_ioctl, 225 radeonfb_mmap, 226 NULL, /* vcons_alloc_screen */ 227 NULL, /* vcons_free_screen */ 228 NULL, /* vcons_show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static struct { 235 uint16_t devid; 236 uint16_t family; 237 uint16_t flags; 238 } radeonfb_devices[] = 239 { 240 /* R100 family */ 241 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 246 /* RV100 family */ 247 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 252 /* RS100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 256 /* RS200/RS250 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 262 /* R200 family */ 263 /* add more R200 products? , 5148 */ 264 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 270 /* RV200 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 276 /* RV250 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 283 /* RS300 family */ 284 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 289 /* RV280 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 298 /* R300 family */ 299 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 308 /* RV350/RV360 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 322 /* R350/R360 family */ 323 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 332 /* RV380/RV370 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 343 /* R420/R423 family */ 344 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 361 { 0, 0, 0 } 362 }; 363 364 static struct { 365 int divider; 366 int mask; 367 } radeonfb_dividers[] = { 368 { 1, 0 }, 369 { 2, 1 }, 370 { 3, 4 }, 371 { 4, 2 }, 372 { 6, 6 }, 373 { 8, 3 }, 374 { 12, 7 }, 375 { 0, 0 } 376 }; 377 378 /* 379 * This table taken from X11. 380 */ 381 static const struct { 382 int family; 383 struct radeon_tmds_pll plls[4]; 384 } radeonfb_tmds_pll[] = { 385 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RS100, {{0, 0}}}, 388 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 389 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 392 { RADEON_RS300, {{0, 0}}}, 393 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 394 { RADEON_R300, {{-1, 0xb01cb}}}, 395 { RADEON_R350, {{-1, 0xb01cb}}}, 396 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 397 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_R420, {{-1, 0xb01cb}}}, 399 }; 400 401 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 402 403 404 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 405 radeonfb_match, radeonfb_attach, NULL, NULL); 406 407 static int 408 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 409 { 410 struct pci_attach_args *pa = aux; 411 int i; 412 413 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 414 return 0; 415 416 for (i = 0; radeonfb_devices[i].devid; i++) { 417 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 418 return 100; /* high to defeat VGA/VESA */ 419 } 420 421 return 0; 422 } 423 424 static void 425 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 426 { 427 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 428 struct pci_attach_args *pa = aux; 429 const char *mptr; 430 bus_size_t bsz; 431 pcireg_t screg; 432 int i, j; 433 uint32_t v; 434 435 sc->sc_id = pa->pa_id; 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 438 break; 439 } 440 441 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 442 sizeof(sc->sc_devinfo)); 443 444 aprint_naive("\n"); 445 aprint_normal(": %s\n", sc->sc_devinfo); 446 447 KASSERT(radeonfb_devices[i].devid != 0); 448 sc->sc_pt = pa->pa_tag; 449 sc->sc_pc = pa->pa_pc; 450 sc->sc_family = radeonfb_devices[i].family; 451 sc->sc_flags = radeonfb_devices[i].flags; 452 453 /* enable memory and IO access */ 454 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 455 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 456 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 457 458 /* 459 * Some flags are general to entire chip families, and rather 460 * than clutter up the table with them, we go ahead and set 461 * them here. 462 */ 463 switch (sc->sc_family) { 464 case RADEON_RS100: 465 case RADEON_RS200: 466 sc->sc_flags |= RFB_IGP | RFB_RV100; 467 break; 468 469 case RADEON_RV100: 470 case RADEON_RV200: 471 case RADEON_RV250: 472 case RADEON_RV280: 473 sc->sc_flags |= RFB_RV100; 474 break; 475 476 case RADEON_RS300: 477 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 478 break; 479 480 case RADEON_R300: 481 case RADEON_RV350: 482 case RADEON_R350: 483 case RADEON_RV380: 484 case RADEON_R420: 485 /* newer chips */ 486 sc->sc_flags |= RFB_R300; 487 break; 488 489 case RADEON_R100: 490 sc->sc_flags |= RFB_NCRTC2; 491 break; 492 } 493 494 /* 495 * XXX: to support true multihead, this must change. 496 */ 497 sc->sc_ndisplays = 1; 498 499 /* XXX: */ 500 if (!HAS_CRTC2(sc)) { 501 sc->sc_ndisplays = 1; 502 } 503 504 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 505 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 506 &sc->sc_regsz) != 0) { 507 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 508 goto error; 509 } 510 511 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 512 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 513 &sc->sc_iosz) != 0) { 514 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 515 } 516 517 /* scratch register test... */ 518 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 519 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 520 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 521 goto error; 522 } 523 524 PRINTREG(RADEON_BIOS_4_SCRATCH); 525 PRINTREG(RADEON_FP_GEN_CNTL); 526 PRINTREG(RADEON_FP2_GEN_CNTL); 527 PRINTREG(RADEON_TMDS_CNTL); 528 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 529 PRINTREG(RADEON_TMDS_PLL_CNTL); 530 PRINTREG(RADEON_LVDS_GEN_CNTL); 531 PRINTREG(RADEON_FP_HORZ_STRETCH); 532 PRINTREG(RADEON_FP_VERT_STRETCH); 533 534 /* XXX: RV100 specific */ 535 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 536 537 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 538 RADEON_TMDS_TRANSMITTER_PLLEN, 539 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 540 541 radeonfb_i2c_init(sc); 542 543 radeonfb_loadbios(sc, pa); 544 545 #ifdef RADEON_BIOS_INIT 546 if (radeonfb_bios_init(sc)) { 547 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 548 goto error; 549 } 550 #endif 551 552 if (radeonfb_getclocks(sc)) { 553 aprint_error("%s: Unable to get reference clocks from BIOS\n", 554 XNAME(sc)); 555 goto error; 556 } 557 558 if (radeonfb_gettmds(sc)) { 559 aprint_error("%s: Unable to identify TMDS PLL settings\n", 560 XNAME(sc)); 561 goto error; 562 } 563 564 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 565 "minpll = %d, maxpll = %d\n", XNAME(sc), 566 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 567 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 568 569 radeonfb_getconnectors(sc); 570 571 radeonfb_set_fbloc(sc); 572 573 for (i = 0; radeonfb_limits[i].size; i++) { 574 if (sc->sc_memsz >= radeonfb_limits[i].size) { 575 sc->sc_maxx = radeonfb_limits[i].maxx; 576 sc->sc_maxy = radeonfb_limits[i].maxy; 577 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 578 /* framebuffer offset, start at a 4K page */ 579 sc->sc_fboffset = sc->sc_memsz / 580 radeonfb_limits[i].maxdisp; 581 /* 582 * we use the fbsize to figure out where we can store 583 * things like cursor data. 584 */ 585 sc->sc_fbsize = 586 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 587 RADEON_STRIDEALIGN) * sc->sc_maxy, 588 4096); 589 break; 590 } 591 } 592 593 594 radeonfb_init_misc(sc); 595 radeonfb_init_palette(sc, 0); 596 if (HAS_CRTC2(sc)) 597 radeonfb_init_palette(sc, 1); 598 599 /* program the DAC wirings */ 600 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 601 switch (sc->sc_ports[i].rp_dac_type) { 602 case RADEON_DAC_PRIMARY: 603 PATCH32(sc, RADEON_DAC_CNTL2, 604 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 605 ~RADEON_DAC2_DAC_CLK_SEL); 606 break; 607 case RADEON_DAC_TVDAC: 608 /* we always use the TVDAC to drive a secondary analog 609 * CRT for now. if we ever support TV-out this will 610 * have to change. 611 */ 612 SET32(sc, RADEON_DAC_CNTL2, 613 RADEON_DAC2_DAC2_CLK_SEL); 614 PATCH32(sc, RADEON_DISP_HW_DEBUG, 615 i ? 0 : RADEON_CRT2_DISP1_SEL, 616 ~RADEON_CRT2_DISP1_SEL); 617 break; 618 } 619 } 620 PRINTREG(RADEON_DAC_CNTL2); 621 PRINTREG(RADEON_DISP_HW_DEBUG); 622 623 /* other DAC programming */ 624 v = GET32(sc, RADEON_DAC_CNTL); 625 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 626 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 627 PUT32(sc, RADEON_DAC_CNTL, v); 628 PRINTREG(RADEON_DAC_CNTL); 629 630 /* XXX: this may need more investigation */ 631 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 632 PRINTREG(RADEON_TV_DAC_CNTL); 633 634 /* enable TMDS */ 635 SET32(sc, RADEON_FP_GEN_CNTL, 636 RADEON_FP_TMDS_EN | 637 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 638 RADEON_FP_CRTC_DONT_SHADOW_HEND); 639 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 640 if (HAS_CRTC2(sc)) 641 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 642 643 /* 644 * we use bus_space_map instead of pci_mapreg, because we don't 645 * need the full aperature space. no point in wasting virtual 646 * address space we don't intend to use, right? 647 */ 648 if ((sc->sc_memsz < (4096 * 1024)) || 649 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 650 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 651 (bsz < sc->sc_memsz)) { 652 sc->sc_memsz = 0; 653 aprint_error("%s: Bad frame buffer configuration\n", 654 XNAME(sc)); 655 goto error; 656 } 657 658 /* 64 MB should be enough -- more just wastes map entries */ 659 if (sc->sc_memsz > (64 << 20)) 660 sc->sc_memsz = (64 << 20); 661 662 sc->sc_memt = pa->pa_memt; 663 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 664 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 665 sc->sc_memsz = 0; 666 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 667 goto error; 668 } 669 670 aprint_normal("%s: %d MB aperture at 0x%08x, " 671 "%d KB registers at 0x%08x\n", XNAME(sc), 672 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 673 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 674 675 /* setup default video mode from devprop (allows PROM override) */ 676 sc->sc_defaultmode = radeonfb_default_mode; 677 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 678 "videomode", &mptr)) { 679 680 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 681 sc->sc_defaultmode = sc->sc_modebuf; 682 } 683 684 /* initialize some basic display parameters */ 685 for (i = 0; i < sc->sc_ndisplays; i++) { 686 struct radeonfb_display *dp = &sc->sc_displays[i]; 687 struct rasops_info *ri; 688 long defattr; 689 struct wsemuldisplaydev_attach_args aa; 690 691 /* 692 * Figure out how many "displays" (desktops) we are going to 693 * support. If more than one, then each CRTC gets its own 694 * programming. 695 * 696 * XXX: this code needs to change to support mergedfb. 697 * XXX: would be nice to allow this to be overridden 698 */ 699 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 700 DPRINTF(("dual crtcs!\n")); 701 dp->rd_ncrtcs = 2; 702 dp->rd_crtcs[0].rc_number = 0; 703 dp->rd_crtcs[1].rc_number = 1; 704 } else { 705 dp->rd_ncrtcs = 1; 706 dp->rd_crtcs[0].rc_number = i; 707 } 708 709 /* set up port pointer */ 710 for (j = 0; j < dp->rd_ncrtcs; j++) { 711 dp->rd_crtcs[j].rc_port = 712 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 713 } 714 715 dp->rd_softc = sc; 716 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 717 dp->rd_bg = WS_DEFAULT_BG; 718 #if 0 719 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 720 #else 721 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 722 #endif 723 /* for text mode, we pick a resolution that won't 724 * require panning */ 725 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 726 727 aprint_normal("%s: display %d: " 728 "virtual resolution %dx%d at %d bpp\n", 729 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 730 731 /* now select the *video mode* that we will use */ 732 for (j = 0; j < dp->rd_ncrtcs; j++) { 733 const struct videomode *vmp; 734 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 735 dp->rd_virtx, dp->rd_virty); 736 dp->rd_crtcs[j].rc_videomode = *vmp; 737 printf("%s: port %d: physical %dx%d %dHz\n", 738 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 739 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 740 vmp->htotal), vmp->vtotal)); 741 } 742 743 /* N.B.: radeon wants 64-byte aligned stride */ 744 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 745 //dp->rd_stride = sc->sc_maxx * sc->sc_maxbpp / 8; 746 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 747 748 dp->rd_offset = sc->sc_fboffset * i; 749 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 750 sc->sc_memh) + dp->rd_offset; 751 dp->rd_curoff = sc->sc_fbsize; 752 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 753 754 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 755 756 switch (dp->rd_bpp) { 757 case 8: 758 dp->rd_format = 2; 759 break; 760 case 32: 761 dp->rd_format = 6; 762 break; 763 default: 764 aprint_error("%s: bad depth %d\n", XNAME(sc), 765 dp->rd_bpp); 766 goto error; 767 } 768 769 printf("init engine\n"); 770 /* XXX: this seems suspicious - per display engine 771 initialization? */ 772 radeonfb_engine_init(dp); 773 774 /* copy the template into place */ 775 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 776 dp->rd_wsscreens = dp->rd_wsscreens_storage; 777 778 /* and make up the list */ 779 dp->rd_wsscreenlist.nscreens = 1; 780 dp->rd_wsscreenlist.screens = 781 (const struct wsscreen_descr **)&dp->rd_wsscreens; 782 783 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 784 &radeonfb_accessops); 785 786 dp->rd_vd.init_screen = radeonfb_init_screen; 787 788 dp->rd_console = 1; 789 790 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 791 792 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 793 dp->rd_console, &defattr); 794 795 ri = &dp->rd_vscreen.scr_ri; 796 dp->rd_wsscreens->textops = &ri->ri_ops; 797 dp->rd_wsscreens->capabilities = ri->ri_caps; 798 dp->rd_wsscreens->nrows = ri->ri_rows; 799 dp->rd_wsscreens->ncols = ri->ri_cols; 800 801 #ifdef SPLASHSCREEN 802 dp->rd_splash.si_depth = ri->ri_depth; 803 dp->rd_splash.si_bits = ri->ri_bits; 804 dp->rd_splash.si_hwbits = ri->ri_hwbits; 805 dp->rd_splash.si_width = ri->ri_width; 806 dp->rd_splash.si_height = ri->ri_height; 807 dp->rd_splash.si_stride = ri->ri_stride; 808 dp->rd_splash.si_fillrect = NULL; 809 #endif 810 if (dp->rd_console) { 811 812 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 813 defattr); 814 #ifdef SPLASHSCREEN 815 splash_render(&dp->rd_splash, 816 SPLASH_F_CENTER|SPLASH_F_FILL); 817 #endif 818 819 #ifdef SPLASHSCREEN_PROGRESS 820 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 821 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 822 dp->rd_progress.sp_left = (dp->rd_virtx - 823 dp->rd_progress.sp_width) / 2; 824 dp->rd_progress.sp_height = 20; 825 dp->rd_progress.sp_state = -1; 826 dp->rd_progress.sp_si = &dp->rd_splash; 827 splash_progress_init(&dp->rd_progress); 828 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 829 #endif 830 831 } else { 832 833 /* 834 * since we're not the console we can postpone 835 * the rest until someone actually allocates a 836 * screen for us. but we do clear the screen 837 * at least. 838 */ 839 memset(ri->ri_bits, 0, 1024); 840 841 radeonfb_modeswitch(dp); 842 #ifdef SPLASHSCREEN 843 splash_render(&dp->rd_splash, 844 SPLASH_F_CENTER|SPLASH_F_FILL); 845 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 846 #endif 847 } 848 849 aa.console = dp->rd_console; 850 aa.scrdata = &dp->rd_wsscreenlist; 851 aa.accessops = &radeonfb_accessops; 852 aa.accesscookie = &dp->rd_vd; 853 854 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 855 radeonfb_blank(dp, 0); 856 857 /* Initialise delayed lvds operations for backlight. */ 858 callout_init(&dp->rd_bl_lvds_co); 859 callout_setfunc(&dp->rd_bl_lvds_co, 860 radeonfb_lvds_callout, dp); 861 } 862 863 return; 864 865 error: 866 if (sc->sc_biossz) 867 free(sc->sc_bios, M_DEVBUF); 868 869 if (sc->sc_regsz) 870 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 871 872 if (sc->sc_memsz) 873 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 874 } 875 876 int 877 radeonfb_ioctl(void *v, void *vs, 878 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 879 { 880 struct vcons_data *vd; 881 struct radeonfb_display *dp; 882 struct radeonfb_softc *sc; 883 struct wsdisplay_param *param; 884 885 vd = (struct vcons_data *)v; 886 dp = (struct radeonfb_display *)vd->cookie; 887 sc = dp->rd_softc; 888 889 switch (cmd) { 890 case WSDISPLAYIO_GTYPE: 891 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 892 return 0; 893 894 case WSDISPLAYIO_GINFO: 895 if (vd->active != NULL) { 896 struct wsdisplay_fbinfo *fb; 897 fb = (struct wsdisplay_fbinfo *)d; 898 fb->width = dp->rd_virtx; 899 fb->height = dp->rd_virty; 900 fb->depth = dp->rd_bpp; 901 fb->cmsize = 256; 902 return 0; 903 } else 904 return ENODEV; 905 case WSDISPLAYIO_GVIDEO: 906 if (radeonfb_isblank(dp)) 907 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 908 else 909 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 910 return 0; 911 912 case WSDISPLAYIO_SVIDEO: 913 radeonfb_blank(dp, 914 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 915 return 0; 916 917 case WSDISPLAYIO_GETCMAP: 918 #if 0 919 if (dp->rd_bpp == 8) 920 return radeonfb_getcmap(sc, 921 (struct wsdisplay_cmap *)d); 922 #endif 923 return EINVAL; 924 925 case WSDISPLAYIO_PUTCMAP: 926 #if 0 927 if (dp->rd_bpp == 8) 928 return radeonfb_putcmap(sc, 929 (struct wsdisplay_cmap *)d); 930 #endif 931 return EINVAL; 932 933 case WSDISPLAYIO_LINEBYTES: 934 *(unsigned *)d = dp->rd_stride; 935 return 0; 936 937 case WSDISPLAYIO_SMODE: 938 if (*(int *)d != dp->rd_wsmode) { 939 dp->rd_wsmode = *(int *)d; 940 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 941 (dp->rd_vd.active)) { 942 vcons_redraw_screen(dp->rd_vd.active); 943 } 944 } 945 return 0; 946 947 case WSDISPLAYIO_GCURMAX: 948 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 949 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 950 return 0; 951 952 case WSDISPLAYIO_SCURSOR: 953 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 954 955 case WSDISPLAYIO_GCURSOR: 956 return EPASSTHROUGH; 957 958 case WSDISPLAYIO_GCURPOS: 959 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 960 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 961 return 0; 962 963 case WSDISPLAYIO_SCURPOS: 964 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 965 966 case WSDISPLAYIO_SSPLASH: 967 #if defined(SPLASHSCREEN) 968 if (*(int *)d == 1) { 969 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 970 splash_render(&dp->rd_splash, 971 SPLASH_F_CENTER|SPLASH_F_FILL); 972 } else 973 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 974 return 0; 975 #else 976 return ENODEV; 977 #endif 978 case WSDISPLAYIO_SPROGRESS: 979 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 980 dp->rd_progress.sp_force = 1; 981 splash_progress_update(&dp->rd_progress); 982 dp->rd_progress.sp_force = 0; 983 return 0; 984 #else 985 return ENODEV; 986 #endif 987 case WSDISPLAYIO_GETPARAM: 988 param = (struct wsdisplay_param *)d; 989 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 990 param->min = 0; 991 param->max = RADEONFB_BACKLIGHT_MAX; 992 param->curval = radeonfb_get_backlight(dp); 993 return 0; 994 } 995 return EPASSTHROUGH; 996 997 case WSDISPLAYIO_SETPARAM: 998 param = (struct wsdisplay_param *)d; 999 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1000 return radeonfb_set_backlight(dp, param->curval); 1001 } 1002 return EPASSTHROUGH; 1003 1004 default: 1005 return EPASSTHROUGH; 1006 } 1007 } 1008 1009 paddr_t 1010 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1011 { 1012 struct vcons_data *vd; 1013 struct radeonfb_display *dp; 1014 struct radeonfb_softc *sc; 1015 #ifdef RADEONFB_MMAP_BARS 1016 struct lwp *me; 1017 #endif 1018 paddr_t pa; 1019 1020 vd = (struct vcons_data *)v; 1021 dp = (struct radeonfb_display *)vd->cookie; 1022 sc = dp->rd_softc; 1023 1024 /* XXX: note that we don't allow mapping of registers right now */ 1025 /* XXX: this means that the XFree86 radeon driver won't work */ 1026 1027 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1028 pa = bus_space_mmap(sc->sc_memt, 1029 sc->sc_memaddr + dp->rd_offset + offset, 0, 1030 prot, BUS_SPACE_MAP_LINEAR); 1031 return pa; 1032 } 1033 1034 #ifdef RADEONFB_MMAP_BARS 1035 /* 1036 * restrict all other mappings to processes with superuser privileges 1037 * or the kernel itself 1038 */ 1039 me = curlwp; 1040 if (me != NULL) { 1041 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1042 NULL) != 0) { 1043 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1044 return -1; 1045 } 1046 } 1047 1048 if ((offset >= sc->sc_regaddr) && 1049 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1050 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1051 BUS_SPACE_MAP_LINEAR); 1052 } 1053 1054 if ((offset >= sc->sc_memaddr) && 1055 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1056 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1057 BUS_SPACE_MAP_LINEAR); 1058 } 1059 1060 #ifdef macppc 1061 /* allow mapping of IO space */ 1062 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1063 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1064 BUS_SPACE_MAP_LINEAR); 1065 return pa; 1066 } 1067 #endif /* macppc */ 1068 1069 #endif /* RADEONFB_MMAP_BARS */ 1070 1071 return -1; 1072 } 1073 1074 static void 1075 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1076 { 1077 bus_space_tag_t romt; 1078 bus_space_handle_t romh, biosh; 1079 bus_size_t romsz; 1080 bus_addr_t ptr; 1081 1082 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1083 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1084 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1085 return; 1086 } 1087 1088 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1089 &sc->sc_biossz); 1090 if (sc->sc_biossz == 0) { 1091 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1092 return; 1093 } 1094 1095 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1096 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1097 1098 /* unmap the PCI expansion rom */ 1099 bus_space_unmap(romt, romh, romsz); 1100 1101 /* turn off rom decoder now */ 1102 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1103 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1104 ~PCI_MAPREG_ROM_ENABLE); 1105 1106 ptr = GETBIOS16(sc, 0x48); 1107 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1108 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1109 sc->sc_flags |= RFB_ATOM; 1110 } 1111 1112 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1113 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1114 } 1115 1116 1117 uint32_t 1118 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1119 { 1120 1121 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1122 } 1123 1124 void 1125 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1126 { 1127 1128 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1129 } 1130 1131 void 1132 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1133 uint32_t andmask, uint32_t ormask) 1134 { 1135 int s; 1136 uint32_t val; 1137 1138 s = splhigh(); 1139 val = radeonfb_get32(sc, reg); 1140 val = (val & andmask) | ormask; 1141 radeonfb_put32(sc, reg, val); 1142 splx(s); 1143 } 1144 1145 uint32_t 1146 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1147 { 1148 int s; 1149 uint32_t val; 1150 1151 s = splhigh(); 1152 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1153 val = radeonfb_get32(sc, RADEON_MM_DATA); 1154 splx(s); 1155 1156 return (val); 1157 } 1158 1159 void 1160 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1161 { 1162 int s; 1163 1164 s = splhigh(); 1165 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1166 radeonfb_put32(sc, RADEON_MM_DATA, val); 1167 splx(s); 1168 } 1169 1170 void 1171 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1172 uint32_t andmask, uint32_t ormask) 1173 { 1174 int s; 1175 uint32_t val; 1176 1177 s = splhigh(); 1178 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1179 val = radeonfb_get32(sc, RADEON_MM_DATA); 1180 val = (val & andmask) | ormask; 1181 radeonfb_put32(sc, RADEON_MM_DATA, val); 1182 splx(s); 1183 } 1184 1185 uint32_t 1186 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1187 { 1188 int s; 1189 uint32_t val; 1190 1191 s = splhigh(); 1192 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1193 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1194 if (HAS_R300CG(sc)) 1195 radeonfb_r300cg_workaround(sc); 1196 splx(s); 1197 1198 return (val); 1199 } 1200 1201 void 1202 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1203 { 1204 int s; 1205 1206 s = splhigh(); 1207 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1208 RADEON_PLL_WR_EN); 1209 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1210 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1211 splx(s); 1212 } 1213 1214 void 1215 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1216 uint32_t andmask, uint32_t ormask) 1217 { 1218 int s; 1219 uint32_t val; 1220 1221 s = splhigh(); 1222 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1223 RADEON_PLL_WR_EN); 1224 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1225 val = (val & andmask) | ormask; 1226 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1227 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1228 splx(s); 1229 } 1230 1231 int 1232 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1233 { 1234 uint32_t saved; 1235 1236 saved = GET32(sc, reg); 1237 PUT32(sc, reg, v); 1238 if (GET32(sc, reg) != v) { 1239 return -1; 1240 } 1241 PUT32(sc, reg, saved); 1242 return 0; 1243 } 1244 1245 uintmax_t 1246 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1247 uintmax_t defval) 1248 { 1249 prop_number_t pn; 1250 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1251 if (pn == NULL) { 1252 return defval; 1253 } 1254 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1255 return (prop_number_integer_value(pn)); 1256 } 1257 1258 int 1259 radeonfb_getclocks(struct radeonfb_softc *sc) 1260 { 1261 bus_addr_t ptr; 1262 int refclk = 0; 1263 int refdiv = 0; 1264 int minpll = 0; 1265 int maxpll = 0; 1266 1267 /* load initial property values if port/board provides them */ 1268 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1269 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1270 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1271 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1272 1273 if (refclk && refdiv && minpll && maxpll) 1274 goto dontprobe; 1275 1276 if (!sc->sc_biossz) { 1277 /* no BIOS */ 1278 aprint_verbose("%s: No video BIOS, using default clocks\n", 1279 XNAME(sc)); 1280 if (IS_IGP(sc)) 1281 refclk = refclk ? refclk : 1432; 1282 else 1283 refclk = refclk ? refclk : 2700; 1284 refdiv = refdiv ? refdiv : 12; 1285 minpll = minpll ? minpll : 12500; 1286 maxpll = maxpll ? maxpll : 35000; 1287 } else if (IS_ATOM(sc)) { 1288 /* ATOM BIOS */ 1289 ptr = GETBIOS16(sc, 0x48); 1290 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1291 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1292 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1293 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1294 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1295 /* 1296 * ATOM BIOS doesn't supply a reference divider, so we 1297 * have to probe for it. 1298 */ 1299 if (refdiv < 2) 1300 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1301 RADEON_PPLL_REF_DIV_MASK; 1302 /* 1303 * if probe is zero, just assume one that should work 1304 * for most parts 1305 */ 1306 if (refdiv < 2) 1307 refdiv = 12; 1308 1309 } else { 1310 /* Legacy BIOS */ 1311 ptr = GETBIOS16(sc, 0x48); 1312 ptr = GETBIOS16(sc, ptr + 0x30); 1313 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1314 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1315 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1316 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1317 } 1318 1319 1320 dontprobe: 1321 sc->sc_refclk = refclk * 10; 1322 sc->sc_refdiv = refdiv; 1323 sc->sc_minpll = minpll * 10; 1324 sc->sc_maxpll = maxpll * 10; 1325 return 0; 1326 } 1327 1328 int 1329 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1330 uint32_t *postdivbit, uint32_t *feedbackdiv) 1331 { 1332 int i; 1333 uint32_t outfreq; 1334 int div; 1335 1336 DPRINTF(("dot clock: %u\n", dotclock)); 1337 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1338 outfreq = div * dotclock; 1339 if ((outfreq >= sc->sc_minpll) && 1340 (outfreq <= sc->sc_maxpll)) { 1341 DPRINTF(("outfreq: %u\n", outfreq)); 1342 *postdivbit = 1343 ((uint32_t)radeonfb_dividers[i].mask << 16); 1344 DPRINTF(("post divider: %d (mask %x)\n", div, 1345 *postdivbit)); 1346 break; 1347 } 1348 } 1349 1350 if (div == 0) 1351 return 1; 1352 1353 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1354 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1355 return 0; 1356 } 1357 1358 #if 0 1359 #ifdef RADEON_DEBUG 1360 static void 1361 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1362 { 1363 char asc[17]; 1364 unsigned ptr = (unsigned)buffer; 1365 char *start = (char *)(ptr & ~0xf); 1366 char *end = (char *)(ptr + size); 1367 1368 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1369 1370 if (pfx == NULL) { 1371 pfx = ""; 1372 } 1373 1374 while (start < end) { 1375 unsigned offset = (unsigned)start & 0xf; 1376 if (offset == 0) { 1377 printf("%s%x: ", pfx, (unsigned)start); 1378 } 1379 if (((unsigned)start < ptr) || 1380 ((unsigned)start >= (ptr + size))) { 1381 printf(" "); 1382 asc[offset] = ' '; 1383 } else { 1384 printf("%02x", *(unsigned char *)start); 1385 if ((*start >= ' ') && (*start <= '~')) { 1386 asc[offset] = *start; 1387 } else { 1388 asc[offset] = '.'; 1389 } 1390 } 1391 asc[offset + 1] = 0; 1392 if (offset % 2) { 1393 printf(" "); 1394 } 1395 if (offset == 15) { 1396 printf(" %s\n", asc); 1397 } 1398 start++; 1399 } 1400 } 1401 #endif 1402 #endif 1403 1404 int 1405 radeonfb_getconnectors(struct radeonfb_softc *sc) 1406 { 1407 int i; 1408 int found = 0; 1409 1410 for (i = 0; i < 2; i++) { 1411 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1412 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1413 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1414 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1415 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1416 } 1417 1418 /* 1419 * This logic is borrowed from Xorg's radeon driver. 1420 */ 1421 if (!sc->sc_biossz) 1422 goto nobios; 1423 1424 if (IS_ATOM(sc)) { 1425 /* not done yet */ 1426 } else { 1427 uint16_t ptr; 1428 int port = 0; 1429 1430 ptr = GETBIOS16(sc, 0x48); 1431 ptr = GETBIOS16(sc, ptr + 0x50); 1432 for (i = 1; i < 4; i++) { 1433 uint16_t entry; 1434 uint8_t conn, ddc, dac, tmds; 1435 1436 /* 1437 * Parse the connector table. From reading the code, 1438 * it appears to made up of 16-bit entries for each 1439 * connector. The 16-bits are defined as: 1440 * 1441 * bits 12-15 - connector type (0 == end of table) 1442 * bits 8-11 - DDC type 1443 * bits 5-7 - ??? 1444 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1445 * bits 1-3 - ??? 1446 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1447 */ 1448 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1449 break; 1450 entry = GETBIOS16(sc, ptr + i * 2); 1451 1452 conn = (entry >> 12) & 0xf; 1453 ddc = (entry >> 8) & 0xf; 1454 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1455 RADEON_DAC_PRIMARY; 1456 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1457 RADEON_TMDS_INT; 1458 1459 if (conn == RADEON_CONN_NONE) 1460 continue; /* no connector */ 1461 1462 if ((found > 0) && 1463 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1464 /* duplicate entry for same connector */ 1465 continue; 1466 } 1467 1468 /* internal DDC_DVI port gets priority */ 1469 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1470 port = 0; 1471 else 1472 port = 1; 1473 1474 sc->sc_ports[port].rp_ddc_type = 1475 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1476 sc->sc_ports[port].rp_dac_type = dac; 1477 sc->sc_ports[port].rp_conn_type = 1478 min(conn, RADEON_CONN_UNSUPPORTED) ; 1479 1480 sc->sc_ports[port].rp_tmds_type = tmds; 1481 1482 if ((conn != RADEON_CONN_DVI_I) && 1483 (conn != RADEON_CONN_DVI_D) && 1484 (tmds == RADEON_TMDS_INT)) 1485 sc->sc_ports[port].rp_tmds_type = 1486 RADEON_TMDS_UNKNOWN; 1487 1488 found += (port + 1); 1489 } 1490 } 1491 1492 nobios: 1493 if (!found) { 1494 DPRINTF(("No connector info in BIOS!\n")); 1495 /* default, port 0 = internal TMDS, port 1 = CRT */ 1496 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1497 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1498 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1499 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1500 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1501 1502 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1503 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1504 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1505 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1506 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1507 } 1508 1509 /* 1510 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1511 * these chips should use TVDAC for the VGA port. 1512 */ 1513 if (HAS_SDAC(sc)) { 1514 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1515 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1516 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1517 } else { 1518 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1519 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1520 } 1521 } else if (!HAS_CRTC2(sc)) { 1522 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1523 } 1524 1525 for (i = 0; i < 2; i++) { 1526 char edid[128]; 1527 uint8_t ddc; 1528 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1529 1530 DPRINTF(("Port #%d:\n", i)); 1531 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1532 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1533 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1534 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1535 1536 sc->sc_ports[i].rp_edid_valid = 0; 1537 ddc = sc->sc_ports[i].rp_ddc_type; 1538 if (ddc != RADEON_DDC_NONE) { 1539 if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1540 (edid_parse(edid, eip) == 0)) { 1541 sc->sc_ports[i].rp_edid_valid = 1; 1542 edid_print(eip); 1543 } 1544 } 1545 } 1546 1547 return found; 1548 } 1549 1550 int 1551 radeonfb_gettmds(struct radeonfb_softc *sc) 1552 { 1553 int i; 1554 1555 if (!sc->sc_biossz) { 1556 goto nobios; 1557 } 1558 1559 if (IS_ATOM(sc)) { 1560 /* XXX: not done yet */ 1561 } else { 1562 uint16_t ptr; 1563 int n; 1564 1565 ptr = GETBIOS16(sc, 0x48); 1566 ptr = GETBIOS16(sc, ptr + 0x34); 1567 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1568 if (GETBIOS8(sc, ptr) == 3) { 1569 /* revision three table */ 1570 n = GETBIOS8(sc, ptr + 5) + 1; 1571 n = min(n, 4); 1572 1573 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1574 for (i = 0; i < n; i++) { 1575 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1576 ptr + i * 10 + 8); 1577 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1578 ptr + i * 10 + 0x10); 1579 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1580 sc->sc_tmds_pll[i].rtp_freq, 1581 sc->sc_tmds_pll[i].rtp_pll)); 1582 } 1583 return 0; 1584 } 1585 } 1586 1587 nobios: 1588 DPRINTF(("no suitable DFP table present\n")); 1589 for (i = 0; 1590 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1591 i++) { 1592 int j; 1593 1594 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1595 continue; 1596 1597 for (j = 0; j < 4; j++) { 1598 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1599 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1600 sc->sc_tmds_pll[j].rtp_freq, 1601 sc->sc_tmds_pll[j].rtp_pll)); 1602 } 1603 return 0; 1604 } 1605 1606 return -1; 1607 } 1608 1609 const struct videomode * 1610 radeonfb_modelookup(const char *name) 1611 { 1612 int i; 1613 1614 for (i = 0; i < videomode_count; i++) 1615 if (!strcmp(name, videomode_list[i].name)) 1616 return &videomode_list[i]; 1617 1618 return NULL; 1619 } 1620 1621 void 1622 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1623 { 1624 if (crtc) { 1625 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1626 RADEON_P2PLL_ATOMIC_UPDATE_R); 1627 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1628 } else { 1629 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1630 RADEON_PPLL_ATOMIC_UPDATE_R); 1631 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1632 } 1633 } 1634 1635 void 1636 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1637 { 1638 int i; 1639 1640 for (i = 10000; i; i--) { 1641 if (crtc) { 1642 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1643 RADEON_P2PLL_ATOMIC_UPDATE_R) 1644 break; 1645 } else { 1646 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1647 RADEON_PPLL_ATOMIC_UPDATE_R) 1648 break; 1649 } 1650 } 1651 } 1652 1653 void 1654 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1655 { 1656 uint32_t pbit = 0; 1657 uint32_t feed = 0; 1658 uint32_t data; 1659 #if 1 1660 int i; 1661 #endif 1662 1663 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1664 1665 if (crtc == 0) { 1666 1667 /* XXXX: mobility workaround missing */ 1668 /* XXXX: R300 stuff missing */ 1669 1670 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1671 RADEON_VCLK_SRC_SEL_CPUCLK, 1672 ~RADEON_VCLK_SRC_SEL_MASK); 1673 1674 /* put vclk into reset, use atomic updates */ 1675 SETPLL(sc, RADEON_PPLL_CNTL, 1676 RADEON_PPLL_REFCLK_SEL | 1677 RADEON_PPLL_FBCLK_SEL | 1678 RADEON_PPLL_RESET | 1679 RADEON_PPLL_ATOMIC_UPDATE_EN | 1680 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1681 1682 /* select clock 3 */ 1683 #if 0 1684 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1685 ~RADEON_PLL_DIV_SEL); 1686 #else 1687 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1688 ~RADEON_PLL_DIV_SEL); 1689 #endif 1690 1691 /* XXX: R300 family -- program divider differently? */ 1692 1693 /* program reference divider */ 1694 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1695 ~RADEON_PPLL_REF_DIV_MASK); 1696 PRINTPLL(RADEON_PPLL_REF_DIV); 1697 1698 #if 0 1699 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1700 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1701 RADEON_PPLL_POST3_DIV_MASK); 1702 data |= pbit; 1703 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1704 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1705 #else 1706 for (i = 0; i < 4; i++) { 1707 } 1708 #endif 1709 1710 /* use the atomic update */ 1711 radeonfb_pllwriteupdate(sc, crtc); 1712 1713 /* and wait for it to complete */ 1714 radeonfb_pllwaitatomicread(sc, crtc); 1715 1716 /* program HTOTAL (why?) */ 1717 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1718 1719 /* drop reset */ 1720 CLRPLL(sc, RADEON_PPLL_CNTL, 1721 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1722 RADEON_PPLL_ATOMIC_UPDATE_EN | 1723 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1724 1725 PRINTPLL(RADEON_PPLL_CNTL); 1726 1727 /* give clock time to lock */ 1728 delay(50000); 1729 1730 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1731 RADEON_VCLK_SRC_SEL_PPLLCLK, 1732 ~RADEON_VCLK_SRC_SEL_MASK); 1733 1734 } else { 1735 1736 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1737 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1738 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1739 1740 /* put vclk into reset, use atomic updates */ 1741 SETPLL(sc, RADEON_P2PLL_CNTL, 1742 RADEON_P2PLL_RESET | 1743 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1744 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1745 1746 /* XXX: R300 family -- program divider differently? */ 1747 1748 /* program reference divider */ 1749 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1750 ~RADEON_P2PLL_REF_DIV_MASK); 1751 1752 /* program feedback and post dividers */ 1753 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1754 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1755 RADEON_P2PLL_POST0_DIV_MASK); 1756 data |= pbit; 1757 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1758 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1759 1760 /* use the atomic update */ 1761 radeonfb_pllwriteupdate(sc, crtc); 1762 1763 /* and wait for it to complete */ 1764 radeonfb_pllwaitatomicread(sc, crtc); 1765 1766 /* program HTOTAL (why?) */ 1767 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1768 1769 /* drop reset */ 1770 CLRPLL(sc, RADEON_P2PLL_CNTL, 1771 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1772 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1773 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1774 1775 /* allow time for clock to lock */ 1776 delay(50000); 1777 1778 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1779 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1780 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1781 } 1782 PRINTREG(RADEON_CRTC_MORE_CNTL); 1783 } 1784 1785 void 1786 radeonfb_modeswitch(struct radeonfb_display *dp) 1787 { 1788 struct radeonfb_softc *sc = dp->rd_softc; 1789 int i; 1790 1791 /* blank the display while we switch modes */ 1792 //radeonfb_blank(dp, 1); 1793 1794 #if 0 1795 SET32(sc, RADEON_CRTC_EXT_CNTL, 1796 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1797 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1798 #endif 1799 1800 /* these registers might get in the way... */ 1801 PUT32(sc, RADEON_OVR_CLR, 0); 1802 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1803 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1804 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1805 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1806 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1807 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1808 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1809 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1810 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1811 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1812 1813 for (i = 0; i < dp->rd_ncrtcs; i++) 1814 radeonfb_setcrtc(dp, i); 1815 1816 /* activate the display */ 1817 //radeonfb_blank(dp, 0); 1818 } 1819 1820 void 1821 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1822 { 1823 int crtc; 1824 struct videomode *mode; 1825 struct radeonfb_softc *sc; 1826 struct radeonfb_crtc *cp; 1827 uint32_t v; 1828 uint32_t gencntl; 1829 uint32_t htotaldisp; 1830 uint32_t hsyncstrt; 1831 uint32_t vtotaldisp; 1832 uint32_t vsyncstrt; 1833 uint32_t fphsyncstrt; 1834 uint32_t fpvsyncstrt; 1835 uint32_t fphtotaldisp; 1836 uint32_t fpvtotaldisp; 1837 uint32_t pitch; 1838 1839 sc = dp->rd_softc; 1840 cp = &dp->rd_crtcs[index]; 1841 crtc = cp->rc_number; 1842 mode = &cp->rc_videomode; 1843 1844 #if 1 1845 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1846 (dp->rd_bpp * 8)); 1847 #else 1848 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1849 (sc->sc_maxbpp * 8)); 1850 #endif 1851 //pitch = pitch | (pitch << 16); 1852 1853 switch (crtc) { 1854 case 0: 1855 gencntl = RADEON_CRTC_GEN_CNTL; 1856 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1857 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1858 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1859 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1860 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1861 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1862 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1863 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1864 break; 1865 case 1: 1866 gencntl = RADEON_CRTC2_GEN_CNTL; 1867 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1868 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1869 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1870 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1871 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1872 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1873 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1874 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1875 break; 1876 default: 1877 panic("Bad CRTC!"); 1878 break; 1879 } 1880 1881 /* 1882 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1883 */ 1884 /* only bother with 32bpp and 8bpp */ 1885 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1886 1887 if (crtc == 1) { 1888 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1889 } else { 1890 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1891 } 1892 1893 if (mode->flags & VID_DBLSCAN) 1894 v |= RADEON_CRTC2_DBL_SCAN_EN; 1895 1896 if (mode->flags & VID_INTERLACE) 1897 v |= RADEON_CRTC2_INTERLACE_EN; 1898 1899 if (mode->flags & VID_CSYNC) { 1900 v |= RADEON_CRTC2_CSYNC_EN; 1901 if (crtc == 1) 1902 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1903 } 1904 1905 PUT32(sc, gencntl, v); 1906 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1907 1908 /* 1909 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1910 */ 1911 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1912 if (crtc == 0) { 1913 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1914 RADEON_CRTC_DISPLAY_DIS); 1915 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1916 if (mode->flags & VID_CSYNC) 1917 v |= RADEON_CRTC_VSYNC_TRISTAT; 1918 } 1919 /* unconditional turn on CRT, in case first CRTC is DFP */ 1920 v |= RADEON_CRTC_CRT_ON; 1921 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1922 PRINTREG(RADEON_CRTC_EXT_CNTL); 1923 1924 /* 1925 * H_TOTAL_DISP 1926 */ 1927 v = ((mode->hdisplay / 8) - 1) << 16; 1928 v |= (mode->htotal / 8) - 1; 1929 PUT32(sc, htotaldisp, v); 1930 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1931 PUT32(sc, fphtotaldisp, v); 1932 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1933 1934 /* 1935 * H_SYNC_STRT_WID 1936 */ 1937 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1938 v |= mode->hsync_start; 1939 if (mode->flags & VID_NHSYNC) 1940 v |= RADEON_CRTC_H_SYNC_POL; 1941 PUT32(sc, hsyncstrt, v); 1942 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1943 PUT32(sc, fphsyncstrt, v); 1944 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1945 1946 /* 1947 * V_TOTAL_DISP 1948 */ 1949 v = ((mode->vdisplay - 1) << 16); 1950 v |= (mode->vtotal - 1); 1951 PUT32(sc, vtotaldisp, v); 1952 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1953 PUT32(sc, fpvtotaldisp, v); 1954 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1955 1956 /* 1957 * V_SYNC_STRT_WID 1958 */ 1959 v = ((mode->vsync_end - mode->vsync_start) << 16); 1960 v |= (mode->vsync_start - 1); 1961 if (mode->flags & VID_NVSYNC) 1962 v |= RADEON_CRTC_V_SYNC_POL; 1963 PUT32(sc, vsyncstrt, v); 1964 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1965 PUT32(sc, fpvsyncstrt, v); 1966 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1967 1968 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1969 1970 switch (crtc) { 1971 case 0: 1972 PUT32(sc, RADEON_CRTC_OFFSET, 0); 1973 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1974 PUT32(sc, RADEON_CRTC_PITCH, pitch); 1975 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1976 1977 CLR32(sc, RADEON_CRTC_EXT_CNTL, 1978 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1979 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1980 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1981 PRINTREG(RADEON_CRTC_EXT_CNTL); 1982 PRINTREG(RADEON_CRTC_GEN_CNTL); 1983 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1984 break; 1985 1986 case 1: 1987 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 1988 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 1989 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 1990 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 1991 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 1992 RADEON_CRTC2_VSYNC_DIS | 1993 RADEON_CRTC2_HSYNC_DIS | 1994 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 1995 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1996 break; 1997 } 1998 } 1999 2000 int 2001 radeonfb_isblank(struct radeonfb_display *dp) 2002 { 2003 uint32_t reg, mask; 2004 2005 if (dp->rd_crtcs[0].rc_number) { 2006 reg = RADEON_CRTC2_GEN_CNTL; 2007 mask = RADEON_CRTC2_DISP_DIS; 2008 } else { 2009 reg = RADEON_CRTC_EXT_CNTL; 2010 mask = RADEON_CRTC_DISPLAY_DIS; 2011 } 2012 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2013 } 2014 2015 void 2016 radeonfb_blank(struct radeonfb_display *dp, int blank) 2017 { 2018 struct radeonfb_softc *sc = dp->rd_softc; 2019 uint32_t reg, mask; 2020 uint32_t fpreg, fpval; 2021 int i; 2022 2023 for (i = 0; i < dp->rd_ncrtcs; i++) { 2024 2025 if (dp->rd_crtcs[i].rc_number) { 2026 reg = RADEON_CRTC2_GEN_CNTL; 2027 mask = RADEON_CRTC2_DISP_DIS; 2028 fpreg = RADEON_FP2_GEN_CNTL; 2029 fpval = RADEON_FP2_ON; 2030 } else { 2031 reg = RADEON_CRTC_EXT_CNTL; 2032 mask = RADEON_CRTC_DISPLAY_DIS; 2033 fpreg = RADEON_FP_GEN_CNTL; 2034 fpval = RADEON_FP_FPON; 2035 } 2036 2037 if (blank) { 2038 SET32(sc, reg, mask); 2039 CLR32(sc, fpreg, fpval); 2040 } else { 2041 CLR32(sc, reg, mask); 2042 SET32(sc, fpreg, fpval); 2043 } 2044 } 2045 PRINTREG(RADEON_FP_GEN_CNTL); 2046 PRINTREG(RADEON_FP2_GEN_CNTL); 2047 } 2048 2049 void 2050 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2051 long *defattr) 2052 { 2053 struct radeonfb_display *dp = cookie; 2054 struct rasops_info *ri = &scr->scr_ri; 2055 2056 /* initialize font subsystem */ 2057 wsfont_init(); 2058 2059 DPRINTF(("init screen called, existing %d\n", existing)); 2060 2061 ri->ri_depth = dp->rd_bpp; 2062 ri->ri_width = dp->rd_virtx; 2063 ri->ri_height = dp->rd_virty; 2064 ri->ri_stride = dp->rd_stride; 2065 ri->ri_flg = RI_CENTER; 2066 ri->ri_bits = (void *)dp->rd_fbptr; 2067 2068 /* XXX: 32 bpp only */ 2069 /* this is rgb in "big-endian order..." */ 2070 ri->ri_rnum = 8; 2071 ri->ri_gnum = 8; 2072 ri->ri_bnum = 8; 2073 ri->ri_rpos = 16; 2074 ri->ri_gpos = 8; 2075 ri->ri_bpos = 0; 2076 2077 if (existing) { 2078 ri->ri_flg |= RI_CLEAR; 2079 2080 /* start a modeswitch now */ 2081 radeonfb_modeswitch(dp); 2082 } 2083 2084 /* 2085 * XXX: font selection should be based on properties, with some 2086 * normal/reasonable default. 2087 */ 2088 ri->ri_caps = WSSCREEN_WSCOLORS; 2089 2090 /* initialize and look for an initial font */ 2091 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2092 2093 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2094 dp->rd_virtx / ri->ri_font->fontwidth); 2095 2096 /* enable acceleration */ 2097 ri->ri_ops.copyrows = radeonfb_copyrows; 2098 ri->ri_ops.copycols = radeonfb_copycols; 2099 ri->ri_ops.eraserows = radeonfb_eraserows; 2100 ri->ri_ops.erasecols = radeonfb_erasecols; 2101 ri->ri_ops.allocattr = radeonfb_allocattr; 2102 ri->ri_ops.putchar = radeonfb_putchar; 2103 ri->ri_ops.cursor = radeonfb_cursor; 2104 } 2105 2106 void 2107 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2108 { 2109 uint32_t gen, ext, gen2 = 0; 2110 uint32_t agploc, aperbase, apersize, mcfbloc; 2111 2112 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2113 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2114 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2115 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2116 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2117 2118 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2119 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2120 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2121 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2122 2123 if (HAS_CRTC2(sc)) { 2124 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2125 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2126 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2127 } 2128 2129 delay(100000); 2130 2131 mcfbloc = (aperbase >> 16) | 2132 ((aperbase + (apersize - 1)) & 0xffff0000); 2133 2134 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2135 sc->sc_memsz = apersize; 2136 2137 if (((agploc & 0xffff) << 16) != 2138 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2139 agploc = mcfbloc & 0xffff0000U; 2140 agploc |= ((agploc + 0x10000) >> 16); 2141 } 2142 2143 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2144 2145 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2146 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2147 2148 DPRINTF(("aperbase = %u\n", aperbase)); 2149 PRINTREG(RADEON_MC_FB_LOCATION); 2150 PRINTREG(RADEON_MC_AGP_LOCATION); 2151 2152 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2153 2154 if (HAS_CRTC2(sc)) 2155 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2156 2157 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2158 2159 #if 0 2160 /* XXX: what is this AGP garbage? :-) */ 2161 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2162 #endif 2163 2164 delay(100000); 2165 2166 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2167 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2168 2169 if (HAS_CRTC2(sc)) 2170 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2171 } 2172 2173 void 2174 radeonfb_init_misc(struct radeonfb_softc *sc) 2175 { 2176 PUT32(sc, RADEON_BUS_CNTL, 2177 RADEON_BUS_MASTER_DIS | 2178 RADEON_BUS_PREFETCH_MODE_ACT | 2179 RADEON_BUS_PCI_READ_RETRY_EN | 2180 RADEON_BUS_PCI_WRT_RETRY_EN | 2181 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2182 RADEON_BUS_MSTR_RD_MULT | 2183 RADEON_BUS_MSTR_RD_LINE | 2184 RADEON_BUS_RD_DISCARD_EN | 2185 RADEON_BUS_MSTR_DISCONNECT_EN | 2186 RADEON_BUS_READ_BURST); 2187 2188 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2189 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2190 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2191 PUT32(sc, RADEON_RBBM_CNTL, 2192 (3 << RADEON_RB_SETTLE_SHIFT) | 2193 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2194 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2195 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2196 2197 /* XXX: figure out what these mean! */ 2198 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2199 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2200 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2201 2202 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2203 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2204 } 2205 2206 /* 2207 * This loads a linear color map for true color. 2208 */ 2209 void 2210 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2211 { 2212 int i; 2213 uint32_t vclk; 2214 2215 #define DAC_WIDTH ((1 << 10) - 1) 2216 #define CLUT_WIDTH ((1 << 8) - 1) 2217 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2218 2219 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2220 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2221 2222 if (crtc) 2223 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2224 else 2225 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2226 2227 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2228 for (i = 0; i <= CLUT_WIDTH; ++i) { 2229 PUT32(sc, RADEON_PALETTE_30_DATA, 2230 (CLUT_COLOR(i) << 10) | 2231 (CLUT_COLOR(i) << 20) | 2232 (CLUT_COLOR(i))); 2233 } 2234 2235 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2236 PRINTREG(RADEON_DAC_CNTL2); 2237 2238 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2239 } 2240 2241 /* 2242 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2243 */ 2244 void 2245 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2246 { 2247 uint32_t tmp, save; 2248 2249 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2250 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2251 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2252 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2253 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2254 } 2255 2256 /* 2257 * Acceleration entry points. 2258 */ 2259 static void 2260 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2261 { 2262 struct rasops_info *ri = cookie; 2263 struct vcons_screen *scr = ri->ri_hw; 2264 struct radeonfb_display *dp = scr->scr_cookie; 2265 uint32_t x, y, w, h; 2266 uint32_t bg, fg; 2267 uint8_t *data; 2268 2269 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2270 return; 2271 2272 if (!CHAR_IN_FONT(c, ri->ri_font)) 2273 return; 2274 2275 w = ri->ri_font->fontwidth; 2276 h = ri->ri_font->fontheight; 2277 2278 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2279 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2280 2281 x = ri->ri_xorigin + col * w; 2282 y = ri->ri_yorigin + row * h; 2283 2284 if (c == 0x20) { 2285 radeonfb_rectfill(dp, x, y, w, h, bg); 2286 } else { 2287 data = (uint8_t *)ri->ri_font->data + 2288 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2289 2290 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2291 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2292 } 2293 } 2294 2295 static void 2296 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2297 { 2298 struct rasops_info *ri = cookie; 2299 struct vcons_screen *scr = ri->ri_hw; 2300 struct radeonfb_display *dp = scr->scr_cookie; 2301 uint32_t x, y, w, h, fg, bg, ul; 2302 2303 /* XXX: check for full emulation mode? */ 2304 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2305 x = ri->ri_xorigin; 2306 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2307 w = ri->ri_emuwidth; 2308 h = ri->ri_font->fontheight * nrows; 2309 2310 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2311 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2312 } 2313 } 2314 2315 static void 2316 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2317 { 2318 struct rasops_info *ri = cookie; 2319 struct vcons_screen *scr = ri->ri_hw; 2320 struct radeonfb_display *dp = scr->scr_cookie; 2321 uint32_t x, ys, yd, w, h; 2322 2323 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2324 x = ri->ri_xorigin; 2325 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2326 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2327 w = ri->ri_emuwidth; 2328 h = ri->ri_font->fontheight * nrows; 2329 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2330 RADEON_ROP3_S, 0xffffffff); 2331 } 2332 } 2333 2334 static void 2335 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2336 { 2337 struct rasops_info *ri = cookie; 2338 struct vcons_screen *scr = ri->ri_hw; 2339 struct radeonfb_display *dp = scr->scr_cookie; 2340 uint32_t xs, xd, y, w, h; 2341 2342 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2343 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2344 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2345 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2346 w = ri->ri_font->fontwidth * ncols; 2347 h = ri->ri_font->fontheight; 2348 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2349 RADEON_ROP3_S, 0xffffffff); 2350 } 2351 } 2352 2353 static void 2354 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2355 long fillattr) 2356 { 2357 struct rasops_info *ri = cookie; 2358 struct vcons_screen *scr = ri->ri_hw; 2359 struct radeonfb_display *dp = scr->scr_cookie; 2360 uint32_t x, y, w, h, fg, bg, ul; 2361 2362 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2363 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2364 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2365 w = ri->ri_font->fontwidth * ncols; 2366 h = ri->ri_font->fontheight; 2367 2368 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2369 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2370 } 2371 } 2372 2373 static void 2374 radeonfb_cursor(void *cookie, int on, int row, int col) 2375 { 2376 struct rasops_info *ri = cookie; 2377 struct vcons_screen *scr = ri->ri_hw; 2378 struct radeonfb_display *dp = scr->scr_cookie; 2379 int x, y, wi, he; 2380 2381 wi = ri->ri_font->fontwidth; 2382 he = ri->ri_font->fontheight; 2383 2384 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2385 x = ri->ri_ccol * wi + ri->ri_xorigin; 2386 y = ri->ri_crow * he + ri->ri_yorigin; 2387 /* first turn off the old cursor */ 2388 if (ri->ri_flg & RI_CURSOR) { 2389 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2390 RADEON_ROP3_Dn, 0xffffffff); 2391 ri->ri_flg &= ~RI_CURSOR; 2392 } 2393 ri->ri_crow = row; 2394 ri->ri_ccol = col; 2395 /* then (possibly) turn on the new one */ 2396 if (on) { 2397 x = ri->ri_ccol * wi + ri->ri_xorigin; 2398 y = ri->ri_crow * he + ri->ri_yorigin; 2399 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2400 RADEON_ROP3_Dn, 0xffffffff); 2401 ri->ri_flg |= RI_CURSOR; 2402 } 2403 } else { 2404 scr->scr_ri.ri_crow = row; 2405 scr->scr_ri.ri_ccol = col; 2406 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2407 } 2408 } 2409 2410 static int 2411 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2412 { 2413 if ((fg == 0) && (bg == 0)) { 2414 fg = WS_DEFAULT_FG; 2415 bg = WS_DEFAULT_BG; 2416 } 2417 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2418 return 0; 2419 } 2420 2421 /* 2422 * Underlying acceleration support. 2423 */ 2424 static void 2425 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2426 int height, uint32_t fg, uint32_t bg) 2427 { 2428 struct radeonfb_softc *sc = dp->rd_softc; 2429 uint32_t gmc; 2430 uint32_t padded_width = (width+7) & 0xfff8; 2431 uint32_t topleft, bottomright; 2432 2433 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2434 2435 if (width != padded_width) { 2436 2437 radeonfb_wait_fifo(sc, 2); 2438 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2439 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2440 ((xd + width) & 0x1fff); 2441 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2442 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2443 } 2444 2445 radeonfb_wait_fifo(sc, 5); 2446 2447 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2448 RADEON_GMC_BRUSH_NONE | 2449 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2450 //RADEON_GMC_BYTE_LSB_TO_MSB | 2451 RADEON_GMC_DST_CLIPPING | 2452 RADEON_ROP3_S | 2453 RADEON_DP_SRC_SOURCE_HOST_DATA | 2454 RADEON_GMC_CLR_CMP_CNTL_DIS | 2455 RADEON_GMC_WR_MSK_DIS | 2456 gmc); 2457 2458 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2459 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2460 2461 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2462 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2463 2464 } 2465 2466 static void 2467 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2468 { 2469 struct radeonfb_softc *sc = dp->rd_softc; 2470 int i; 2471 uint32_t latch = 0; 2472 int shift = 0; 2473 2474 for (i = 0; i < count; i++) { 2475 latch |= (data[i] << shift); 2476 if (shift == 24) { 2477 radeonfb_wait_fifo(sc, 1); 2478 PUT32(sc, RADEON_HOST_DATA0, latch); 2479 latch = 0; 2480 shift = 0; 2481 } else 2482 shift += 8; 2483 } 2484 if (shift != 0) { 2485 radeonfb_wait_fifo(sc, 1); 2486 PUT32(sc, RADEON_HOST_DATA0, latch); 2487 } 2488 radeonfb_unclip(sc); 2489 } 2490 2491 static void 2492 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2493 int width, int height, uint32_t color) 2494 { 2495 struct radeonfb_softc *sc = dp->rd_softc; 2496 uint32_t gmc; 2497 2498 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2499 2500 radeonfb_wait_fifo(sc, 6); 2501 2502 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2503 RADEON_GMC_BRUSH_SOLID_COLOR | 2504 RADEON_GMC_SRC_DATATYPE_COLOR | 2505 RADEON_GMC_CLR_CMP_CNTL_DIS | 2506 RADEON_ROP3_P | gmc); 2507 2508 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2509 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2510 PUT32(sc, RADEON_DP_CNTL, 2511 RADEON_DST_X_LEFT_TO_RIGHT | 2512 RADEON_DST_Y_TOP_TO_BOTTOM); 2513 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2514 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2515 2516 /* 2517 * XXX: we don't wait for the fifo to empty -- that would slow 2518 * things down! The linux radeonfb driver waits, but xfree doesn't 2519 */ 2520 /* XXX: for now we do, to make it safe for direct drawing */ 2521 radeonfb_engine_idle(sc); 2522 } 2523 2524 static void 2525 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2526 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2527 { 2528 struct radeonfb_softc *sc = dp->rd_softc; 2529 uint32_t gmc; 2530 uint32_t dir; 2531 2532 if (dsty < srcy) { 2533 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2534 } else { 2535 srcy += height - 1; 2536 dsty += height - 1; 2537 dir = 0; 2538 } 2539 if (dstx < srcx) { 2540 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2541 } else { 2542 srcx += width - 1; 2543 dstx += width - 1; 2544 } 2545 2546 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2547 2548 radeonfb_wait_fifo(sc, 6); 2549 2550 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2551 //RADEON_GMC_SRC_CLIPPING | 2552 RADEON_GMC_BRUSH_SOLID_COLOR | 2553 RADEON_GMC_SRC_DATATYPE_COLOR | 2554 RADEON_GMC_CLR_CMP_CNTL_DIS | 2555 RADEON_DP_SRC_SOURCE_MEMORY | 2556 rop | gmc); 2557 2558 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2559 PUT32(sc, RADEON_DP_CNTL, dir); 2560 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2561 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2562 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2563 2564 /* 2565 * XXX: we don't wait for the fifo to empty -- that would slow 2566 * things down! The linux radeonfb driver waits, but xfree doesn't 2567 */ 2568 /* XXX: for now we do, to make it safe for direct drawing */ 2569 radeonfb_engine_idle(sc); 2570 } 2571 2572 static void 2573 radeonfb_engine_idle(struct radeonfb_softc *sc) 2574 { 2575 int i; 2576 2577 radeonfb_wait_fifo(sc, 64); 2578 for (i = RADEON_TIMEOUT; i; i--) { 2579 if ((GET32(sc, RADEON_RBBM_STATUS) & 2580 RADEON_RBBM_ACTIVE) == 0) { 2581 radeonfb_engine_flush(sc); 2582 break; 2583 } 2584 } 2585 } 2586 2587 static void 2588 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2589 { 2590 int i; 2591 2592 for (i = RADEON_TIMEOUT; i; i--) { 2593 if ((GET32(sc, RADEON_RBBM_STATUS) & 2594 RADEON_RBBM_FIFOCNT_MASK) >= n) 2595 return; 2596 } 2597 #ifdef DIAGNOSTIC 2598 if (!i) 2599 printf("%s: timed out waiting for fifo (%x)\n", 2600 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2601 #endif 2602 } 2603 2604 static void 2605 radeonfb_engine_flush(struct radeonfb_softc *sc) 2606 { 2607 int i; 2608 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2609 for (i = RADEON_TIMEOUT; i; i--) { 2610 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2611 RADEON_RB2D_DC_BUSY) == 0) 2612 break; 2613 } 2614 #ifdef DIAGNOSTIC 2615 if (!i) 2616 printf("%s: engine flush timed out!\n", XNAME(sc)); 2617 #endif 2618 } 2619 2620 static inline void 2621 radeonfb_unclip(struct radeonfb_softc *sc) 2622 { 2623 2624 radeonfb_wait_fifo(sc, 2); 2625 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2626 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2627 } 2628 2629 static void 2630 radeonfb_engine_init(struct radeonfb_display *dp) 2631 { 2632 struct radeonfb_softc *sc = dp->rd_softc; 2633 uint32_t pitch; 2634 2635 /* no 3D */ 2636 PUT32(sc, RADEON_RB3D_CNTL, 0); 2637 2638 radeonfb_engine_reset(sc); 2639 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2640 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2641 2642 radeonfb_wait_fifo(sc, 1); 2643 if (!IS_R300(sc)) 2644 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2645 2646 radeonfb_wait_fifo(sc, 3); 2647 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2648 (pitch << 22) | (sc->sc_aperbase >> 10)); 2649 2650 2651 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2652 (pitch << 22) | (sc->sc_aperbase >> 10)); 2653 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2654 (pitch << 22) | (sc->sc_aperbase >> 10)); 2655 2656 radeonfb_wait_fifo(sc, 1); 2657 #if _BYTE_ORDER == _BIG_ENDIAN 2658 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2659 #else 2660 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2661 #endif 2662 2663 /* default scissors -- no clipping */ 2664 radeonfb_wait_fifo(sc, 1); 2665 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2666 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2667 2668 radeonfb_wait_fifo(sc, 1); 2669 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2670 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2671 RADEON_GMC_CLR_CMP_CNTL_DIS | 2672 RADEON_GMC_BRUSH_SOLID_COLOR | 2673 RADEON_GMC_SRC_DATATYPE_COLOR); 2674 2675 radeonfb_wait_fifo(sc, 7); 2676 PUT32(sc, RADEON_DST_LINE_START, 0); 2677 PUT32(sc, RADEON_DST_LINE_END, 0); 2678 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2679 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2680 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2681 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2682 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2683 2684 radeonfb_engine_idle(sc); 2685 } 2686 2687 static void 2688 radeonfb_engine_reset(struct radeonfb_softc *sc) 2689 { 2690 uint32_t hpc, rbbm, mclkcntl, clkindex; 2691 2692 radeonfb_engine_flush(sc); 2693 2694 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2695 if (HAS_R300CG(sc)) 2696 radeonfb_r300cg_workaround(sc); 2697 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2698 2699 /* 2700 * According to comments in XFree code, resetting the HDP via 2701 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2702 * So we use HOST_PATH_CNTL instead. 2703 */ 2704 2705 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2706 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2707 if (IS_R300(sc)) { 2708 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2709 RADEON_SOFT_RESET_CP | 2710 RADEON_SOFT_RESET_HI | 2711 RADEON_SOFT_RESET_E2); 2712 GET32(sc, RADEON_RBBM_SOFT_RESET); 2713 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2714 /* 2715 * XXX: this bit is not defined in any ATI docs I have, 2716 * nor in the XFree code, but XFree does it. Why? 2717 */ 2718 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2719 } else { 2720 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2721 RADEON_SOFT_RESET_CP | 2722 RADEON_SOFT_RESET_SE | 2723 RADEON_SOFT_RESET_RE | 2724 RADEON_SOFT_RESET_PP | 2725 RADEON_SOFT_RESET_E2 | 2726 RADEON_SOFT_RESET_RB); 2727 GET32(sc, RADEON_RBBM_SOFT_RESET); 2728 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2729 ~(RADEON_SOFT_RESET_CP | 2730 RADEON_SOFT_RESET_SE | 2731 RADEON_SOFT_RESET_RE | 2732 RADEON_SOFT_RESET_PP | 2733 RADEON_SOFT_RESET_E2 | 2734 RADEON_SOFT_RESET_RB)); 2735 GET32(sc, RADEON_RBBM_SOFT_RESET); 2736 } 2737 2738 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2739 GET32(sc, RADEON_HOST_PATH_CNTL); 2740 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2741 2742 if (IS_R300(sc)) 2743 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2744 2745 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2746 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2747 2748 if (HAS_R300CG(sc)) 2749 radeonfb_r300cg_workaround(sc); 2750 } 2751 2752 static int 2753 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2754 { 2755 int x, y; 2756 2757 x = pos->x; 2758 y = pos->y; 2759 2760 /* 2761 * This doesn't let a cursor move off the screen. I'm not 2762 * sure if this will have negative effects for e.g. Xinerama. 2763 * I'd guess Xinerama handles it by changing the cursor shape, 2764 * but that needs verification. 2765 */ 2766 if (x >= dp->rd_virtx) 2767 x = dp->rd_virtx - 1; 2768 if (x < 0) 2769 x = 0; 2770 if (y >= dp->rd_virty) 2771 y = dp->rd_virty - 1; 2772 if (y < 0) 2773 y = 0; 2774 2775 dp->rd_cursor.rc_pos.x = x; 2776 dp->rd_cursor.rc_pos.y = y; 2777 2778 radeonfb_cursor_position(dp); 2779 return 0; 2780 } 2781 2782 static int 2783 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2784 { 2785 unsigned flags; 2786 2787 uint8_t r[2], g[2], b[2]; 2788 unsigned index, count; 2789 int i, err; 2790 int pitch, size; 2791 struct radeonfb_cursor nc; 2792 2793 flags = wc->which; 2794 2795 /* copy old values */ 2796 nc = dp->rd_cursor; 2797 2798 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2799 index = wc->cmap.index; 2800 count = wc->cmap.count; 2801 2802 if (index >= 2 || (index + count) > 2) 2803 return EINVAL; 2804 2805 err = copyin(wc->cmap.red, &r[index], count); 2806 if (err) 2807 return err; 2808 err = copyin(wc->cmap.green, &g[index], count); 2809 if (err) 2810 return err; 2811 err = copyin(wc->cmap.blue, &b[index], count); 2812 if (err) 2813 return err; 2814 2815 for (i = index; i < index + count; i++) { 2816 nc.rc_cmap[i] = 2817 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2818 } 2819 } 2820 2821 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2822 if ((wc->size.x > RADEON_CURSORMAXX) || 2823 (wc->size.y > RADEON_CURSORMAXY)) 2824 return EINVAL; 2825 2826 /* figure bytes per line */ 2827 pitch = (wc->size.x + 7) / 8; 2828 size = pitch * wc->size.y; 2829 2830 /* clear the old cursor and mask */ 2831 memset(nc.rc_image, 0, 512); 2832 memset(nc.rc_mask, 0, 512); 2833 2834 nc.rc_size = wc->size; 2835 2836 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2837 return err; 2838 2839 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2840 return err; 2841 } 2842 2843 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2844 nc.rc_hot = wc->hot; 2845 if (nc.rc_hot.x >= nc.rc_size.x) 2846 nc.rc_hot.x = nc.rc_size.x - 1; 2847 if (nc.rc_hot.y >= nc.rc_size.y) 2848 nc.rc_hot.y = nc.rc_size.y - 1; 2849 } 2850 2851 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2852 nc.rc_pos = wc->pos; 2853 if (nc.rc_pos.x >= dp->rd_virtx) 2854 nc.rc_pos.x = dp->rd_virtx - 1; 2855 #if 0 2856 if (nc.rc_pos.x < 0) 2857 nc.rc_pos.x = 0; 2858 #endif 2859 if (nc.rc_pos.y >= dp->rd_virty) 2860 nc.rc_pos.y = dp->rd_virty - 1; 2861 #if 0 2862 if (nc.rc_pos.y < 0) 2863 nc.rc_pos.y = 0; 2864 #endif 2865 } 2866 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2867 nc.rc_visible = wc->enable; 2868 } 2869 2870 dp->rd_cursor = nc; 2871 radeonfb_cursor_update(dp, wc->which); 2872 2873 return 0; 2874 } 2875 2876 /* 2877 * Change the cursor shape. Call this with the cursor locked to avoid 2878 * flickering/tearing. 2879 */ 2880 static void 2881 radeonfb_cursor_shape(struct radeonfb_display *dp) 2882 { 2883 uint8_t and[512], xor[512]; 2884 int i, j, src, dst, pitch; 2885 const uint8_t *msk = dp->rd_cursor.rc_mask; 2886 const uint8_t *img = dp->rd_cursor.rc_image; 2887 2888 /* 2889 * Radeon cursor data interleaves one line of AND data followed 2890 * by a line of XOR data. (Each line corresponds to a whole hardware 2891 * pitch - i.e. 64 pixels or 8 bytes.) 2892 * 2893 * The cursor is displayed using the following table: 2894 * 2895 * AND XOR Result 2896 * ---------------------- 2897 * 0 0 Cursor color 0 2898 * 0 1 Cursor color 1 2899 * 1 0 Transparent 2900 * 1 1 Complement of background 2901 * 2902 * Our masks are therefore different from what we were passed. 2903 * Passed in, I'm assuming the data represents either color 0 or 1, 2904 * and a mask, so the passed in table looks like: 2905 * 2906 * IMG Mask Result 2907 * ----------------------- 2908 * 0 0 Transparent 2909 * 0 1 Cursor color 0 2910 * 1 0 Transparent 2911 * 1 1 Cursor color 1 2912 * 2913 * IF mask bit == 1, AND = 0, XOR = color. 2914 * IF mask bit == 0, AND = 1, XOR = 0. 2915 * 2916 * hence: AND = ~(mask); XOR = color & ~(mask); 2917 */ 2918 2919 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2920 2921 /* start by assuming all bits are transparent */ 2922 memset(and, 0xff, 512); 2923 memset(xor, 0x00, 512); 2924 2925 src = 0; 2926 dst = 0; 2927 for (i = 0; i < 64; i++) { 2928 for (j = 0; j < 64; j += 8) { 2929 if ((i < dp->rd_cursor.rc_size.y) && 2930 (j < dp->rd_cursor.rc_size.x)) { 2931 2932 /* take care to leave odd bits alone */ 2933 and[dst] &= ~(msk[src]); 2934 xor[dst] = img[src] & msk[src]; 2935 src++; 2936 } 2937 dst++; 2938 } 2939 } 2940 2941 /* copy the image into place */ 2942 for (i = 0; i < 64; i++) { 2943 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2944 &and[i * 8], 8); 2945 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2946 &xor[i * 8], 8); 2947 } 2948 } 2949 2950 static void 2951 radeonfb_cursor_position(struct radeonfb_display *dp) 2952 { 2953 struct radeonfb_softc *sc = dp->rd_softc; 2954 uint32_t offset, hvoff, hvpos; /* registers */ 2955 uint32_t coff; /* cursor offset */ 2956 int i, x, y, xoff, yoff, crtcoff; 2957 2958 /* 2959 * XXX: this also needs to handle pan/scan 2960 */ 2961 for (i = 0; i < dp->rd_ncrtcs; i++) { 2962 2963 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2964 2965 if (rcp->rc_number) { 2966 offset = RADEON_CUR2_OFFSET; 2967 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2968 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2969 crtcoff = RADEON_CRTC2_OFFSET; 2970 } else { 2971 offset = RADEON_CUR_OFFSET; 2972 hvoff = RADEON_CUR_HORZ_VERT_OFF; 2973 hvpos = RADEON_CUR_HORZ_VERT_POSN; 2974 crtcoff = RADEON_CRTC_OFFSET; 2975 } 2976 2977 x = dp->rd_cursor.rc_pos.x; 2978 y = dp->rd_cursor.rc_pos.y; 2979 2980 while (y < rcp->rc_yoffset) { 2981 rcp->rc_yoffset -= RADEON_PANINCREMENT; 2982 } 2983 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 2984 rcp->rc_yoffset += RADEON_PANINCREMENT; 2985 } 2986 while (x < rcp->rc_xoffset) { 2987 rcp->rc_xoffset -= RADEON_PANINCREMENT; 2988 } 2989 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 2990 rcp->rc_xoffset += RADEON_PANINCREMENT; 2991 } 2992 2993 /* adjust for the cursor's hotspot */ 2994 x -= dp->rd_cursor.rc_hot.x; 2995 y -= dp->rd_cursor.rc_hot.y; 2996 xoff = yoff = 0; 2997 2998 if (x >= dp->rd_virtx) 2999 x = dp->rd_virtx - 1; 3000 if (y >= dp->rd_virty) 3001 y = dp->rd_virty - 1; 3002 3003 /* now adjust cursor so it is relative to viewport */ 3004 x -= rcp->rc_xoffset; 3005 y -= rcp->rc_yoffset; 3006 3007 /* 3008 * no need to check for fall off, because we should 3009 * never move off the screen entirely! 3010 */ 3011 coff = 0; 3012 if (x < 0) { 3013 xoff = -x; 3014 x = 0; 3015 } 3016 if (y < 0) { 3017 yoff = -y; 3018 y = 0; 3019 coff = (yoff * 2) * 8; 3020 } 3021 3022 /* pan the display */ 3023 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3024 rcp->rc_xoffset); 3025 3026 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3027 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3028 /* NB: this unlocks the cursor */ 3029 PUT32(sc, hvpos, (x << 16) | y); 3030 } 3031 } 3032 3033 static void 3034 radeonfb_cursor_visible(struct radeonfb_display *dp) 3035 { 3036 int i; 3037 uint32_t gencntl, bit; 3038 3039 for (i = 0; i < dp->rd_ncrtcs; i++) { 3040 if (dp->rd_crtcs[i].rc_number) { 3041 gencntl = RADEON_CRTC2_GEN_CNTL; 3042 bit = RADEON_CRTC2_CUR_EN; 3043 } else { 3044 gencntl = RADEON_CRTC_GEN_CNTL; 3045 bit = RADEON_CRTC_CUR_EN; 3046 } 3047 3048 if (dp->rd_cursor.rc_visible) 3049 SET32(dp->rd_softc, gencntl, bit); 3050 else 3051 CLR32(dp->rd_softc, gencntl, bit); 3052 } 3053 } 3054 3055 static void 3056 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3057 { 3058 int i; 3059 uint32_t c0reg, c1reg; 3060 struct radeonfb_softc *sc = dp->rd_softc; 3061 3062 for (i = 0; i < dp->rd_ncrtcs; i++) { 3063 if (dp->rd_crtcs[i].rc_number) { 3064 c0reg = RADEON_CUR2_CLR0; 3065 c1reg = RADEON_CUR2_CLR1; 3066 } else { 3067 c0reg = RADEON_CUR_CLR0; 3068 c1reg = RADEON_CUR_CLR1; 3069 } 3070 3071 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3072 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3073 } 3074 } 3075 3076 static void 3077 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3078 { 3079 struct radeonfb_softc *sc; 3080 int i; 3081 3082 sc = dp->rd_softc; 3083 for (i = 0; i < dp->rd_ncrtcs; i++) { 3084 if (dp->rd_crtcs[i].rc_number) { 3085 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3086 } else { 3087 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3088 } 3089 } 3090 3091 if (which & WSDISPLAY_CURSOR_DOCMAP) 3092 radeonfb_cursor_cmap(dp); 3093 3094 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3095 radeonfb_cursor_shape(dp); 3096 3097 if (which & WSDISPLAY_CURSOR_DOCUR) 3098 radeonfb_cursor_visible(dp); 3099 3100 /* this one is unconditional, because it updates other stuff */ 3101 radeonfb_cursor_position(dp); 3102 } 3103 3104 static struct videomode * 3105 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3106 { 3107 int r1, r2; 3108 3109 /* otherwise pick the higher refresh rate */ 3110 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3111 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3112 3113 return (r1 < r2 ? m2 : m1); 3114 } 3115 3116 static const struct videomode * 3117 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3118 int x, int y) 3119 { 3120 struct edid_info *ep = &rp->rp_edid; 3121 struct videomode *vmp = NULL; 3122 int i; 3123 3124 if (!rp->rp_edid_valid) { 3125 /* fallback to safe mode */ 3126 return radeonfb_modelookup(sc->sc_defaultmode); 3127 } 3128 3129 /* always choose the preferred mode first! */ 3130 if (ep->edid_preferred_mode) { 3131 3132 /* XXX: add auto-stretching support for native mode */ 3133 3134 /* this may want panning to occur, btw */ 3135 if ((ep->edid_preferred_mode->hdisplay <= x) && 3136 (ep->edid_preferred_mode->vdisplay <= y)) 3137 return ep->edid_preferred_mode; 3138 } 3139 3140 for (i = 0; i < ep->edid_nmodes; i++) { 3141 /* 3142 * We elect to pick a resolution that is too large for 3143 * the monitor than one that is too small. This means 3144 * that we will prefer to pan rather than to try to 3145 * center a smaller display on a larger screen. In 3146 * practice, this shouldn't matter because if a 3147 * monitor can support a larger resolution, it can 3148 * probably also support the smaller. A specific 3149 * exception is fixed format panels, but hopefully 3150 * they are properly dealt with by the "autostretch" 3151 * logic above. 3152 */ 3153 if ((ep->edid_modes[i].hdisplay > x) || 3154 (ep->edid_modes[i].vdisplay > y)) { 3155 continue; 3156 } 3157 3158 /* 3159 * at this point, the display mode is no larger than 3160 * what we've requested. 3161 */ 3162 if (vmp == NULL) 3163 vmp = &ep->edid_modes[i]; 3164 3165 /* eliminate smaller modes */ 3166 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3167 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3168 continue; 3169 3170 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3171 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3172 vmp = &ep->edid_modes[i]; 3173 continue; 3174 } 3175 3176 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3177 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3178 3179 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3180 } 3181 3182 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3183 } 3184 3185 static int 3186 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3187 { 3188 int i; 3189 3190 for (i = 0; i < nlist; i++) { 3191 if ((x == list[i].hdisplay) && 3192 (y == list[i].vdisplay)) { 3193 return 1; 3194 } 3195 } 3196 return 0; 3197 } 3198 3199 static void 3200 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3201 int pan) 3202 { 3203 struct radeonfb_port *rp; 3204 struct edid_info *ep; 3205 int i, j; 3206 3207 *x = 0; 3208 *y = 0; 3209 3210 if (pan) { 3211 for (i = 0; i < dp->rd_ncrtcs; i++) { 3212 rp = dp->rd_crtcs[i].rc_port; 3213 ep = &rp->rp_edid; 3214 if (!rp->rp_edid_valid) { 3215 /* monitor not present */ 3216 continue; 3217 } 3218 3219 /* 3220 * For now we are ignoring "conflict" that 3221 * could occur when mixing some modes like 3222 * 1280x1024 and 1400x800. It isn't clear 3223 * which is better, so the first one wins. 3224 */ 3225 for (j = 0; j < ep->edid_nmodes; j++) { 3226 /* 3227 * ignore resolutions that are too big for 3228 * the radeon 3229 */ 3230 if (ep->edid_modes[j].hdisplay > 3231 dp->rd_softc->sc_maxx) 3232 continue; 3233 if (ep->edid_modes[j].vdisplay > 3234 dp->rd_softc->sc_maxy) 3235 continue; 3236 3237 /* 3238 * pick largest resolution, the 3239 * smaller monitor will pan 3240 */ 3241 if ((ep->edid_modes[j].hdisplay >= *x) && 3242 (ep->edid_modes[j].vdisplay >= *y)) { 3243 *x = ep->edid_modes[j].hdisplay; 3244 *y = ep->edid_modes[j].vdisplay; 3245 } 3246 } 3247 } 3248 3249 } else { 3250 struct videomode modes[64]; 3251 int nmodes = 0; 3252 int valid = 0; 3253 3254 for (i = 0; i < dp->rd_ncrtcs; i++) { 3255 /* 3256 * pick the largest resolution in common. 3257 */ 3258 rp = dp->rd_crtcs[i].rc_port; 3259 ep = &rp->rp_edid; 3260 3261 if (!rp->rp_edid_valid) 3262 continue; 3263 3264 if (!valid) { 3265 /* initialize starting list */ 3266 for (j = 0; j < ep->edid_nmodes; j++) { 3267 /* 3268 * ignore resolutions that are 3269 * too big for the radeon 3270 */ 3271 if (ep->edid_modes[j].hdisplay > 3272 dp->rd_softc->sc_maxx) 3273 continue; 3274 if (ep->edid_modes[j].vdisplay > 3275 dp->rd_softc->sc_maxy) 3276 continue; 3277 3278 modes[nmodes] = ep->edid_modes[j]; 3279 nmodes++; 3280 } 3281 valid = 1; 3282 } else { 3283 /* merge into preexisting list */ 3284 for (j = 0; j < nmodes; j++) { 3285 if (!radeonfb_hasres(ep->edid_modes, 3286 ep->edid_nmodes, 3287 modes[j].hdisplay, 3288 modes[j].vdisplay)) { 3289 modes[j] = modes[nmodes]; 3290 j--; 3291 nmodes--; 3292 } 3293 } 3294 } 3295 } 3296 3297 /* now we have to pick from the merged list */ 3298 for (i = 0; i < nmodes; i++) { 3299 if ((modes[i].hdisplay >= *x) && 3300 (modes[i].vdisplay >= *y)) { 3301 *x = modes[i].hdisplay; 3302 *y = modes[i].vdisplay; 3303 } 3304 } 3305 } 3306 3307 if ((*x == 0) || (*y == 0)) { 3308 /* fallback to safe mode */ 3309 *x = 640; 3310 *y = 480; 3311 } 3312 } 3313 3314 3315 /* Get the current backlight level for the display. */ 3316 3317 static int 3318 radeonfb_get_backlight(struct radeonfb_display *dp) 3319 { 3320 int s; 3321 uint32_t level; 3322 3323 s = spltty(); 3324 3325 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3326 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3327 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3328 3329 /* 3330 * On some chips, we should negate the backlight level. 3331 * XXX Find out on which chips. 3332 */ 3333 #ifdef RADEONFB_BACKLIGHT_NEGATED 3334 level = RADEONFB_BACKLIGHT_MAX - level; 3335 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3336 3337 splx(s); 3338 3339 return level; 3340 } 3341 3342 /* Set the backlight to the given level for the display. */ 3343 3344 static int 3345 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3346 { 3347 struct radeonfb_softc *sc; 3348 int rlevel, s; 3349 uint32_t lvds; 3350 3351 s = spltty(); 3352 3353 if (level < 0) 3354 level = 0; 3355 else if (level >= RADEONFB_BACKLIGHT_MAX) 3356 level = RADEONFB_BACKLIGHT_MAX; 3357 3358 sc = dp->rd_softc; 3359 3360 /* On some chips, we should negate the backlight level. */ 3361 #ifdef RADEONFB_BACKLIGHT_NEGATED 3362 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3363 #else 3364 rlevel = level; 3365 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3366 3367 callout_stop(&dp->rd_bl_lvds_co); 3368 radeonfb_engine_idle(sc); 3369 3370 /* 3371 * Turn off the display if the backlight is set to 0, since the 3372 * display is useless without backlight anyway. 3373 */ 3374 if (level == 0) 3375 radeonfb_blank(dp, 1); 3376 else if (radeonfb_get_backlight(dp) == 0) 3377 radeonfb_blank(dp, 0); 3378 3379 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3380 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3381 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3382 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3383 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3384 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3385 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3386 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3387 lvds |= RADEON_LVDS_ON; 3388 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3389 } else { 3390 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3391 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3392 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3393 } 3394 3395 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3396 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3397 /* XXX What is the correct delay? */ 3398 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3399 3400 splx(s); 3401 3402 return 0; 3403 } 3404 3405 /* 3406 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3407 * Set the delayed bits in the register, and clear the stored delayed 3408 * value. 3409 */ 3410 3411 static void radeonfb_lvds_callout(void *arg) 3412 { 3413 struct radeonfb_display *dp = arg; 3414 int s; 3415 3416 s = splhigh(); 3417 3418 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3419 dp->rd_bl_lvds_val); 3420 dp->rd_bl_lvds_val = 0; 3421 3422 splx(s); 3423 } 3424
Indexes created Mon Oct 20 08:09:54 GMT 2025