radeonfb.c revision 1.7.2.3
1 /* $NetBSD: radeonfb.c,v 1.7.2.3 2007/05/12 15:44:38 pavel Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.7.2.3 2007/05/12 15:44:38 pavel Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static int radeonfb_get_backlight(struct radeonfb_display *); 167 static int radeonfb_set_backlight(struct radeonfb_display *, int); 168 static void radeonfb_lvds_callout(void *); 169 170 static struct videomode *radeonfb_best_refresh(struct videomode *, 171 struct videomode *); 172 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 173 uint16_t *, int); 174 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 175 struct radeonfb_port *, int, int); 176 177 #ifdef RADEON_DEBUG 178 int radeon_debug = 1; 179 #define DPRINTF(x) \ 180 if (radeon_debug) printf x 181 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 182 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 183 #else 184 #define DPRINTF(x) 185 #define PRINTREG(r) 186 #define PRINTPLL(r) 187 #endif 188 189 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 190 191 #ifndef RADEON_DEFAULT_MODE 192 /* any reasonably modern display should handle this */ 193 #define RADEON_DEFAULT_MODE "1024x768x60" 194 #endif 195 196 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 197 198 static struct { 199 int size; /* minimum memory size (MB) */ 200 int maxx; /* maximum x dimension */ 201 int maxy; /* maximum y dimension */ 202 int maxbpp; /* maximum bpp */ 203 int maxdisp; /* maximum logical display count */ 204 } radeonfb_limits[] = { 205 { 32, 2048, 1536, 32, 2 }, 206 { 16, 1600, 1200, 32, 2 }, 207 { 8, 1600, 1200, 32, 1 }, 208 { 0, 0, 0, 0, 0 }, 209 }; 210 211 static struct wsscreen_descr radeonfb_stdscreen = { 212 "fb", /* name */ 213 0, 0, /* ncols, nrows */ 214 NULL, /* textops */ 215 8, 16, /* fontwidth, fontheight */ 216 WSSCREEN_WSCOLORS, /* capabilities */ 217 0, /* modecookie */ 218 }; 219 220 struct wsdisplay_accessops radeonfb_accessops = { 221 radeonfb_ioctl, 222 radeonfb_mmap, 223 NULL, /* vcons_alloc_screen */ 224 NULL, /* vcons_free_screen */ 225 NULL, /* vcons_show_screen */ 226 NULL, /* load_font */ 227 NULL, /* pollc */ 228 NULL, /* scroll */ 229 }; 230 231 static struct { 232 uint16_t devid; 233 uint16_t family; 234 uint16_t flags; 235 } radeonfb_devices[] = 236 { 237 /* R100 family */ 238 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 239 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 240 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 241 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 242 243 /* RV100 family */ 244 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 245 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 246 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 247 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 248 249 /* RS100 family */ 250 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 251 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 252 253 /* RS200/RS250 family */ 254 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 255 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 257 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 258 259 /* R200 family */ 260 /* add more R200 products? , 5148 */ 261 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 266 267 /* RV200 family */ 268 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 269 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 271 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 272 273 /* RV250 family */ 274 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 279 280 /* RS300 family */ 281 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 285 286 /* RV280 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 294 295 /* R300 family */ 296 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 304 305 /* RV350/RV360 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 318 319 /* R350/R360 family */ 320 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 328 329 /* RV380/RV370 family */ 330 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 339 340 /* R420/R423 family */ 341 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 357 358 { 0, 0, 0 } 359 }; 360 361 static struct { 362 int divider; 363 int mask; 364 } radeonfb_dividers[] = { 365 { 1, 0 }, 366 { 2, 1 }, 367 { 3, 4 }, 368 { 4, 2 }, 369 { 6, 6 }, 370 { 8, 3 }, 371 { 12, 7 }, 372 { 0, 0 } 373 }; 374 375 /* 376 * This table taken from X11. 377 */ 378 static const struct { 379 int family; 380 struct radeon_tmds_pll plls[4]; 381 } radeonfb_tmds_pll[] = { 382 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 383 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 384 { RADEON_RS100, {{0, 0}}}, 385 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 388 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 389 { RADEON_RS300, {{0, 0}}}, 390 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 391 { RADEON_R300, {{-1, 0xb01cb}}}, 392 { RADEON_R350, {{-1, 0xb01cb}}}, 393 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 394 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 395 { RADEON_R420, {{-1, 0xb01cb}}}, 396 }; 397 398 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 399 400 401 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 402 radeonfb_match, radeonfb_attach, NULL, NULL); 403 404 static int 405 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 406 { 407 struct pci_attach_args *pa = aux; 408 int i; 409 410 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 411 return 0; 412 413 for (i = 0; radeonfb_devices[i].devid; i++) { 414 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 415 return 100; /* high to defeat VGA/VESA */ 416 } 417 418 return 0; 419 } 420 421 static void 422 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 423 { 424 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 425 struct pci_attach_args *pa = aux; 426 const char *mptr; 427 bus_size_t bsz; 428 pcireg_t screg; 429 int i, j; 430 uint32_t v; 431 432 sc->sc_id = pa->pa_id; 433 for (i = 0; radeonfb_devices[i].devid; i++) { 434 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 435 break; 436 } 437 438 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 439 sizeof(sc->sc_devinfo)); 440 441 aprint_naive("\n"); 442 aprint_normal(": %s\n", sc->sc_devinfo); 443 444 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 445 446 KASSERT(radeonfb_devices[i].devid != 0); 447 sc->sc_pt = pa->pa_tag; 448 sc->sc_pc = pa->pa_pc; 449 sc->sc_family = radeonfb_devices[i].family; 450 sc->sc_flags = radeonfb_devices[i].flags; 451 452 /* enable memory and IO access */ 453 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 454 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 455 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 456 457 /* 458 * Some flags are general to entire chip families, and rather 459 * than clutter up the table with them, we go ahead and set 460 * them here. 461 */ 462 switch (sc->sc_family) { 463 case RADEON_RS100: 464 case RADEON_RS200: 465 sc->sc_flags |= RFB_IGP | RFB_RV100; 466 break; 467 468 case RADEON_RV100: 469 case RADEON_RV200: 470 case RADEON_RV250: 471 case RADEON_RV280: 472 sc->sc_flags |= RFB_RV100; 473 break; 474 475 case RADEON_RS300: 476 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 477 break; 478 479 case RADEON_R300: 480 case RADEON_RV350: 481 case RADEON_R350: 482 case RADEON_RV380: 483 case RADEON_R420: 484 /* newer chips */ 485 sc->sc_flags |= RFB_R300; 486 break; 487 488 case RADEON_R100: 489 sc->sc_flags |= RFB_NCRTC2; 490 break; 491 } 492 493 if ((sc->sc_family == RADEON_RV200) || 494 (sc->sc_family == RADEON_RV250) || 495 (sc->sc_family == RADEON_RV280) || 496 (sc->sc_family == RADEON_RV350)) { 497 int inverted = 0; 498 /* backlight level is linear */ 499 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 500 prop_dictionary_get_bool(device_properties(&sc->sc_dev), 501 "backlight_level_reverted", &inverted); 502 if (inverted) { 503 DPRINTF(("nope, it's inverted\n")); 504 sc->sc_flags |= RFB_INV_BLIGHT; 505 } 506 } else 507 sc->sc_flags |= RFB_INV_BLIGHT; 508 509 /* 510 * XXX: to support true multihead, this must change. 511 */ 512 sc->sc_ndisplays = 1; 513 514 /* XXX: */ 515 if (!HAS_CRTC2(sc)) { 516 sc->sc_ndisplays = 1; 517 } 518 519 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 520 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 521 &sc->sc_regsz) != 0) { 522 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 523 goto error; 524 } 525 526 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 527 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 528 &sc->sc_iosz) != 0) { 529 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 530 } 531 532 /* scratch register test... */ 533 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 534 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 535 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 536 goto error; 537 } 538 539 PRINTREG(RADEON_BIOS_4_SCRATCH); 540 PRINTREG(RADEON_FP_GEN_CNTL); 541 PRINTREG(RADEON_FP2_GEN_CNTL); 542 PRINTREG(RADEON_TMDS_CNTL); 543 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 544 PRINTREG(RADEON_TMDS_PLL_CNTL); 545 PRINTREG(RADEON_LVDS_GEN_CNTL); 546 PRINTREG(RADEON_FP_HORZ_STRETCH); 547 PRINTREG(RADEON_FP_VERT_STRETCH); 548 549 /* XXX: RV100 specific */ 550 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 551 552 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 553 RADEON_TMDS_TRANSMITTER_PLLEN, 554 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 555 556 radeonfb_i2c_init(sc); 557 558 radeonfb_loadbios(sc, pa); 559 560 #ifdef RADEON_BIOS_INIT 561 if (radeonfb_bios_init(sc)) { 562 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 563 goto error; 564 } 565 #endif 566 567 if (radeonfb_getclocks(sc)) { 568 aprint_error("%s: Unable to get reference clocks from BIOS\n", 569 XNAME(sc)); 570 goto error; 571 } 572 573 if (radeonfb_gettmds(sc)) { 574 aprint_error("%s: Unable to identify TMDS PLL settings\n", 575 XNAME(sc)); 576 goto error; 577 } 578 579 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 580 "minpll = %d, maxpll = %d\n", XNAME(sc), 581 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 582 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 583 584 radeonfb_getconnectors(sc); 585 586 radeonfb_set_fbloc(sc); 587 588 for (i = 0; radeonfb_limits[i].size; i++) { 589 if (sc->sc_memsz >= radeonfb_limits[i].size) { 590 sc->sc_maxx = radeonfb_limits[i].maxx; 591 sc->sc_maxy = radeonfb_limits[i].maxy; 592 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 593 /* framebuffer offset, start at a 4K page */ 594 sc->sc_fboffset = sc->sc_memsz / 595 radeonfb_limits[i].maxdisp; 596 /* 597 * we use the fbsize to figure out where we can store 598 * things like cursor data. 599 */ 600 sc->sc_fbsize = 601 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 602 RADEON_STRIDEALIGN) * sc->sc_maxy, 603 4096); 604 break; 605 } 606 } 607 608 609 radeonfb_init_misc(sc); 610 radeonfb_init_palette(sc, 0); 611 if (HAS_CRTC2(sc)) 612 radeonfb_init_palette(sc, 1); 613 614 /* program the DAC wirings */ 615 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 616 switch (sc->sc_ports[i].rp_dac_type) { 617 case RADEON_DAC_PRIMARY: 618 PATCH32(sc, RADEON_DAC_CNTL2, 619 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 620 ~RADEON_DAC2_DAC_CLK_SEL); 621 break; 622 case RADEON_DAC_TVDAC: 623 /* we always use the TVDAC to drive a secondary analog 624 * CRT for now. if we ever support TV-out this will 625 * have to change. 626 */ 627 SET32(sc, RADEON_DAC_CNTL2, 628 RADEON_DAC2_DAC2_CLK_SEL); 629 PATCH32(sc, RADEON_DISP_HW_DEBUG, 630 i ? 0 : RADEON_CRT2_DISP1_SEL, 631 ~RADEON_CRT2_DISP1_SEL); 632 break; 633 } 634 } 635 PRINTREG(RADEON_DAC_CNTL2); 636 PRINTREG(RADEON_DISP_HW_DEBUG); 637 638 /* other DAC programming */ 639 v = GET32(sc, RADEON_DAC_CNTL); 640 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 641 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 642 PUT32(sc, RADEON_DAC_CNTL, v); 643 PRINTREG(RADEON_DAC_CNTL); 644 645 /* XXX: this may need more investigation */ 646 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 647 PRINTREG(RADEON_TV_DAC_CNTL); 648 649 /* enable TMDS */ 650 SET32(sc, RADEON_FP_GEN_CNTL, 651 RADEON_FP_TMDS_EN | 652 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 653 RADEON_FP_CRTC_DONT_SHADOW_HEND); 654 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 655 if (HAS_CRTC2(sc)) 656 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 657 658 /* 659 * we use bus_space_map instead of pci_mapreg, because we don't 660 * need the full aperature space. no point in wasting virtual 661 * address space we don't intend to use, right? 662 */ 663 if ((sc->sc_memsz < (4096 * 1024)) || 664 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 665 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 666 (bsz < sc->sc_memsz)) { 667 sc->sc_memsz = 0; 668 aprint_error("%s: Bad frame buffer configuration\n", 669 XNAME(sc)); 670 goto error; 671 } 672 673 /* 64 MB should be enough -- more just wastes map entries */ 674 if (sc->sc_memsz > (64 << 20)) 675 sc->sc_memsz = (64 << 20); 676 677 sc->sc_memt = pa->pa_memt; 678 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 679 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 680 sc->sc_memsz = 0; 681 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 682 goto error; 683 } 684 685 aprint_normal("%s: %d MB aperture at 0x%08x, " 686 "%d KB registers at 0x%08x\n", XNAME(sc), 687 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 688 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 689 690 /* setup default video mode from devprop (allows PROM override) */ 691 sc->sc_defaultmode = radeonfb_default_mode; 692 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 693 "videomode", &mptr)) { 694 695 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 696 sc->sc_defaultmode = sc->sc_modebuf; 697 } 698 699 /* initialize some basic display parameters */ 700 for (i = 0; i < sc->sc_ndisplays; i++) { 701 struct radeonfb_display *dp = &sc->sc_displays[i]; 702 struct rasops_info *ri; 703 long defattr; 704 struct wsemuldisplaydev_attach_args aa; 705 706 /* 707 * Figure out how many "displays" (desktops) we are going to 708 * support. If more than one, then each CRTC gets its own 709 * programming. 710 * 711 * XXX: this code needs to change to support mergedfb. 712 * XXX: would be nice to allow this to be overridden 713 */ 714 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 715 DPRINTF(("dual crtcs!\n")); 716 dp->rd_ncrtcs = 2; 717 dp->rd_crtcs[0].rc_number = 0; 718 dp->rd_crtcs[1].rc_number = 1; 719 } else { 720 dp->rd_ncrtcs = 1; 721 dp->rd_crtcs[0].rc_number = i; 722 } 723 724 /* set up port pointer */ 725 for (j = 0; j < dp->rd_ncrtcs; j++) { 726 dp->rd_crtcs[j].rc_port = 727 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 728 } 729 730 dp->rd_softc = sc; 731 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 732 dp->rd_bg = WS_DEFAULT_BG; 733 #if 0 734 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 735 #else 736 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 737 #endif 738 /* for text mode, we pick a resolution that won't 739 * require panning */ 740 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 741 742 aprint_normal("%s: display %d: " 743 "virtual resolution %dx%d at %d bpp\n", 744 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 745 746 /* now select the *video mode* that we will use */ 747 for (j = 0; j < dp->rd_ncrtcs; j++) { 748 const struct videomode *vmp; 749 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 750 dp->rd_virtx, dp->rd_virty); 751 dp->rd_crtcs[j].rc_videomode = *vmp; 752 printf("%s: port %d: physical %dx%d %dHz\n", 753 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 754 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 755 vmp->htotal), vmp->vtotal)); 756 } 757 758 /* N.B.: radeon wants 64-byte aligned stride */ 759 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 760 //dp->rd_stride = sc->sc_maxx * sc->sc_maxbpp / 8; 761 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 762 763 dp->rd_offset = sc->sc_fboffset * i; 764 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 765 sc->sc_memh) + dp->rd_offset; 766 dp->rd_curoff = sc->sc_fbsize; 767 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 768 769 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 770 771 switch (dp->rd_bpp) { 772 case 8: 773 dp->rd_format = 2; 774 break; 775 case 32: 776 dp->rd_format = 6; 777 break; 778 default: 779 aprint_error("%s: bad depth %d\n", XNAME(sc), 780 dp->rd_bpp); 781 goto error; 782 } 783 784 printf("init engine\n"); 785 /* XXX: this seems suspicious - per display engine 786 initialization? */ 787 radeonfb_engine_init(dp); 788 789 /* copy the template into place */ 790 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 791 dp->rd_wsscreens = dp->rd_wsscreens_storage; 792 793 /* and make up the list */ 794 dp->rd_wsscreenlist.nscreens = 1; 795 dp->rd_wsscreenlist.screens = 796 (const struct wsscreen_descr **)&dp->rd_wsscreens; 797 798 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 799 &radeonfb_accessops); 800 801 dp->rd_vd.init_screen = radeonfb_init_screen; 802 803 dp->rd_console = 1; 804 805 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 806 807 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 808 dp->rd_console, &defattr); 809 810 ri = &dp->rd_vscreen.scr_ri; 811 dp->rd_wsscreens->textops = &ri->ri_ops; 812 dp->rd_wsscreens->capabilities = ri->ri_caps; 813 dp->rd_wsscreens->nrows = ri->ri_rows; 814 dp->rd_wsscreens->ncols = ri->ri_cols; 815 816 #ifdef SPLASHSCREEN 817 dp->rd_splash.si_depth = ri->ri_depth; 818 dp->rd_splash.si_bits = ri->ri_bits; 819 dp->rd_splash.si_hwbits = ri->ri_hwbits; 820 dp->rd_splash.si_width = ri->ri_width; 821 dp->rd_splash.si_height = ri->ri_height; 822 dp->rd_splash.si_stride = ri->ri_stride; 823 dp->rd_splash.si_fillrect = NULL; 824 #endif 825 if (dp->rd_console) { 826 827 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 828 defattr); 829 #ifdef SPLASHSCREEN 830 splash_render(&dp->rd_splash, 831 SPLASH_F_CENTER|SPLASH_F_FILL); 832 #endif 833 834 #ifdef SPLASHSCREEN_PROGRESS 835 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 836 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 837 dp->rd_progress.sp_left = (dp->rd_virtx - 838 dp->rd_progress.sp_width) / 2; 839 dp->rd_progress.sp_height = 20; 840 dp->rd_progress.sp_state = -1; 841 dp->rd_progress.sp_si = &dp->rd_splash; 842 splash_progress_init(&dp->rd_progress); 843 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 844 #endif 845 846 } else { 847 848 /* 849 * since we're not the console we can postpone 850 * the rest until someone actually allocates a 851 * screen for us. but we do clear the screen 852 * at least. 853 */ 854 memset(ri->ri_bits, 0, 1024); 855 856 radeonfb_modeswitch(dp); 857 #ifdef SPLASHSCREEN 858 splash_render(&dp->rd_splash, 859 SPLASH_F_CENTER|SPLASH_F_FILL); 860 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 861 #endif 862 } 863 864 aa.console = dp->rd_console; 865 aa.scrdata = &dp->rd_wsscreenlist; 866 aa.accessops = &radeonfb_accessops; 867 aa.accesscookie = &dp->rd_vd; 868 869 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 870 radeonfb_blank(dp, 0); 871 872 /* Initialise delayed lvds operations for backlight. */ 873 callout_init(&dp->rd_bl_lvds_co); 874 callout_setfunc(&dp->rd_bl_lvds_co, 875 radeonfb_lvds_callout, dp); 876 } 877 878 return; 879 880 error: 881 if (sc->sc_biossz) 882 free(sc->sc_bios, M_DEVBUF); 883 884 if (sc->sc_regsz) 885 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 886 887 if (sc->sc_memsz) 888 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 889 } 890 891 int 892 radeonfb_ioctl(void *v, void *vs, 893 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 894 { 895 struct vcons_data *vd; 896 struct radeonfb_display *dp; 897 struct radeonfb_softc *sc; 898 struct wsdisplay_param *param; 899 900 vd = (struct vcons_data *)v; 901 dp = (struct radeonfb_display *)vd->cookie; 902 sc = dp->rd_softc; 903 904 switch (cmd) { 905 case WSDISPLAYIO_GTYPE: 906 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 907 return 0; 908 909 case WSDISPLAYIO_GINFO: 910 if (vd->active != NULL) { 911 struct wsdisplay_fbinfo *fb; 912 fb = (struct wsdisplay_fbinfo *)d; 913 fb->width = dp->rd_virtx; 914 fb->height = dp->rd_virty; 915 fb->depth = dp->rd_bpp; 916 fb->cmsize = 256; 917 return 0; 918 } else 919 return ENODEV; 920 case WSDISPLAYIO_GVIDEO: 921 if (radeonfb_isblank(dp)) 922 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 923 else 924 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 925 return 0; 926 927 case WSDISPLAYIO_SVIDEO: 928 radeonfb_blank(dp, 929 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 930 return 0; 931 932 case WSDISPLAYIO_GETCMAP: 933 #if 0 934 if (dp->rd_bpp == 8) 935 return radeonfb_getcmap(sc, 936 (struct wsdisplay_cmap *)d); 937 #endif 938 return EINVAL; 939 940 case WSDISPLAYIO_PUTCMAP: 941 #if 0 942 if (dp->rd_bpp == 8) 943 return radeonfb_putcmap(sc, 944 (struct wsdisplay_cmap *)d); 945 #endif 946 return EINVAL; 947 948 case WSDISPLAYIO_LINEBYTES: 949 *(unsigned *)d = dp->rd_stride; 950 return 0; 951 952 case WSDISPLAYIO_SMODE: 953 if (*(int *)d != dp->rd_wsmode) { 954 dp->rd_wsmode = *(int *)d; 955 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 956 (dp->rd_vd.active)) { 957 vcons_redraw_screen(dp->rd_vd.active); 958 } 959 } 960 return 0; 961 962 case WSDISPLAYIO_GCURMAX: 963 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 964 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 965 return 0; 966 967 case WSDISPLAYIO_SCURSOR: 968 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 969 970 case WSDISPLAYIO_GCURSOR: 971 return EPASSTHROUGH; 972 973 case WSDISPLAYIO_GCURPOS: 974 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 975 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 976 return 0; 977 978 case WSDISPLAYIO_SCURPOS: 979 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 980 981 case WSDISPLAYIO_SSPLASH: 982 #if defined(SPLASHSCREEN) 983 if (*(int *)d == 1) { 984 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 985 splash_render(&dp->rd_splash, 986 SPLASH_F_CENTER|SPLASH_F_FILL); 987 } else 988 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 989 return 0; 990 #else 991 return ENODEV; 992 #endif 993 case WSDISPLAYIO_SPROGRESS: 994 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 995 dp->rd_progress.sp_force = 1; 996 splash_progress_update(&dp->rd_progress); 997 dp->rd_progress.sp_force = 0; 998 return 0; 999 #else 1000 return ENODEV; 1001 #endif 1002 case WSDISPLAYIO_GETPARAM: 1003 param = (struct wsdisplay_param *)d; 1004 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1005 param->min = 0; 1006 param->max = RADEONFB_BACKLIGHT_MAX; 1007 param->curval = radeonfb_get_backlight(dp); 1008 return 0; 1009 } 1010 return EPASSTHROUGH; 1011 1012 case WSDISPLAYIO_SETPARAM: 1013 param = (struct wsdisplay_param *)d; 1014 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1015 return radeonfb_set_backlight(dp, param->curval); 1016 } 1017 return EPASSTHROUGH; 1018 1019 default: 1020 return EPASSTHROUGH; 1021 } 1022 } 1023 1024 paddr_t 1025 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1026 { 1027 struct vcons_data *vd; 1028 struct radeonfb_display *dp; 1029 struct radeonfb_softc *sc; 1030 #ifdef RADEONFB_MMAP_BARS 1031 struct lwp *me; 1032 #endif 1033 paddr_t pa; 1034 1035 vd = (struct vcons_data *)v; 1036 dp = (struct radeonfb_display *)vd->cookie; 1037 sc = dp->rd_softc; 1038 1039 /* XXX: note that we don't allow mapping of registers right now */ 1040 /* XXX: this means that the XFree86 radeon driver won't work */ 1041 1042 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1043 pa = bus_space_mmap(sc->sc_memt, 1044 sc->sc_memaddr + dp->rd_offset + offset, 0, 1045 prot, BUS_SPACE_MAP_LINEAR); 1046 return pa; 1047 } 1048 1049 #ifdef RADEONFB_MMAP_BARS 1050 /* 1051 * restrict all other mappings to processes with superuser privileges 1052 * or the kernel itself 1053 */ 1054 me = curlwp; 1055 if (me != NULL) { 1056 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1057 NULL) != 0) { 1058 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1059 return -1; 1060 } 1061 } 1062 1063 if ((offset >= sc->sc_regaddr) && 1064 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1065 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1066 BUS_SPACE_MAP_LINEAR); 1067 } 1068 1069 if ((offset >= sc->sc_memaddr) && 1070 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1071 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1072 BUS_SPACE_MAP_LINEAR); 1073 } 1074 1075 #ifdef macppc 1076 /* allow mapping of IO space */ 1077 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1078 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1079 BUS_SPACE_MAP_LINEAR); 1080 return pa; 1081 } 1082 #endif /* macppc */ 1083 1084 #endif /* RADEONFB_MMAP_BARS */ 1085 1086 return -1; 1087 } 1088 1089 static void 1090 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1091 { 1092 bus_space_tag_t romt; 1093 bus_space_handle_t romh, biosh; 1094 bus_size_t romsz; 1095 bus_addr_t ptr; 1096 1097 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1098 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1099 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1100 return; 1101 } 1102 1103 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1104 &sc->sc_biossz); 1105 if (sc->sc_biossz == 0) { 1106 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1107 return; 1108 } 1109 1110 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1111 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1112 1113 /* unmap the PCI expansion rom */ 1114 bus_space_unmap(romt, romh, romsz); 1115 1116 /* turn off rom decoder now */ 1117 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1118 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1119 ~PCI_MAPREG_ROM_ENABLE); 1120 1121 ptr = GETBIOS16(sc, 0x48); 1122 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1123 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1124 sc->sc_flags |= RFB_ATOM; 1125 } 1126 1127 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1128 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1129 } 1130 1131 1132 uint32_t 1133 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1134 { 1135 1136 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1137 } 1138 1139 void 1140 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1141 { 1142 1143 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1144 } 1145 1146 void 1147 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1148 uint32_t andmask, uint32_t ormask) 1149 { 1150 int s; 1151 uint32_t val; 1152 1153 s = splhigh(); 1154 val = radeonfb_get32(sc, reg); 1155 val = (val & andmask) | ormask; 1156 radeonfb_put32(sc, reg, val); 1157 splx(s); 1158 } 1159 1160 uint32_t 1161 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1162 { 1163 int s; 1164 uint32_t val; 1165 1166 s = splhigh(); 1167 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1168 val = radeonfb_get32(sc, RADEON_MM_DATA); 1169 splx(s); 1170 1171 return (val); 1172 } 1173 1174 void 1175 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1176 { 1177 int s; 1178 1179 s = splhigh(); 1180 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1181 radeonfb_put32(sc, RADEON_MM_DATA, val); 1182 splx(s); 1183 } 1184 1185 void 1186 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1187 uint32_t andmask, uint32_t ormask) 1188 { 1189 int s; 1190 uint32_t val; 1191 1192 s = splhigh(); 1193 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1194 val = radeonfb_get32(sc, RADEON_MM_DATA); 1195 val = (val & andmask) | ormask; 1196 radeonfb_put32(sc, RADEON_MM_DATA, val); 1197 splx(s); 1198 } 1199 1200 uint32_t 1201 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1202 { 1203 int s; 1204 uint32_t val; 1205 1206 s = splhigh(); 1207 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1208 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1209 if (HAS_R300CG(sc)) 1210 radeonfb_r300cg_workaround(sc); 1211 splx(s); 1212 1213 return (val); 1214 } 1215 1216 void 1217 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1218 { 1219 int s; 1220 1221 s = splhigh(); 1222 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1223 RADEON_PLL_WR_EN); 1224 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1225 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1226 splx(s); 1227 } 1228 1229 void 1230 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1231 uint32_t andmask, uint32_t ormask) 1232 { 1233 int s; 1234 uint32_t val; 1235 1236 s = splhigh(); 1237 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1238 RADEON_PLL_WR_EN); 1239 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1240 val = (val & andmask) | ormask; 1241 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1242 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1243 splx(s); 1244 } 1245 1246 int 1247 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1248 { 1249 uint32_t saved; 1250 1251 saved = GET32(sc, reg); 1252 PUT32(sc, reg, v); 1253 if (GET32(sc, reg) != v) { 1254 return -1; 1255 } 1256 PUT32(sc, reg, saved); 1257 return 0; 1258 } 1259 1260 uintmax_t 1261 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1262 uintmax_t defval) 1263 { 1264 prop_number_t pn; 1265 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1266 if (pn == NULL) { 1267 return defval; 1268 } 1269 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1270 return (prop_number_integer_value(pn)); 1271 } 1272 1273 int 1274 radeonfb_getclocks(struct radeonfb_softc *sc) 1275 { 1276 bus_addr_t ptr; 1277 int refclk = 0; 1278 int refdiv = 0; 1279 int minpll = 0; 1280 int maxpll = 0; 1281 1282 /* load initial property values if port/board provides them */ 1283 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1284 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1285 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1286 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1287 1288 if (refclk && refdiv && minpll && maxpll) 1289 goto dontprobe; 1290 1291 if (!sc->sc_biossz) { 1292 /* no BIOS */ 1293 aprint_verbose("%s: No video BIOS, using default clocks\n", 1294 XNAME(sc)); 1295 if (IS_IGP(sc)) 1296 refclk = refclk ? refclk : 1432; 1297 else 1298 refclk = refclk ? refclk : 2700; 1299 refdiv = refdiv ? refdiv : 12; 1300 minpll = minpll ? minpll : 12500; 1301 maxpll = maxpll ? maxpll : 35000; 1302 } else if (IS_ATOM(sc)) { 1303 /* ATOM BIOS */ 1304 ptr = GETBIOS16(sc, 0x48); 1305 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1306 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1307 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1308 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1309 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1310 /* 1311 * ATOM BIOS doesn't supply a reference divider, so we 1312 * have to probe for it. 1313 */ 1314 if (refdiv < 2) 1315 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1316 RADEON_PPLL_REF_DIV_MASK; 1317 /* 1318 * if probe is zero, just assume one that should work 1319 * for most parts 1320 */ 1321 if (refdiv < 2) 1322 refdiv = 12; 1323 1324 } else { 1325 /* Legacy BIOS */ 1326 ptr = GETBIOS16(sc, 0x48); 1327 ptr = GETBIOS16(sc, ptr + 0x30); 1328 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1329 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1330 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1331 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1332 } 1333 1334 1335 dontprobe: 1336 sc->sc_refclk = refclk * 10; 1337 sc->sc_refdiv = refdiv; 1338 sc->sc_minpll = minpll * 10; 1339 sc->sc_maxpll = maxpll * 10; 1340 return 0; 1341 } 1342 1343 int 1344 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1345 uint32_t *postdivbit, uint32_t *feedbackdiv) 1346 { 1347 int i; 1348 uint32_t outfreq; 1349 int div; 1350 1351 DPRINTF(("dot clock: %u\n", dotclock)); 1352 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1353 outfreq = div * dotclock; 1354 if ((outfreq >= sc->sc_minpll) && 1355 (outfreq <= sc->sc_maxpll)) { 1356 DPRINTF(("outfreq: %u\n", outfreq)); 1357 *postdivbit = 1358 ((uint32_t)radeonfb_dividers[i].mask << 16); 1359 DPRINTF(("post divider: %d (mask %x)\n", div, 1360 *postdivbit)); 1361 break; 1362 } 1363 } 1364 1365 if (div == 0) 1366 return 1; 1367 1368 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1369 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1370 return 0; 1371 } 1372 1373 #if 0 1374 #ifdef RADEON_DEBUG 1375 static void 1376 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1377 { 1378 char asc[17]; 1379 unsigned ptr = (unsigned)buffer; 1380 char *start = (char *)(ptr & ~0xf); 1381 char *end = (char *)(ptr + size); 1382 1383 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1384 1385 if (pfx == NULL) { 1386 pfx = ""; 1387 } 1388 1389 while (start < end) { 1390 unsigned offset = (unsigned)start & 0xf; 1391 if (offset == 0) { 1392 printf("%s%x: ", pfx, (unsigned)start); 1393 } 1394 if (((unsigned)start < ptr) || 1395 ((unsigned)start >= (ptr + size))) { 1396 printf(" "); 1397 asc[offset] = ' '; 1398 } else { 1399 printf("%02x", *(unsigned char *)start); 1400 if ((*start >= ' ') && (*start <= '~')) { 1401 asc[offset] = *start; 1402 } else { 1403 asc[offset] = '.'; 1404 } 1405 } 1406 asc[offset + 1] = 0; 1407 if (offset % 2) { 1408 printf(" "); 1409 } 1410 if (offset == 15) { 1411 printf(" %s\n", asc); 1412 } 1413 start++; 1414 } 1415 } 1416 #endif 1417 #endif 1418 1419 int 1420 radeonfb_getconnectors(struct radeonfb_softc *sc) 1421 { 1422 int i; 1423 int found = 0; 1424 1425 for (i = 0; i < 2; i++) { 1426 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1427 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1428 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1429 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1430 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1431 } 1432 1433 /* 1434 * This logic is borrowed from Xorg's radeon driver. 1435 */ 1436 if (!sc->sc_biossz) 1437 goto nobios; 1438 1439 if (IS_ATOM(sc)) { 1440 /* not done yet */ 1441 } else { 1442 uint16_t ptr; 1443 int port = 0; 1444 1445 ptr = GETBIOS16(sc, 0x48); 1446 ptr = GETBIOS16(sc, ptr + 0x50); 1447 for (i = 1; i < 4; i++) { 1448 uint16_t entry; 1449 uint8_t conn, ddc, dac, tmds; 1450 1451 /* 1452 * Parse the connector table. From reading the code, 1453 * it appears to made up of 16-bit entries for each 1454 * connector. The 16-bits are defined as: 1455 * 1456 * bits 12-15 - connector type (0 == end of table) 1457 * bits 8-11 - DDC type 1458 * bits 5-7 - ??? 1459 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1460 * bits 1-3 - ??? 1461 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1462 */ 1463 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1464 break; 1465 entry = GETBIOS16(sc, ptr + i * 2); 1466 1467 conn = (entry >> 12) & 0xf; 1468 ddc = (entry >> 8) & 0xf; 1469 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1470 RADEON_DAC_PRIMARY; 1471 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1472 RADEON_TMDS_INT; 1473 1474 if (conn == RADEON_CONN_NONE) 1475 continue; /* no connector */ 1476 1477 if ((found > 0) && 1478 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1479 /* duplicate entry for same connector */ 1480 continue; 1481 } 1482 1483 /* internal DDC_DVI port gets priority */ 1484 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1485 port = 0; 1486 else 1487 port = 1; 1488 1489 sc->sc_ports[port].rp_ddc_type = 1490 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1491 sc->sc_ports[port].rp_dac_type = dac; 1492 sc->sc_ports[port].rp_conn_type = 1493 min(conn, RADEON_CONN_UNSUPPORTED) ; 1494 1495 sc->sc_ports[port].rp_tmds_type = tmds; 1496 1497 if ((conn != RADEON_CONN_DVI_I) && 1498 (conn != RADEON_CONN_DVI_D) && 1499 (tmds == RADEON_TMDS_INT)) 1500 sc->sc_ports[port].rp_tmds_type = 1501 RADEON_TMDS_UNKNOWN; 1502 1503 found += (port + 1); 1504 } 1505 } 1506 1507 nobios: 1508 if (!found) { 1509 DPRINTF(("No connector info in BIOS!\n")); 1510 /* default, port 0 = internal TMDS, port 1 = CRT */ 1511 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1512 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1513 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1514 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1515 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1516 1517 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1518 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1519 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1520 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1521 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1522 } 1523 1524 /* 1525 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1526 * these chips should use TVDAC for the VGA port. 1527 */ 1528 if (HAS_SDAC(sc)) { 1529 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1530 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1531 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1532 } else { 1533 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1534 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1535 } 1536 } else if (!HAS_CRTC2(sc)) { 1537 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1538 } 1539 1540 for (i = 0; i < 2; i++) { 1541 char edid[128]; 1542 uint8_t ddc; 1543 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1544 prop_data_t edid_data; 1545 1546 DPRINTF(("Port #%d:\n", i)); 1547 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1548 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1549 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1550 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1551 1552 sc->sc_ports[i].rp_edid_valid = 0; 1553 /* first look for static EDID data */ 1554 if ((edid_data = prop_dictionary_get(device_properties( 1555 &sc->sc_dev), "EDID")) != NULL) { 1556 1557 aprint_normal("%s: using static EDID\n", 1558 sc->sc_dev.dv_xname); 1559 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1560 if (edid_parse(edid, eip) == 0) { 1561 1562 sc->sc_ports[i].rp_edid_valid = 1; 1563 edid_print(eip); 1564 } 1565 } 1566 /* if we didn't find any we'll try to talk to the monitor */ 1567 if (sc->sc_ports[i].rp_edid_valid != 1) { 1568 1569 ddc = sc->sc_ports[i].rp_ddc_type; 1570 if (ddc != RADEON_DDC_NONE) { 1571 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1572 == 0) && (edid_parse(edid, eip) == 0)) { 1573 1574 sc->sc_ports[i].rp_edid_valid = 1; 1575 edid_print(eip); 1576 } 1577 } 1578 } 1579 } 1580 1581 return found; 1582 } 1583 1584 int 1585 radeonfb_gettmds(struct radeonfb_softc *sc) 1586 { 1587 int i; 1588 1589 if (!sc->sc_biossz) { 1590 goto nobios; 1591 } 1592 1593 if (IS_ATOM(sc)) { 1594 /* XXX: not done yet */ 1595 } else { 1596 uint16_t ptr; 1597 int n; 1598 1599 ptr = GETBIOS16(sc, 0x48); 1600 ptr = GETBIOS16(sc, ptr + 0x34); 1601 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1602 if (GETBIOS8(sc, ptr) == 3) { 1603 /* revision three table */ 1604 n = GETBIOS8(sc, ptr + 5) + 1; 1605 n = min(n, 4); 1606 1607 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1608 for (i = 0; i < n; i++) { 1609 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1610 ptr + i * 10 + 8); 1611 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1612 ptr + i * 10 + 0x10); 1613 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1614 sc->sc_tmds_pll[i].rtp_freq, 1615 sc->sc_tmds_pll[i].rtp_pll)); 1616 } 1617 return 0; 1618 } 1619 } 1620 1621 nobios: 1622 DPRINTF(("no suitable DFP table present\n")); 1623 for (i = 0; 1624 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1625 i++) { 1626 int j; 1627 1628 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1629 continue; 1630 1631 for (j = 0; j < 4; j++) { 1632 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1633 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1634 sc->sc_tmds_pll[j].rtp_freq, 1635 sc->sc_tmds_pll[j].rtp_pll)); 1636 } 1637 return 0; 1638 } 1639 1640 return -1; 1641 } 1642 1643 const struct videomode * 1644 radeonfb_modelookup(const char *name) 1645 { 1646 int i; 1647 1648 for (i = 0; i < videomode_count; i++) 1649 if (!strcmp(name, videomode_list[i].name)) 1650 return &videomode_list[i]; 1651 1652 return NULL; 1653 } 1654 1655 void 1656 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1657 { 1658 if (crtc) { 1659 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1660 RADEON_P2PLL_ATOMIC_UPDATE_R); 1661 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1662 } else { 1663 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1664 RADEON_PPLL_ATOMIC_UPDATE_R); 1665 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1666 } 1667 } 1668 1669 void 1670 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1671 { 1672 int i; 1673 1674 for (i = 10000; i; i--) { 1675 if (crtc) { 1676 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1677 RADEON_P2PLL_ATOMIC_UPDATE_R) 1678 break; 1679 } else { 1680 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1681 RADEON_PPLL_ATOMIC_UPDATE_R) 1682 break; 1683 } 1684 } 1685 } 1686 1687 void 1688 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1689 { 1690 uint32_t pbit = 0; 1691 uint32_t feed = 0; 1692 uint32_t data; 1693 #if 1 1694 int i; 1695 #endif 1696 1697 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1698 1699 if (crtc == 0) { 1700 1701 /* XXXX: mobility workaround missing */ 1702 /* XXXX: R300 stuff missing */ 1703 1704 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1705 RADEON_VCLK_SRC_SEL_CPUCLK, 1706 ~RADEON_VCLK_SRC_SEL_MASK); 1707 1708 /* put vclk into reset, use atomic updates */ 1709 SETPLL(sc, RADEON_PPLL_CNTL, 1710 RADEON_PPLL_REFCLK_SEL | 1711 RADEON_PPLL_FBCLK_SEL | 1712 RADEON_PPLL_RESET | 1713 RADEON_PPLL_ATOMIC_UPDATE_EN | 1714 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1715 1716 /* select clock 3 */ 1717 #if 0 1718 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1719 ~RADEON_PLL_DIV_SEL); 1720 #else 1721 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1722 ~RADEON_PLL_DIV_SEL); 1723 #endif 1724 1725 /* XXX: R300 family -- program divider differently? */ 1726 1727 /* program reference divider */ 1728 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1729 ~RADEON_PPLL_REF_DIV_MASK); 1730 PRINTPLL(RADEON_PPLL_REF_DIV); 1731 1732 #if 0 1733 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1734 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1735 RADEON_PPLL_POST3_DIV_MASK); 1736 data |= pbit; 1737 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1738 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1739 #else 1740 for (i = 0; i < 4; i++) { 1741 } 1742 #endif 1743 1744 /* use the atomic update */ 1745 radeonfb_pllwriteupdate(sc, crtc); 1746 1747 /* and wait for it to complete */ 1748 radeonfb_pllwaitatomicread(sc, crtc); 1749 1750 /* program HTOTAL (why?) */ 1751 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1752 1753 /* drop reset */ 1754 CLRPLL(sc, RADEON_PPLL_CNTL, 1755 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1756 RADEON_PPLL_ATOMIC_UPDATE_EN | 1757 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1758 1759 PRINTPLL(RADEON_PPLL_CNTL); 1760 1761 /* give clock time to lock */ 1762 delay(50000); 1763 1764 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1765 RADEON_VCLK_SRC_SEL_PPLLCLK, 1766 ~RADEON_VCLK_SRC_SEL_MASK); 1767 1768 } else { 1769 1770 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1771 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1772 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1773 1774 /* put vclk into reset, use atomic updates */ 1775 SETPLL(sc, RADEON_P2PLL_CNTL, 1776 RADEON_P2PLL_RESET | 1777 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1778 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1779 1780 /* XXX: R300 family -- program divider differently? */ 1781 1782 /* program reference divider */ 1783 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1784 ~RADEON_P2PLL_REF_DIV_MASK); 1785 1786 /* program feedback and post dividers */ 1787 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1788 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1789 RADEON_P2PLL_POST0_DIV_MASK); 1790 data |= pbit; 1791 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1792 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1793 1794 /* use the atomic update */ 1795 radeonfb_pllwriteupdate(sc, crtc); 1796 1797 /* and wait for it to complete */ 1798 radeonfb_pllwaitatomicread(sc, crtc); 1799 1800 /* program HTOTAL (why?) */ 1801 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1802 1803 /* drop reset */ 1804 CLRPLL(sc, RADEON_P2PLL_CNTL, 1805 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1806 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1807 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1808 1809 /* allow time for clock to lock */ 1810 delay(50000); 1811 1812 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1813 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1814 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1815 } 1816 PRINTREG(RADEON_CRTC_MORE_CNTL); 1817 } 1818 1819 void 1820 radeonfb_modeswitch(struct radeonfb_display *dp) 1821 { 1822 struct radeonfb_softc *sc = dp->rd_softc; 1823 int i; 1824 1825 /* blank the display while we switch modes */ 1826 //radeonfb_blank(dp, 1); 1827 1828 #if 0 1829 SET32(sc, RADEON_CRTC_EXT_CNTL, 1830 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1831 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1832 #endif 1833 1834 /* these registers might get in the way... */ 1835 PUT32(sc, RADEON_OVR_CLR, 0); 1836 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1837 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1838 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1839 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1840 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1841 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1842 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1843 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1844 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1845 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1846 1847 for (i = 0; i < dp->rd_ncrtcs; i++) 1848 radeonfb_setcrtc(dp, i); 1849 1850 /* activate the display */ 1851 //radeonfb_blank(dp, 0); 1852 } 1853 1854 void 1855 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1856 { 1857 int crtc; 1858 struct videomode *mode; 1859 struct radeonfb_softc *sc; 1860 struct radeonfb_crtc *cp; 1861 uint32_t v; 1862 uint32_t gencntl; 1863 uint32_t htotaldisp; 1864 uint32_t hsyncstrt; 1865 uint32_t vtotaldisp; 1866 uint32_t vsyncstrt; 1867 uint32_t fphsyncstrt; 1868 uint32_t fpvsyncstrt; 1869 uint32_t fphtotaldisp; 1870 uint32_t fpvtotaldisp; 1871 uint32_t pitch; 1872 1873 sc = dp->rd_softc; 1874 cp = &dp->rd_crtcs[index]; 1875 crtc = cp->rc_number; 1876 mode = &cp->rc_videomode; 1877 1878 #if 1 1879 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1880 (dp->rd_bpp * 8)); 1881 #else 1882 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1883 (sc->sc_maxbpp * 8)); 1884 #endif 1885 //pitch = pitch | (pitch << 16); 1886 1887 switch (crtc) { 1888 case 0: 1889 gencntl = RADEON_CRTC_GEN_CNTL; 1890 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1891 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1892 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1893 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1894 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1895 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1896 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1897 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1898 break; 1899 case 1: 1900 gencntl = RADEON_CRTC2_GEN_CNTL; 1901 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1902 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1903 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1904 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1905 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1906 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1907 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1908 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1909 break; 1910 default: 1911 panic("Bad CRTC!"); 1912 break; 1913 } 1914 1915 /* 1916 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1917 */ 1918 /* only bother with 32bpp and 8bpp */ 1919 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1920 1921 if (crtc == 1) { 1922 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1923 } else { 1924 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1925 } 1926 1927 if (mode->flags & VID_DBLSCAN) 1928 v |= RADEON_CRTC2_DBL_SCAN_EN; 1929 1930 if (mode->flags & VID_INTERLACE) 1931 v |= RADEON_CRTC2_INTERLACE_EN; 1932 1933 if (mode->flags & VID_CSYNC) { 1934 v |= RADEON_CRTC2_CSYNC_EN; 1935 if (crtc == 1) 1936 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1937 } 1938 1939 PUT32(sc, gencntl, v); 1940 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1941 1942 /* 1943 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1944 */ 1945 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1946 if (crtc == 0) { 1947 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1948 RADEON_CRTC_DISPLAY_DIS); 1949 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1950 if (mode->flags & VID_CSYNC) 1951 v |= RADEON_CRTC_VSYNC_TRISTAT; 1952 } 1953 /* unconditional turn on CRT, in case first CRTC is DFP */ 1954 v |= RADEON_CRTC_CRT_ON; 1955 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1956 PRINTREG(RADEON_CRTC_EXT_CNTL); 1957 1958 /* 1959 * H_TOTAL_DISP 1960 */ 1961 v = ((mode->hdisplay / 8) - 1) << 16; 1962 v |= (mode->htotal / 8) - 1; 1963 PUT32(sc, htotaldisp, v); 1964 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1965 PUT32(sc, fphtotaldisp, v); 1966 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1967 1968 /* 1969 * H_SYNC_STRT_WID 1970 */ 1971 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1972 v |= mode->hsync_start; 1973 if (mode->flags & VID_NHSYNC) 1974 v |= RADEON_CRTC_H_SYNC_POL; 1975 PUT32(sc, hsyncstrt, v); 1976 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1977 PUT32(sc, fphsyncstrt, v); 1978 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1979 1980 /* 1981 * V_TOTAL_DISP 1982 */ 1983 v = ((mode->vdisplay - 1) << 16); 1984 v |= (mode->vtotal - 1); 1985 PUT32(sc, vtotaldisp, v); 1986 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1987 PUT32(sc, fpvtotaldisp, v); 1988 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1989 1990 /* 1991 * V_SYNC_STRT_WID 1992 */ 1993 v = ((mode->vsync_end - mode->vsync_start) << 16); 1994 v |= (mode->vsync_start - 1); 1995 if (mode->flags & VID_NVSYNC) 1996 v |= RADEON_CRTC_V_SYNC_POL; 1997 PUT32(sc, vsyncstrt, v); 1998 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1999 PUT32(sc, fpvsyncstrt, v); 2000 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2001 2002 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2003 2004 switch (crtc) { 2005 case 0: 2006 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2007 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2008 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2009 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2010 2011 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2012 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2013 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2014 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2015 PRINTREG(RADEON_CRTC_EXT_CNTL); 2016 PRINTREG(RADEON_CRTC_GEN_CNTL); 2017 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2018 break; 2019 2020 case 1: 2021 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2022 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2023 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2024 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2025 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2026 RADEON_CRTC2_VSYNC_DIS | 2027 RADEON_CRTC2_HSYNC_DIS | 2028 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2029 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2030 break; 2031 } 2032 } 2033 2034 int 2035 radeonfb_isblank(struct radeonfb_display *dp) 2036 { 2037 uint32_t reg, mask; 2038 2039 if (dp->rd_crtcs[0].rc_number) { 2040 reg = RADEON_CRTC2_GEN_CNTL; 2041 mask = RADEON_CRTC2_DISP_DIS; 2042 } else { 2043 reg = RADEON_CRTC_EXT_CNTL; 2044 mask = RADEON_CRTC_DISPLAY_DIS; 2045 } 2046 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2047 } 2048 2049 void 2050 radeonfb_blank(struct radeonfb_display *dp, int blank) 2051 { 2052 struct radeonfb_softc *sc = dp->rd_softc; 2053 uint32_t reg, mask; 2054 uint32_t fpreg, fpval; 2055 int i; 2056 2057 for (i = 0; i < dp->rd_ncrtcs; i++) { 2058 2059 if (dp->rd_crtcs[i].rc_number) { 2060 reg = RADEON_CRTC2_GEN_CNTL; 2061 mask = RADEON_CRTC2_DISP_DIS; 2062 fpreg = RADEON_FP2_GEN_CNTL; 2063 fpval = RADEON_FP2_ON; 2064 } else { 2065 reg = RADEON_CRTC_EXT_CNTL; 2066 mask = RADEON_CRTC_DISPLAY_DIS; 2067 fpreg = RADEON_FP_GEN_CNTL; 2068 fpval = RADEON_FP_FPON; 2069 } 2070 2071 if (blank) { 2072 SET32(sc, reg, mask); 2073 CLR32(sc, fpreg, fpval); 2074 } else { 2075 CLR32(sc, reg, mask); 2076 SET32(sc, fpreg, fpval); 2077 } 2078 } 2079 PRINTREG(RADEON_FP_GEN_CNTL); 2080 PRINTREG(RADEON_FP2_GEN_CNTL); 2081 } 2082 2083 void 2084 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2085 long *defattr) 2086 { 2087 struct radeonfb_display *dp = cookie; 2088 struct rasops_info *ri = &scr->scr_ri; 2089 2090 /* initialize font subsystem */ 2091 wsfont_init(); 2092 2093 DPRINTF(("init screen called, existing %d\n", existing)); 2094 2095 ri->ri_depth = dp->rd_bpp; 2096 ri->ri_width = dp->rd_virtx; 2097 ri->ri_height = dp->rd_virty; 2098 ri->ri_stride = dp->rd_stride; 2099 ri->ri_flg = RI_CENTER; 2100 ri->ri_bits = (void *)dp->rd_fbptr; 2101 2102 /* XXX: 32 bpp only */ 2103 /* this is rgb in "big-endian order..." */ 2104 ri->ri_rnum = 8; 2105 ri->ri_gnum = 8; 2106 ri->ri_bnum = 8; 2107 ri->ri_rpos = 16; 2108 ri->ri_gpos = 8; 2109 ri->ri_bpos = 0; 2110 2111 if (existing) { 2112 ri->ri_flg |= RI_CLEAR; 2113 2114 /* start a modeswitch now */ 2115 radeonfb_modeswitch(dp); 2116 } 2117 2118 /* 2119 * XXX: font selection should be based on properties, with some 2120 * normal/reasonable default. 2121 */ 2122 ri->ri_caps = WSSCREEN_WSCOLORS; 2123 2124 /* initialize and look for an initial font */ 2125 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2126 2127 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2128 dp->rd_virtx / ri->ri_font->fontwidth); 2129 2130 /* enable acceleration */ 2131 ri->ri_ops.copyrows = radeonfb_copyrows; 2132 ri->ri_ops.copycols = radeonfb_copycols; 2133 ri->ri_ops.eraserows = radeonfb_eraserows; 2134 ri->ri_ops.erasecols = radeonfb_erasecols; 2135 ri->ri_ops.allocattr = radeonfb_allocattr; 2136 ri->ri_ops.putchar = radeonfb_putchar; 2137 ri->ri_ops.cursor = radeonfb_cursor; 2138 } 2139 2140 void 2141 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2142 { 2143 uint32_t gen, ext, gen2 = 0; 2144 uint32_t agploc, aperbase, apersize, mcfbloc; 2145 2146 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2147 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2148 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2149 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2150 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2151 2152 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2153 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2154 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2155 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2156 2157 if (HAS_CRTC2(sc)) { 2158 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2159 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2160 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2161 } 2162 2163 delay(100000); 2164 2165 mcfbloc = (aperbase >> 16) | 2166 ((aperbase + (apersize - 1)) & 0xffff0000); 2167 2168 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2169 sc->sc_memsz = apersize; 2170 2171 if (((agploc & 0xffff) << 16) != 2172 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2173 agploc = mcfbloc & 0xffff0000U; 2174 agploc |= ((agploc + 0x10000) >> 16); 2175 } 2176 2177 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2178 2179 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2180 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2181 2182 DPRINTF(("aperbase = %u\n", aperbase)); 2183 PRINTREG(RADEON_MC_FB_LOCATION); 2184 PRINTREG(RADEON_MC_AGP_LOCATION); 2185 2186 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2187 2188 if (HAS_CRTC2(sc)) 2189 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2190 2191 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2192 2193 #if 0 2194 /* XXX: what is this AGP garbage? :-) */ 2195 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2196 #endif 2197 2198 delay(100000); 2199 2200 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2201 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2202 2203 if (HAS_CRTC2(sc)) 2204 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2205 } 2206 2207 void 2208 radeonfb_init_misc(struct radeonfb_softc *sc) 2209 { 2210 PUT32(sc, RADEON_BUS_CNTL, 2211 RADEON_BUS_MASTER_DIS | 2212 RADEON_BUS_PREFETCH_MODE_ACT | 2213 RADEON_BUS_PCI_READ_RETRY_EN | 2214 RADEON_BUS_PCI_WRT_RETRY_EN | 2215 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2216 RADEON_BUS_MSTR_RD_MULT | 2217 RADEON_BUS_MSTR_RD_LINE | 2218 RADEON_BUS_RD_DISCARD_EN | 2219 RADEON_BUS_MSTR_DISCONNECT_EN | 2220 RADEON_BUS_READ_BURST); 2221 2222 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2223 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2224 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2225 PUT32(sc, RADEON_RBBM_CNTL, 2226 (3 << RADEON_RB_SETTLE_SHIFT) | 2227 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2228 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2229 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2230 2231 /* XXX: figure out what these mean! */ 2232 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2233 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2234 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2235 2236 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2237 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2238 } 2239 2240 /* 2241 * This loads a linear color map for true color. 2242 */ 2243 void 2244 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2245 { 2246 int i; 2247 uint32_t vclk; 2248 2249 #define DAC_WIDTH ((1 << 10) - 1) 2250 #define CLUT_WIDTH ((1 << 8) - 1) 2251 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2252 2253 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2254 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2255 2256 if (crtc) 2257 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2258 else 2259 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2260 2261 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2262 for (i = 0; i <= CLUT_WIDTH; ++i) { 2263 PUT32(sc, RADEON_PALETTE_30_DATA, 2264 (CLUT_COLOR(i) << 10) | 2265 (CLUT_COLOR(i) << 20) | 2266 (CLUT_COLOR(i))); 2267 } 2268 2269 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2270 PRINTREG(RADEON_DAC_CNTL2); 2271 2272 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2273 } 2274 2275 /* 2276 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2277 */ 2278 void 2279 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2280 { 2281 uint32_t tmp, save; 2282 2283 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2284 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2285 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2286 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2287 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2288 } 2289 2290 /* 2291 * Acceleration entry points. 2292 */ 2293 static void 2294 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2295 { 2296 struct rasops_info *ri = cookie; 2297 struct vcons_screen *scr = ri->ri_hw; 2298 struct radeonfb_display *dp = scr->scr_cookie; 2299 uint32_t x, y, w, h; 2300 uint32_t bg, fg; 2301 uint8_t *data; 2302 2303 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2304 return; 2305 2306 if (!CHAR_IN_FONT(c, ri->ri_font)) 2307 return; 2308 2309 w = ri->ri_font->fontwidth; 2310 h = ri->ri_font->fontheight; 2311 2312 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2313 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2314 2315 x = ri->ri_xorigin + col * w; 2316 y = ri->ri_yorigin + row * h; 2317 2318 if (c == 0x20) { 2319 radeonfb_rectfill(dp, x, y, w, h, bg); 2320 } else { 2321 data = (uint8_t *)ri->ri_font->data + 2322 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2323 2324 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2325 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2326 } 2327 } 2328 2329 static void 2330 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2331 { 2332 struct rasops_info *ri = cookie; 2333 struct vcons_screen *scr = ri->ri_hw; 2334 struct radeonfb_display *dp = scr->scr_cookie; 2335 uint32_t x, y, w, h, fg, bg, ul; 2336 2337 /* XXX: check for full emulation mode? */ 2338 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2339 x = ri->ri_xorigin; 2340 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2341 w = ri->ri_emuwidth; 2342 h = ri->ri_font->fontheight * nrows; 2343 2344 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2345 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2346 } 2347 } 2348 2349 static void 2350 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2351 { 2352 struct rasops_info *ri = cookie; 2353 struct vcons_screen *scr = ri->ri_hw; 2354 struct radeonfb_display *dp = scr->scr_cookie; 2355 uint32_t x, ys, yd, w, h; 2356 2357 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2358 x = ri->ri_xorigin; 2359 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2360 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2361 w = ri->ri_emuwidth; 2362 h = ri->ri_font->fontheight * nrows; 2363 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2364 RADEON_ROP3_S, 0xffffffff); 2365 } 2366 } 2367 2368 static void 2369 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2370 { 2371 struct rasops_info *ri = cookie; 2372 struct vcons_screen *scr = ri->ri_hw; 2373 struct radeonfb_display *dp = scr->scr_cookie; 2374 uint32_t xs, xd, y, w, h; 2375 2376 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2377 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2378 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2379 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2380 w = ri->ri_font->fontwidth * ncols; 2381 h = ri->ri_font->fontheight; 2382 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2383 RADEON_ROP3_S, 0xffffffff); 2384 } 2385 } 2386 2387 static void 2388 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2389 long fillattr) 2390 { 2391 struct rasops_info *ri = cookie; 2392 struct vcons_screen *scr = ri->ri_hw; 2393 struct radeonfb_display *dp = scr->scr_cookie; 2394 uint32_t x, y, w, h, fg, bg, ul; 2395 2396 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2397 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2398 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2399 w = ri->ri_font->fontwidth * ncols; 2400 h = ri->ri_font->fontheight; 2401 2402 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2403 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2404 } 2405 } 2406 2407 static void 2408 radeonfb_cursor(void *cookie, int on, int row, int col) 2409 { 2410 struct rasops_info *ri = cookie; 2411 struct vcons_screen *scr = ri->ri_hw; 2412 struct radeonfb_display *dp = scr->scr_cookie; 2413 int x, y, wi, he; 2414 2415 wi = ri->ri_font->fontwidth; 2416 he = ri->ri_font->fontheight; 2417 2418 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2419 x = ri->ri_ccol * wi + ri->ri_xorigin; 2420 y = ri->ri_crow * he + ri->ri_yorigin; 2421 /* first turn off the old cursor */ 2422 if (ri->ri_flg & RI_CURSOR) { 2423 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2424 RADEON_ROP3_Dn, 0xffffffff); 2425 ri->ri_flg &= ~RI_CURSOR; 2426 } 2427 ri->ri_crow = row; 2428 ri->ri_ccol = col; 2429 /* then (possibly) turn on the new one */ 2430 if (on) { 2431 x = ri->ri_ccol * wi + ri->ri_xorigin; 2432 y = ri->ri_crow * he + ri->ri_yorigin; 2433 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2434 RADEON_ROP3_Dn, 0xffffffff); 2435 ri->ri_flg |= RI_CURSOR; 2436 } 2437 } else { 2438 scr->scr_ri.ri_crow = row; 2439 scr->scr_ri.ri_ccol = col; 2440 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2441 } 2442 } 2443 2444 static int 2445 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2446 { 2447 if ((fg == 0) && (bg == 0)) { 2448 fg = WS_DEFAULT_FG; 2449 bg = WS_DEFAULT_BG; 2450 } 2451 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2452 return 0; 2453 } 2454 2455 /* 2456 * Underlying acceleration support. 2457 */ 2458 static void 2459 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2460 int height, uint32_t fg, uint32_t bg) 2461 { 2462 struct radeonfb_softc *sc = dp->rd_softc; 2463 uint32_t gmc; 2464 uint32_t padded_width = (width+7) & 0xfff8; 2465 uint32_t topleft, bottomright; 2466 2467 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2468 2469 if (width != padded_width) { 2470 2471 radeonfb_wait_fifo(sc, 2); 2472 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2473 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2474 ((xd + width) & 0x1fff); 2475 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2476 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2477 } 2478 2479 radeonfb_wait_fifo(sc, 5); 2480 2481 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2482 RADEON_GMC_BRUSH_NONE | 2483 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2484 //RADEON_GMC_BYTE_LSB_TO_MSB | 2485 RADEON_GMC_DST_CLIPPING | 2486 RADEON_ROP3_S | 2487 RADEON_DP_SRC_SOURCE_HOST_DATA | 2488 RADEON_GMC_CLR_CMP_CNTL_DIS | 2489 RADEON_GMC_WR_MSK_DIS | 2490 gmc); 2491 2492 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2493 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2494 2495 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2496 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2497 2498 } 2499 2500 static void 2501 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2502 { 2503 struct radeonfb_softc *sc = dp->rd_softc; 2504 int i; 2505 uint32_t latch = 0; 2506 int shift = 0; 2507 2508 for (i = 0; i < count; i++) { 2509 latch |= (data[i] << shift); 2510 if (shift == 24) { 2511 radeonfb_wait_fifo(sc, 1); 2512 PUT32(sc, RADEON_HOST_DATA0, latch); 2513 latch = 0; 2514 shift = 0; 2515 } else 2516 shift += 8; 2517 } 2518 if (shift != 0) { 2519 radeonfb_wait_fifo(sc, 1); 2520 PUT32(sc, RADEON_HOST_DATA0, latch); 2521 } 2522 radeonfb_unclip(sc); 2523 } 2524 2525 static void 2526 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2527 int width, int height, uint32_t color) 2528 { 2529 struct radeonfb_softc *sc = dp->rd_softc; 2530 uint32_t gmc; 2531 2532 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2533 2534 radeonfb_wait_fifo(sc, 6); 2535 2536 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2537 RADEON_GMC_BRUSH_SOLID_COLOR | 2538 RADEON_GMC_SRC_DATATYPE_COLOR | 2539 RADEON_GMC_CLR_CMP_CNTL_DIS | 2540 RADEON_ROP3_P | gmc); 2541 2542 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2543 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2544 PUT32(sc, RADEON_DP_CNTL, 2545 RADEON_DST_X_LEFT_TO_RIGHT | 2546 RADEON_DST_Y_TOP_TO_BOTTOM); 2547 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2548 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2549 2550 /* 2551 * XXX: we don't wait for the fifo to empty -- that would slow 2552 * things down! The linux radeonfb driver waits, but xfree doesn't 2553 */ 2554 /* XXX: for now we do, to make it safe for direct drawing */ 2555 radeonfb_engine_idle(sc); 2556 } 2557 2558 static void 2559 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2560 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2561 { 2562 struct radeonfb_softc *sc = dp->rd_softc; 2563 uint32_t gmc; 2564 uint32_t dir; 2565 2566 if (dsty < srcy) { 2567 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2568 } else { 2569 srcy += height - 1; 2570 dsty += height - 1; 2571 dir = 0; 2572 } 2573 if (dstx < srcx) { 2574 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2575 } else { 2576 srcx += width - 1; 2577 dstx += width - 1; 2578 } 2579 2580 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2581 2582 radeonfb_wait_fifo(sc, 6); 2583 2584 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2585 //RADEON_GMC_SRC_CLIPPING | 2586 RADEON_GMC_BRUSH_SOLID_COLOR | 2587 RADEON_GMC_SRC_DATATYPE_COLOR | 2588 RADEON_GMC_CLR_CMP_CNTL_DIS | 2589 RADEON_DP_SRC_SOURCE_MEMORY | 2590 rop | gmc); 2591 2592 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2593 PUT32(sc, RADEON_DP_CNTL, dir); 2594 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2595 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2596 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2597 2598 /* 2599 * XXX: we don't wait for the fifo to empty -- that would slow 2600 * things down! The linux radeonfb driver waits, but xfree doesn't 2601 */ 2602 /* XXX: for now we do, to make it safe for direct drawing */ 2603 radeonfb_engine_idle(sc); 2604 } 2605 2606 static void 2607 radeonfb_engine_idle(struct radeonfb_softc *sc) 2608 { 2609 int i; 2610 2611 radeonfb_wait_fifo(sc, 64); 2612 for (i = RADEON_TIMEOUT; i; i--) { 2613 if ((GET32(sc, RADEON_RBBM_STATUS) & 2614 RADEON_RBBM_ACTIVE) == 0) { 2615 radeonfb_engine_flush(sc); 2616 break; 2617 } 2618 } 2619 } 2620 2621 static void 2622 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2623 { 2624 int i; 2625 2626 for (i = RADEON_TIMEOUT; i; i--) { 2627 if ((GET32(sc, RADEON_RBBM_STATUS) & 2628 RADEON_RBBM_FIFOCNT_MASK) >= n) 2629 return; 2630 } 2631 #ifdef DIAGNOSTIC 2632 if (!i) 2633 printf("%s: timed out waiting for fifo (%x)\n", 2634 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2635 #endif 2636 } 2637 2638 static void 2639 radeonfb_engine_flush(struct radeonfb_softc *sc) 2640 { 2641 int i; 2642 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2643 for (i = RADEON_TIMEOUT; i; i--) { 2644 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2645 RADEON_RB2D_DC_BUSY) == 0) 2646 break; 2647 } 2648 #ifdef DIAGNOSTIC 2649 if (!i) 2650 printf("%s: engine flush timed out!\n", XNAME(sc)); 2651 #endif 2652 } 2653 2654 static inline void 2655 radeonfb_unclip(struct radeonfb_softc *sc) 2656 { 2657 2658 radeonfb_wait_fifo(sc, 2); 2659 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2660 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2661 } 2662 2663 static void 2664 radeonfb_engine_init(struct radeonfb_display *dp) 2665 { 2666 struct radeonfb_softc *sc = dp->rd_softc; 2667 uint32_t pitch; 2668 2669 /* no 3D */ 2670 PUT32(sc, RADEON_RB3D_CNTL, 0); 2671 2672 radeonfb_engine_reset(sc); 2673 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2674 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2675 2676 radeonfb_wait_fifo(sc, 1); 2677 if (!IS_R300(sc)) 2678 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2679 2680 radeonfb_wait_fifo(sc, 3); 2681 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2682 (pitch << 22) | (sc->sc_aperbase >> 10)); 2683 2684 2685 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2686 (pitch << 22) | (sc->sc_aperbase >> 10)); 2687 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2688 (pitch << 22) | (sc->sc_aperbase >> 10)); 2689 2690 radeonfb_wait_fifo(sc, 1); 2691 #if _BYTE_ORDER == _BIG_ENDIAN 2692 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2693 #else 2694 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2695 #endif 2696 2697 /* default scissors -- no clipping */ 2698 radeonfb_wait_fifo(sc, 1); 2699 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2700 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2701 2702 radeonfb_wait_fifo(sc, 1); 2703 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2704 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2705 RADEON_GMC_CLR_CMP_CNTL_DIS | 2706 RADEON_GMC_BRUSH_SOLID_COLOR | 2707 RADEON_GMC_SRC_DATATYPE_COLOR); 2708 2709 radeonfb_wait_fifo(sc, 7); 2710 PUT32(sc, RADEON_DST_LINE_START, 0); 2711 PUT32(sc, RADEON_DST_LINE_END, 0); 2712 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2713 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2714 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2715 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2716 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2717 2718 radeonfb_engine_idle(sc); 2719 } 2720 2721 static void 2722 radeonfb_engine_reset(struct radeonfb_softc *sc) 2723 { 2724 uint32_t hpc, rbbm, mclkcntl, clkindex; 2725 2726 radeonfb_engine_flush(sc); 2727 2728 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2729 if (HAS_R300CG(sc)) 2730 radeonfb_r300cg_workaround(sc); 2731 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2732 2733 /* 2734 * According to comments in XFree code, resetting the HDP via 2735 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2736 * So we use HOST_PATH_CNTL instead. 2737 */ 2738 2739 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2740 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2741 if (IS_R300(sc)) { 2742 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2743 RADEON_SOFT_RESET_CP | 2744 RADEON_SOFT_RESET_HI | 2745 RADEON_SOFT_RESET_E2); 2746 GET32(sc, RADEON_RBBM_SOFT_RESET); 2747 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2748 /* 2749 * XXX: this bit is not defined in any ATI docs I have, 2750 * nor in the XFree code, but XFree does it. Why? 2751 */ 2752 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2753 } else { 2754 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2755 RADEON_SOFT_RESET_CP | 2756 RADEON_SOFT_RESET_SE | 2757 RADEON_SOFT_RESET_RE | 2758 RADEON_SOFT_RESET_PP | 2759 RADEON_SOFT_RESET_E2 | 2760 RADEON_SOFT_RESET_RB); 2761 GET32(sc, RADEON_RBBM_SOFT_RESET); 2762 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2763 ~(RADEON_SOFT_RESET_CP | 2764 RADEON_SOFT_RESET_SE | 2765 RADEON_SOFT_RESET_RE | 2766 RADEON_SOFT_RESET_PP | 2767 RADEON_SOFT_RESET_E2 | 2768 RADEON_SOFT_RESET_RB)); 2769 GET32(sc, RADEON_RBBM_SOFT_RESET); 2770 } 2771 2772 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2773 GET32(sc, RADEON_HOST_PATH_CNTL); 2774 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2775 2776 if (IS_R300(sc)) 2777 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2778 2779 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2780 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2781 2782 if (HAS_R300CG(sc)) 2783 radeonfb_r300cg_workaround(sc); 2784 } 2785 2786 static int 2787 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2788 { 2789 int x, y; 2790 2791 x = pos->x; 2792 y = pos->y; 2793 2794 /* 2795 * This doesn't let a cursor move off the screen. I'm not 2796 * sure if this will have negative effects for e.g. Xinerama. 2797 * I'd guess Xinerama handles it by changing the cursor shape, 2798 * but that needs verification. 2799 */ 2800 if (x >= dp->rd_virtx) 2801 x = dp->rd_virtx - 1; 2802 if (x < 0) 2803 x = 0; 2804 if (y >= dp->rd_virty) 2805 y = dp->rd_virty - 1; 2806 if (y < 0) 2807 y = 0; 2808 2809 dp->rd_cursor.rc_pos.x = x; 2810 dp->rd_cursor.rc_pos.y = y; 2811 2812 radeonfb_cursor_position(dp); 2813 return 0; 2814 } 2815 2816 static int 2817 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2818 { 2819 unsigned flags; 2820 2821 uint8_t r[2], g[2], b[2]; 2822 unsigned index, count; 2823 int i, err; 2824 int pitch, size; 2825 struct radeonfb_cursor nc; 2826 2827 flags = wc->which; 2828 2829 /* copy old values */ 2830 nc = dp->rd_cursor; 2831 2832 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2833 index = wc->cmap.index; 2834 count = wc->cmap.count; 2835 2836 if (index >= 2 || (index + count) > 2) 2837 return EINVAL; 2838 2839 err = copyin(wc->cmap.red, &r[index], count); 2840 if (err) 2841 return err; 2842 err = copyin(wc->cmap.green, &g[index], count); 2843 if (err) 2844 return err; 2845 err = copyin(wc->cmap.blue, &b[index], count); 2846 if (err) 2847 return err; 2848 2849 for (i = index; i < index + count; i++) { 2850 nc.rc_cmap[i] = 2851 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2852 } 2853 } 2854 2855 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2856 if ((wc->size.x > RADEON_CURSORMAXX) || 2857 (wc->size.y > RADEON_CURSORMAXY)) 2858 return EINVAL; 2859 2860 /* figure bytes per line */ 2861 pitch = (wc->size.x + 7) / 8; 2862 size = pitch * wc->size.y; 2863 2864 /* clear the old cursor and mask */ 2865 memset(nc.rc_image, 0, 512); 2866 memset(nc.rc_mask, 0, 512); 2867 2868 nc.rc_size = wc->size; 2869 2870 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2871 return err; 2872 2873 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2874 return err; 2875 } 2876 2877 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2878 nc.rc_hot = wc->hot; 2879 if (nc.rc_hot.x >= nc.rc_size.x) 2880 nc.rc_hot.x = nc.rc_size.x - 1; 2881 if (nc.rc_hot.y >= nc.rc_size.y) 2882 nc.rc_hot.y = nc.rc_size.y - 1; 2883 } 2884 2885 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2886 nc.rc_pos = wc->pos; 2887 if (nc.rc_pos.x >= dp->rd_virtx) 2888 nc.rc_pos.x = dp->rd_virtx - 1; 2889 #if 0 2890 if (nc.rc_pos.x < 0) 2891 nc.rc_pos.x = 0; 2892 #endif 2893 if (nc.rc_pos.y >= dp->rd_virty) 2894 nc.rc_pos.y = dp->rd_virty - 1; 2895 #if 0 2896 if (nc.rc_pos.y < 0) 2897 nc.rc_pos.y = 0; 2898 #endif 2899 } 2900 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2901 nc.rc_visible = wc->enable; 2902 } 2903 2904 dp->rd_cursor = nc; 2905 radeonfb_cursor_update(dp, wc->which); 2906 2907 return 0; 2908 } 2909 2910 /* 2911 * Change the cursor shape. Call this with the cursor locked to avoid 2912 * flickering/tearing. 2913 */ 2914 static void 2915 radeonfb_cursor_shape(struct radeonfb_display *dp) 2916 { 2917 uint8_t and[512], xor[512]; 2918 int i, j, src, dst, pitch; 2919 const uint8_t *msk = dp->rd_cursor.rc_mask; 2920 const uint8_t *img = dp->rd_cursor.rc_image; 2921 2922 /* 2923 * Radeon cursor data interleaves one line of AND data followed 2924 * by a line of XOR data. (Each line corresponds to a whole hardware 2925 * pitch - i.e. 64 pixels or 8 bytes.) 2926 * 2927 * The cursor is displayed using the following table: 2928 * 2929 * AND XOR Result 2930 * ---------------------- 2931 * 0 0 Cursor color 0 2932 * 0 1 Cursor color 1 2933 * 1 0 Transparent 2934 * 1 1 Complement of background 2935 * 2936 * Our masks are therefore different from what we were passed. 2937 * Passed in, I'm assuming the data represents either color 0 or 1, 2938 * and a mask, so the passed in table looks like: 2939 * 2940 * IMG Mask Result 2941 * ----------------------- 2942 * 0 0 Transparent 2943 * 0 1 Cursor color 0 2944 * 1 0 Transparent 2945 * 1 1 Cursor color 1 2946 * 2947 * IF mask bit == 1, AND = 0, XOR = color. 2948 * IF mask bit == 0, AND = 1, XOR = 0. 2949 * 2950 * hence: AND = ~(mask); XOR = color & ~(mask); 2951 */ 2952 2953 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2954 2955 /* start by assuming all bits are transparent */ 2956 memset(and, 0xff, 512); 2957 memset(xor, 0x00, 512); 2958 2959 src = 0; 2960 dst = 0; 2961 for (i = 0; i < 64; i++) { 2962 for (j = 0; j < 64; j += 8) { 2963 if ((i < dp->rd_cursor.rc_size.y) && 2964 (j < dp->rd_cursor.rc_size.x)) { 2965 2966 /* take care to leave odd bits alone */ 2967 and[dst] &= ~(msk[src]); 2968 xor[dst] = img[src] & msk[src]; 2969 src++; 2970 } 2971 dst++; 2972 } 2973 } 2974 2975 /* copy the image into place */ 2976 for (i = 0; i < 64; i++) { 2977 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2978 &and[i * 8], 8); 2979 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2980 &xor[i * 8], 8); 2981 } 2982 } 2983 2984 static void 2985 radeonfb_cursor_position(struct radeonfb_display *dp) 2986 { 2987 struct radeonfb_softc *sc = dp->rd_softc; 2988 uint32_t offset, hvoff, hvpos; /* registers */ 2989 uint32_t coff; /* cursor offset */ 2990 int i, x, y, xoff, yoff, crtcoff; 2991 2992 /* 2993 * XXX: this also needs to handle pan/scan 2994 */ 2995 for (i = 0; i < dp->rd_ncrtcs; i++) { 2996 2997 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2998 2999 if (rcp->rc_number) { 3000 offset = RADEON_CUR2_OFFSET; 3001 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3002 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3003 crtcoff = RADEON_CRTC2_OFFSET; 3004 } else { 3005 offset = RADEON_CUR_OFFSET; 3006 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3007 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3008 crtcoff = RADEON_CRTC_OFFSET; 3009 } 3010 3011 x = dp->rd_cursor.rc_pos.x; 3012 y = dp->rd_cursor.rc_pos.y; 3013 3014 while (y < rcp->rc_yoffset) { 3015 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3016 } 3017 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3018 rcp->rc_yoffset += RADEON_PANINCREMENT; 3019 } 3020 while (x < rcp->rc_xoffset) { 3021 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3022 } 3023 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3024 rcp->rc_xoffset += RADEON_PANINCREMENT; 3025 } 3026 3027 /* adjust for the cursor's hotspot */ 3028 x -= dp->rd_cursor.rc_hot.x; 3029 y -= dp->rd_cursor.rc_hot.y; 3030 xoff = yoff = 0; 3031 3032 if (x >= dp->rd_virtx) 3033 x = dp->rd_virtx - 1; 3034 if (y >= dp->rd_virty) 3035 y = dp->rd_virty - 1; 3036 3037 /* now adjust cursor so it is relative to viewport */ 3038 x -= rcp->rc_xoffset; 3039 y -= rcp->rc_yoffset; 3040 3041 /* 3042 * no need to check for fall off, because we should 3043 * never move off the screen entirely! 3044 */ 3045 coff = 0; 3046 if (x < 0) { 3047 xoff = -x; 3048 x = 0; 3049 } 3050 if (y < 0) { 3051 yoff = -y; 3052 y = 0; 3053 coff = (yoff * 2) * 8; 3054 } 3055 3056 /* pan the display */ 3057 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3058 rcp->rc_xoffset); 3059 3060 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3061 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3062 /* NB: this unlocks the cursor */ 3063 PUT32(sc, hvpos, (x << 16) | y); 3064 } 3065 } 3066 3067 static void 3068 radeonfb_cursor_visible(struct radeonfb_display *dp) 3069 { 3070 int i; 3071 uint32_t gencntl, bit; 3072 3073 for (i = 0; i < dp->rd_ncrtcs; i++) { 3074 if (dp->rd_crtcs[i].rc_number) { 3075 gencntl = RADEON_CRTC2_GEN_CNTL; 3076 bit = RADEON_CRTC2_CUR_EN; 3077 } else { 3078 gencntl = RADEON_CRTC_GEN_CNTL; 3079 bit = RADEON_CRTC_CUR_EN; 3080 } 3081 3082 if (dp->rd_cursor.rc_visible) 3083 SET32(dp->rd_softc, gencntl, bit); 3084 else 3085 CLR32(dp->rd_softc, gencntl, bit); 3086 } 3087 } 3088 3089 static void 3090 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3091 { 3092 int i; 3093 uint32_t c0reg, c1reg; 3094 struct radeonfb_softc *sc = dp->rd_softc; 3095 3096 for (i = 0; i < dp->rd_ncrtcs; i++) { 3097 if (dp->rd_crtcs[i].rc_number) { 3098 c0reg = RADEON_CUR2_CLR0; 3099 c1reg = RADEON_CUR2_CLR1; 3100 } else { 3101 c0reg = RADEON_CUR_CLR0; 3102 c1reg = RADEON_CUR_CLR1; 3103 } 3104 3105 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3106 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3107 } 3108 } 3109 3110 static void 3111 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3112 { 3113 struct radeonfb_softc *sc; 3114 int i; 3115 3116 sc = dp->rd_softc; 3117 for (i = 0; i < dp->rd_ncrtcs; i++) { 3118 if (dp->rd_crtcs[i].rc_number) { 3119 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3120 } else { 3121 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3122 } 3123 } 3124 3125 if (which & WSDISPLAY_CURSOR_DOCMAP) 3126 radeonfb_cursor_cmap(dp); 3127 3128 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3129 radeonfb_cursor_shape(dp); 3130 3131 if (which & WSDISPLAY_CURSOR_DOCUR) 3132 radeonfb_cursor_visible(dp); 3133 3134 /* this one is unconditional, because it updates other stuff */ 3135 radeonfb_cursor_position(dp); 3136 } 3137 3138 static struct videomode * 3139 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3140 { 3141 int r1, r2; 3142 3143 /* otherwise pick the higher refresh rate */ 3144 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3145 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3146 3147 return (r1 < r2 ? m2 : m1); 3148 } 3149 3150 static const struct videomode * 3151 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3152 int x, int y) 3153 { 3154 struct edid_info *ep = &rp->rp_edid; 3155 struct videomode *vmp = NULL; 3156 int i; 3157 3158 if (!rp->rp_edid_valid) { 3159 /* fallback to safe mode */ 3160 return radeonfb_modelookup(sc->sc_defaultmode); 3161 } 3162 3163 /* always choose the preferred mode first! */ 3164 if (ep->edid_preferred_mode) { 3165 3166 /* XXX: add auto-stretching support for native mode */ 3167 3168 /* this may want panning to occur, btw */ 3169 if ((ep->edid_preferred_mode->hdisplay <= x) && 3170 (ep->edid_preferred_mode->vdisplay <= y)) 3171 return ep->edid_preferred_mode; 3172 } 3173 3174 for (i = 0; i < ep->edid_nmodes; i++) { 3175 /* 3176 * We elect to pick a resolution that is too large for 3177 * the monitor than one that is too small. This means 3178 * that we will prefer to pan rather than to try to 3179 * center a smaller display on a larger screen. In 3180 * practice, this shouldn't matter because if a 3181 * monitor can support a larger resolution, it can 3182 * probably also support the smaller. A specific 3183 * exception is fixed format panels, but hopefully 3184 * they are properly dealt with by the "autostretch" 3185 * logic above. 3186 */ 3187 if ((ep->edid_modes[i].hdisplay > x) || 3188 (ep->edid_modes[i].vdisplay > y)) { 3189 continue; 3190 } 3191 3192 /* 3193 * at this point, the display mode is no larger than 3194 * what we've requested. 3195 */ 3196 if (vmp == NULL) 3197 vmp = &ep->edid_modes[i]; 3198 3199 /* eliminate smaller modes */ 3200 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3201 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3202 continue; 3203 3204 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3205 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3206 vmp = &ep->edid_modes[i]; 3207 continue; 3208 } 3209 3210 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3211 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3212 3213 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3214 } 3215 3216 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3217 } 3218 3219 static int 3220 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3221 { 3222 int i; 3223 3224 for (i = 0; i < nlist; i++) { 3225 if ((x == list[i].hdisplay) && 3226 (y == list[i].vdisplay)) { 3227 return 1; 3228 } 3229 } 3230 return 0; 3231 } 3232 3233 static void 3234 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3235 int pan) 3236 { 3237 struct radeonfb_port *rp; 3238 struct edid_info *ep; 3239 int i, j; 3240 3241 *x = 0; 3242 *y = 0; 3243 3244 if (pan) { 3245 for (i = 0; i < dp->rd_ncrtcs; i++) { 3246 rp = dp->rd_crtcs[i].rc_port; 3247 ep = &rp->rp_edid; 3248 if (!rp->rp_edid_valid) { 3249 /* monitor not present */ 3250 continue; 3251 } 3252 3253 /* 3254 * For now we are ignoring "conflict" that 3255 * could occur when mixing some modes like 3256 * 1280x1024 and 1400x800. It isn't clear 3257 * which is better, so the first one wins. 3258 */ 3259 for (j = 0; j < ep->edid_nmodes; j++) { 3260 /* 3261 * ignore resolutions that are too big for 3262 * the radeon 3263 */ 3264 if (ep->edid_modes[j].hdisplay > 3265 dp->rd_softc->sc_maxx) 3266 continue; 3267 if (ep->edid_modes[j].vdisplay > 3268 dp->rd_softc->sc_maxy) 3269 continue; 3270 3271 /* 3272 * pick largest resolution, the 3273 * smaller monitor will pan 3274 */ 3275 if ((ep->edid_modes[j].hdisplay >= *x) && 3276 (ep->edid_modes[j].vdisplay >= *y)) { 3277 *x = ep->edid_modes[j].hdisplay; 3278 *y = ep->edid_modes[j].vdisplay; 3279 } 3280 } 3281 } 3282 3283 } else { 3284 struct videomode modes[64]; 3285 int nmodes = 0; 3286 int valid = 0; 3287 3288 for (i = 0; i < dp->rd_ncrtcs; i++) { 3289 /* 3290 * pick the largest resolution in common. 3291 */ 3292 rp = dp->rd_crtcs[i].rc_port; 3293 ep = &rp->rp_edid; 3294 3295 if (!rp->rp_edid_valid) 3296 continue; 3297 3298 if (!valid) { 3299 /* initialize starting list */ 3300 for (j = 0; j < ep->edid_nmodes; j++) { 3301 /* 3302 * ignore resolutions that are 3303 * too big for the radeon 3304 */ 3305 if (ep->edid_modes[j].hdisplay > 3306 dp->rd_softc->sc_maxx) 3307 continue; 3308 if (ep->edid_modes[j].vdisplay > 3309 dp->rd_softc->sc_maxy) 3310 continue; 3311 3312 modes[nmodes] = ep->edid_modes[j]; 3313 nmodes++; 3314 } 3315 valid = 1; 3316 } else { 3317 /* merge into preexisting list */ 3318 for (j = 0; j < nmodes; j++) { 3319 if (!radeonfb_hasres(ep->edid_modes, 3320 ep->edid_nmodes, 3321 modes[j].hdisplay, 3322 modes[j].vdisplay)) { 3323 modes[j] = modes[nmodes]; 3324 j--; 3325 nmodes--; 3326 } 3327 } 3328 } 3329 } 3330 3331 /* now we have to pick from the merged list */ 3332 for (i = 0; i < nmodes; i++) { 3333 if ((modes[i].hdisplay >= *x) && 3334 (modes[i].vdisplay >= *y)) { 3335 *x = modes[i].hdisplay; 3336 *y = modes[i].vdisplay; 3337 } 3338 } 3339 } 3340 3341 if ((*x == 0) || (*y == 0)) { 3342 /* fallback to safe mode */ 3343 *x = 640; 3344 *y = 480; 3345 } 3346 } 3347 3348 /* 3349 * backlight levels are linear on: 3350 * - RV200, RV250, RV280, RV350 3351 * - but NOT on PowerBook4,3 6,3 6,5 3352 * according to Linux' radeonfb 3353 */ 3354 3355 /* Get the current backlight level for the display. */ 3356 3357 static int 3358 radeonfb_get_backlight(struct radeonfb_display *dp) 3359 { 3360 int s; 3361 uint32_t level; 3362 3363 s = spltty(); 3364 3365 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3366 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3367 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3368 3369 /* 3370 * On some chips, we should negate the backlight level. 3371 * XXX Find out on which chips. 3372 */ 3373 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3374 level = RADEONFB_BACKLIGHT_MAX - level; 3375 3376 splx(s); 3377 3378 return level; 3379 } 3380 3381 /* Set the backlight to the given level for the display. */ 3382 3383 static int 3384 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3385 { 3386 struct radeonfb_softc *sc; 3387 int rlevel, s; 3388 uint32_t lvds; 3389 3390 s = spltty(); 3391 3392 if (level < 0) 3393 level = 0; 3394 else if (level >= RADEONFB_BACKLIGHT_MAX) 3395 level = RADEONFB_BACKLIGHT_MAX; 3396 3397 sc = dp->rd_softc; 3398 3399 /* On some chips, we should negate the backlight level. */ 3400 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 3401 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3402 } else 3403 rlevel = level; 3404 3405 callout_stop(&dp->rd_bl_lvds_co); 3406 radeonfb_engine_idle(sc); 3407 3408 /* 3409 * Turn off the display if the backlight is set to 0, since the 3410 * display is useless without backlight anyway. 3411 */ 3412 if (level == 0) 3413 radeonfb_blank(dp, 1); 3414 else if (radeonfb_get_backlight(dp) == 0) 3415 radeonfb_blank(dp, 0); 3416 3417 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3418 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3419 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3420 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3421 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3422 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3423 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3424 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3425 lvds |= RADEON_LVDS_ON; 3426 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3427 } else { 3428 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3429 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3430 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3431 } 3432 3433 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3434 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3435 /* XXX What is the correct delay? */ 3436 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3437 3438 splx(s); 3439 3440 return 0; 3441 } 3442 3443 /* 3444 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3445 * Set the delayed bits in the register, and clear the stored delayed 3446 * value. 3447 */ 3448 3449 static void radeonfb_lvds_callout(void *arg) 3450 { 3451 struct radeonfb_display *dp = arg; 3452 int s; 3453 3454 s = splhigh(); 3455 3456 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3457 dp->rd_bl_lvds_val); 3458 dp->rd_bl_lvds_val = 0; 3459 3460 splx(s); 3461 } 3462
Indexes created Sat Oct 18 08:10:09 GMT 2025