radeonfb.c revision 1.70
1 /* $NetBSD: radeonfb.c,v 1.70 2012/12/31 10:31:19 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.70 2012/12/31 10:31:19 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 /* R420/R423 family */ 358 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 375 376 { 0, 0, 0 } 377 }; 378 379 static struct { 380 int divider; 381 int mask; 382 } radeonfb_dividers[] = { 383 { 16, 5 }, 384 { 12, 7 }, 385 { 8, 3 }, 386 { 6, 6 }, 387 { 4, 2 }, 388 { 3, 4 }, 389 { 2, 1 }, 390 { 1, 0 }, 391 { 0, 0 } 392 }; 393 394 /* 395 * This table taken from X11. 396 */ 397 static const struct { 398 int family; 399 struct radeon_tmds_pll plls[4]; 400 } radeonfb_tmds_pll[] = { 401 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 402 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RS100, {{0, 0}}}, 404 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 408 { RADEON_RS300, {{0, 0}}}, 409 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 410 { RADEON_R300, {{-1, 0xb01cb}}}, 411 { RADEON_R350, {{-1, 0xb01cb}}}, 412 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 413 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 414 { RADEON_R420, {{-1, 0xb01cb}}}, 415 }; 416 417 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 418 419 420 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 421 radeonfb_match, radeonfb_attach, NULL, NULL); 422 423 static int 424 radeonfb_match(device_t parent, cfdata_t match, void *aux) 425 { 426 const struct pci_attach_args *pa = aux; 427 int i; 428 429 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 430 return 0; 431 432 for (i = 0; radeonfb_devices[i].devid; i++) { 433 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 434 return 100; /* high to defeat VGA/VESA */ 435 } 436 437 return 0; 438 } 439 440 static void 441 radeonfb_attach(device_t parent, device_t dev, void *aux) 442 { 443 struct radeonfb_softc *sc = device_private(dev); 444 const struct pci_attach_args *pa = aux; 445 const char *mptr; 446 bus_size_t bsz; 447 pcireg_t screg; 448 int i, j, fg, bg, ul, flags; 449 uint32_t v; 450 451 sc->sc_dev = dev; 452 sc->sc_id = pa->pa_id; 453 for (i = 0; radeonfb_devices[i].devid; i++) { 454 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 455 break; 456 } 457 458 pci_aprint_devinfo(pa, NULL); 459 460 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 461 462 KASSERT(radeonfb_devices[i].devid != 0); 463 sc->sc_pt = pa->pa_tag; 464 sc->sc_iot = pa->pa_iot; 465 sc->sc_pc = pa->pa_pc; 466 sc->sc_family = radeonfb_devices[i].family; 467 sc->sc_flags = radeonfb_devices[i].flags; 468 469 /* enable memory and IO access */ 470 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 471 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 472 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 473 474 /* 475 * Some flags are general to entire chip families, and rather 476 * than clutter up the table with them, we go ahead and set 477 * them here. 478 */ 479 switch (sc->sc_family) { 480 case RADEON_RS100: 481 case RADEON_RS200: 482 sc->sc_flags |= RFB_IGP | RFB_RV100; 483 break; 484 485 case RADEON_RV100: 486 case RADEON_RV200: 487 case RADEON_RV250: 488 case RADEON_RV280: 489 sc->sc_flags |= RFB_RV100; 490 break; 491 492 case RADEON_RS300: 493 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 494 break; 495 496 case RADEON_R300: 497 case RADEON_RV350: 498 case RADEON_R350: 499 case RADEON_RV380: 500 case RADEON_R420: 501 /* newer chips */ 502 sc->sc_flags |= RFB_R300; 503 break; 504 505 case RADEON_R100: 506 sc->sc_flags |= RFB_NCRTC2; 507 break; 508 } 509 510 if ((sc->sc_family == RADEON_RV200) || 511 (sc->sc_family == RADEON_RV250) || 512 (sc->sc_family == RADEON_RV280) || 513 (sc->sc_family == RADEON_RV350)) { 514 bool inverted = 0; 515 /* backlight level is linear */ 516 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 517 prop_dictionary_get_bool(device_properties(sc->sc_dev), 518 "backlight_level_reverted", &inverted); 519 if (inverted) { 520 DPRINTF(("nope, it's inverted\n")); 521 sc->sc_flags |= RFB_INV_BLIGHT; 522 } 523 } else 524 sc->sc_flags |= RFB_INV_BLIGHT; 525 526 /* 527 * XXX: to support true multihead, this must change. 528 */ 529 sc->sc_ndisplays = 1; 530 531 /* XXX: */ 532 if (!HAS_CRTC2(sc)) { 533 sc->sc_ndisplays = 1; 534 } 535 536 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 537 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 538 &sc->sc_regsz) != 0) { 539 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 540 goto error; 541 } 542 543 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 544 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 545 { 546 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 547 goto error; 548 } 549 sc->sc_romt = sc->sc_memt; 550 551 sc->sc_mapped = TRUE; 552 553 /* scratch register test... */ 554 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 555 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 556 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 557 goto error; 558 } 559 560 PRINTREG(RADEON_CRTC_EXT_CNTL); 561 PRINTREG(RADEON_CRTC_GEN_CNTL); 562 PRINTREG(RADEON_CRTC2_GEN_CNTL); 563 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 564 PRINTREG(RADEON_DAC_CNTL2); 565 PRINTREG(RADEON_FP_GEN_CNTL); 566 PRINTREG(RADEON_FP2_GEN_CNTL); 567 568 PRINTREG(RADEON_BIOS_4_SCRATCH); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 571 PRINTREG(RADEON_FP2_GEN_CNTL); 572 PRINTREG(RADEON_TMDS_CNTL); 573 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 574 PRINTREG(RADEON_TMDS_PLL_CNTL); 575 PRINTREG(RADEON_LVDS_GEN_CNTL); 576 PRINTREG(RADEON_FP_HORZ_STRETCH); 577 PRINTREG(RADEON_FP_VERT_STRETCH); 578 579 if (IS_RV100(sc)) 580 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 581 582 /* XXX 583 * according to xf86-video-radeon R3xx has this bit backwards 584 */ 585 if (IS_R300(sc)) { 586 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 587 0, 588 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 589 } else { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 RADEON_TMDS_TRANSMITTER_PLLEN, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } 594 595 radeonfb_i2c_init(sc); 596 597 radeonfb_loadbios(sc, pa); 598 599 #ifdef RADEONFB_BIOS_INIT 600 if (radeonfb_bios_init(sc)) { 601 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 602 } 603 #endif 604 605 if (radeonfb_getclocks(sc)) { 606 aprint_error("%s: Unable to get reference clocks from BIOS\n", 607 XNAME(sc)); 608 goto error; 609 } 610 611 if (radeonfb_gettmds(sc)) { 612 aprint_error("%s: Unable to identify TMDS PLL settings\n", 613 XNAME(sc)); 614 goto error; 615 } 616 617 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 618 "minpll = %d, maxpll = %d\n", XNAME(sc), 619 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 620 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 621 622 radeonfb_getconnectors(sc); 623 624 radeonfb_set_fbloc(sc); 625 626 for (i = 0; radeonfb_limits[i].size; i++) { 627 if (sc->sc_memsz >= radeonfb_limits[i].size) { 628 sc->sc_maxx = radeonfb_limits[i].maxx; 629 sc->sc_maxy = radeonfb_limits[i].maxy; 630 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 631 /* framebuffer offset, start at a 4K page */ 632 sc->sc_fboffset = sc->sc_memsz / 633 radeonfb_limits[i].maxdisp; 634 /* 635 * we use the fbsize to figure out where we can store 636 * things like cursor data. 637 */ 638 sc->sc_fbsize = 639 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 640 RADEON_STRIDEALIGN) * sc->sc_maxy, 641 4096); 642 break; 643 } 644 } 645 646 647 radeonfb_init_misc(sc); 648 649 /* program the DAC wirings */ 650 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 651 switch (sc->sc_ports[i].rp_dac_type) { 652 case RADEON_DAC_PRIMARY: 653 PATCH32(sc, RADEON_DAC_CNTL2, 654 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 655 ~RADEON_DAC2_DAC_CLK_SEL); 656 break; 657 case RADEON_DAC_TVDAC: 658 /* we always use the TVDAC to drive a secondary analog 659 * CRT for now. if we ever support TV-out this will 660 * have to change. 661 */ 662 SET32(sc, RADEON_DAC_CNTL2, 663 RADEON_DAC2_DAC2_CLK_SEL); 664 PATCH32(sc, RADEON_DISP_HW_DEBUG, 665 i ? 0 : RADEON_CRT2_DISP1_SEL, 666 ~RADEON_CRT2_DISP1_SEL); 667 /* we're using CRTC2 for the 2nd port */ 668 if (sc->sc_ports[i].rp_number == 1) { 669 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 670 RADEON_DISP_DAC2_SOURCE_CRTC2, 671 ~RADEON_DISP_DAC2_SOURCE_MASK); 672 } 673 674 break; 675 } 676 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 677 sc->sc_ports[i].rp_tmds_type)); 678 switch (sc->sc_ports[i].rp_tmds_type) { 679 case RADEON_TMDS_INT: 680 /* point FP0 at the CRTC this port uses */ 681 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 682 __func__, sc->sc_ports[i].rp_number)); 683 if (IS_R300(sc)) { 684 PATCH32(sc, RADEON_FP_GEN_CNTL, 685 sc->sc_ports[i].rp_number ? 686 R200_FP_SOURCE_SEL_CRTC2 : 687 R200_FP_SOURCE_SEL_CRTC1, 688 ~R200_FP_SOURCE_SEL_MASK); 689 } else { 690 PATCH32(sc, RADEON_FP_GEN_CNTL, 691 sc->sc_ports[i].rp_number ? 692 RADEON_FP_SEL_CRTC2 : 693 RADEON_FP_SEL_CRTC1, 694 ~RADEON_FP_SEL_MASK); 695 } 696 } 697 } 698 PRINTREG(RADEON_DAC_CNTL2); 699 PRINTREG(RADEON_DISP_HW_DEBUG); 700 701 /* other DAC programming */ 702 v = GET32(sc, RADEON_DAC_CNTL); 703 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 704 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 705 PUT32(sc, RADEON_DAC_CNTL, v); 706 PRINTREG(RADEON_DAC_CNTL); 707 708 /* XXX: this may need more investigation */ 709 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 710 PRINTREG(RADEON_TV_DAC_CNTL); 711 712 /* enable TMDS */ 713 SET32(sc, RADEON_FP_GEN_CNTL, 714 RADEON_FP_TMDS_EN | 715 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 716 RADEON_FP_CRTC_DONT_SHADOW_HEND); 717 /* 718 * XXX 719 * no idea why this is necessary - if I do not clear this bit on my 720 * iBook G4 the screen remains black, even though it's already clear. 721 * It needs to be set on my Sun XVR-100 for the DVI port to work 722 * TODO: 723 * see if this is still necessary now that CRTCs, DACs and outputs are 724 * getting wired up in a halfway sane way 725 */ 726 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 727 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 728 } else { 729 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 730 } 731 732 /* 733 * we use bus_space_map instead of pci_mapreg, because we don't 734 * need the full aperature space. no point in wasting virtual 735 * address space we don't intend to use, right? 736 */ 737 if ((sc->sc_memsz < (4096 * 1024)) || 738 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 739 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 740 (bsz < sc->sc_memsz)) { 741 sc->sc_memsz = 0; 742 aprint_error("%s: Bad frame buffer configuration\n", 743 XNAME(sc)); 744 goto error; 745 } 746 747 /* 64 MB should be enough -- more just wastes map entries */ 748 if (sc->sc_memsz > (64 << 20)) 749 sc->sc_memsz = (64 << 20); 750 751 sc->sc_memt = pa->pa_memt; 752 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 753 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 754 sc->sc_memsz = 0; 755 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 756 goto error; 757 } 758 759 aprint_normal("%s: %d MB aperture at 0x%08x, " 760 "%d KB registers at 0x%08x\n", XNAME(sc), 761 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 762 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 763 764 /* setup default video mode from devprop (allows PROM override) */ 765 sc->sc_defaultmode = radeonfb_default_mode; 766 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 767 "videomode", &mptr)) { 768 769 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 770 sc->sc_defaultmode = sc->sc_modebuf; 771 } 772 773 /* initialize some basic display parameters */ 774 for (i = 0; i < sc->sc_ndisplays; i++) { 775 struct radeonfb_display *dp = &sc->sc_displays[i]; 776 struct rasops_info *ri; 777 long defattr; 778 struct wsemuldisplaydev_attach_args aa; 779 780 /* 781 * Figure out how many "displays" (desktops) we are going to 782 * support. If more than one, then each CRTC gets its own 783 * programming. 784 * 785 * XXX: this code needs to change to support mergedfb. 786 * XXX: would be nice to allow this to be overridden 787 */ 788 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 789 DPRINTF(("dual crtcs!\n")); 790 dp->rd_ncrtcs = 2; 791 dp->rd_crtcs[0].rc_port = 792 &sc->sc_ports[0]; 793 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 794 dp->rd_crtcs[1].rc_port = 795 &sc->sc_ports[1]; 796 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 797 } else { 798 dp->rd_ncrtcs = 1; 799 dp->rd_crtcs[0].rc_port = 800 &sc->sc_ports[i]; 801 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 802 } 803 804 dp->rd_softc = sc; 805 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 806 dp->rd_bg = WS_DEFAULT_BG; 807 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 808 809 /* for text mode, we pick a resolution that won't 810 * require panning */ 811 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 812 813 aprint_normal("%s: display %d: " 814 "initial virtual resolution %dx%d at %d bpp\n", 815 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 816 817 /* now select the *video mode* that we will use */ 818 for (j = 0; j < dp->rd_ncrtcs; j++) { 819 const struct videomode *vmp; 820 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 821 dp->rd_virtx, dp->rd_virty); 822 823 /* 824 * virtual resolution should be at least as high as 825 * physical 826 */ 827 if (dp->rd_virtx < vmp->hdisplay || 828 dp->rd_virty < vmp->vdisplay) { 829 dp->rd_virtx = vmp->hdisplay; 830 dp->rd_virty = vmp->vdisplay; 831 } 832 833 dp->rd_crtcs[j].rc_videomode = *vmp; 834 printf("%s: port %d: physical %dx%d %dHz\n", 835 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 836 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 837 vmp->htotal), vmp->vtotal)); 838 } 839 840 /* N.B.: radeon wants 64-byte aligned stride */ 841 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 842 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 843 DPRINTF(("stride: %d\n", dp->rd_stride)); 844 845 dp->rd_offset = sc->sc_fboffset * i; 846 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 847 sc->sc_memh) + dp->rd_offset; 848 dp->rd_curoff = sc->sc_fbsize; 849 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 850 851 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 852 853 switch (dp->rd_bpp) { 854 case 8: 855 dp->rd_format = 2; 856 break; 857 case 32: 858 dp->rd_format = 6; 859 break; 860 default: 861 aprint_error("%s: bad depth %d\n", XNAME(sc), 862 dp->rd_bpp); 863 goto error; 864 } 865 866 DPRINTF(("init engine\n")); 867 /* XXX: this seems suspicious - per display engine 868 initialization? */ 869 radeonfb_engine_init(dp); 870 871 /* copy the template into place */ 872 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 873 dp->rd_wsscreens = dp->rd_wsscreens_storage; 874 875 /* and make up the list */ 876 dp->rd_wsscreenlist.nscreens = 1; 877 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 878 879 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 880 &radeonfb_accessops); 881 882 dp->rd_vd.init_screen = radeonfb_init_screen; 883 884 #ifdef RADEONFB_DEBUG 885 dp->rd_virty -= 200; 886 #endif 887 888 dp->rd_console = 0; 889 prop_dictionary_get_bool(device_properties(sc->sc_dev), 890 "is_console", &dp->rd_console); 891 892 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 893 894 895 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 896 dp->rd_console, &defattr); 897 898 ri = &dp->rd_vscreen.scr_ri; 899 900 /* clear the screen */ 901 rasops_unpack_attr(defattr, &fg, &bg, &ul); 902 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 903 ri->ri_devcmap[bg & 0xf]); 904 905 dp->rd_wsscreens->textops = &ri->ri_ops; 906 dp->rd_wsscreens->capabilities = ri->ri_caps; 907 dp->rd_wsscreens->nrows = ri->ri_rows; 908 dp->rd_wsscreens->ncols = ri->ri_cols; 909 910 #ifdef SPLASHSCREEN 911 dp->rd_splash.si_depth = ri->ri_depth; 912 dp->rd_splash.si_bits = ri->ri_bits; 913 dp->rd_splash.si_hwbits = ri->ri_hwbits; 914 dp->rd_splash.si_width = ri->ri_width; 915 dp->rd_splash.si_height = ri->ri_height; 916 dp->rd_splash.si_stride = ri->ri_stride; 917 dp->rd_splash.si_fillrect = NULL; 918 #endif 919 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 920 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 921 dp->rd_gc.gc_rop = RADEON_ROP3_S; 922 dp->rd_gc.gc_blitcookie = dp; 923 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 924 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 925 dp->rd_virtx, 926 ri->ri_font->fontwidth, 927 ri->ri_font->fontheight, 928 defattr); 929 if (dp->rd_console) { 930 931 radeonfb_modeswitch(dp); 932 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 933 defattr); 934 #ifdef SPLASHSCREEN 935 if (splash_render(&dp->rd_splash, 936 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 937 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 938 else 939 #endif 940 vcons_replay_msgbuf(&dp->rd_vscreen); 941 } else { 942 943 /* 944 * since we're not the console we can postpone 945 * the rest until someone actually allocates a 946 * screen for us. but we do clear the screen 947 * at least. 948 */ 949 memset(ri->ri_bits, 0, 1024); 950 951 radeonfb_modeswitch(dp); 952 #ifdef SPLASHSCREEN 953 if (splash_render(&dp->rd_splash, 954 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 955 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 956 #endif 957 } 958 959 aa.console = dp->rd_console; 960 aa.scrdata = &dp->rd_wsscreenlist; 961 aa.accessops = &radeonfb_accessops; 962 aa.accesscookie = &dp->rd_vd; 963 964 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 965 966 radeonfb_blank(dp, 0); 967 968 /* Initialise delayed lvds operations for backlight. */ 969 callout_init(&dp->rd_bl_lvds_co, 0); 970 callout_setfunc(&dp->rd_bl_lvds_co, 971 radeonfb_lvds_callout, dp); 972 dp->rd_bl_on = 1; 973 dp->rd_bl_level = radeonfb_get_backlight(dp); 974 radeonfb_set_backlight(dp, dp->rd_bl_level); 975 } 976 977 for (i = i; i < RADEON_NDISPLAYS; i++) 978 radeonfb_init_palette(&sc->sc_displays[i]); 979 980 if (HAS_CRTC2(sc)) { 981 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 982 } 983 984 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 985 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 986 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 987 radeonfb_brightness_up, TRUE); 988 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 989 radeonfb_brightness_down, TRUE); 990 991 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 992 993 PRINTREG(RADEON_CRTC_EXT_CNTL); 994 PRINTREG(RADEON_CRTC_GEN_CNTL); 995 PRINTREG(RADEON_CRTC2_GEN_CNTL); 996 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 997 PRINTREG(RADEON_DAC_CNTL2); 998 PRINTREG(RADEON_FP_GEN_CNTL); 999 PRINTREG(RADEON_FP2_GEN_CNTL); 1000 1001 return; 1002 1003 error: 1004 if (sc->sc_biossz) 1005 free(sc->sc_bios, M_DEVBUF); 1006 1007 if (sc->sc_regsz) 1008 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1009 1010 if (sc->sc_memsz) 1011 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1012 } 1013 1014 static void 1015 radeonfb_map(struct radeonfb_softc *sc) 1016 { 1017 if (!sc->sc_mapped) { 1018 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1019 &sc->sc_regh) != 0) { 1020 aprint_error_dev(sc->sc_dev, 1021 "unable to map registers!\n"); 1022 return; 1023 } 1024 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1025 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1026 sc->sc_memsz = 0; 1027 aprint_error_dev(sc->sc_dev, 1028 "Unable to map frame buffer\n"); 1029 return; 1030 } 1031 sc->sc_mapped = TRUE; 1032 } 1033 } 1034 1035 static void 1036 radeonfb_unmap(struct radeonfb_softc *sc) 1037 { 1038 if (sc->sc_mapped) { 1039 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1040 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1041 sc->sc_mapped = FALSE; 1042 } 1043 } 1044 1045 static int 1046 radeonfb_drm_print(void *aux, const char *pnp) 1047 { 1048 if (pnp) 1049 aprint_normal("drm at %s", pnp); 1050 return (UNCONF); 1051 } 1052 1053 int 1054 radeonfb_ioctl(void *v, void *vs, 1055 unsigned long cmd, void *d, int flag, struct lwp *l) 1056 { 1057 struct vcons_data *vd; 1058 struct radeonfb_display *dp; 1059 struct radeonfb_softc *sc; 1060 struct wsdisplay_param *param; 1061 1062 vd = (struct vcons_data *)v; 1063 dp = (struct radeonfb_display *)vd->cookie; 1064 sc = dp->rd_softc; 1065 1066 switch (cmd) { 1067 case WSDISPLAYIO_GTYPE: 1068 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1069 return 0; 1070 1071 case WSDISPLAYIO_GINFO: 1072 if (vd->active != NULL) { 1073 struct wsdisplay_fbinfo *fb; 1074 fb = (struct wsdisplay_fbinfo *)d; 1075 fb->width = dp->rd_virtx; 1076 fb->height = dp->rd_virty; 1077 fb->depth = dp->rd_bpp; 1078 fb->cmsize = 256; 1079 return 0; 1080 } else 1081 return ENODEV; 1082 case WSDISPLAYIO_GVIDEO: 1083 if (radeonfb_isblank(dp)) 1084 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1085 else 1086 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1087 return 0; 1088 1089 case WSDISPLAYIO_SVIDEO: 1090 radeonfb_blank(dp, 1091 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1092 return 0; 1093 1094 case WSDISPLAYIO_GETCMAP: 1095 #if 0 1096 if (dp->rd_bpp == 8) 1097 return radeonfb_getcmap(sc, 1098 (struct wsdisplay_cmap *)d); 1099 #endif 1100 return EINVAL; 1101 1102 case WSDISPLAYIO_PUTCMAP: 1103 #if 0 1104 if (dp->rd_bpp == 8) 1105 return radeonfb_putcmap(sc, 1106 (struct wsdisplay_cmap *)d); 1107 #endif 1108 return EINVAL; 1109 1110 case WSDISPLAYIO_LINEBYTES: 1111 *(unsigned *)d = dp->rd_stride; 1112 return 0; 1113 1114 case WSDISPLAYIO_SMODE: 1115 if (*(int *)d != dp->rd_wsmode) { 1116 dp->rd_wsmode = *(int *)d; 1117 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1118 (dp->rd_vd.active)) { 1119 radeonfb_map(sc); 1120 radeonfb_engine_init(dp); 1121 glyphcache_wipe(&dp->rd_gc); 1122 radeonfb_init_palette(dp); 1123 radeonfb_modeswitch(dp); 1124 vcons_redraw_screen(dp->rd_vd.active); 1125 } else { 1126 radeonfb_unmap(sc); 1127 } 1128 } 1129 return 0; 1130 1131 case WSDISPLAYIO_GCURMAX: 1132 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1133 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1134 return 0; 1135 1136 case WSDISPLAYIO_SCURSOR: 1137 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1138 1139 case WSDISPLAYIO_GCURSOR: 1140 return EPASSTHROUGH; 1141 1142 case WSDISPLAYIO_GCURPOS: 1143 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1144 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1145 return 0; 1146 1147 case WSDISPLAYIO_SCURPOS: 1148 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1149 1150 case WSDISPLAYIO_SSPLASH: 1151 #if defined(SPLASHSCREEN) 1152 if (*(int *)d == 1) { 1153 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1154 splash_render(&dp->rd_splash, 1155 SPLASH_F_CENTER|SPLASH_F_FILL); 1156 } else 1157 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1158 return 0; 1159 #else 1160 return ENODEV; 1161 #endif 1162 case WSDISPLAYIO_GETPARAM: 1163 param = (struct wsdisplay_param *)d; 1164 switch (param->param) { 1165 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1166 param->min = 0; 1167 param->max = 255; 1168 param->curval = dp->rd_bl_level; 1169 return 0; 1170 case WSDISPLAYIO_PARAM_BACKLIGHT: 1171 param->min = 0; 1172 param->max = RADEONFB_BACKLIGHT_MAX; 1173 param->curval = dp->rd_bl_on; 1174 return 0; 1175 } 1176 return EPASSTHROUGH; 1177 1178 case WSDISPLAYIO_SETPARAM: 1179 param = (struct wsdisplay_param *)d; 1180 switch (param->param) { 1181 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1182 radeonfb_set_backlight(dp, param->curval); 1183 return 0; 1184 case WSDISPLAYIO_PARAM_BACKLIGHT: 1185 radeonfb_switch_backlight(dp, param->curval); 1186 return 0; 1187 } 1188 return EPASSTHROUGH; 1189 1190 /* PCI config read/write passthrough. */ 1191 case PCI_IOC_CFGREAD: 1192 case PCI_IOC_CFGWRITE: 1193 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1194 1195 case WSDISPLAYIO_GET_BUSID: 1196 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1197 sc->sc_pt, d); 1198 1199 case WSDISPLAYIO_GET_EDID: { 1200 struct wsdisplayio_edid_info *ei = d; 1201 return wsdisplayio_get_edid(sc->sc_dev, ei); 1202 } 1203 1204 default: 1205 return EPASSTHROUGH; 1206 } 1207 } 1208 1209 paddr_t 1210 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1211 { 1212 struct vcons_data *vd; 1213 struct radeonfb_display *dp; 1214 struct radeonfb_softc *sc; 1215 paddr_t pa; 1216 1217 vd = (struct vcons_data *)v; 1218 dp = (struct radeonfb_display *)vd->cookie; 1219 sc = dp->rd_softc; 1220 1221 /* XXX: note that we don't allow mapping of registers right now */ 1222 /* XXX: this means that the XFree86 radeon driver won't work */ 1223 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1224 pa = bus_space_mmap(sc->sc_memt, 1225 sc->sc_memaddr + dp->rd_offset + offset, 0, 1226 prot, BUS_SPACE_MAP_LINEAR); 1227 return pa; 1228 } 1229 1230 #ifdef RADEONFB_MMAP_BARS 1231 /* 1232 * restrict all other mappings to processes with superuser privileges 1233 * or the kernel itself 1234 */ 1235 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1236 NULL, NULL, NULL, NULL) != 0) { 1237 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1238 return -1; 1239 } 1240 1241 if ((offset >= sc->sc_regaddr) && 1242 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1243 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1244 BUS_SPACE_MAP_LINEAR); 1245 } 1246 1247 if ((offset >= sc->sc_memaddr) && 1248 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1249 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1250 BUS_SPACE_MAP_LINEAR); 1251 } 1252 1253 if ((offset >= sc->sc_romaddr) && 1254 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1255 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1256 BUS_SPACE_MAP_LINEAR); 1257 } 1258 1259 #ifdef PCI_MAGIC_IO_RANGE 1260 /* allow mapping of IO space */ 1261 if ((offset >= PCI_MAGIC_IO_RANGE) && 1262 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1263 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1264 0, prot, 0); 1265 return pa; 1266 } 1267 #endif /* PCI_MAGIC_IO_RANGE */ 1268 1269 #endif /* RADEONFB_MMAP_BARS */ 1270 1271 return -1; 1272 } 1273 1274 static void 1275 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1276 { 1277 bus_space_tag_t romt; 1278 bus_space_handle_t romh, biosh; 1279 bus_size_t romsz; 1280 bus_addr_t ptr; 1281 1282 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1283 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1284 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1285 return; 1286 } 1287 1288 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1289 &sc->sc_biossz); 1290 if (sc->sc_biossz == 0) { 1291 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1292 return; 1293 } 1294 1295 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1296 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1297 1298 /* unmap the PCI expansion rom */ 1299 bus_space_unmap(romt, romh, romsz); 1300 1301 /* turn off rom decoder now */ 1302 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1303 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1304 ~PCI_MAPREG_ROM_ENABLE); 1305 1306 ptr = GETBIOS16(sc, 0x48); 1307 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1308 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1309 sc->sc_flags |= RFB_ATOM; 1310 } 1311 1312 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1313 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1314 } 1315 1316 1317 uint32_t 1318 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1319 { 1320 1321 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1322 } 1323 1324 void 1325 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1326 { 1327 1328 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1329 } 1330 1331 void 1332 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1333 { 1334 1335 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1336 } 1337 1338 void 1339 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1340 uint32_t andmask, uint32_t ormask) 1341 { 1342 int s; 1343 uint32_t val; 1344 1345 s = splhigh(); 1346 val = radeonfb_get32(sc, reg); 1347 val = (val & andmask) | ormask; 1348 radeonfb_put32(sc, reg, val); 1349 splx(s); 1350 } 1351 1352 uint32_t 1353 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1354 { 1355 int s; 1356 uint32_t val; 1357 1358 s = splhigh(); 1359 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1360 val = radeonfb_get32(sc, RADEON_MM_DATA); 1361 splx(s); 1362 1363 return (val); 1364 } 1365 1366 void 1367 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1368 { 1369 int s; 1370 1371 s = splhigh(); 1372 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1373 radeonfb_put32(sc, RADEON_MM_DATA, val); 1374 splx(s); 1375 } 1376 1377 void 1378 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1379 uint32_t andmask, uint32_t ormask) 1380 { 1381 int s; 1382 uint32_t val; 1383 1384 s = splhigh(); 1385 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1386 val = radeonfb_get32(sc, RADEON_MM_DATA); 1387 val = (val & andmask) | ormask; 1388 radeonfb_put32(sc, RADEON_MM_DATA, val); 1389 splx(s); 1390 } 1391 1392 uint32_t 1393 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1394 { 1395 int s; 1396 uint32_t val; 1397 1398 s = splhigh(); 1399 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1400 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1401 if (HAS_R300CG(sc)) 1402 radeonfb_r300cg_workaround(sc); 1403 splx(s); 1404 1405 return (val); 1406 } 1407 1408 void 1409 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1410 { 1411 int s; 1412 1413 s = splhigh(); 1414 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1415 RADEON_PLL_WR_EN); 1416 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1417 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1418 splx(s); 1419 } 1420 1421 void 1422 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1423 uint32_t andmask, uint32_t ormask) 1424 { 1425 int s; 1426 uint32_t val; 1427 1428 s = splhigh(); 1429 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1430 RADEON_PLL_WR_EN); 1431 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1432 val = (val & andmask) | ormask; 1433 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1434 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1435 splx(s); 1436 } 1437 1438 int 1439 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1440 { 1441 uint32_t saved; 1442 1443 saved = GET32(sc, reg); 1444 PUT32(sc, reg, v); 1445 if (GET32(sc, reg) != v) { 1446 return -1; 1447 } 1448 PUT32(sc, reg, saved); 1449 return 0; 1450 } 1451 1452 uintmax_t 1453 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1454 uintmax_t defval) 1455 { 1456 prop_number_t pn; 1457 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1458 if (pn == NULL) { 1459 return defval; 1460 } 1461 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1462 return (prop_number_integer_value(pn)); 1463 } 1464 1465 int 1466 radeonfb_getclocks(struct radeonfb_softc *sc) 1467 { 1468 bus_addr_t ptr; 1469 int refclk = 0; 1470 int refdiv = 0; 1471 int minpll = 0; 1472 int maxpll = 0; 1473 1474 /* load initial property values if port/board provides them */ 1475 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1476 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1477 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1478 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1479 1480 PRINTPLL(RADEON_PPLL_REF_DIV); 1481 PRINTPLL(RADEON_PPLL_DIV_0); 1482 PRINTPLL(RADEON_PPLL_DIV_1); 1483 PRINTPLL(RADEON_PPLL_DIV_2); 1484 PRINTPLL(RADEON_PPLL_DIV_3); 1485 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1486 PRINTPLL(RADEON_P2PLL_REF_DIV); 1487 PRINTPLL(RADEON_P2PLL_DIV_0); 1488 1489 if (refclk && refdiv && minpll && maxpll) 1490 goto dontprobe; 1491 1492 if (!sc->sc_biossz) { 1493 /* no BIOS */ 1494 aprint_verbose("%s: No video BIOS, using default clocks\n", 1495 XNAME(sc)); 1496 if (IS_IGP(sc)) 1497 refclk = refclk ? refclk : 1432; 1498 else 1499 refclk = refclk ? refclk : 2700; 1500 refdiv = refdiv ? refdiv : 12; 1501 minpll = minpll ? minpll : 12500; 1502 /* XXX 1503 * Need to check if the firmware or something programmed a 1504 * higher value than this, and if so, bump it. 1505 * The RV280 in my iBook is unhappy if the PLL input is less 1506 * than 360MHz 1507 */ 1508 maxpll = maxpll ? maxpll : 40000/*35000*/; 1509 } else if (IS_ATOM(sc)) { 1510 /* ATOM BIOS */ 1511 ptr = GETBIOS16(sc, 0x48); 1512 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1513 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1514 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1515 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1516 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1517 /* 1518 * ATOM BIOS doesn't supply a reference divider, so we 1519 * have to probe for it. 1520 */ 1521 if (refdiv < 2) 1522 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1523 RADEON_PPLL_REF_DIV_MASK; 1524 /* 1525 * if probe is zero, just assume one that should work 1526 * for most parts 1527 */ 1528 if (refdiv < 2) 1529 refdiv = 12; 1530 1531 } else { 1532 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1533 /* Legacy BIOS */ 1534 ptr = GETBIOS16(sc, 0x48); 1535 ptr = GETBIOS16(sc, ptr + 0x30); 1536 if (IS_R300(sc)) { 1537 refdiv = refdiv ? refdiv : 1538 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1539 R300_PPLL_REF_DIV_ACC_SHIFT; 1540 } else { 1541 refdiv = refdiv ? refdiv : 1542 tmp & RADEON_PPLL_REF_DIV_MASK; 1543 } 1544 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1545 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1546 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1547 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1548 } 1549 1550 1551 dontprobe: 1552 sc->sc_refclk = refclk * 10; 1553 sc->sc_refdiv = refdiv; 1554 sc->sc_minpll = minpll * 10; 1555 sc->sc_maxpll = maxpll * 10; 1556 return 0; 1557 } 1558 1559 int 1560 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1561 uint32_t *postdivbit, uint32_t *feedbackdiv) 1562 { 1563 int i; 1564 uint32_t outfreq; 1565 int div; 1566 1567 DPRINTF(("dot clock: %u\n", dotclock)); 1568 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1569 outfreq = div * dotclock; 1570 if ((outfreq >= sc->sc_minpll) && 1571 (outfreq <= sc->sc_maxpll)) { 1572 DPRINTF(("outfreq: %u\n", outfreq)); 1573 *postdivbit = 1574 ((uint32_t)radeonfb_dividers[i].mask << 16); 1575 DPRINTF(("post divider: %d (mask %x)\n", div, 1576 *postdivbit)); 1577 break; 1578 } 1579 } 1580 1581 if (div == 0) 1582 return 1; 1583 1584 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1585 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1586 return 0; 1587 } 1588 1589 #if 0 1590 #ifdef RADEONFB_DEBUG 1591 static void 1592 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1593 { 1594 char asc[17]; 1595 unsigned ptr = (unsigned)buffer; 1596 char *start = (char *)(ptr & ~0xf); 1597 char *end = (char *)(ptr + size); 1598 1599 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1600 1601 if (pfx == NULL) { 1602 pfx = ""; 1603 } 1604 1605 while (start < end) { 1606 unsigned offset = (unsigned)start & 0xf; 1607 if (offset == 0) { 1608 printf("%s%x: ", pfx, (unsigned)start); 1609 } 1610 if (((unsigned)start < ptr) || 1611 ((unsigned)start >= (ptr + size))) { 1612 printf(" "); 1613 asc[offset] = ' '; 1614 } else { 1615 printf("%02x", *(unsigned char *)start); 1616 if ((*start >= ' ') && (*start <= '~')) { 1617 asc[offset] = *start; 1618 } else { 1619 asc[offset] = '.'; 1620 } 1621 } 1622 asc[offset + 1] = 0; 1623 if (offset % 2) { 1624 printf(" "); 1625 } 1626 if (offset == 15) { 1627 printf(" %s\n", asc); 1628 } 1629 start++; 1630 } 1631 } 1632 #endif 1633 #endif 1634 1635 int 1636 radeonfb_getconnectors(struct radeonfb_softc *sc) 1637 { 1638 int i; 1639 int found = 0; 1640 1641 for (i = 0; i < 2; i++) { 1642 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1643 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1644 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1645 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1646 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1647 } 1648 1649 /* 1650 * This logic is borrowed from Xorg's radeon driver. 1651 */ 1652 if (!sc->sc_biossz) 1653 goto nobios; 1654 1655 if (IS_ATOM(sc)) { 1656 /* not done yet */ 1657 } else { 1658 uint16_t ptr; 1659 int port = 0; 1660 1661 ptr = GETBIOS16(sc, 0x48); 1662 ptr = GETBIOS16(sc, ptr + 0x50); 1663 for (i = 1; i < 4; i++) { 1664 uint16_t entry; 1665 uint8_t conn, ddc, dac, tmds; 1666 1667 /* 1668 * Parse the connector table. From reading the code, 1669 * it appears to made up of 16-bit entries for each 1670 * connector. The 16-bits are defined as: 1671 * 1672 * bits 12-15 - connector type (0 == end of table) 1673 * bits 8-11 - DDC type 1674 * bits 5-7 - ??? 1675 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1676 * bits 1-3 - ??? 1677 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1678 */ 1679 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1680 break; 1681 entry = GETBIOS16(sc, ptr + i * 2); 1682 1683 conn = (entry >> 12) & 0xf; 1684 ddc = (entry >> 8) & 0xf; 1685 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1686 RADEON_DAC_PRIMARY; 1687 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1688 RADEON_TMDS_INT; 1689 1690 if (conn == RADEON_CONN_NONE) 1691 continue; /* no connector */ 1692 1693 if ((found > 0) && 1694 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1695 /* duplicate entry for same connector */ 1696 continue; 1697 } 1698 1699 /* internal DDC_DVI port gets priority */ 1700 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1701 port = 0; 1702 else 1703 port = 1; 1704 1705 sc->sc_ports[port].rp_ddc_type = 1706 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1707 sc->sc_ports[port].rp_dac_type = dac; 1708 sc->sc_ports[port].rp_conn_type = 1709 min(conn, RADEON_CONN_UNSUPPORTED) ; 1710 1711 sc->sc_ports[port].rp_tmds_type = tmds; 1712 1713 if ((conn != RADEON_CONN_DVI_I) && 1714 (conn != RADEON_CONN_DVI_D) && 1715 (tmds == RADEON_TMDS_INT)) 1716 sc->sc_ports[port].rp_tmds_type = 1717 RADEON_TMDS_UNKNOWN; 1718 sc->sc_ports[port].rp_number = i - 1; 1719 1720 found += (port + 1); 1721 } 1722 } 1723 1724 nobios: 1725 if (!found) { 1726 DPRINTF(("No connector info in BIOS!\n")); 1727 if IS_MOBILITY(sc) { 1728 /* default, port 0 = internal TMDS, port 1 = CRT */ 1729 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1730 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1731 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1732 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1733 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1734 sc->sc_ports[0].rp_number = 0; 1735 1736 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1737 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1738 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1739 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1740 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1741 sc->sc_ports[1].rp_number = 1; 1742 } else { 1743 /* default, port 0 = DVI, port 1 = CRT */ 1744 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1745 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1746 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1747 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1748 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1749 sc->sc_ports[0].rp_number = 1; 1750 1751 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1752 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1753 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1754 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1755 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1756 sc->sc_ports[1].rp_number = 0; 1757 } 1758 } 1759 1760 /* 1761 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1762 * these chips should use TVDAC for the VGA port. 1763 */ 1764 if (HAS_SDAC(sc)) { 1765 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1766 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1767 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1768 } else { 1769 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1770 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1771 } 1772 } else if (!HAS_CRTC2(sc)) { 1773 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1774 } 1775 1776 for (i = 0; i < 2; i++) { 1777 char edid[128]; 1778 uint8_t ddc; 1779 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1780 prop_data_t edid_data; 1781 1782 DPRINTF(("Port #%d:\n", i)); 1783 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1784 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1785 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1786 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1787 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1788 1789 sc->sc_ports[i].rp_edid_valid = 0; 1790 /* first look for static EDID data */ 1791 if ((edid_data = prop_dictionary_get(device_properties( 1792 sc->sc_dev), "EDID")) != NULL) { 1793 1794 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1795 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1796 if (edid_parse(edid, eip) == 0) { 1797 1798 sc->sc_ports[i].rp_edid_valid = 1; 1799 } 1800 } 1801 /* if we didn't find any we'll try to talk to the monitor */ 1802 if (sc->sc_ports[i].rp_edid_valid != 1) { 1803 1804 ddc = sc->sc_ports[i].rp_ddc_type; 1805 if (ddc != RADEON_DDC_NONE) { 1806 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1807 == 0) && (edid_parse(edid, eip) == 0)) { 1808 1809 sc->sc_ports[i].rp_edid_valid = 1; 1810 #ifdef RADEONFB_DEBUG 1811 edid_print(eip); 1812 #endif 1813 } 1814 } 1815 } 1816 } 1817 1818 return found; 1819 } 1820 1821 int 1822 radeonfb_gettmds(struct radeonfb_softc *sc) 1823 { 1824 int i; 1825 1826 if (!sc->sc_biossz) { 1827 goto nobios; 1828 } 1829 1830 if (IS_ATOM(sc)) { 1831 /* XXX: not done yet */ 1832 } else { 1833 uint16_t ptr; 1834 int n; 1835 1836 ptr = GETBIOS16(sc, 0x48); 1837 ptr = GETBIOS16(sc, ptr + 0x34); 1838 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1839 if (GETBIOS8(sc, ptr) == 3) { 1840 /* revision three table */ 1841 n = GETBIOS8(sc, ptr + 5) + 1; 1842 n = min(n, 4); 1843 1844 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1845 for (i = 0; i < n; i++) { 1846 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1847 ptr + i * 10 + 8); 1848 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1849 ptr + i * 10 + 0x10); 1850 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1851 sc->sc_tmds_pll[i].rtp_freq, 1852 sc->sc_tmds_pll[i].rtp_pll)); 1853 } 1854 return 0; 1855 } 1856 } 1857 1858 nobios: 1859 DPRINTF(("no suitable DFP table present\n")); 1860 for (i = 0; 1861 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1862 i++) { 1863 int j; 1864 1865 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1866 continue; 1867 1868 for (j = 0; j < 4; j++) { 1869 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1870 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1871 sc->sc_tmds_pll[j].rtp_freq, 1872 sc->sc_tmds_pll[j].rtp_pll)); 1873 } 1874 return 0; 1875 } 1876 1877 return -1; 1878 } 1879 1880 const struct videomode * 1881 radeonfb_modelookup(const char *name) 1882 { 1883 int i; 1884 1885 for (i = 0; i < videomode_count; i++) 1886 if (!strcmp(name, videomode_list[i].name)) 1887 return &videomode_list[i]; 1888 1889 return NULL; 1890 } 1891 1892 void 1893 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1894 { 1895 if (crtc) { 1896 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1897 RADEON_P2PLL_ATOMIC_UPDATE_R); 1898 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1899 } else { 1900 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1901 RADEON_PPLL_ATOMIC_UPDATE_R); 1902 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1903 } 1904 } 1905 1906 void 1907 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1908 { 1909 int i; 1910 1911 for (i = 10000; i; i--) { 1912 if (crtc) { 1913 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1914 RADEON_P2PLL_ATOMIC_UPDATE_R) 1915 break; 1916 } else { 1917 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1918 RADEON_PPLL_ATOMIC_UPDATE_R) 1919 break; 1920 } 1921 } 1922 } 1923 1924 void 1925 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1926 { 1927 uint32_t pbit = 0; 1928 uint32_t feed = 0; 1929 uint32_t data, refdiv, div0; 1930 1931 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1932 1933 if (crtc == 0) { 1934 1935 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1936 if (IS_R300(sc)) { 1937 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1938 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1939 } else { 1940 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1941 sc->sc_refdiv; 1942 } 1943 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1944 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1945 RADEON_PPLL_POST3_DIV_MASK); 1946 div0 |= pbit; 1947 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1948 1949 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1950 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1951 /* 1952 * nothing to do here, the PLL is already where we 1953 * want it 1954 */ 1955 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1956 ~RADEON_PLL_DIV_SEL); 1957 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1958 return; 1959 } 1960 1961 /* alright, we do need to reprogram stuff */ 1962 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1963 RADEON_VCLK_SRC_SEL_CPUCLK, 1964 ~RADEON_VCLK_SRC_SEL_MASK); 1965 1966 /* put vclk into reset, use atomic updates */ 1967 SETPLL(sc, RADEON_PPLL_CNTL, 1968 RADEON_PPLL_REFCLK_SEL | 1969 RADEON_PPLL_FBCLK_SEL | 1970 RADEON_PPLL_RESET | 1971 RADEON_PPLL_ATOMIC_UPDATE_EN | 1972 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1973 1974 /* select clock 0 */ 1975 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1976 ~RADEON_PLL_DIV_SEL); 1977 1978 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1979 1980 /* xf86-video-radeon does this, not sure why */ 1981 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1982 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1983 1984 /* use the atomic update */ 1985 radeonfb_pllwriteupdate(sc, crtc); 1986 1987 /* and wait for it to complete */ 1988 radeonfb_pllwaitatomicread(sc, crtc); 1989 1990 /* program HTOTAL (why?) */ 1991 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1992 1993 /* drop reset */ 1994 CLRPLL(sc, RADEON_PPLL_CNTL, 1995 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1996 RADEON_PPLL_ATOMIC_UPDATE_EN | 1997 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1998 1999 PRINTPLL(RADEON_PPLL_CNTL); 2000 PRINTPLL(RADEON_PPLL_REF_DIV); 2001 PRINTPLL(RADEON_PPLL_DIV_3); 2002 2003 /* give clock time to lock */ 2004 delay(50000); 2005 2006 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2007 RADEON_VCLK_SRC_SEL_PPLLCLK, 2008 ~RADEON_VCLK_SRC_SEL_MASK); 2009 2010 } else { 2011 2012 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2013 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2014 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2015 2016 /* put vclk into reset, use atomic updates */ 2017 SETPLL(sc, RADEON_P2PLL_CNTL, 2018 RADEON_P2PLL_RESET | 2019 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2020 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2021 2022 /* program reference divider */ 2023 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2024 ~RADEON_P2PLL_REF_DIV_MASK); 2025 2026 /* program feedback and post dividers */ 2027 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2028 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2029 RADEON_P2PLL_POST0_DIV_MASK); 2030 data |= pbit; 2031 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2032 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2033 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2034 2035 PRINTPLL(RADEON_P2PLL_REF_DIV); 2036 PRINTPLL(RADEON_P2PLL_DIV_0); 2037 2038 /* use the atomic update */ 2039 radeonfb_pllwriteupdate(sc, crtc); 2040 2041 /* and wait for it to complete */ 2042 radeonfb_pllwaitatomicread(sc, crtc); 2043 2044 /* program HTOTAL (why?) */ 2045 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2046 2047 /* drop reset */ 2048 CLRPLL(sc, RADEON_P2PLL_CNTL, 2049 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2050 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2051 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2052 2053 /* allow time for clock to lock */ 2054 delay(50000); 2055 2056 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2057 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2058 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2059 } 2060 PRINTREG(RADEON_CRTC_MORE_CNTL); 2061 } 2062 2063 void 2064 radeonfb_modeswitch(struct radeonfb_display *dp) 2065 { 2066 struct radeonfb_softc *sc = dp->rd_softc; 2067 int i; 2068 2069 /* blank the display while we switch modes */ 2070 radeonfb_blank(dp, 1); 2071 2072 #if 0 2073 SET32(sc, RADEON_CRTC_EXT_CNTL, 2074 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2075 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2076 #endif 2077 2078 /* these registers might get in the way... */ 2079 PUT32(sc, RADEON_OVR_CLR, 0); 2080 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2081 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2082 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2083 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2084 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2085 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2086 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2087 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2088 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2089 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2090 2091 for (i = 0; i < dp->rd_ncrtcs; i++) 2092 radeonfb_setcrtc(dp, i); 2093 2094 /* activate the display */ 2095 radeonfb_blank(dp, 0); 2096 } 2097 2098 void 2099 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2100 { 2101 int crtc; 2102 struct videomode *mode; 2103 struct radeonfb_softc *sc; 2104 struct radeonfb_crtc *cp; 2105 uint32_t v; 2106 uint32_t gencntl; 2107 uint32_t htotaldisp; 2108 uint32_t hsyncstrt; 2109 uint32_t vtotaldisp; 2110 uint32_t vsyncstrt; 2111 uint32_t fphsyncstrt; 2112 uint32_t fpvsyncstrt; 2113 uint32_t fphtotaldisp; 2114 uint32_t fpvtotaldisp; 2115 uint32_t pitch; 2116 2117 sc = dp->rd_softc; 2118 cp = &dp->rd_crtcs[index]; 2119 crtc = cp->rc_number; 2120 mode = &cp->rc_videomode; 2121 2122 #if 1 2123 pitch = dp->rd_stride / dp->rd_bpp; 2124 #else 2125 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2126 (sc->sc_maxbpp * 8)); 2127 #endif 2128 switch (crtc) { 2129 case 0: 2130 gencntl = RADEON_CRTC_GEN_CNTL; 2131 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2132 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2133 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2134 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2135 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2136 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2137 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2138 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2139 break; 2140 case 1: 2141 gencntl = RADEON_CRTC2_GEN_CNTL; 2142 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2143 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2144 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2145 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2146 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2147 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2148 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2149 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2150 break; 2151 default: 2152 panic("Bad CRTC!"); 2153 break; 2154 } 2155 2156 /* 2157 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2158 */ 2159 /* only bother with 32bpp and 8bpp */ 2160 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2161 2162 if (crtc == 1) { 2163 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2164 } else { 2165 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2166 } 2167 2168 if (mode->flags & VID_DBLSCAN) 2169 v |= RADEON_CRTC2_DBL_SCAN_EN; 2170 2171 if (mode->flags & VID_INTERLACE) 2172 v |= RADEON_CRTC2_INTERLACE_EN; 2173 2174 if (mode->flags & VID_CSYNC) { 2175 v |= RADEON_CRTC2_CSYNC_EN; 2176 if (crtc == 1) 2177 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2178 } 2179 2180 PUT32(sc, gencntl, v); 2181 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2182 2183 /* 2184 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2185 */ 2186 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2187 if (crtc == 0) { 2188 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2189 RADEON_CRTC_DISPLAY_DIS); 2190 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2191 if (mode->flags & VID_CSYNC) 2192 v |= RADEON_CRTC_VSYNC_TRISTAT; 2193 } 2194 /* unconditional turn on CRT, in case first CRTC is DFP */ 2195 v |= RADEON_CRTC_CRT_ON; 2196 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2197 PRINTREG(RADEON_CRTC_EXT_CNTL); 2198 2199 /* 2200 * H_TOTAL_DISP 2201 */ 2202 v = ((mode->hdisplay / 8) - 1) << 16; 2203 v |= (mode->htotal / 8) - 1; 2204 PUT32(sc, htotaldisp, v); 2205 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2206 PUT32(sc, fphtotaldisp, v); 2207 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2208 2209 /* 2210 * H_SYNC_STRT_WID 2211 */ 2212 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2213 v |= mode->hsync_start; 2214 if (mode->flags & VID_NHSYNC) 2215 v |= RADEON_CRTC_H_SYNC_POL; 2216 PUT32(sc, hsyncstrt, v); 2217 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2218 PUT32(sc, fphsyncstrt, v); 2219 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2220 2221 /* 2222 * V_TOTAL_DISP 2223 */ 2224 v = ((mode->vdisplay - 1) << 16); 2225 v |= (mode->vtotal - 1); 2226 PUT32(sc, vtotaldisp, v); 2227 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2228 PUT32(sc, fpvtotaldisp, v); 2229 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2230 2231 /* 2232 * V_SYNC_STRT_WID 2233 */ 2234 v = ((mode->vsync_end - mode->vsync_start) << 16); 2235 v |= (mode->vsync_start - 1); 2236 if (mode->flags & VID_NVSYNC) 2237 v |= RADEON_CRTC_V_SYNC_POL; 2238 PUT32(sc, vsyncstrt, v); 2239 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2240 PUT32(sc, fpvsyncstrt, v); 2241 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2242 2243 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2244 2245 switch (crtc) { 2246 case 0: 2247 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2248 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2249 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2250 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2251 2252 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2253 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2254 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2255 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2256 PRINTREG(RADEON_CRTC_EXT_CNTL); 2257 PRINTREG(RADEON_CRTC_GEN_CNTL); 2258 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2259 break; 2260 2261 case 1: 2262 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2263 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2264 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2265 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2266 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2267 RADEON_CRTC2_VSYNC_DIS | 2268 RADEON_CRTC2_HSYNC_DIS | 2269 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2270 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2271 break; 2272 } 2273 } 2274 2275 int 2276 radeonfb_isblank(struct radeonfb_display *dp) 2277 { 2278 uint32_t reg, mask; 2279 2280 if(!dp->rd_softc->sc_mapped) 2281 return 1; 2282 2283 if (dp->rd_crtcs[0].rc_number) { 2284 reg = RADEON_CRTC2_GEN_CNTL; 2285 mask = RADEON_CRTC2_DISP_DIS; 2286 } else { 2287 reg = RADEON_CRTC_EXT_CNTL; 2288 mask = RADEON_CRTC_DISPLAY_DIS; 2289 } 2290 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2291 } 2292 2293 void 2294 radeonfb_blank(struct radeonfb_display *dp, int blank) 2295 { 2296 struct radeonfb_softc *sc = dp->rd_softc; 2297 uint32_t reg, mask; 2298 uint32_t fpreg, fpval; 2299 int i; 2300 2301 if (!sc->sc_mapped) 2302 return; 2303 2304 for (i = 0; i < dp->rd_ncrtcs; i++) { 2305 2306 if (dp->rd_crtcs[i].rc_number) { 2307 reg = RADEON_CRTC2_GEN_CNTL; 2308 mask = RADEON_CRTC2_DISP_DIS; 2309 fpreg = RADEON_FP2_GEN_CNTL; 2310 fpval = RADEON_FP2_ON; 2311 } else { 2312 reg = RADEON_CRTC_EXT_CNTL; 2313 mask = RADEON_CRTC_DISPLAY_DIS; 2314 fpreg = RADEON_FP_GEN_CNTL; 2315 fpval = RADEON_FP_FPON; 2316 } 2317 2318 if (blank) { 2319 SET32(sc, reg, mask); 2320 CLR32(sc, fpreg, fpval); 2321 } else { 2322 CLR32(sc, reg, mask); 2323 SET32(sc, fpreg, fpval); 2324 } 2325 } 2326 PRINTREG(RADEON_FP_GEN_CNTL); 2327 PRINTREG(RADEON_FP2_GEN_CNTL); 2328 } 2329 2330 void 2331 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2332 long *defattr) 2333 { 2334 struct radeonfb_display *dp = cookie; 2335 struct rasops_info *ri = &scr->scr_ri; 2336 2337 /* initialize font subsystem */ 2338 wsfont_init(); 2339 2340 DPRINTF(("init screen called, existing %d\n", existing)); 2341 2342 ri->ri_depth = dp->rd_bpp; 2343 ri->ri_width = dp->rd_virtx; 2344 ri->ri_height = dp->rd_virty; 2345 ri->ri_stride = dp->rd_stride; 2346 ri->ri_flg = RI_CENTER; 2347 switch (ri->ri_depth) { 2348 case 8: 2349 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2350 break; 2351 case 32: 2352 ri->ri_flg |= RI_ENABLE_ALPHA; 2353 /* we run radeons in RGB even on SPARC hardware */ 2354 ri->ri_rnum = 8; 2355 ri->ri_gnum = 8; 2356 ri->ri_bnum = 8; 2357 ri->ri_rpos = 16; 2358 ri->ri_gpos = 8; 2359 ri->ri_bpos = 0; 2360 break; 2361 } 2362 2363 ri->ri_bits = (void *)dp->rd_fbptr; 2364 2365 #ifdef VCONS_DRAW_INTR 2366 scr->scr_flags |= VCONS_DONT_READ; 2367 #endif 2368 2369 if (existing) { 2370 ri->ri_flg |= RI_CLEAR; 2371 2372 /* start a modeswitch now */ 2373 radeonfb_modeswitch(dp); 2374 } 2375 2376 /* 2377 * XXX: font selection should be based on properties, with some 2378 * normal/reasonable default. 2379 */ 2380 2381 /* initialize and look for an initial font */ 2382 rasops_init(ri, 0, 0); 2383 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2384 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2385 2386 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2387 dp->rd_virtx / ri->ri_font->fontwidth); 2388 2389 /* enable acceleration */ 2390 dp->rd_putchar = ri->ri_ops.putchar; 2391 ri->ri_ops.copyrows = radeonfb_copyrows; 2392 ri->ri_ops.copycols = radeonfb_copycols; 2393 ri->ri_ops.eraserows = radeonfb_eraserows; 2394 ri->ri_ops.erasecols = radeonfb_erasecols; 2395 /* pick a putchar method based on font and Radeon model */ 2396 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2397 /* got a bitmap font */ 2398 if (IS_R300(dp->rd_softc)) { 2399 /* 2400 * radeonfb_putchar() doesn't work right on some R3xx 2401 * so we use software drawing here, the wrapper just 2402 * makes sure the engine is idle before scribbling 2403 * into vram 2404 */ 2405 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2406 } else { 2407 ri->ri_ops.putchar = radeonfb_putchar; 2408 } 2409 } else { 2410 /* got an alpha font */ 2411 switch(ri->ri_depth) { 2412 case 32: 2413 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2414 break; 2415 case 8: 2416 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2417 break; 2418 default: 2419 /* XXX this should never happen */ 2420 panic("%s: depth is not 8 or 32 but we got an" \ 2421 " alpha font?!", __func__); 2422 } 2423 } 2424 ri->ri_ops.cursor = radeonfb_cursor; 2425 } 2426 2427 void 2428 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2429 { 2430 uint32_t gen, ext, gen2 = 0; 2431 uint32_t agploc, aperbase, apersize, mcfbloc; 2432 2433 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2434 /* XXX */ 2435 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2436 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2437 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2438 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2439 2440 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2441 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2442 #if 0 2443 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2444 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2445 #endif 2446 2447 if (HAS_CRTC2(sc)) { 2448 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2449 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2450 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2451 } 2452 2453 delay(100000); 2454 2455 mcfbloc = (aperbase >> 16) | 2456 ((aperbase + (apersize - 1)) & 0xffff0000); 2457 2458 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2459 sc->sc_memsz = apersize; 2460 2461 if (((agploc & 0xffff) << 16) != 2462 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2463 agploc = mcfbloc & 0xffff0000U; 2464 agploc |= ((agploc + 0x10000) >> 16); 2465 } 2466 2467 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2468 2469 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2470 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2471 2472 DPRINTF(("aperbase = %u\n", aperbase)); 2473 PRINTREG(RADEON_MC_FB_LOCATION); 2474 PRINTREG(RADEON_MC_AGP_LOCATION); 2475 2476 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2477 2478 if (HAS_CRTC2(sc)) 2479 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2480 2481 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2482 2483 #if 0 2484 /* XXX: what is this AGP garbage? :-) */ 2485 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2486 #endif 2487 2488 delay(100000); 2489 2490 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2491 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2492 2493 if (HAS_CRTC2(sc)) 2494 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2495 } 2496 2497 void 2498 radeonfb_init_misc(struct radeonfb_softc *sc) 2499 { 2500 PUT32(sc, RADEON_BUS_CNTL, 2501 RADEON_BUS_MASTER_DIS | 2502 RADEON_BUS_PREFETCH_MODE_ACT | 2503 RADEON_BUS_PCI_READ_RETRY_EN | 2504 RADEON_BUS_PCI_WRT_RETRY_EN | 2505 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2506 RADEON_BUS_MSTR_RD_MULT | 2507 RADEON_BUS_MSTR_RD_LINE | 2508 RADEON_BUS_RD_DISCARD_EN | 2509 RADEON_BUS_MSTR_DISCONNECT_EN | 2510 RADEON_BUS_READ_BURST); 2511 2512 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2513 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2514 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2515 PUT32(sc, RADEON_RBBM_CNTL, 2516 (3 << RADEON_RB_SETTLE_SHIFT) | 2517 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2518 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2519 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2520 2521 /* XXX: figure out what these mean! */ 2522 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2523 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2524 #if 0 2525 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2526 #endif 2527 2528 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2529 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2530 } 2531 2532 /* 2533 * This loads a linear color map for true color. 2534 */ 2535 void 2536 radeonfb_init_palette(struct radeonfb_display *dp) 2537 { 2538 struct radeonfb_softc *sc = dp->rd_softc; 2539 int i, cc; 2540 uint32_t vclk; 2541 int crtc; 2542 2543 #define DAC_WIDTH ((1 << 10) - 1) 2544 #define CLUT_WIDTH ((1 << 8) - 1) 2545 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2546 2547 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2548 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2549 2550 /* initialize the palette for every CRTC used by this display */ 2551 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2552 crtc = dp->rd_crtcs[cc].rc_number; 2553 2554 if (crtc) 2555 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2556 else 2557 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2558 2559 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2560 2561 if (dp->rd_bpp == 0) 2562 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; 2563 2564 if (dp->rd_bpp == 8) { 2565 /* ANSI palette */ 2566 int j = 0; 2567 uint32_t tmp, r, g, b; 2568 2569 for (i = 0; i <= CLUT_WIDTH; ++i) { 2570 tmp = i & 0xe0; 2571 /* 2572 * replicate bits so 0xe0 maps to a red value of 0xff 2573 * in order to make white look actually white 2574 */ 2575 tmp |= (tmp >> 3) | (tmp >> 6); 2576 r = tmp; 2577 2578 tmp = (i & 0x1c) << 3; 2579 tmp |= (tmp >> 3) | (tmp >> 6); 2580 g = tmp; 2581 2582 tmp = (i & 0x03) << 6; 2583 tmp |= tmp >> 2; 2584 tmp |= tmp >> 4; 2585 b = tmp; 2586 2587 PUT32(sc, RADEON_PALETTE_30_DATA, 2588 (r << 22) | 2589 (g << 12) | 2590 (b << 2)); 2591 j += 3; 2592 } 2593 } else { 2594 /* linear ramp */ 2595 for (i = 0; i <= CLUT_WIDTH; ++i) { 2596 PUT32(sc, RADEON_PALETTE_30_DATA, 2597 (CLUT_COLOR(i) << 10) | 2598 (CLUT_COLOR(i) << 20) | 2599 (CLUT_COLOR(i))); 2600 } 2601 } 2602 } 2603 2604 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2605 PRINTREG(RADEON_DAC_CNTL2); 2606 2607 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2608 } 2609 2610 /* 2611 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2612 */ 2613 void 2614 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2615 { 2616 uint32_t tmp, save; 2617 2618 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2619 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2620 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2621 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2622 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2623 } 2624 2625 /* 2626 * Acceleration entry points. 2627 */ 2628 2629 /* this one draws characters using bitmap fonts */ 2630 static void 2631 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2632 { 2633 struct rasops_info *ri = cookie; 2634 struct vcons_screen *scr = ri->ri_hw; 2635 struct radeonfb_display *dp = scr->scr_cookie; 2636 struct radeonfb_softc *sc = dp->rd_softc; 2637 struct wsdisplay_font *font = PICK_FONT(ri, c); 2638 uint32_t w, h; 2639 int xd, yd, offset, i; 2640 uint32_t bg, fg, gmc; 2641 uint32_t reg; 2642 uint8_t *data8; 2643 uint16_t *data16; 2644 void *data; 2645 2646 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2647 return; 2648 2649 if (!CHAR_IN_FONT(c, font)) 2650 return; 2651 2652 w = font->fontwidth; 2653 h = font->fontheight; 2654 2655 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2656 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2657 2658 xd = ri->ri_xorigin + col * w; 2659 yd = ri->ri_yorigin + row * h; 2660 2661 if (c == 0x20) { 2662 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2663 return; 2664 } 2665 data = WSFONT_GLYPH(c, font); 2666 2667 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2668 2669 radeonfb_wait_fifo(sc, 9); 2670 2671 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2672 RADEON_GMC_BRUSH_NONE | 2673 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2674 RADEON_GMC_DST_CLIPPING | 2675 RADEON_ROP3_S | 2676 RADEON_DP_SRC_SOURCE_HOST_DATA | 2677 RADEON_GMC_CLR_CMP_CNTL_DIS | 2678 RADEON_GMC_WR_MSK_DIS | 2679 gmc); 2680 2681 PUT32(sc, RADEON_SC_LEFT, xd); 2682 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2683 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2684 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2685 PUT32(sc, RADEON_DP_CNTL, 2686 RADEON_DST_X_LEFT_TO_RIGHT | 2687 RADEON_DST_Y_TOP_TO_BOTTOM); 2688 2689 PUT32(sc, RADEON_SRC_X_Y, 0); 2690 offset = 32 - (font->stride << 3); 2691 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2692 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2693 2694 radeonfb_wait_fifo(sc, h); 2695 switch (font->stride) { 2696 case 1: { 2697 data8 = data; 2698 for (i = 0; i < h; i++) { 2699 reg = *data8; 2700 #if BYTE_ORDER == LITTLE_ENDIAN 2701 reg = reg << 24; 2702 #endif 2703 bus_space_write_stream_4(sc->sc_regt, 2704 sc->sc_regh, RADEON_HOST_DATA0, reg); 2705 data8++; 2706 } 2707 break; 2708 } 2709 case 2: { 2710 data16 = data; 2711 for (i = 0; i < h; i++) { 2712 reg = *data16; 2713 #if BYTE_ORDER == LITTLE_ENDIAN 2714 reg = reg << 16; 2715 #endif 2716 bus_space_write_stream_4(sc->sc_regt, 2717 sc->sc_regh, RADEON_HOST_DATA0, reg); 2718 data16++; 2719 } 2720 break; 2721 } 2722 } 2723 if (attr & 1) 2724 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2725 } 2726 2727 /* ... while this one is for anti-aliased ones */ 2728 static void 2729 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2730 { 2731 struct rasops_info *ri = cookie; 2732 struct vcons_screen *scr = ri->ri_hw; 2733 struct radeonfb_display *dp = scr->scr_cookie; 2734 struct radeonfb_softc *sc = dp->rd_softc; 2735 struct wsdisplay_font *font = PICK_FONT(ri, c); 2736 uint32_t bg, fg, gmc; 2737 uint8_t *data; 2738 int w, h, xd, yd; 2739 int i, r, g, b, aval; 2740 int rf, gf, bf, rb, gb, bb; 2741 uint32_t pixel; 2742 int rv; 2743 2744 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2745 return; 2746 2747 if (!CHAR_IN_FONT(c, font)) 2748 return; 2749 2750 w = font->fontwidth; 2751 h = font->fontheight; 2752 2753 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2754 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2755 2756 xd = ri->ri_xorigin + col * w; 2757 yd = ri->ri_yorigin + row * h; 2758 2759 if (c == 0x20) { 2760 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2761 if (attr & 1) 2762 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2763 return; 2764 } 2765 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2766 if (rv == GC_OK) 2767 return; 2768 2769 data = WSFONT_GLYPH(c, font); 2770 2771 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2772 2773 radeonfb_wait_fifo(sc, 5); 2774 2775 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2776 RADEON_GMC_BRUSH_NONE | 2777 RADEON_GMC_SRC_DATATYPE_COLOR | 2778 RADEON_ROP3_S | 2779 RADEON_DP_SRC_SOURCE_HOST_DATA | 2780 RADEON_GMC_CLR_CMP_CNTL_DIS | 2781 RADEON_GMC_WR_MSK_DIS | 2782 gmc); 2783 2784 PUT32(sc, RADEON_DP_CNTL, 2785 RADEON_DST_X_LEFT_TO_RIGHT | 2786 RADEON_DST_Y_TOP_TO_BOTTOM); 2787 2788 PUT32(sc, RADEON_SRC_X_Y, 0); 2789 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2790 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2791 2792 rf = (fg >> 16) & 0xff; 2793 rb = (bg >> 16) & 0xff; 2794 gf = (fg >> 8) & 0xff; 2795 gb = (bg >> 8) & 0xff; 2796 bf = fg & 0xff; 2797 bb = bg & 0xff; 2798 2799 /* 2800 * I doubt we can upload data faster than even the slowest Radeon 2801 * could process them, especially when doing the alpha blending stuff 2802 * along the way, so just make sure there's some room in the FIFO and 2803 * then hammer away 2804 * As it turns out we can, so make periodic stops to let the FIFO 2805 * drain. 2806 */ 2807 radeonfb_wait_fifo(sc, 20); 2808 for (i = 0; i < ri->ri_fontscale; i++) { 2809 aval = *data; 2810 data++; 2811 if (aval == 0) { 2812 pixel = bg; 2813 } else if (aval == 255) { 2814 pixel = fg; 2815 } else { 2816 r = aval * rf + (255 - aval) * rb; 2817 g = aval * gf + (255 - aval) * gb; 2818 b = aval * bf + (255 - aval) * bb; 2819 pixel = (r & 0xff00) << 8 | 2820 (g & 0xff00) | 2821 (b & 0xff00) >> 8; 2822 } 2823 if (i & 16) 2824 radeonfb_wait_fifo(sc, 20); 2825 PUT32(sc, RADEON_HOST_DATA0, pixel); 2826 } 2827 if (rv == GC_ADD) { 2828 glyphcache_add(&dp->rd_gc, c, xd, yd); 2829 } else 2830 if (attr & 1) 2831 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2832 2833 } 2834 2835 static void 2836 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2837 { 2838 struct rasops_info *ri = cookie; 2839 struct vcons_screen *scr = ri->ri_hw; 2840 struct radeonfb_display *dp = scr->scr_cookie; 2841 struct radeonfb_softc *sc = dp->rd_softc; 2842 struct wsdisplay_font *font = PICK_FONT(ri, c); 2843 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2844 int i, x, y, wi, he, r, g, b, aval; 2845 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2846 uint8_t *data8; 2847 int rv, cnt; 2848 2849 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2850 return; 2851 2852 if (!CHAR_IN_FONT(c, font)) 2853 return; 2854 2855 wi = font->fontwidth; 2856 he = font->fontheight; 2857 2858 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2859 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2860 2861 x = ri->ri_xorigin + col * wi; 2862 y = ri->ri_yorigin + row * he; 2863 2864 if (c == 0x20) { 2865 radeonfb_rectfill(dp, x, y, wi, he, bg); 2866 if (attr & 1) 2867 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2868 return; 2869 } 2870 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2871 if (rv == GC_OK) 2872 return; 2873 2874 data8 = WSFONT_GLYPH(c, font); 2875 2876 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2877 2878 radeonfb_wait_fifo(sc, 5); 2879 2880 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2881 RADEON_GMC_BRUSH_NONE | 2882 RADEON_GMC_SRC_DATATYPE_COLOR | 2883 RADEON_ROP3_S | 2884 RADEON_DP_SRC_SOURCE_HOST_DATA | 2885 RADEON_GMC_CLR_CMP_CNTL_DIS | 2886 RADEON_GMC_WR_MSK_DIS | 2887 gmc); 2888 2889 PUT32(sc, RADEON_DP_CNTL, 2890 RADEON_DST_X_LEFT_TO_RIGHT | 2891 RADEON_DST_Y_TOP_TO_BOTTOM); 2892 2893 PUT32(sc, RADEON_SRC_X_Y, 0); 2894 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2895 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2896 2897 /* 2898 * we need the RGB colours here, so get offsets into rasops_cmap 2899 */ 2900 fgo = ((attr >> 24) & 0xf) * 3; 2901 bgo = ((attr >> 16) & 0xf) * 3; 2902 2903 r0 = rasops_cmap[bgo]; 2904 r1 = rasops_cmap[fgo]; 2905 g0 = rasops_cmap[bgo + 1]; 2906 g1 = rasops_cmap[fgo + 1]; 2907 b0 = rasops_cmap[bgo + 2]; 2908 b1 = rasops_cmap[fgo + 2]; 2909 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2910 bg8 = R3G3B2(r0, g0, b0); 2911 fg8 = R3G3B2(r1, g1, b1); 2912 2913 radeonfb_wait_fifo(sc, 20); 2914 cnt = 0; 2915 for (i = 0; i < ri->ri_fontscale; i++) { 2916 aval = *data8; 2917 if (aval == 0) { 2918 pixel = bg8; 2919 } else if (aval == 255) { 2920 pixel = fg8; 2921 } else { 2922 r = aval * r1 + (255 - aval) * r0; 2923 g = aval * g1 + (255 - aval) * g0; 2924 b = aval * b1 + (255 - aval) * b0; 2925 pixel = ((r & 0xe000) >> 8) | 2926 ((g & 0xe000) >> 11) | 2927 ((b & 0xc000) >> 14); 2928 } 2929 latch |= pixel << (8 * (i & 3)); 2930 /* write in 32bit chunks */ 2931 if ((i & 3) == 3) { 2932 PUT32(sc, RADEON_HOST_DATA0, latch); 2933 /* 2934 * not strictly necessary, old data should be shifted 2935 * out 2936 */ 2937 latch = 0; 2938 cnt++; 2939 if (cnt > 16) { 2940 cnt = 0; 2941 radeonfb_wait_fifo(sc, 20); 2942 } 2943 } 2944 data8++; 2945 } 2946 /* if we have pixels left in latch write them out */ 2947 if ((i & 3) != 0) { 2948 /* 2949 * radeon is weird - apparently leftover pixels are written 2950 * from the middle, not from the left as everything else 2951 */ 2952 PUT32(sc, RADEON_HOST_DATA0, latch); 2953 } 2954 2955 if (rv == GC_ADD) { 2956 glyphcache_add(&dp->rd_gc, c, x, y); 2957 } else 2958 if (attr & 1) 2959 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2960 2961 } 2962 2963 /* 2964 * wrapper for software character drawing 2965 * just sync the engine and call rasops*_putchar() 2966 */ 2967 2968 static void 2969 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2970 { 2971 struct rasops_info *ri = cookie; 2972 struct vcons_screen *scr = ri->ri_hw; 2973 struct radeonfb_display *dp = scr->scr_cookie; 2974 2975 radeonfb_engine_idle(dp->rd_softc); 2976 dp->rd_putchar(ri, row, col, c, attr); 2977 } 2978 2979 static void 2980 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2981 { 2982 struct rasops_info *ri = cookie; 2983 struct vcons_screen *scr = ri->ri_hw; 2984 struct radeonfb_display *dp = scr->scr_cookie; 2985 uint32_t x, y, w, h, fg, bg, ul; 2986 2987 /* XXX: check for full emulation mode? */ 2988 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2989 x = ri->ri_xorigin; 2990 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2991 w = ri->ri_emuwidth; 2992 h = ri->ri_font->fontheight * nrows; 2993 2994 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2995 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2996 } 2997 } 2998 2999 static void 3000 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3001 { 3002 struct rasops_info *ri = cookie; 3003 struct vcons_screen *scr = ri->ri_hw; 3004 struct radeonfb_display *dp = scr->scr_cookie; 3005 uint32_t x, ys, yd, w, h; 3006 3007 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3008 x = ri->ri_xorigin; 3009 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3010 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3011 w = ri->ri_emuwidth; 3012 h = ri->ri_font->fontheight * nrows; 3013 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3014 RADEON_ROP3_S); 3015 } 3016 } 3017 3018 static void 3019 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3020 { 3021 struct rasops_info *ri = cookie; 3022 struct vcons_screen *scr = ri->ri_hw; 3023 struct radeonfb_display *dp = scr->scr_cookie; 3024 uint32_t xs, xd, y, w, h; 3025 3026 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3027 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3028 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3029 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3030 w = ri->ri_font->fontwidth * ncols; 3031 h = ri->ri_font->fontheight; 3032 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3033 RADEON_ROP3_S); 3034 } 3035 } 3036 3037 static void 3038 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3039 long fillattr) 3040 { 3041 struct rasops_info *ri = cookie; 3042 struct vcons_screen *scr = ri->ri_hw; 3043 struct radeonfb_display *dp = scr->scr_cookie; 3044 uint32_t x, y, w, h, fg, bg, ul; 3045 3046 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3047 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3048 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3049 w = ri->ri_font->fontwidth * ncols; 3050 h = ri->ri_font->fontheight; 3051 3052 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3053 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3054 } 3055 } 3056 3057 static void 3058 radeonfb_cursor(void *cookie, int on, int row, int col) 3059 { 3060 struct rasops_info *ri = cookie; 3061 struct vcons_screen *scr = ri->ri_hw; 3062 struct radeonfb_display *dp = scr->scr_cookie; 3063 int x, y, wi, he; 3064 3065 wi = ri->ri_font->fontwidth; 3066 he = ri->ri_font->fontheight; 3067 3068 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3069 x = ri->ri_ccol * wi + ri->ri_xorigin; 3070 y = ri->ri_crow * he + ri->ri_yorigin; 3071 /* first turn off the old cursor */ 3072 if (ri->ri_flg & RI_CURSOR) { 3073 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3074 RADEON_ROP3_Dn); 3075 ri->ri_flg &= ~RI_CURSOR; 3076 } 3077 ri->ri_crow = row; 3078 ri->ri_ccol = col; 3079 /* then (possibly) turn on the new one */ 3080 if (on) { 3081 x = ri->ri_ccol * wi + ri->ri_xorigin; 3082 y = ri->ri_crow * he + ri->ri_yorigin; 3083 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3084 RADEON_ROP3_Dn); 3085 ri->ri_flg |= RI_CURSOR; 3086 } 3087 } else { 3088 scr->scr_ri.ri_crow = row; 3089 scr->scr_ri.ri_ccol = col; 3090 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3091 } 3092 } 3093 3094 /* 3095 * Underlying acceleration support. 3096 */ 3097 3098 static void 3099 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3100 int width, int height, uint32_t color) 3101 { 3102 struct radeonfb_softc *sc = dp->rd_softc; 3103 uint32_t gmc; 3104 3105 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3106 3107 radeonfb_wait_fifo(sc, 6); 3108 3109 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3110 RADEON_GMC_BRUSH_SOLID_COLOR | 3111 RADEON_GMC_SRC_DATATYPE_COLOR | 3112 RADEON_GMC_CLR_CMP_CNTL_DIS | 3113 RADEON_ROP3_P | gmc); 3114 3115 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3116 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3117 PUT32(sc, RADEON_DP_CNTL, 3118 RADEON_DST_X_LEFT_TO_RIGHT | 3119 RADEON_DST_Y_TOP_TO_BOTTOM); 3120 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3121 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3122 3123 } 3124 3125 static void 3126 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3127 int width, int height, long attr) 3128 { 3129 struct radeonfb_display *dp = cookie; 3130 3131 radeonfb_rectfill(dp, dstx, dsty, width, height, 3132 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3133 } 3134 3135 static void 3136 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3137 int dstx, int dsty, int width, int height, int rop) 3138 { 3139 struct radeonfb_display *dp = cookie; 3140 struct radeonfb_softc *sc = dp->rd_softc; 3141 uint32_t gmc; 3142 uint32_t dir; 3143 3144 if (dsty < srcy) { 3145 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3146 } else { 3147 srcy += height - 1; 3148 dsty += height - 1; 3149 dir = 0; 3150 } 3151 if (dstx < srcx) { 3152 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3153 } else { 3154 srcx += width - 1; 3155 dstx += width - 1; 3156 } 3157 3158 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3159 3160 radeonfb_wait_fifo(sc, 6); 3161 3162 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3163 RADEON_GMC_BRUSH_SOLID_COLOR | 3164 RADEON_GMC_SRC_DATATYPE_COLOR | 3165 RADEON_GMC_CLR_CMP_CNTL_DIS | 3166 RADEON_DP_SRC_SOURCE_MEMORY | 3167 rop | gmc); 3168 3169 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3170 PUT32(sc, RADEON_DP_CNTL, dir); 3171 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3172 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3173 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3174 } 3175 3176 static void 3177 radeonfb_engine_idle(struct radeonfb_softc *sc) 3178 { 3179 3180 radeonfb_wait_fifo(sc, 64); 3181 while ((GET32(sc, RADEON_RBBM_STATUS) & 3182 RADEON_RBBM_ACTIVE) != 0); 3183 radeonfb_engine_flush(sc); 3184 } 3185 3186 static inline void 3187 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3188 { 3189 int i; 3190 3191 for (i = RADEON_TIMEOUT; i; i--) { 3192 if ((GET32(sc, RADEON_RBBM_STATUS) & 3193 RADEON_RBBM_FIFOCNT_MASK) >= n) 3194 return; 3195 } 3196 #ifdef DIAGNOSTIC 3197 if (!i) 3198 printf("%s: timed out waiting for fifo (%x)\n", 3199 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3200 #endif 3201 } 3202 3203 static void 3204 radeonfb_engine_flush(struct radeonfb_softc *sc) 3205 { 3206 int i = 0; 3207 3208 if (IS_R300(sc)) { 3209 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3210 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3211 i++; 3212 } 3213 } else { 3214 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3215 RADEON_RB2D_DC_FLUSH_ALL); 3216 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3217 RADEON_RB2D_DC_BUSY) { 3218 i++; 3219 } 3220 } 3221 #ifdef DIAGNOSTIC 3222 if (i > RADEON_TIMEOUT) 3223 printf("%s: engine flush timed out!\n", XNAME(sc)); 3224 #endif 3225 } 3226 3227 static inline void 3228 radeonfb_unclip(struct radeonfb_softc *sc) 3229 { 3230 3231 radeonfb_wait_fifo(sc, 2); 3232 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3233 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3234 } 3235 3236 static void 3237 radeonfb_engine_init(struct radeonfb_display *dp) 3238 { 3239 struct radeonfb_softc *sc = dp->rd_softc; 3240 uint32_t pitch; 3241 volatile uint32_t junk; 3242 3243 /* no 3D */ 3244 PUT32(sc, RADEON_RB3D_CNTL, 0); 3245 3246 radeonfb_engine_reset(sc); 3247 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3248 3249 radeonfb_wait_fifo(sc, 1); 3250 if (!IS_R300(sc)) 3251 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3252 3253 radeonfb_wait_fifo(sc, 3); 3254 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3255 (pitch << 22) | (sc->sc_aperbase >> 10)); 3256 3257 3258 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3259 (pitch << 22) | (sc->sc_aperbase >> 10)); 3260 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3261 (pitch << 22) | (sc->sc_aperbase >> 10)); 3262 3263 junk = GET32(sc, RADEON_DP_DATATYPE); 3264 3265 /* default scissors -- no clipping */ 3266 radeonfb_wait_fifo(sc, 1); 3267 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3268 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3269 3270 radeonfb_wait_fifo(sc, 1); 3271 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3272 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3273 RADEON_GMC_CLR_CMP_CNTL_DIS | 3274 RADEON_GMC_BRUSH_SOLID_COLOR | 3275 RADEON_GMC_SRC_DATATYPE_COLOR); 3276 3277 radeonfb_wait_fifo(sc, 10); 3278 PUT32(sc, RADEON_DST_LINE_START, 0); 3279 PUT32(sc, RADEON_DST_LINE_END, 0); 3280 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3281 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3282 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3283 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3284 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3285 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3286 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3287 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3288 radeonfb_engine_idle(sc); 3289 } 3290 3291 static void 3292 radeonfb_engine_reset(struct radeonfb_softc *sc) 3293 { 3294 uint32_t hpc, rbbm, mclkcntl, clkindex; 3295 3296 radeonfb_engine_flush(sc); 3297 3298 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3299 if (HAS_R300CG(sc)) 3300 radeonfb_r300cg_workaround(sc); 3301 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3302 3303 /* 3304 * According to comments in XFree code, resetting the HDP via 3305 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3306 * So we use HOST_PATH_CNTL instead. 3307 */ 3308 3309 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3310 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3311 if (IS_R300(sc)) { 3312 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3313 RADEON_SOFT_RESET_CP | 3314 RADEON_SOFT_RESET_HI | 3315 RADEON_SOFT_RESET_E2); 3316 GET32(sc, RADEON_RBBM_SOFT_RESET); 3317 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3318 /* 3319 * XXX: this bit is not defined in any ATI docs I have, 3320 * nor in the XFree code, but XFree does it. Why? 3321 */ 3322 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3323 } else { 3324 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3325 RADEON_SOFT_RESET_CP | 3326 RADEON_SOFT_RESET_SE | 3327 RADEON_SOFT_RESET_RE | 3328 RADEON_SOFT_RESET_PP | 3329 RADEON_SOFT_RESET_E2 | 3330 RADEON_SOFT_RESET_RB); 3331 GET32(sc, RADEON_RBBM_SOFT_RESET); 3332 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3333 ~(RADEON_SOFT_RESET_CP | 3334 RADEON_SOFT_RESET_SE | 3335 RADEON_SOFT_RESET_RE | 3336 RADEON_SOFT_RESET_PP | 3337 RADEON_SOFT_RESET_E2 | 3338 RADEON_SOFT_RESET_RB)); 3339 GET32(sc, RADEON_RBBM_SOFT_RESET); 3340 } 3341 3342 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3343 GET32(sc, RADEON_HOST_PATH_CNTL); 3344 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3345 3346 if (IS_R300(sc)) 3347 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3348 3349 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3350 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3351 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3352 3353 if (HAS_R300CG(sc)) 3354 radeonfb_r300cg_workaround(sc); 3355 } 3356 3357 static int 3358 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3359 { 3360 int x, y; 3361 3362 x = pos->x; 3363 y = pos->y; 3364 3365 /* 3366 * This doesn't let a cursor move off the screen. I'm not 3367 * sure if this will have negative effects for e.g. Xinerama. 3368 * I'd guess Xinerama handles it by changing the cursor shape, 3369 * but that needs verification. 3370 */ 3371 if (x >= dp->rd_virtx) 3372 x = dp->rd_virtx - 1; 3373 if (x < 0) 3374 x = 0; 3375 if (y >= dp->rd_virty) 3376 y = dp->rd_virty - 1; 3377 if (y < 0) 3378 y = 0; 3379 3380 dp->rd_cursor.rc_pos.x = x; 3381 dp->rd_cursor.rc_pos.y = y; 3382 3383 radeonfb_cursor_position(dp); 3384 return 0; 3385 } 3386 3387 static int 3388 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3389 { 3390 unsigned flags; 3391 3392 uint8_t r[2], g[2], b[2]; 3393 unsigned index, count; 3394 int i, err; 3395 int pitch, size; 3396 struct radeonfb_cursor nc; 3397 3398 flags = wc->which; 3399 3400 /* copy old values */ 3401 nc = dp->rd_cursor; 3402 3403 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3404 index = wc->cmap.index; 3405 count = wc->cmap.count; 3406 3407 if (index >= 2 || (index + count) > 2) 3408 return EINVAL; 3409 3410 err = copyin(wc->cmap.red, &r[index], count); 3411 if (err) 3412 return err; 3413 err = copyin(wc->cmap.green, &g[index], count); 3414 if (err) 3415 return err; 3416 err = copyin(wc->cmap.blue, &b[index], count); 3417 if (err) 3418 return err; 3419 3420 for (i = index; i < index + count; i++) { 3421 nc.rc_cmap[i] = 3422 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3423 } 3424 } 3425 3426 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3427 if ((wc->size.x > RADEON_CURSORMAXX) || 3428 (wc->size.y > RADEON_CURSORMAXY)) 3429 return EINVAL; 3430 3431 /* figure bytes per line */ 3432 pitch = (wc->size.x + 7) / 8; 3433 size = pitch * wc->size.y; 3434 3435 /* clear the old cursor and mask */ 3436 memset(nc.rc_image, 0, 512); 3437 memset(nc.rc_mask, 0, 512); 3438 3439 nc.rc_size = wc->size; 3440 3441 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3442 return err; 3443 3444 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3445 return err; 3446 } 3447 3448 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3449 nc.rc_hot = wc->hot; 3450 if (nc.rc_hot.x >= nc.rc_size.x) 3451 nc.rc_hot.x = nc.rc_size.x - 1; 3452 if (nc.rc_hot.y >= nc.rc_size.y) 3453 nc.rc_hot.y = nc.rc_size.y - 1; 3454 } 3455 3456 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3457 nc.rc_pos = wc->pos; 3458 if (nc.rc_pos.x >= dp->rd_virtx) 3459 nc.rc_pos.x = dp->rd_virtx - 1; 3460 #if 0 3461 if (nc.rc_pos.x < 0) 3462 nc.rc_pos.x = 0; 3463 #endif 3464 if (nc.rc_pos.y >= dp->rd_virty) 3465 nc.rc_pos.y = dp->rd_virty - 1; 3466 #if 0 3467 if (nc.rc_pos.y < 0) 3468 nc.rc_pos.y = 0; 3469 #endif 3470 } 3471 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3472 nc.rc_visible = wc->enable; 3473 } 3474 3475 dp->rd_cursor = nc; 3476 radeonfb_cursor_update(dp, wc->which); 3477 3478 return 0; 3479 } 3480 3481 /* 3482 * Change the cursor shape. Call this with the cursor locked to avoid 3483 * flickering/tearing. 3484 */ 3485 static void 3486 radeonfb_cursor_shape(struct radeonfb_display *dp) 3487 { 3488 uint8_t and[512], xor[512]; 3489 int i, j, src, dst, pitch; 3490 const uint8_t *msk = dp->rd_cursor.rc_mask; 3491 const uint8_t *img = dp->rd_cursor.rc_image; 3492 3493 /* 3494 * Radeon cursor data interleaves one line of AND data followed 3495 * by a line of XOR data. (Each line corresponds to a whole hardware 3496 * pitch - i.e. 64 pixels or 8 bytes.) 3497 * 3498 * The cursor is displayed using the following table: 3499 * 3500 * AND XOR Result 3501 * ---------------------- 3502 * 0 0 Cursor color 0 3503 * 0 1 Cursor color 1 3504 * 1 0 Transparent 3505 * 1 1 Complement of background 3506 * 3507 * Our masks are therefore different from what we were passed. 3508 * Passed in, I'm assuming the data represents either color 0 or 1, 3509 * and a mask, so the passed in table looks like: 3510 * 3511 * IMG Mask Result 3512 * ----------------------- 3513 * 0 0 Transparent 3514 * 0 1 Cursor color 0 3515 * 1 0 Transparent 3516 * 1 1 Cursor color 1 3517 * 3518 * IF mask bit == 1, AND = 0, XOR = color. 3519 * IF mask bit == 0, AND = 1, XOR = 0. 3520 * 3521 * hence: AND = ~(mask); XOR = color & ~(mask); 3522 */ 3523 3524 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3525 3526 /* start by assuming all bits are transparent */ 3527 memset(and, 0xff, 512); 3528 memset(xor, 0x00, 512); 3529 3530 src = 0; 3531 dst = 0; 3532 for (i = 0; i < 64; i++) { 3533 for (j = 0; j < 64; j += 8) { 3534 if ((i < dp->rd_cursor.rc_size.y) && 3535 (j < dp->rd_cursor.rc_size.x)) { 3536 3537 /* take care to leave odd bits alone */ 3538 and[dst] &= ~(msk[src]); 3539 xor[dst] = img[src] & msk[src]; 3540 src++; 3541 } 3542 dst++; 3543 } 3544 } 3545 3546 /* copy the image into place */ 3547 for (i = 0; i < 64; i++) { 3548 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3549 &and[i * 8], 8); 3550 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3551 &xor[i * 8], 8); 3552 } 3553 } 3554 3555 static void 3556 radeonfb_cursor_position(struct radeonfb_display *dp) 3557 { 3558 struct radeonfb_softc *sc = dp->rd_softc; 3559 uint32_t offset, hvoff, hvpos; /* registers */ 3560 uint32_t coff; /* cursor offset */ 3561 int i, x, y, xoff, yoff, crtcoff; 3562 3563 /* 3564 * XXX: this also needs to handle pan/scan 3565 */ 3566 for (i = 0; i < dp->rd_ncrtcs; i++) { 3567 3568 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3569 3570 if (rcp->rc_number) { 3571 offset = RADEON_CUR2_OFFSET; 3572 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3573 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3574 crtcoff = RADEON_CRTC2_OFFSET; 3575 } else { 3576 offset = RADEON_CUR_OFFSET; 3577 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3578 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3579 crtcoff = RADEON_CRTC_OFFSET; 3580 } 3581 3582 x = dp->rd_cursor.rc_pos.x; 3583 y = dp->rd_cursor.rc_pos.y; 3584 3585 while (y < rcp->rc_yoffset) { 3586 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3587 } 3588 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3589 rcp->rc_yoffset += RADEON_PANINCREMENT; 3590 } 3591 while (x < rcp->rc_xoffset) { 3592 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3593 } 3594 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3595 rcp->rc_xoffset += RADEON_PANINCREMENT; 3596 } 3597 3598 /* adjust for the cursor's hotspot */ 3599 x -= dp->rd_cursor.rc_hot.x; 3600 y -= dp->rd_cursor.rc_hot.y; 3601 xoff = yoff = 0; 3602 3603 if (x >= dp->rd_virtx) 3604 x = dp->rd_virtx - 1; 3605 if (y >= dp->rd_virty) 3606 y = dp->rd_virty - 1; 3607 3608 /* now adjust cursor so it is relative to viewport */ 3609 x -= rcp->rc_xoffset; 3610 y -= rcp->rc_yoffset; 3611 3612 /* 3613 * no need to check for fall off, because we should 3614 * never move off the screen entirely! 3615 */ 3616 coff = 0; 3617 if (x < 0) { 3618 xoff = -x; 3619 x = 0; 3620 } 3621 if (y < 0) { 3622 yoff = -y; 3623 y = 0; 3624 coff = (yoff * 2) * 8; 3625 } 3626 3627 /* pan the display */ 3628 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3629 rcp->rc_xoffset); 3630 3631 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3632 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3633 /* NB: this unlocks the cursor */ 3634 PUT32(sc, hvpos, (x << 16) | y); 3635 } 3636 } 3637 3638 static void 3639 radeonfb_cursor_visible(struct radeonfb_display *dp) 3640 { 3641 int i; 3642 uint32_t gencntl, bit; 3643 3644 for (i = 0; i < dp->rd_ncrtcs; i++) { 3645 if (dp->rd_crtcs[i].rc_number) { 3646 gencntl = RADEON_CRTC2_GEN_CNTL; 3647 bit = RADEON_CRTC2_CUR_EN; 3648 } else { 3649 gencntl = RADEON_CRTC_GEN_CNTL; 3650 bit = RADEON_CRTC_CUR_EN; 3651 } 3652 3653 if (dp->rd_cursor.rc_visible) 3654 SET32(dp->rd_softc, gencntl, bit); 3655 else 3656 CLR32(dp->rd_softc, gencntl, bit); 3657 } 3658 } 3659 3660 static void 3661 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3662 { 3663 int i; 3664 uint32_t c0reg, c1reg; 3665 struct radeonfb_softc *sc = dp->rd_softc; 3666 3667 for (i = 0; i < dp->rd_ncrtcs; i++) { 3668 if (dp->rd_crtcs[i].rc_number) { 3669 c0reg = RADEON_CUR2_CLR0; 3670 c1reg = RADEON_CUR2_CLR1; 3671 } else { 3672 c0reg = RADEON_CUR_CLR0; 3673 c1reg = RADEON_CUR_CLR1; 3674 } 3675 3676 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3677 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3678 } 3679 } 3680 3681 static void 3682 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3683 { 3684 struct radeonfb_softc *sc; 3685 int i; 3686 3687 sc = dp->rd_softc; 3688 for (i = 0; i < dp->rd_ncrtcs; i++) { 3689 if (dp->rd_crtcs[i].rc_number) { 3690 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3691 } else { 3692 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3693 } 3694 } 3695 3696 if (which & WSDISPLAY_CURSOR_DOCMAP) 3697 radeonfb_cursor_cmap(dp); 3698 3699 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3700 radeonfb_cursor_shape(dp); 3701 3702 if (which & WSDISPLAY_CURSOR_DOCUR) 3703 radeonfb_cursor_visible(dp); 3704 3705 /* this one is unconditional, because it updates other stuff */ 3706 radeonfb_cursor_position(dp); 3707 } 3708 3709 static struct videomode * 3710 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3711 { 3712 int r1, r2; 3713 3714 /* otherwise pick the higher refresh rate */ 3715 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3716 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3717 3718 return (r1 < r2 ? m2 : m1); 3719 } 3720 3721 static const struct videomode * 3722 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3723 int x, int y) 3724 { 3725 struct edid_info *ep = &rp->rp_edid; 3726 struct videomode *vmp = NULL; 3727 int i; 3728 3729 if (!rp->rp_edid_valid) { 3730 /* fallback to safe mode */ 3731 return radeonfb_modelookup(sc->sc_defaultmode); 3732 } 3733 3734 /* always choose the preferred mode first! */ 3735 if (ep->edid_preferred_mode) { 3736 3737 /* XXX: add auto-stretching support for native mode */ 3738 3739 /* this may want panning to occur, btw */ 3740 if ((ep->edid_preferred_mode->hdisplay <= x) && 3741 (ep->edid_preferred_mode->vdisplay <= y)) 3742 return ep->edid_preferred_mode; 3743 } 3744 3745 for (i = 0; i < ep->edid_nmodes; i++) { 3746 /* 3747 * We elect to pick a resolution that is too large for 3748 * the monitor than one that is too small. This means 3749 * that we will prefer to pan rather than to try to 3750 * center a smaller display on a larger screen. In 3751 * practice, this shouldn't matter because if a 3752 * monitor can support a larger resolution, it can 3753 * probably also support the smaller. A specific 3754 * exception is fixed format panels, but hopefully 3755 * they are properly dealt with by the "autostretch" 3756 * logic above. 3757 */ 3758 if ((ep->edid_modes[i].hdisplay > x) || 3759 (ep->edid_modes[i].vdisplay > y)) { 3760 continue; 3761 } 3762 3763 /* 3764 * at this point, the display mode is no larger than 3765 * what we've requested. 3766 */ 3767 if (vmp == NULL) 3768 vmp = &ep->edid_modes[i]; 3769 3770 /* eliminate smaller modes */ 3771 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3772 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3773 continue; 3774 3775 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3776 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3777 vmp = &ep->edid_modes[i]; 3778 continue; 3779 } 3780 3781 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3782 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3783 3784 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3785 } 3786 3787 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3788 } 3789 3790 static int 3791 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3792 { 3793 int i; 3794 3795 for (i = 0; i < nlist; i++) { 3796 if ((x == list[i].hdisplay) && 3797 (y == list[i].vdisplay)) { 3798 return 1; 3799 } 3800 } 3801 return 0; 3802 } 3803 3804 static void 3805 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3806 int pan) 3807 { 3808 struct radeonfb_port *rp; 3809 struct edid_info *ep; 3810 int i, j; 3811 3812 *x = 0; 3813 *y = 0; 3814 3815 if (pan) { 3816 for (i = 0; i < dp->rd_ncrtcs; i++) { 3817 rp = dp->rd_crtcs[i].rc_port; 3818 ep = &rp->rp_edid; 3819 if (!rp->rp_edid_valid) { 3820 /* monitor not present */ 3821 continue; 3822 } 3823 3824 /* 3825 * For now we are ignoring "conflict" that 3826 * could occur when mixing some modes like 3827 * 1280x1024 and 1400x800. It isn't clear 3828 * which is better, so the first one wins. 3829 */ 3830 for (j = 0; j < ep->edid_nmodes; j++) { 3831 /* 3832 * ignore resolutions that are too big for 3833 * the radeon 3834 */ 3835 if (ep->edid_modes[j].hdisplay > 3836 dp->rd_softc->sc_maxx) 3837 continue; 3838 if (ep->edid_modes[j].vdisplay > 3839 dp->rd_softc->sc_maxy) 3840 continue; 3841 3842 /* 3843 * pick largest resolution, the 3844 * smaller monitor will pan 3845 */ 3846 if ((ep->edid_modes[j].hdisplay >= *x) && 3847 (ep->edid_modes[j].vdisplay >= *y)) { 3848 *x = ep->edid_modes[j].hdisplay; 3849 *y = ep->edid_modes[j].vdisplay; 3850 } 3851 } 3852 } 3853 3854 } else { 3855 struct videomode modes[64]; 3856 int nmodes = 0; 3857 int valid = 0; 3858 3859 for (i = 0; i < dp->rd_ncrtcs; i++) { 3860 /* 3861 * pick the largest resolution in common. 3862 */ 3863 rp = dp->rd_crtcs[i].rc_port; 3864 ep = &rp->rp_edid; 3865 3866 if (!rp->rp_edid_valid) 3867 continue; 3868 3869 if (!valid) { 3870 /* 3871 * Pick the preferred mode for this port 3872 * if available. 3873 */ 3874 if (ep->edid_preferred_mode) { 3875 struct videomode *vmp = 3876 ep->edid_preferred_mode; 3877 3878 if ((vmp->hdisplay <= 3879 dp->rd_softc->sc_maxx) && 3880 (vmp->vdisplay <= 3881 dp->rd_softc->sc_maxy)) 3882 modes[nmodes++] = *vmp; 3883 } else { 3884 3885 /* initialize starting list */ 3886 for (j = 0; j < ep->edid_nmodes; j++) { 3887 /* 3888 * ignore resolutions that are 3889 * too big for the radeon 3890 */ 3891 if (ep->edid_modes[j].hdisplay > 3892 dp->rd_softc->sc_maxx) 3893 continue; 3894 if (ep->edid_modes[j].vdisplay > 3895 dp->rd_softc->sc_maxy) 3896 continue; 3897 3898 modes[nmodes] = 3899 ep->edid_modes[j]; 3900 nmodes++; 3901 } 3902 } 3903 valid = 1; 3904 } else { 3905 /* merge into preexisting list */ 3906 for (j = 0; j < nmodes; j++) { 3907 if (!radeonfb_hasres(ep->edid_modes, 3908 ep->edid_nmodes, 3909 modes[j].hdisplay, 3910 modes[j].vdisplay)) { 3911 modes[j] = modes[nmodes]; 3912 j--; 3913 nmodes--; 3914 } 3915 } 3916 } 3917 } 3918 3919 /* now we have to pick from the merged list */ 3920 for (i = 0; i < nmodes; i++) { 3921 if ((modes[i].hdisplay >= *x) && 3922 (modes[i].vdisplay >= *y)) { 3923 *x = modes[i].hdisplay; 3924 *y = modes[i].vdisplay; 3925 } 3926 } 3927 } 3928 3929 if ((*x == 0) || (*y == 0)) { 3930 /* fallback to safe mode */ 3931 *x = 640; 3932 *y = 480; 3933 } 3934 } 3935 3936 /* 3937 * backlight levels are linear on: 3938 * - RV200, RV250, RV280, RV350 3939 * - but NOT on PowerBook4,3 6,3 6,5 3940 * according to Linux' radeonfb 3941 */ 3942 3943 /* Get the current backlight level for the display. */ 3944 3945 static int 3946 radeonfb_get_backlight(struct radeonfb_display *dp) 3947 { 3948 int s; 3949 uint32_t level; 3950 3951 s = spltty(); 3952 3953 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3954 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3955 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3956 3957 /* 3958 * On some chips, we should negate the backlight level. 3959 * XXX Find out on which chips. 3960 */ 3961 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3962 level = RADEONFB_BACKLIGHT_MAX - level; 3963 3964 splx(s); 3965 3966 return level; 3967 } 3968 3969 /* Set the backlight to the given level for the display. */ 3970 static void 3971 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3972 { 3973 if (dp->rd_bl_on == on) 3974 return; 3975 dp->rd_bl_on = on; 3976 radeonfb_set_backlight(dp, dp->rd_bl_level); 3977 } 3978 3979 static int 3980 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3981 { 3982 struct radeonfb_softc *sc; 3983 int rlevel, s; 3984 uint32_t lvds; 3985 3986 s = spltty(); 3987 3988 dp->rd_bl_level = level; 3989 if (dp->rd_bl_on == 0) 3990 level = 0; 3991 3992 if (level < 0) 3993 level = 0; 3994 else if (level >= RADEONFB_BACKLIGHT_MAX) 3995 level = RADEONFB_BACKLIGHT_MAX; 3996 3997 sc = dp->rd_softc; 3998 3999 /* On some chips, we should negate the backlight level. */ 4000 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4001 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4002 } else 4003 rlevel = level; 4004 4005 callout_stop(&dp->rd_bl_lvds_co); 4006 radeonfb_engine_idle(sc); 4007 4008 /* 4009 * Turn off the display if the backlight is set to 0, since the 4010 * display is useless without backlight anyway. 4011 */ 4012 if (level == 0) 4013 radeonfb_blank(dp, 1); 4014 else if (radeonfb_get_backlight(dp) == 0) 4015 radeonfb_blank(dp, 0); 4016 4017 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4018 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4019 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4020 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4021 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4022 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4023 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4024 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4025 lvds |= RADEON_LVDS_ON; 4026 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4027 } else { 4028 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4029 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4030 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4031 } 4032 4033 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4034 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4035 /* XXX What is the correct delay? */ 4036 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4037 4038 splx(s); 4039 4040 return 0; 4041 } 4042 4043 /* 4044 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4045 * Set the delayed bits in the register, and clear the stored delayed 4046 * value. 4047 */ 4048 4049 static void radeonfb_lvds_callout(void *arg) 4050 { 4051 struct radeonfb_display *dp = arg; 4052 int s; 4053 4054 s = splhigh(); 4055 4056 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4057 dp->rd_bl_lvds_val); 4058 dp->rd_bl_lvds_val = 0; 4059 4060 splx(s); 4061 } 4062 4063 static void 4064 radeonfb_brightness_up(device_t dev) 4065 { 4066 struct radeonfb_softc *sc = device_private(dev); 4067 struct radeonfb_display *dp = &sc->sc_displays[0]; 4068 int level; 4069 4070 /* we assume the main display is the first one - need a better way */ 4071 if (sc->sc_ndisplays < 1) return; 4072 /* make sure pushing the hotkeys always has an effect */ 4073 dp->rd_bl_on = 1; 4074 level = dp->rd_bl_level; 4075 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4076 radeonfb_set_backlight(dp, level); 4077 } 4078 4079 static void 4080 radeonfb_brightness_down(device_t dev) 4081 { 4082 struct radeonfb_softc *sc = device_private(dev); 4083 struct radeonfb_display *dp = &sc->sc_displays[0]; 4084 int level; 4085 4086 /* we assume the main display is the first one - need a better way */ 4087 if (sc->sc_ndisplays < 1) return; 4088 /* make sure pushing the hotkeys always has an effect */ 4089 dp->rd_bl_on = 1; 4090 level = dp->rd_bl_level; 4091 level = max(0, level - 5); 4092 radeonfb_set_backlight(dp, level); 4093 } 4094
Indexes created Wed Sep 24 05:09:52 GMT 2025