radeonfb.c revision 1.72
1 /* $NetBSD: radeonfb.c,v 1.72 2012/12/31 11:11:17 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.72 2012/12/31 11:11:17 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 174 175 static int radeonfb_set_backlight(struct radeonfb_display *, int); 176 static int radeonfb_get_backlight(struct radeonfb_display *); 177 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 178 static void radeonfb_lvds_callout(void *); 179 180 static void radeonfb_brightness_up(device_t); 181 static void radeonfb_brightness_down(device_t); 182 183 static struct videomode *radeonfb_best_refresh(struct videomode *, 184 struct videomode *); 185 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 186 uint16_t *, int); 187 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 188 struct radeonfb_port *, int, int); 189 190 static int radeonfb_drm_print(void *, const char *); 191 192 #ifdef RADEONFB_DEBUG 193 int radeon_debug = 1; 194 #define DPRINTF(x) \ 195 if (radeon_debug) printf x 196 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 197 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 198 #else 199 #define DPRINTF(x) 200 #define PRINTREG(r) 201 #define PRINTPLL(r) 202 #endif 203 204 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 205 206 #ifndef RADEON_DEFAULT_MODE 207 /* any reasonably modern display should handle this */ 208 #define RADEON_DEFAULT_MODE "1024x768x60" 209 #endif 210 211 extern const u_char rasops_cmap[768]; 212 213 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 214 215 static struct { 216 int size; /* minimum memory size (MB) */ 217 int maxx; /* maximum x dimension */ 218 int maxy; /* maximum y dimension */ 219 int maxbpp; /* maximum bpp */ 220 int maxdisp; /* maximum logical display count */ 221 } radeonfb_limits[] = { 222 { 32, 2048, 1536, 32, 2 }, 223 { 16, 1600, 1200, 32, 2 }, 224 { 8, 1600, 1200, 32, 1 }, 225 { 0, 0, 0, 0, 0 }, 226 }; 227 228 static struct wsscreen_descr radeonfb_stdscreen = { 229 "fb", /* name */ 230 0, 0, /* ncols, nrows */ 231 NULL, /* textops */ 232 8, 16, /* fontwidth, fontheight */ 233 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 234 0, /* modecookie */ 235 }; 236 237 struct wsdisplay_accessops radeonfb_accessops = { 238 radeonfb_ioctl, 239 radeonfb_mmap, 240 NULL, /* vcons_alloc_screen */ 241 NULL, /* vcons_free_screen */ 242 NULL, /* vcons_show_screen */ 243 NULL, /* load_font */ 244 NULL, /* pollc */ 245 NULL, /* scroll */ 246 }; 247 248 static struct { 249 uint16_t devid; 250 uint16_t family; 251 uint16_t flags; 252 } radeonfb_devices[] = 253 { 254 /* R100 family */ 255 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 256 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 257 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 259 260 /* RV100 family */ 261 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 262 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 263 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 265 266 /* RS100 family */ 267 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 269 270 /* RS200/RS250 family */ 271 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 275 276 /* R200 family */ 277 /* add more R200 products? , 5148 */ 278 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 280 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 283 284 /* RV200 family */ 285 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 286 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 287 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 289 290 /* RV250 family */ 291 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 296 297 /* RS300 family */ 298 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 302 303 /* RV280 family */ 304 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 311 312 /* R300 family */ 313 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 321 322 /* RV350/RV360 family */ 323 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 335 336 /* R350/R360 family */ 337 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 338 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 339 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 345 346 /* RV380/RV370 family */ 347 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 348 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 349 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 352 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 356 357 #if notyet 358 /* R420/R423 family */ 359 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 376 #endif 377 { 0, 0, 0 } 378 }; 379 380 static struct { 381 int divider; 382 int mask; 383 } radeonfb_dividers[] = { 384 { 16, 5 }, 385 { 12, 7 }, 386 { 8, 3 }, 387 { 6, 6 }, 388 { 4, 2 }, 389 { 3, 4 }, 390 { 2, 1 }, 391 { 1, 0 }, 392 { 0, 0 } 393 }; 394 395 /* 396 * This table taken from X11. 397 */ 398 static const struct { 399 int family; 400 struct radeon_tmds_pll plls[4]; 401 } radeonfb_tmds_pll[] = { 402 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 403 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 404 { RADEON_RS100, {{0, 0}}}, 405 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 408 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 409 { RADEON_RS300, {{0, 0}}}, 410 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 411 { RADEON_R300, {{-1, 0xb01cb}}}, 412 { RADEON_R350, {{-1, 0xb01cb}}}, 413 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 414 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 415 { RADEON_R420, {{-1, 0xb01cb}}}, 416 }; 417 418 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 419 420 421 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 422 radeonfb_match, radeonfb_attach, NULL, NULL); 423 424 static int 425 radeonfb_match(device_t parent, cfdata_t match, void *aux) 426 { 427 const struct pci_attach_args *pa = aux; 428 int i; 429 430 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 431 return 0; 432 433 for (i = 0; radeonfb_devices[i].devid; i++) { 434 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 435 return 100; /* high to defeat VGA/VESA */ 436 } 437 438 return 0; 439 } 440 441 static void 442 radeonfb_attach(device_t parent, device_t dev, void *aux) 443 { 444 struct radeonfb_softc *sc = device_private(dev); 445 const struct pci_attach_args *pa = aux; 446 const char *mptr; 447 bus_size_t bsz; 448 pcireg_t screg; 449 int i, j, fg, bg, ul, flags; 450 uint32_t v; 451 452 sc->sc_dev = dev; 453 sc->sc_id = pa->pa_id; 454 for (i = 0; radeonfb_devices[i].devid; i++) { 455 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 456 break; 457 } 458 459 pci_aprint_devinfo(pa, NULL); 460 461 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 462 463 KASSERT(radeonfb_devices[i].devid != 0); 464 sc->sc_pt = pa->pa_tag; 465 sc->sc_iot = pa->pa_iot; 466 sc->sc_pc = pa->pa_pc; 467 sc->sc_family = radeonfb_devices[i].family; 468 sc->sc_flags = radeonfb_devices[i].flags; 469 470 /* enable memory and IO access */ 471 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 472 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 473 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 474 475 /* 476 * Some flags are general to entire chip families, and rather 477 * than clutter up the table with them, we go ahead and set 478 * them here. 479 */ 480 switch (sc->sc_family) { 481 case RADEON_RS100: 482 case RADEON_RS200: 483 sc->sc_flags |= RFB_IGP | RFB_RV100; 484 break; 485 486 case RADEON_RV100: 487 case RADEON_RV200: 488 case RADEON_RV250: 489 case RADEON_RV280: 490 sc->sc_flags |= RFB_RV100; 491 break; 492 493 case RADEON_RS300: 494 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 495 break; 496 497 case RADEON_R300: 498 case RADEON_RV350: 499 case RADEON_R350: 500 case RADEON_RV380: 501 case RADEON_R420: 502 /* newer chips */ 503 sc->sc_flags |= RFB_R300; 504 break; 505 506 case RADEON_R100: 507 sc->sc_flags |= RFB_NCRTC2; 508 break; 509 } 510 511 if ((sc->sc_family == RADEON_RV200) || 512 (sc->sc_family == RADEON_RV250) || 513 (sc->sc_family == RADEON_RV280) || 514 (sc->sc_family == RADEON_RV350)) { 515 bool inverted = 0; 516 /* backlight level is linear */ 517 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 518 prop_dictionary_get_bool(device_properties(sc->sc_dev), 519 "backlight_level_reverted", &inverted); 520 if (inverted) { 521 DPRINTF(("nope, it's inverted\n")); 522 sc->sc_flags |= RFB_INV_BLIGHT; 523 } 524 } else 525 sc->sc_flags |= RFB_INV_BLIGHT; 526 527 /* 528 * XXX: to support true multihead, this must change. 529 */ 530 sc->sc_ndisplays = 1; 531 532 /* XXX: */ 533 if (!HAS_CRTC2(sc)) { 534 sc->sc_ndisplays = 1; 535 } 536 537 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 538 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 539 &sc->sc_regsz) != 0) { 540 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 541 goto error; 542 } 543 544 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 545 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 546 { 547 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 548 goto error; 549 } 550 sc->sc_romt = sc->sc_memt; 551 552 sc->sc_mapped = TRUE; 553 554 /* scratch register test... */ 555 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 556 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 557 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 558 goto error; 559 } 560 561 PRINTREG(RADEON_CRTC_EXT_CNTL); 562 PRINTREG(RADEON_CRTC_GEN_CNTL); 563 PRINTREG(RADEON_CRTC2_GEN_CNTL); 564 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 565 PRINTREG(RADEON_DAC_CNTL2); 566 PRINTREG(RADEON_FP_GEN_CNTL); 567 PRINTREG(RADEON_FP2_GEN_CNTL); 568 569 PRINTREG(RADEON_BIOS_4_SCRATCH); 570 PRINTREG(RADEON_FP_GEN_CNTL); 571 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 572 PRINTREG(RADEON_FP2_GEN_CNTL); 573 PRINTREG(RADEON_TMDS_CNTL); 574 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 575 PRINTREG(RADEON_TMDS_PLL_CNTL); 576 PRINTREG(RADEON_LVDS_GEN_CNTL); 577 PRINTREG(RADEON_FP_HORZ_STRETCH); 578 PRINTREG(RADEON_FP_VERT_STRETCH); 579 580 if (IS_RV100(sc)) 581 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 582 583 /* XXX 584 * according to xf86-video-radeon R3xx has this bit backwards 585 */ 586 if (IS_R300(sc)) { 587 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 588 0, 589 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 590 } else { 591 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 592 RADEON_TMDS_TRANSMITTER_PLLEN, 593 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 594 } 595 596 radeonfb_i2c_init(sc); 597 598 radeonfb_loadbios(sc, pa); 599 600 #ifdef RADEONFB_BIOS_INIT 601 if (radeonfb_bios_init(sc)) { 602 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 603 } 604 #endif 605 606 if (radeonfb_getclocks(sc)) { 607 aprint_error("%s: Unable to get reference clocks from BIOS\n", 608 XNAME(sc)); 609 goto error; 610 } 611 612 if (radeonfb_gettmds(sc)) { 613 aprint_error("%s: Unable to identify TMDS PLL settings\n", 614 XNAME(sc)); 615 goto error; 616 } 617 618 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 619 "minpll = %d, maxpll = %d\n", XNAME(sc), 620 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 621 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 622 623 radeonfb_getconnectors(sc); 624 625 radeonfb_set_fbloc(sc); 626 627 for (i = 0; radeonfb_limits[i].size; i++) { 628 if (sc->sc_memsz >= radeonfb_limits[i].size) { 629 sc->sc_maxx = radeonfb_limits[i].maxx; 630 sc->sc_maxy = radeonfb_limits[i].maxy; 631 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 632 /* framebuffer offset, start at a 4K page */ 633 sc->sc_fboffset = sc->sc_memsz / 634 radeonfb_limits[i].maxdisp; 635 /* 636 * we use the fbsize to figure out where we can store 637 * things like cursor data. 638 */ 639 sc->sc_fbsize = 640 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 641 RADEON_STRIDEALIGN) * sc->sc_maxy, 642 4096); 643 break; 644 } 645 } 646 647 648 radeonfb_init_misc(sc); 649 650 /* program the DAC wirings */ 651 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 652 switch (sc->sc_ports[i].rp_dac_type) { 653 case RADEON_DAC_PRIMARY: 654 PATCH32(sc, RADEON_DAC_CNTL2, 655 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 656 ~RADEON_DAC2_DAC_CLK_SEL); 657 break; 658 case RADEON_DAC_TVDAC: 659 /* we always use the TVDAC to drive a secondary analog 660 * CRT for now. if we ever support TV-out this will 661 * have to change. 662 */ 663 SET32(sc, RADEON_DAC_CNTL2, 664 RADEON_DAC2_DAC2_CLK_SEL); 665 PATCH32(sc, RADEON_DISP_HW_DEBUG, 666 i ? 0 : RADEON_CRT2_DISP1_SEL, 667 ~RADEON_CRT2_DISP1_SEL); 668 /* we're using CRTC2 for the 2nd port */ 669 if (sc->sc_ports[i].rp_number == 1) { 670 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 671 RADEON_DISP_DAC2_SOURCE_CRTC2, 672 ~RADEON_DISP_DAC2_SOURCE_MASK); 673 } 674 675 break; 676 } 677 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 678 sc->sc_ports[i].rp_tmds_type)); 679 switch (sc->sc_ports[i].rp_tmds_type) { 680 case RADEON_TMDS_INT: 681 /* point FP0 at the CRTC this port uses */ 682 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 683 __func__, sc->sc_ports[i].rp_number)); 684 if (IS_R300(sc)) { 685 PATCH32(sc, RADEON_FP_GEN_CNTL, 686 sc->sc_ports[i].rp_number ? 687 R200_FP_SOURCE_SEL_CRTC2 : 688 R200_FP_SOURCE_SEL_CRTC1, 689 ~R200_FP_SOURCE_SEL_MASK); 690 } else { 691 PATCH32(sc, RADEON_FP_GEN_CNTL, 692 sc->sc_ports[i].rp_number ? 693 RADEON_FP_SEL_CRTC2 : 694 RADEON_FP_SEL_CRTC1, 695 ~RADEON_FP_SEL_MASK); 696 } 697 } 698 } 699 PRINTREG(RADEON_DAC_CNTL2); 700 PRINTREG(RADEON_DISP_HW_DEBUG); 701 702 /* other DAC programming */ 703 v = GET32(sc, RADEON_DAC_CNTL); 704 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 705 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 706 PUT32(sc, RADEON_DAC_CNTL, v); 707 PRINTREG(RADEON_DAC_CNTL); 708 709 /* XXX: this may need more investigation */ 710 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 711 PRINTREG(RADEON_TV_DAC_CNTL); 712 713 /* enable TMDS */ 714 SET32(sc, RADEON_FP_GEN_CNTL, 715 RADEON_FP_TMDS_EN | 716 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 717 RADEON_FP_CRTC_DONT_SHADOW_HEND); 718 /* 719 * XXX 720 * no idea why this is necessary - if I do not clear this bit on my 721 * iBook G4 the screen remains black, even though it's already clear. 722 * It needs to be set on my Sun XVR-100 for the DVI port to work 723 * TODO: 724 * see if this is still necessary now that CRTCs, DACs and outputs are 725 * getting wired up in a halfway sane way 726 */ 727 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 728 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 729 } else { 730 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 731 } 732 733 /* 734 * we use bus_space_map instead of pci_mapreg, because we don't 735 * need the full aperature space. no point in wasting virtual 736 * address space we don't intend to use, right? 737 */ 738 if ((sc->sc_memsz < (4096 * 1024)) || 739 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 740 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 741 (bsz < sc->sc_memsz)) { 742 sc->sc_memsz = 0; 743 aprint_error("%s: Bad frame buffer configuration\n", 744 XNAME(sc)); 745 goto error; 746 } 747 748 /* 64 MB should be enough -- more just wastes map entries */ 749 if (sc->sc_memsz > (64 << 20)) 750 sc->sc_memsz = (64 << 20); 751 752 sc->sc_memt = pa->pa_memt; 753 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 754 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 755 sc->sc_memsz = 0; 756 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 757 goto error; 758 } 759 760 aprint_normal("%s: %d MB aperture at 0x%08x, " 761 "%d KB registers at 0x%08x\n", XNAME(sc), 762 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 763 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 764 765 /* setup default video mode from devprop (allows PROM override) */ 766 sc->sc_defaultmode = radeonfb_default_mode; 767 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 768 "videomode", &mptr)) { 769 770 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 771 sc->sc_defaultmode = sc->sc_modebuf; 772 } 773 774 /* initialize some basic display parameters */ 775 for (i = 0; i < sc->sc_ndisplays; i++) { 776 struct radeonfb_display *dp = &sc->sc_displays[i]; 777 struct rasops_info *ri; 778 long defattr; 779 struct wsemuldisplaydev_attach_args aa; 780 781 /* 782 * Figure out how many "displays" (desktops) we are going to 783 * support. If more than one, then each CRTC gets its own 784 * programming. 785 * 786 * XXX: this code needs to change to support mergedfb. 787 * XXX: would be nice to allow this to be overridden 788 */ 789 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 790 DPRINTF(("dual crtcs!\n")); 791 dp->rd_ncrtcs = 2; 792 dp->rd_crtcs[0].rc_port = 793 &sc->sc_ports[0]; 794 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 795 dp->rd_crtcs[1].rc_port = 796 &sc->sc_ports[1]; 797 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 798 } else { 799 dp->rd_ncrtcs = 1; 800 dp->rd_crtcs[0].rc_port = 801 &sc->sc_ports[i]; 802 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 803 } 804 805 dp->rd_softc = sc; 806 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 807 dp->rd_bg = WS_DEFAULT_BG; 808 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 809 810 /* for text mode, we pick a resolution that won't 811 * require panning */ 812 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 813 814 aprint_normal("%s: display %d: " 815 "initial virtual resolution %dx%d at %d bpp\n", 816 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 817 818 /* now select the *video mode* that we will use */ 819 for (j = 0; j < dp->rd_ncrtcs; j++) { 820 const struct videomode *vmp; 821 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 822 dp->rd_virtx, dp->rd_virty); 823 824 /* 825 * virtual resolution should be at least as high as 826 * physical 827 */ 828 if (dp->rd_virtx < vmp->hdisplay || 829 dp->rd_virty < vmp->vdisplay) { 830 dp->rd_virtx = vmp->hdisplay; 831 dp->rd_virty = vmp->vdisplay; 832 } 833 834 dp->rd_crtcs[j].rc_videomode = *vmp; 835 printf("%s: port %d: physical %dx%d %dHz\n", 836 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 837 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 838 vmp->htotal), vmp->vtotal)); 839 } 840 841 /* N.B.: radeon wants 64-byte aligned stride */ 842 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 843 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 844 DPRINTF(("stride: %d\n", dp->rd_stride)); 845 846 dp->rd_offset = sc->sc_fboffset * i; 847 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 848 sc->sc_memh) + dp->rd_offset; 849 dp->rd_curoff = sc->sc_fbsize; 850 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 851 852 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 853 854 switch (dp->rd_bpp) { 855 case 8: 856 dp->rd_format = 2; 857 break; 858 case 32: 859 dp->rd_format = 6; 860 break; 861 default: 862 aprint_error("%s: bad depth %d\n", XNAME(sc), 863 dp->rd_bpp); 864 goto error; 865 } 866 867 DPRINTF(("init engine\n")); 868 /* XXX: this seems suspicious - per display engine 869 initialization? */ 870 radeonfb_engine_init(dp); 871 872 /* copy the template into place */ 873 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 874 dp->rd_wsscreens = dp->rd_wsscreens_storage; 875 876 /* and make up the list */ 877 dp->rd_wsscreenlist.nscreens = 1; 878 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 879 880 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 881 &radeonfb_accessops); 882 883 dp->rd_vd.init_screen = radeonfb_init_screen; 884 885 #ifdef RADEONFB_DEBUG 886 dp->rd_virty -= 200; 887 #endif 888 889 dp->rd_console = 0; 890 prop_dictionary_get_bool(device_properties(sc->sc_dev), 891 "is_console", &dp->rd_console); 892 893 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 894 895 896 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 897 dp->rd_console, &defattr); 898 899 ri = &dp->rd_vscreen.scr_ri; 900 901 /* clear the screen */ 902 rasops_unpack_attr(defattr, &fg, &bg, &ul); 903 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 904 ri->ri_devcmap[bg & 0xf]); 905 906 dp->rd_wsscreens->textops = &ri->ri_ops; 907 dp->rd_wsscreens->capabilities = ri->ri_caps; 908 dp->rd_wsscreens->nrows = ri->ri_rows; 909 dp->rd_wsscreens->ncols = ri->ri_cols; 910 911 #ifdef SPLASHSCREEN 912 dp->rd_splash.si_depth = ri->ri_depth; 913 dp->rd_splash.si_bits = ri->ri_bits; 914 dp->rd_splash.si_hwbits = ri->ri_hwbits; 915 dp->rd_splash.si_width = ri->ri_width; 916 dp->rd_splash.si_height = ri->ri_height; 917 dp->rd_splash.si_stride = ri->ri_stride; 918 dp->rd_splash.si_fillrect = NULL; 919 #endif 920 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 921 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 922 dp->rd_gc.gc_rop = RADEON_ROP3_S; 923 dp->rd_gc.gc_blitcookie = dp; 924 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 925 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 926 dp->rd_virtx, 927 ri->ri_font->fontwidth, 928 ri->ri_font->fontheight, 929 defattr); 930 if (dp->rd_console) { 931 932 radeonfb_modeswitch(dp); 933 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 934 defattr); 935 #ifdef SPLASHSCREEN 936 if (splash_render(&dp->rd_splash, 937 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 938 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 939 else 940 #endif 941 vcons_replay_msgbuf(&dp->rd_vscreen); 942 } else { 943 944 /* 945 * since we're not the console we can postpone 946 * the rest until someone actually allocates a 947 * screen for us. but we do clear the screen 948 * at least. 949 */ 950 memset(ri->ri_bits, 0, 1024); 951 952 radeonfb_modeswitch(dp); 953 #ifdef SPLASHSCREEN 954 if (splash_render(&dp->rd_splash, 955 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 956 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 957 #endif 958 } 959 960 aa.console = dp->rd_console; 961 aa.scrdata = &dp->rd_wsscreenlist; 962 aa.accessops = &radeonfb_accessops; 963 aa.accesscookie = &dp->rd_vd; 964 965 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 966 967 radeonfb_blank(dp, 0); 968 969 /* Initialise delayed lvds operations for backlight. */ 970 callout_init(&dp->rd_bl_lvds_co, 0); 971 callout_setfunc(&dp->rd_bl_lvds_co, 972 radeonfb_lvds_callout, dp); 973 dp->rd_bl_on = 1; 974 dp->rd_bl_level = radeonfb_get_backlight(dp); 975 radeonfb_set_backlight(dp, dp->rd_bl_level); 976 } 977 978 for (i = 0; i < RADEON_NDISPLAYS; i++) 979 radeonfb_init_palette(&sc->sc_displays[i]); 980 981 if (HAS_CRTC2(sc)) { 982 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 983 } 984 985 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 986 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 987 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 988 radeonfb_brightness_up, TRUE); 989 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 990 radeonfb_brightness_down, TRUE); 991 992 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 993 994 PRINTREG(RADEON_CRTC_EXT_CNTL); 995 PRINTREG(RADEON_CRTC_GEN_CNTL); 996 PRINTREG(RADEON_CRTC2_GEN_CNTL); 997 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 998 PRINTREG(RADEON_DAC_CNTL2); 999 PRINTREG(RADEON_FP_GEN_CNTL); 1000 PRINTREG(RADEON_FP2_GEN_CNTL); 1001 1002 return; 1003 1004 error: 1005 if (sc->sc_biossz) 1006 free(sc->sc_bios, M_DEVBUF); 1007 1008 if (sc->sc_regsz) 1009 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1010 1011 if (sc->sc_memsz) 1012 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1013 } 1014 1015 static void 1016 radeonfb_map(struct radeonfb_softc *sc) 1017 { 1018 if (!sc->sc_mapped) { 1019 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1020 &sc->sc_regh) != 0) { 1021 aprint_error_dev(sc->sc_dev, 1022 "unable to map registers!\n"); 1023 return; 1024 } 1025 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1026 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1027 sc->sc_memsz = 0; 1028 aprint_error_dev(sc->sc_dev, 1029 "Unable to map frame buffer\n"); 1030 return; 1031 } 1032 sc->sc_mapped = TRUE; 1033 } 1034 } 1035 1036 static void 1037 radeonfb_unmap(struct radeonfb_softc *sc) 1038 { 1039 if (sc->sc_mapped) { 1040 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1041 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1042 sc->sc_mapped = FALSE; 1043 } 1044 } 1045 1046 static int 1047 radeonfb_drm_print(void *aux, const char *pnp) 1048 { 1049 if (pnp) 1050 aprint_normal("drm at %s", pnp); 1051 return (UNCONF); 1052 } 1053 1054 int 1055 radeonfb_ioctl(void *v, void *vs, 1056 unsigned long cmd, void *d, int flag, struct lwp *l) 1057 { 1058 struct vcons_data *vd; 1059 struct radeonfb_display *dp; 1060 struct radeonfb_softc *sc; 1061 struct wsdisplay_param *param; 1062 1063 vd = (struct vcons_data *)v; 1064 dp = (struct radeonfb_display *)vd->cookie; 1065 sc = dp->rd_softc; 1066 1067 switch (cmd) { 1068 case WSDISPLAYIO_GTYPE: 1069 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1070 return 0; 1071 1072 case WSDISPLAYIO_GINFO: 1073 if (vd->active != NULL) { 1074 struct wsdisplay_fbinfo *fb; 1075 fb = (struct wsdisplay_fbinfo *)d; 1076 fb->width = dp->rd_virtx; 1077 fb->height = dp->rd_virty; 1078 fb->depth = dp->rd_bpp; 1079 fb->cmsize = 256; 1080 return 0; 1081 } else 1082 return ENODEV; 1083 case WSDISPLAYIO_GVIDEO: 1084 if (radeonfb_isblank(dp)) 1085 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1086 else 1087 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1088 return 0; 1089 1090 case WSDISPLAYIO_SVIDEO: 1091 radeonfb_blank(dp, 1092 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1093 return 0; 1094 1095 case WSDISPLAYIO_GETCMAP: 1096 #if 0 1097 if (dp->rd_bpp == 8) 1098 return radeonfb_getcmap(sc, 1099 (struct wsdisplay_cmap *)d); 1100 #endif 1101 return EINVAL; 1102 1103 case WSDISPLAYIO_PUTCMAP: 1104 #if 0 1105 if (dp->rd_bpp == 8) 1106 return radeonfb_putcmap(sc, 1107 (struct wsdisplay_cmap *)d); 1108 #endif 1109 return EINVAL; 1110 1111 case WSDISPLAYIO_LINEBYTES: 1112 *(unsigned *)d = dp->rd_stride; 1113 return 0; 1114 1115 case WSDISPLAYIO_SMODE: 1116 if (*(int *)d != dp->rd_wsmode) { 1117 dp->rd_wsmode = *(int *)d; 1118 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1119 (dp->rd_vd.active)) { 1120 radeonfb_map(sc); 1121 radeonfb_engine_init(dp); 1122 glyphcache_wipe(&dp->rd_gc); 1123 radeonfb_init_palette(dp); 1124 radeonfb_modeswitch(dp); 1125 vcons_redraw_screen(dp->rd_vd.active); 1126 } else { 1127 radeonfb_unmap(sc); 1128 } 1129 } 1130 return 0; 1131 1132 case WSDISPLAYIO_GCURMAX: 1133 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1134 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1135 return 0; 1136 1137 case WSDISPLAYIO_SCURSOR: 1138 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1139 1140 case WSDISPLAYIO_GCURSOR: 1141 return EPASSTHROUGH; 1142 1143 case WSDISPLAYIO_GCURPOS: 1144 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1145 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1146 return 0; 1147 1148 case WSDISPLAYIO_SCURPOS: 1149 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1150 1151 case WSDISPLAYIO_SSPLASH: 1152 #if defined(SPLASHSCREEN) 1153 if (*(int *)d == 1) { 1154 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1155 splash_render(&dp->rd_splash, 1156 SPLASH_F_CENTER|SPLASH_F_FILL); 1157 } else 1158 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1159 return 0; 1160 #else 1161 return ENODEV; 1162 #endif 1163 case WSDISPLAYIO_GETPARAM: 1164 param = (struct wsdisplay_param *)d; 1165 switch (param->param) { 1166 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1167 param->min = 0; 1168 param->max = 255; 1169 param->curval = dp->rd_bl_level; 1170 return 0; 1171 case WSDISPLAYIO_PARAM_BACKLIGHT: 1172 param->min = 0; 1173 param->max = RADEONFB_BACKLIGHT_MAX; 1174 param->curval = dp->rd_bl_on; 1175 return 0; 1176 } 1177 return EPASSTHROUGH; 1178 1179 case WSDISPLAYIO_SETPARAM: 1180 param = (struct wsdisplay_param *)d; 1181 switch (param->param) { 1182 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1183 radeonfb_set_backlight(dp, param->curval); 1184 return 0; 1185 case WSDISPLAYIO_PARAM_BACKLIGHT: 1186 radeonfb_switch_backlight(dp, param->curval); 1187 return 0; 1188 } 1189 return EPASSTHROUGH; 1190 1191 /* PCI config read/write passthrough. */ 1192 case PCI_IOC_CFGREAD: 1193 case PCI_IOC_CFGWRITE: 1194 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1195 1196 case WSDISPLAYIO_GET_BUSID: 1197 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1198 sc->sc_pt, d); 1199 1200 case WSDISPLAYIO_GET_EDID: { 1201 struct wsdisplayio_edid_info *ei = d; 1202 return wsdisplayio_get_edid(sc->sc_dev, ei); 1203 } 1204 1205 default: 1206 return EPASSTHROUGH; 1207 } 1208 } 1209 1210 paddr_t 1211 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1212 { 1213 struct vcons_data *vd; 1214 struct radeonfb_display *dp; 1215 struct radeonfb_softc *sc; 1216 paddr_t pa; 1217 1218 vd = (struct vcons_data *)v; 1219 dp = (struct radeonfb_display *)vd->cookie; 1220 sc = dp->rd_softc; 1221 1222 /* XXX: note that we don't allow mapping of registers right now */ 1223 /* XXX: this means that the XFree86 radeon driver won't work */ 1224 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1225 pa = bus_space_mmap(sc->sc_memt, 1226 sc->sc_memaddr + dp->rd_offset + offset, 0, 1227 prot, BUS_SPACE_MAP_LINEAR); 1228 return pa; 1229 } 1230 1231 #ifdef RADEONFB_MMAP_BARS 1232 /* 1233 * restrict all other mappings to processes with superuser privileges 1234 * or the kernel itself 1235 */ 1236 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1237 NULL, NULL, NULL, NULL) != 0) { 1238 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1239 return -1; 1240 } 1241 1242 if ((offset >= sc->sc_regaddr) && 1243 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1244 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1245 BUS_SPACE_MAP_LINEAR); 1246 } 1247 1248 if ((offset >= sc->sc_memaddr) && 1249 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1250 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1251 BUS_SPACE_MAP_LINEAR); 1252 } 1253 1254 if ((offset >= sc->sc_romaddr) && 1255 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1256 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1257 BUS_SPACE_MAP_LINEAR); 1258 } 1259 1260 #ifdef PCI_MAGIC_IO_RANGE 1261 /* allow mapping of IO space */ 1262 if ((offset >= PCI_MAGIC_IO_RANGE) && 1263 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1264 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1265 0, prot, 0); 1266 return pa; 1267 } 1268 #endif /* PCI_MAGIC_IO_RANGE */ 1269 1270 #endif /* RADEONFB_MMAP_BARS */ 1271 1272 return -1; 1273 } 1274 1275 static void 1276 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1277 { 1278 bus_space_tag_t romt; 1279 bus_space_handle_t romh, biosh; 1280 bus_size_t romsz; 1281 bus_addr_t ptr; 1282 1283 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1284 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1285 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1286 return; 1287 } 1288 1289 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1290 &sc->sc_biossz); 1291 if (sc->sc_biossz == 0) { 1292 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1293 return; 1294 } 1295 1296 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1297 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1298 1299 /* unmap the PCI expansion rom */ 1300 bus_space_unmap(romt, romh, romsz); 1301 1302 /* turn off rom decoder now */ 1303 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1304 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1305 ~PCI_MAPREG_ROM_ENABLE); 1306 1307 ptr = GETBIOS16(sc, 0x48); 1308 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1309 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1310 sc->sc_flags |= RFB_ATOM; 1311 } 1312 1313 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1314 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1315 } 1316 1317 1318 uint32_t 1319 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1320 { 1321 1322 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1323 } 1324 1325 void 1326 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1327 { 1328 1329 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1330 } 1331 1332 void 1333 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1334 { 1335 1336 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1337 } 1338 1339 void 1340 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1341 uint32_t andmask, uint32_t ormask) 1342 { 1343 int s; 1344 uint32_t val; 1345 1346 s = splhigh(); 1347 val = radeonfb_get32(sc, reg); 1348 val = (val & andmask) | ormask; 1349 radeonfb_put32(sc, reg, val); 1350 splx(s); 1351 } 1352 1353 uint32_t 1354 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1355 { 1356 int s; 1357 uint32_t val; 1358 1359 s = splhigh(); 1360 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1361 val = radeonfb_get32(sc, RADEON_MM_DATA); 1362 splx(s); 1363 1364 return (val); 1365 } 1366 1367 void 1368 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1369 { 1370 int s; 1371 1372 s = splhigh(); 1373 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1374 radeonfb_put32(sc, RADEON_MM_DATA, val); 1375 splx(s); 1376 } 1377 1378 void 1379 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1380 uint32_t andmask, uint32_t ormask) 1381 { 1382 int s; 1383 uint32_t val; 1384 1385 s = splhigh(); 1386 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1387 val = radeonfb_get32(sc, RADEON_MM_DATA); 1388 val = (val & andmask) | ormask; 1389 radeonfb_put32(sc, RADEON_MM_DATA, val); 1390 splx(s); 1391 } 1392 1393 uint32_t 1394 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1395 { 1396 int s; 1397 uint32_t val; 1398 1399 s = splhigh(); 1400 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1401 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1402 if (HAS_R300CG(sc)) 1403 radeonfb_r300cg_workaround(sc); 1404 splx(s); 1405 1406 return (val); 1407 } 1408 1409 void 1410 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1411 { 1412 int s; 1413 1414 s = splhigh(); 1415 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1416 RADEON_PLL_WR_EN); 1417 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1418 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1419 splx(s); 1420 } 1421 1422 void 1423 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1424 uint32_t andmask, uint32_t ormask) 1425 { 1426 int s; 1427 uint32_t val; 1428 1429 s = splhigh(); 1430 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1431 RADEON_PLL_WR_EN); 1432 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1433 val = (val & andmask) | ormask; 1434 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1435 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1436 splx(s); 1437 } 1438 1439 int 1440 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1441 { 1442 uint32_t saved; 1443 1444 saved = GET32(sc, reg); 1445 PUT32(sc, reg, v); 1446 if (GET32(sc, reg) != v) { 1447 return -1; 1448 } 1449 PUT32(sc, reg, saved); 1450 return 0; 1451 } 1452 1453 uintmax_t 1454 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1455 uintmax_t defval) 1456 { 1457 prop_number_t pn; 1458 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1459 if (pn == NULL) { 1460 return defval; 1461 } 1462 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1463 return (prop_number_integer_value(pn)); 1464 } 1465 1466 int 1467 radeonfb_getclocks(struct radeonfb_softc *sc) 1468 { 1469 bus_addr_t ptr; 1470 int refclk = 0; 1471 int refdiv = 0; 1472 int minpll = 0; 1473 int maxpll = 0; 1474 1475 /* load initial property values if port/board provides them */ 1476 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1477 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1478 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1479 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1480 1481 PRINTPLL(RADEON_PPLL_REF_DIV); 1482 PRINTPLL(RADEON_PPLL_DIV_0); 1483 PRINTPLL(RADEON_PPLL_DIV_1); 1484 PRINTPLL(RADEON_PPLL_DIV_2); 1485 PRINTPLL(RADEON_PPLL_DIV_3); 1486 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1487 PRINTPLL(RADEON_P2PLL_REF_DIV); 1488 PRINTPLL(RADEON_P2PLL_DIV_0); 1489 1490 if (refclk && refdiv && minpll && maxpll) 1491 goto dontprobe; 1492 1493 if (!sc->sc_biossz) { 1494 /* no BIOS */ 1495 aprint_verbose("%s: No video BIOS, using default clocks\n", 1496 XNAME(sc)); 1497 if (IS_IGP(sc)) 1498 refclk = refclk ? refclk : 1432; 1499 else 1500 refclk = refclk ? refclk : 2700; 1501 refdiv = refdiv ? refdiv : 12; 1502 minpll = minpll ? minpll : 12500; 1503 /* XXX 1504 * Need to check if the firmware or something programmed a 1505 * higher value than this, and if so, bump it. 1506 * The RV280 in my iBook is unhappy if the PLL input is less 1507 * than 360MHz 1508 */ 1509 maxpll = maxpll ? maxpll : 40000/*35000*/; 1510 } else if (IS_ATOM(sc)) { 1511 /* ATOM BIOS */ 1512 ptr = GETBIOS16(sc, 0x48); 1513 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1514 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1515 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1516 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1517 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1518 /* 1519 * ATOM BIOS doesn't supply a reference divider, so we 1520 * have to probe for it. 1521 */ 1522 if (refdiv < 2) 1523 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1524 RADEON_PPLL_REF_DIV_MASK; 1525 /* 1526 * if probe is zero, just assume one that should work 1527 * for most parts 1528 */ 1529 if (refdiv < 2) 1530 refdiv = 12; 1531 1532 } else { 1533 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1534 /* Legacy BIOS */ 1535 ptr = GETBIOS16(sc, 0x48); 1536 ptr = GETBIOS16(sc, ptr + 0x30); 1537 if (IS_R300(sc)) { 1538 refdiv = refdiv ? refdiv : 1539 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1540 R300_PPLL_REF_DIV_ACC_SHIFT; 1541 } else { 1542 refdiv = refdiv ? refdiv : 1543 tmp & RADEON_PPLL_REF_DIV_MASK; 1544 } 1545 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1546 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1547 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1548 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1549 } 1550 1551 1552 dontprobe: 1553 sc->sc_refclk = refclk * 10; 1554 sc->sc_refdiv = refdiv; 1555 sc->sc_minpll = minpll * 10; 1556 sc->sc_maxpll = maxpll * 10; 1557 return 0; 1558 } 1559 1560 int 1561 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1562 uint32_t *postdivbit, uint32_t *feedbackdiv) 1563 { 1564 int i; 1565 uint32_t outfreq; 1566 int div; 1567 1568 DPRINTF(("dot clock: %u\n", dotclock)); 1569 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1570 outfreq = div * dotclock; 1571 if ((outfreq >= sc->sc_minpll) && 1572 (outfreq <= sc->sc_maxpll)) { 1573 DPRINTF(("outfreq: %u\n", outfreq)); 1574 *postdivbit = 1575 ((uint32_t)radeonfb_dividers[i].mask << 16); 1576 DPRINTF(("post divider: %d (mask %x)\n", div, 1577 *postdivbit)); 1578 break; 1579 } 1580 } 1581 1582 if (div == 0) 1583 return 1; 1584 1585 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1586 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1587 return 0; 1588 } 1589 1590 #if 0 1591 #ifdef RADEONFB_DEBUG 1592 static void 1593 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1594 { 1595 char asc[17]; 1596 unsigned ptr = (unsigned)buffer; 1597 char *start = (char *)(ptr & ~0xf); 1598 char *end = (char *)(ptr + size); 1599 1600 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1601 1602 if (pfx == NULL) { 1603 pfx = ""; 1604 } 1605 1606 while (start < end) { 1607 unsigned offset = (unsigned)start & 0xf; 1608 if (offset == 0) { 1609 printf("%s%x: ", pfx, (unsigned)start); 1610 } 1611 if (((unsigned)start < ptr) || 1612 ((unsigned)start >= (ptr + size))) { 1613 printf(" "); 1614 asc[offset] = ' '; 1615 } else { 1616 printf("%02x", *(unsigned char *)start); 1617 if ((*start >= ' ') && (*start <= '~')) { 1618 asc[offset] = *start; 1619 } else { 1620 asc[offset] = '.'; 1621 } 1622 } 1623 asc[offset + 1] = 0; 1624 if (offset % 2) { 1625 printf(" "); 1626 } 1627 if (offset == 15) { 1628 printf(" %s\n", asc); 1629 } 1630 start++; 1631 } 1632 } 1633 #endif 1634 #endif 1635 1636 int 1637 radeonfb_getconnectors(struct radeonfb_softc *sc) 1638 { 1639 int i; 1640 int found = 0; 1641 1642 for (i = 0; i < 2; i++) { 1643 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1644 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1645 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1646 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1647 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1648 } 1649 1650 /* 1651 * This logic is borrowed from Xorg's radeon driver. 1652 */ 1653 if (!sc->sc_biossz) 1654 goto nobios; 1655 1656 if (IS_ATOM(sc)) { 1657 /* not done yet */ 1658 } else { 1659 uint16_t ptr; 1660 int port = 0; 1661 1662 ptr = GETBIOS16(sc, 0x48); 1663 ptr = GETBIOS16(sc, ptr + 0x50); 1664 for (i = 1; i < 4; i++) { 1665 uint16_t entry; 1666 uint8_t conn, ddc, dac, tmds; 1667 1668 /* 1669 * Parse the connector table. From reading the code, 1670 * it appears to made up of 16-bit entries for each 1671 * connector. The 16-bits are defined as: 1672 * 1673 * bits 12-15 - connector type (0 == end of table) 1674 * bits 8-11 - DDC type 1675 * bits 5-7 - ??? 1676 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1677 * bits 1-3 - ??? 1678 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1679 */ 1680 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1681 break; 1682 entry = GETBIOS16(sc, ptr + i * 2); 1683 1684 conn = (entry >> 12) & 0xf; 1685 ddc = (entry >> 8) & 0xf; 1686 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1687 RADEON_DAC_PRIMARY; 1688 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1689 RADEON_TMDS_INT; 1690 1691 if (conn == RADEON_CONN_NONE) 1692 continue; /* no connector */ 1693 1694 if ((found > 0) && 1695 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1696 /* duplicate entry for same connector */ 1697 continue; 1698 } 1699 1700 /* internal DDC_DVI port gets priority */ 1701 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1702 port = 0; 1703 else 1704 port = 1; 1705 1706 sc->sc_ports[port].rp_ddc_type = 1707 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1708 sc->sc_ports[port].rp_dac_type = dac; 1709 sc->sc_ports[port].rp_conn_type = 1710 min(conn, RADEON_CONN_UNSUPPORTED) ; 1711 1712 sc->sc_ports[port].rp_tmds_type = tmds; 1713 1714 if ((conn != RADEON_CONN_DVI_I) && 1715 (conn != RADEON_CONN_DVI_D) && 1716 (tmds == RADEON_TMDS_INT)) 1717 sc->sc_ports[port].rp_tmds_type = 1718 RADEON_TMDS_UNKNOWN; 1719 sc->sc_ports[port].rp_number = i - 1; 1720 1721 found += (port + 1); 1722 } 1723 } 1724 1725 nobios: 1726 if (!found) { 1727 DPRINTF(("No connector info in BIOS!\n")); 1728 if IS_MOBILITY(sc) { 1729 /* default, port 0 = internal TMDS, port 1 = CRT */ 1730 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1731 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1732 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1733 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1734 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1735 sc->sc_ports[0].rp_number = 0; 1736 1737 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1738 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1739 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1740 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1741 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1742 sc->sc_ports[1].rp_number = 1; 1743 } else { 1744 /* default, port 0 = DVI, port 1 = CRT */ 1745 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1746 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1747 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1748 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1749 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1750 sc->sc_ports[0].rp_number = 1; 1751 1752 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1753 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1754 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1755 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1756 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1757 sc->sc_ports[1].rp_number = 0; 1758 } 1759 } 1760 1761 /* 1762 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1763 * these chips should use TVDAC for the VGA port. 1764 */ 1765 if (HAS_SDAC(sc)) { 1766 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1767 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1768 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1769 } else { 1770 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1771 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1772 } 1773 } else if (!HAS_CRTC2(sc)) { 1774 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1775 } 1776 1777 for (i = 0; i < 2; i++) { 1778 char edid[128]; 1779 uint8_t ddc; 1780 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1781 prop_data_t edid_data; 1782 1783 DPRINTF(("Port #%d:\n", i)); 1784 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1785 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1786 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1787 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1788 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1789 1790 sc->sc_ports[i].rp_edid_valid = 0; 1791 /* first look for static EDID data */ 1792 if ((edid_data = prop_dictionary_get(device_properties( 1793 sc->sc_dev), "EDID")) != NULL) { 1794 1795 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1796 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1797 if (edid_parse(edid, eip) == 0) { 1798 1799 sc->sc_ports[i].rp_edid_valid = 1; 1800 } 1801 } 1802 /* if we didn't find any we'll try to talk to the monitor */ 1803 if (sc->sc_ports[i].rp_edid_valid != 1) { 1804 1805 ddc = sc->sc_ports[i].rp_ddc_type; 1806 if (ddc != RADEON_DDC_NONE) { 1807 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1808 == 0) && (edid_parse(edid, eip) == 0)) { 1809 1810 sc->sc_ports[i].rp_edid_valid = 1; 1811 #ifdef RADEONFB_DEBUG 1812 edid_print(eip); 1813 #endif 1814 } 1815 } 1816 } 1817 } 1818 1819 return found; 1820 } 1821 1822 int 1823 radeonfb_gettmds(struct radeonfb_softc *sc) 1824 { 1825 int i; 1826 1827 if (!sc->sc_biossz) { 1828 goto nobios; 1829 } 1830 1831 if (IS_ATOM(sc)) { 1832 /* XXX: not done yet */ 1833 } else { 1834 uint16_t ptr; 1835 int n; 1836 1837 ptr = GETBIOS16(sc, 0x48); 1838 ptr = GETBIOS16(sc, ptr + 0x34); 1839 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1840 if (GETBIOS8(sc, ptr) == 3) { 1841 /* revision three table */ 1842 n = GETBIOS8(sc, ptr + 5) + 1; 1843 n = min(n, 4); 1844 1845 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1846 for (i = 0; i < n; i++) { 1847 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1848 ptr + i * 10 + 8); 1849 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1850 ptr + i * 10 + 0x10); 1851 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1852 sc->sc_tmds_pll[i].rtp_freq, 1853 sc->sc_tmds_pll[i].rtp_pll)); 1854 } 1855 return 0; 1856 } 1857 } 1858 1859 nobios: 1860 DPRINTF(("no suitable DFP table present\n")); 1861 for (i = 0; 1862 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1863 i++) { 1864 int j; 1865 1866 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1867 continue; 1868 1869 for (j = 0; j < 4; j++) { 1870 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1871 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1872 sc->sc_tmds_pll[j].rtp_freq, 1873 sc->sc_tmds_pll[j].rtp_pll)); 1874 } 1875 return 0; 1876 } 1877 1878 return -1; 1879 } 1880 1881 const struct videomode * 1882 radeonfb_modelookup(const char *name) 1883 { 1884 int i; 1885 1886 for (i = 0; i < videomode_count; i++) 1887 if (!strcmp(name, videomode_list[i].name)) 1888 return &videomode_list[i]; 1889 1890 return NULL; 1891 } 1892 1893 void 1894 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1895 { 1896 if (crtc) { 1897 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1898 RADEON_P2PLL_ATOMIC_UPDATE_R); 1899 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1900 } else { 1901 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1902 RADEON_PPLL_ATOMIC_UPDATE_R); 1903 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1904 } 1905 } 1906 1907 void 1908 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1909 { 1910 int i; 1911 1912 for (i = 10000; i; i--) { 1913 if (crtc) { 1914 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1915 RADEON_P2PLL_ATOMIC_UPDATE_R) 1916 break; 1917 } else { 1918 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1919 RADEON_PPLL_ATOMIC_UPDATE_R) 1920 break; 1921 } 1922 } 1923 } 1924 1925 void 1926 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1927 { 1928 uint32_t pbit = 0; 1929 uint32_t feed = 0; 1930 uint32_t data, refdiv, div0; 1931 1932 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1933 1934 if (crtc == 0) { 1935 1936 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1937 if (IS_R300(sc)) { 1938 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1939 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1940 } else { 1941 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1942 sc->sc_refdiv; 1943 } 1944 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1945 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1946 RADEON_PPLL_POST3_DIV_MASK); 1947 div0 |= pbit; 1948 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1949 1950 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1951 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1952 /* 1953 * nothing to do here, the PLL is already where we 1954 * want it 1955 */ 1956 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1957 ~RADEON_PLL_DIV_SEL); 1958 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1959 return; 1960 } 1961 1962 /* alright, we do need to reprogram stuff */ 1963 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1964 RADEON_VCLK_SRC_SEL_CPUCLK, 1965 ~RADEON_VCLK_SRC_SEL_MASK); 1966 1967 /* put vclk into reset, use atomic updates */ 1968 SETPLL(sc, RADEON_PPLL_CNTL, 1969 RADEON_PPLL_REFCLK_SEL | 1970 RADEON_PPLL_FBCLK_SEL | 1971 RADEON_PPLL_RESET | 1972 RADEON_PPLL_ATOMIC_UPDATE_EN | 1973 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1974 1975 /* select clock 0 */ 1976 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1977 ~RADEON_PLL_DIV_SEL); 1978 1979 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1980 1981 /* xf86-video-radeon does this, not sure why */ 1982 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1983 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1984 1985 /* use the atomic update */ 1986 radeonfb_pllwriteupdate(sc, crtc); 1987 1988 /* and wait for it to complete */ 1989 radeonfb_pllwaitatomicread(sc, crtc); 1990 1991 /* program HTOTAL (why?) */ 1992 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1993 1994 /* drop reset */ 1995 CLRPLL(sc, RADEON_PPLL_CNTL, 1996 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1997 RADEON_PPLL_ATOMIC_UPDATE_EN | 1998 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1999 2000 PRINTPLL(RADEON_PPLL_CNTL); 2001 PRINTPLL(RADEON_PPLL_REF_DIV); 2002 PRINTPLL(RADEON_PPLL_DIV_3); 2003 2004 /* give clock time to lock */ 2005 delay(50000); 2006 2007 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2008 RADEON_VCLK_SRC_SEL_PPLLCLK, 2009 ~RADEON_VCLK_SRC_SEL_MASK); 2010 2011 } else { 2012 2013 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2014 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2015 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2016 2017 /* put vclk into reset, use atomic updates */ 2018 SETPLL(sc, RADEON_P2PLL_CNTL, 2019 RADEON_P2PLL_RESET | 2020 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2021 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2022 2023 /* program reference divider */ 2024 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2025 ~RADEON_P2PLL_REF_DIV_MASK); 2026 2027 /* program feedback and post dividers */ 2028 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2029 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2030 RADEON_P2PLL_POST0_DIV_MASK); 2031 data |= pbit; 2032 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2033 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2034 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2035 2036 PRINTPLL(RADEON_P2PLL_REF_DIV); 2037 PRINTPLL(RADEON_P2PLL_DIV_0); 2038 2039 /* use the atomic update */ 2040 radeonfb_pllwriteupdate(sc, crtc); 2041 2042 /* and wait for it to complete */ 2043 radeonfb_pllwaitatomicread(sc, crtc); 2044 2045 /* program HTOTAL (why?) */ 2046 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2047 2048 /* drop reset */ 2049 CLRPLL(sc, RADEON_P2PLL_CNTL, 2050 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2051 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2052 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2053 2054 /* allow time for clock to lock */ 2055 delay(50000); 2056 2057 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2058 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2059 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2060 } 2061 PRINTREG(RADEON_CRTC_MORE_CNTL); 2062 } 2063 2064 void 2065 radeonfb_modeswitch(struct radeonfb_display *dp) 2066 { 2067 struct radeonfb_softc *sc = dp->rd_softc; 2068 int i; 2069 2070 /* blank the display while we switch modes */ 2071 radeonfb_blank(dp, 1); 2072 2073 #if 0 2074 SET32(sc, RADEON_CRTC_EXT_CNTL, 2075 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2076 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2077 #endif 2078 2079 /* these registers might get in the way... */ 2080 PUT32(sc, RADEON_OVR_CLR, 0); 2081 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2082 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2083 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2084 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2085 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2086 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2087 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2088 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2089 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2090 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2091 2092 for (i = 0; i < dp->rd_ncrtcs; i++) 2093 radeonfb_setcrtc(dp, i); 2094 2095 /* activate the display */ 2096 radeonfb_blank(dp, 0); 2097 } 2098 2099 void 2100 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2101 { 2102 int crtc; 2103 struct videomode *mode; 2104 struct radeonfb_softc *sc; 2105 struct radeonfb_crtc *cp; 2106 uint32_t v; 2107 uint32_t gencntl; 2108 uint32_t htotaldisp; 2109 uint32_t hsyncstrt; 2110 uint32_t vtotaldisp; 2111 uint32_t vsyncstrt; 2112 uint32_t fphsyncstrt; 2113 uint32_t fpvsyncstrt; 2114 uint32_t fphtotaldisp; 2115 uint32_t fpvtotaldisp; 2116 uint32_t pitch; 2117 2118 sc = dp->rd_softc; 2119 cp = &dp->rd_crtcs[index]; 2120 crtc = cp->rc_number; 2121 mode = &cp->rc_videomode; 2122 2123 #if 1 2124 pitch = dp->rd_stride / dp->rd_bpp; 2125 #else 2126 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2127 (sc->sc_maxbpp * 8)); 2128 #endif 2129 switch (crtc) { 2130 case 0: 2131 gencntl = RADEON_CRTC_GEN_CNTL; 2132 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2133 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2134 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2135 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2136 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2137 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2138 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2139 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2140 break; 2141 case 1: 2142 gencntl = RADEON_CRTC2_GEN_CNTL; 2143 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2144 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2145 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2146 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2147 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2148 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2149 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2150 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2151 break; 2152 default: 2153 panic("Bad CRTC!"); 2154 break; 2155 } 2156 2157 /* 2158 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2159 */ 2160 /* only bother with 32bpp and 8bpp */ 2161 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2162 2163 if (crtc == 1) { 2164 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2165 } else { 2166 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2167 } 2168 2169 if (mode->flags & VID_DBLSCAN) 2170 v |= RADEON_CRTC2_DBL_SCAN_EN; 2171 2172 if (mode->flags & VID_INTERLACE) 2173 v |= RADEON_CRTC2_INTERLACE_EN; 2174 2175 if (mode->flags & VID_CSYNC) { 2176 v |= RADEON_CRTC2_CSYNC_EN; 2177 if (crtc == 1) 2178 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2179 } 2180 2181 PUT32(sc, gencntl, v); 2182 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2183 2184 /* 2185 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2186 */ 2187 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2188 if (crtc == 0) { 2189 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2190 RADEON_CRTC_DISPLAY_DIS); 2191 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2192 if (mode->flags & VID_CSYNC) 2193 v |= RADEON_CRTC_VSYNC_TRISTAT; 2194 } 2195 /* unconditional turn on CRT, in case first CRTC is DFP */ 2196 v |= RADEON_CRTC_CRT_ON; 2197 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2198 PRINTREG(RADEON_CRTC_EXT_CNTL); 2199 2200 /* 2201 * H_TOTAL_DISP 2202 */ 2203 v = ((mode->hdisplay / 8) - 1) << 16; 2204 v |= (mode->htotal / 8) - 1; 2205 PUT32(sc, htotaldisp, v); 2206 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2207 PUT32(sc, fphtotaldisp, v); 2208 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2209 2210 /* 2211 * H_SYNC_STRT_WID 2212 */ 2213 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2214 v |= mode->hsync_start; 2215 if (mode->flags & VID_NHSYNC) 2216 v |= RADEON_CRTC_H_SYNC_POL; 2217 PUT32(sc, hsyncstrt, v); 2218 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2219 PUT32(sc, fphsyncstrt, v); 2220 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2221 2222 /* 2223 * V_TOTAL_DISP 2224 */ 2225 v = ((mode->vdisplay - 1) << 16); 2226 v |= (mode->vtotal - 1); 2227 PUT32(sc, vtotaldisp, v); 2228 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2229 PUT32(sc, fpvtotaldisp, v); 2230 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2231 2232 /* 2233 * V_SYNC_STRT_WID 2234 */ 2235 v = ((mode->vsync_end - mode->vsync_start) << 16); 2236 v |= (mode->vsync_start - 1); 2237 if (mode->flags & VID_NVSYNC) 2238 v |= RADEON_CRTC_V_SYNC_POL; 2239 PUT32(sc, vsyncstrt, v); 2240 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2241 PUT32(sc, fpvsyncstrt, v); 2242 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2243 2244 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2245 2246 switch (crtc) { 2247 case 0: 2248 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2249 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2250 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2251 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2252 2253 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2254 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2255 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2256 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2257 PRINTREG(RADEON_CRTC_EXT_CNTL); 2258 PRINTREG(RADEON_CRTC_GEN_CNTL); 2259 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2260 break; 2261 2262 case 1: 2263 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2264 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2265 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2266 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2267 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2268 RADEON_CRTC2_VSYNC_DIS | 2269 RADEON_CRTC2_HSYNC_DIS | 2270 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2271 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2272 break; 2273 } 2274 } 2275 2276 int 2277 radeonfb_isblank(struct radeonfb_display *dp) 2278 { 2279 uint32_t reg, mask; 2280 2281 if(!dp->rd_softc->sc_mapped) 2282 return 1; 2283 2284 if (dp->rd_crtcs[0].rc_number) { 2285 reg = RADEON_CRTC2_GEN_CNTL; 2286 mask = RADEON_CRTC2_DISP_DIS; 2287 } else { 2288 reg = RADEON_CRTC_EXT_CNTL; 2289 mask = RADEON_CRTC_DISPLAY_DIS; 2290 } 2291 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2292 } 2293 2294 void 2295 radeonfb_blank(struct radeonfb_display *dp, int blank) 2296 { 2297 struct radeonfb_softc *sc = dp->rd_softc; 2298 uint32_t reg, mask; 2299 uint32_t fpreg, fpval; 2300 int i; 2301 2302 if (!sc->sc_mapped) 2303 return; 2304 2305 for (i = 0; i < dp->rd_ncrtcs; i++) { 2306 2307 if (dp->rd_crtcs[i].rc_number) { 2308 reg = RADEON_CRTC2_GEN_CNTL; 2309 mask = RADEON_CRTC2_DISP_DIS; 2310 fpreg = RADEON_FP2_GEN_CNTL; 2311 fpval = RADEON_FP2_ON; 2312 } else { 2313 reg = RADEON_CRTC_EXT_CNTL; 2314 mask = RADEON_CRTC_DISPLAY_DIS; 2315 fpreg = RADEON_FP_GEN_CNTL; 2316 fpval = RADEON_FP_FPON; 2317 } 2318 2319 if (blank) { 2320 SET32(sc, reg, mask); 2321 CLR32(sc, fpreg, fpval); 2322 } else { 2323 CLR32(sc, reg, mask); 2324 SET32(sc, fpreg, fpval); 2325 } 2326 } 2327 PRINTREG(RADEON_FP_GEN_CNTL); 2328 PRINTREG(RADEON_FP2_GEN_CNTL); 2329 } 2330 2331 void 2332 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2333 long *defattr) 2334 { 2335 struct radeonfb_display *dp = cookie; 2336 struct rasops_info *ri = &scr->scr_ri; 2337 2338 /* initialize font subsystem */ 2339 wsfont_init(); 2340 2341 DPRINTF(("init screen called, existing %d\n", existing)); 2342 2343 ri->ri_depth = dp->rd_bpp; 2344 ri->ri_width = dp->rd_virtx; 2345 ri->ri_height = dp->rd_virty; 2346 ri->ri_stride = dp->rd_stride; 2347 ri->ri_flg = RI_CENTER; 2348 switch (ri->ri_depth) { 2349 case 8: 2350 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2351 break; 2352 case 32: 2353 ri->ri_flg |= RI_ENABLE_ALPHA; 2354 /* we run radeons in RGB even on SPARC hardware */ 2355 ri->ri_rnum = 8; 2356 ri->ri_gnum = 8; 2357 ri->ri_bnum = 8; 2358 ri->ri_rpos = 16; 2359 ri->ri_gpos = 8; 2360 ri->ri_bpos = 0; 2361 break; 2362 } 2363 2364 ri->ri_bits = (void *)dp->rd_fbptr; 2365 2366 #ifdef VCONS_DRAW_INTR 2367 scr->scr_flags |= VCONS_DONT_READ; 2368 #endif 2369 2370 if (existing) { 2371 ri->ri_flg |= RI_CLEAR; 2372 2373 /* start a modeswitch now */ 2374 radeonfb_modeswitch(dp); 2375 } 2376 2377 /* 2378 * XXX: font selection should be based on properties, with some 2379 * normal/reasonable default. 2380 */ 2381 2382 /* initialize and look for an initial font */ 2383 rasops_init(ri, 0, 0); 2384 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2385 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2386 2387 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2388 dp->rd_virtx / ri->ri_font->fontwidth); 2389 2390 /* enable acceleration */ 2391 dp->rd_putchar = ri->ri_ops.putchar; 2392 ri->ri_ops.copyrows = radeonfb_copyrows; 2393 ri->ri_ops.copycols = radeonfb_copycols; 2394 ri->ri_ops.eraserows = radeonfb_eraserows; 2395 ri->ri_ops.erasecols = radeonfb_erasecols; 2396 /* pick a putchar method based on font and Radeon model */ 2397 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2398 /* got a bitmap font */ 2399 if (IS_R300(dp->rd_softc)) { 2400 /* 2401 * radeonfb_putchar() doesn't work right on some R3xx 2402 * so we use software drawing here, the wrapper just 2403 * makes sure the engine is idle before scribbling 2404 * into vram 2405 */ 2406 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2407 } else { 2408 ri->ri_ops.putchar = radeonfb_putchar; 2409 } 2410 } else { 2411 /* got an alpha font */ 2412 switch(ri->ri_depth) { 2413 case 32: 2414 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2415 break; 2416 case 8: 2417 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2418 break; 2419 default: 2420 /* XXX this should never happen */ 2421 panic("%s: depth is not 8 or 32 but we got an" \ 2422 " alpha font?!", __func__); 2423 } 2424 } 2425 ri->ri_ops.cursor = radeonfb_cursor; 2426 } 2427 2428 void 2429 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2430 { 2431 uint32_t gen, ext, gen2 = 0; 2432 uint32_t agploc, aperbase, apersize, mcfbloc; 2433 2434 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2435 /* XXX */ 2436 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2437 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2438 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2439 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2440 2441 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2442 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2443 #if 0 2444 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2445 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2446 #endif 2447 2448 if (HAS_CRTC2(sc)) { 2449 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2450 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2451 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2452 } 2453 2454 delay(100000); 2455 2456 mcfbloc = (aperbase >> 16) | 2457 ((aperbase + (apersize - 1)) & 0xffff0000); 2458 2459 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2460 sc->sc_memsz = apersize; 2461 2462 if (((agploc & 0xffff) << 16) != 2463 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2464 agploc = mcfbloc & 0xffff0000U; 2465 agploc |= ((agploc + 0x10000) >> 16); 2466 } 2467 2468 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2469 2470 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2471 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2472 2473 DPRINTF(("aperbase = %u\n", aperbase)); 2474 PRINTREG(RADEON_MC_FB_LOCATION); 2475 PRINTREG(RADEON_MC_AGP_LOCATION); 2476 2477 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2478 2479 if (HAS_CRTC2(sc)) 2480 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2481 2482 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2483 2484 #if 0 2485 /* XXX: what is this AGP garbage? :-) */ 2486 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2487 #endif 2488 2489 delay(100000); 2490 2491 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2492 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2493 2494 if (HAS_CRTC2(sc)) 2495 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2496 } 2497 2498 void 2499 radeonfb_init_misc(struct radeonfb_softc *sc) 2500 { 2501 PUT32(sc, RADEON_BUS_CNTL, 2502 RADEON_BUS_MASTER_DIS | 2503 RADEON_BUS_PREFETCH_MODE_ACT | 2504 RADEON_BUS_PCI_READ_RETRY_EN | 2505 RADEON_BUS_PCI_WRT_RETRY_EN | 2506 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2507 RADEON_BUS_MSTR_RD_MULT | 2508 RADEON_BUS_MSTR_RD_LINE | 2509 RADEON_BUS_RD_DISCARD_EN | 2510 RADEON_BUS_MSTR_DISCONNECT_EN | 2511 RADEON_BUS_READ_BURST); 2512 2513 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2514 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2515 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2516 PUT32(sc, RADEON_RBBM_CNTL, 2517 (3 << RADEON_RB_SETTLE_SHIFT) | 2518 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2519 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2520 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2521 2522 /* XXX: figure out what these mean! */ 2523 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2524 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2525 #if 0 2526 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2527 #endif 2528 2529 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2530 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2531 } 2532 2533 /* 2534 * This loads a linear color map for true color. 2535 */ 2536 void 2537 radeonfb_init_palette(struct radeonfb_display *dp) 2538 { 2539 struct radeonfb_softc *sc = dp->rd_softc; 2540 int i, cc; 2541 uint32_t vclk; 2542 int crtc; 2543 2544 #define DAC_WIDTH ((1 << 10) - 1) 2545 #define CLUT_WIDTH ((1 << 8) - 1) 2546 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2547 2548 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2549 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2550 2551 /* initialize the palette for every CRTC used by this display */ 2552 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2553 crtc = dp->rd_crtcs[cc].rc_number; 2554 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2555 2556 if (crtc) 2557 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2558 else 2559 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2560 2561 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2562 2563 if (dp->rd_bpp == 8) { 2564 2565 /* R3G3B2 palette */ 2566 int j = 0; 2567 uint32_t tmp, r, g, b; 2568 2569 for (i = 0; i <= CLUT_WIDTH; ++i) { 2570 tmp = i & 0xe0; 2571 /* 2572 * replicate bits so 0xe0 maps to a red value of 0xff 2573 * in order to make white look actually white 2574 */ 2575 tmp |= (tmp >> 3) | (tmp >> 6); 2576 r = tmp; 2577 2578 tmp = (i & 0x1c) << 3; 2579 tmp |= (tmp >> 3) | (tmp >> 6); 2580 g = tmp; 2581 2582 tmp = (i & 0x03) << 6; 2583 tmp |= tmp >> 2; 2584 tmp |= tmp >> 4; 2585 b = tmp; 2586 2587 PUT32(sc, RADEON_PALETTE_30_DATA, 2588 (r << 22) | 2589 (g << 12) | 2590 (b << 2)); 2591 j += 3; 2592 } 2593 } else { 2594 /* linear ramp */ 2595 for (i = 0; i <= CLUT_WIDTH; ++i) { 2596 PUT32(sc, RADEON_PALETTE_30_DATA, 2597 (CLUT_COLOR(i) << 10) | 2598 (CLUT_COLOR(i) << 20) | 2599 (CLUT_COLOR(i))); 2600 } 2601 } 2602 } 2603 2604 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2605 PRINTREG(RADEON_DAC_CNTL2); 2606 2607 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2608 } 2609 2610 /* 2611 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2612 */ 2613 void 2614 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2615 { 2616 uint32_t tmp, save; 2617 2618 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2619 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2620 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2621 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2622 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2623 } 2624 2625 /* 2626 * Acceleration entry points. 2627 */ 2628 2629 /* this one draws characters using bitmap fonts */ 2630 static void 2631 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2632 { 2633 struct rasops_info *ri = cookie; 2634 struct vcons_screen *scr = ri->ri_hw; 2635 struct radeonfb_display *dp = scr->scr_cookie; 2636 struct radeonfb_softc *sc = dp->rd_softc; 2637 struct wsdisplay_font *font = PICK_FONT(ri, c); 2638 uint32_t w, h; 2639 int xd, yd, offset, i; 2640 uint32_t bg, fg, gmc; 2641 uint32_t reg; 2642 uint8_t *data8; 2643 uint16_t *data16; 2644 void *data; 2645 2646 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2647 return; 2648 2649 if (!CHAR_IN_FONT(c, font)) 2650 return; 2651 2652 w = font->fontwidth; 2653 h = font->fontheight; 2654 2655 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2656 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2657 2658 xd = ri->ri_xorigin + col * w; 2659 yd = ri->ri_yorigin + row * h; 2660 2661 if (c == 0x20) { 2662 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2663 return; 2664 } 2665 data = WSFONT_GLYPH(c, font); 2666 2667 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2668 2669 radeonfb_wait_fifo(sc, 9); 2670 2671 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2672 RADEON_GMC_BRUSH_NONE | 2673 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2674 RADEON_GMC_DST_CLIPPING | 2675 RADEON_ROP3_S | 2676 RADEON_DP_SRC_SOURCE_HOST_DATA | 2677 RADEON_GMC_CLR_CMP_CNTL_DIS | 2678 RADEON_GMC_WR_MSK_DIS | 2679 gmc); 2680 2681 PUT32(sc, RADEON_SC_LEFT, xd); 2682 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2683 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2684 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2685 PUT32(sc, RADEON_DP_CNTL, 2686 RADEON_DST_X_LEFT_TO_RIGHT | 2687 RADEON_DST_Y_TOP_TO_BOTTOM); 2688 2689 PUT32(sc, RADEON_SRC_X_Y, 0); 2690 offset = 32 - (font->stride << 3); 2691 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2692 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2693 2694 radeonfb_wait_fifo(sc, h); 2695 switch (font->stride) { 2696 case 1: { 2697 data8 = data; 2698 for (i = 0; i < h; i++) { 2699 reg = *data8; 2700 #if BYTE_ORDER == LITTLE_ENDIAN 2701 reg = reg << 24; 2702 #endif 2703 bus_space_write_stream_4(sc->sc_regt, 2704 sc->sc_regh, RADEON_HOST_DATA0, reg); 2705 data8++; 2706 } 2707 break; 2708 } 2709 case 2: { 2710 data16 = data; 2711 for (i = 0; i < h; i++) { 2712 reg = *data16; 2713 #if BYTE_ORDER == LITTLE_ENDIAN 2714 reg = reg << 16; 2715 #endif 2716 bus_space_write_stream_4(sc->sc_regt, 2717 sc->sc_regh, RADEON_HOST_DATA0, reg); 2718 data16++; 2719 } 2720 break; 2721 } 2722 } 2723 if (attr & 1) 2724 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2725 } 2726 2727 /* ... while this one is for anti-aliased ones */ 2728 static void 2729 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2730 { 2731 struct rasops_info *ri = cookie; 2732 struct vcons_screen *scr = ri->ri_hw; 2733 struct radeonfb_display *dp = scr->scr_cookie; 2734 struct radeonfb_softc *sc = dp->rd_softc; 2735 struct wsdisplay_font *font = PICK_FONT(ri, c); 2736 uint32_t bg, fg, gmc; 2737 uint8_t *data; 2738 int w, h, xd, yd; 2739 int i, r, g, b, aval; 2740 int rf, gf, bf, rb, gb, bb; 2741 uint32_t pixel; 2742 int rv; 2743 2744 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2745 return; 2746 2747 if (!CHAR_IN_FONT(c, font)) 2748 return; 2749 2750 w = font->fontwidth; 2751 h = font->fontheight; 2752 2753 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2754 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2755 2756 xd = ri->ri_xorigin + col * w; 2757 yd = ri->ri_yorigin + row * h; 2758 2759 if (c == 0x20) { 2760 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2761 if (attr & 1) 2762 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2763 return; 2764 } 2765 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2766 if (rv == GC_OK) 2767 return; 2768 2769 data = WSFONT_GLYPH(c, font); 2770 2771 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2772 2773 radeonfb_wait_fifo(sc, 5); 2774 2775 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2776 RADEON_GMC_BRUSH_NONE | 2777 RADEON_GMC_SRC_DATATYPE_COLOR | 2778 RADEON_ROP3_S | 2779 RADEON_DP_SRC_SOURCE_HOST_DATA | 2780 RADEON_GMC_CLR_CMP_CNTL_DIS | 2781 RADEON_GMC_WR_MSK_DIS | 2782 gmc); 2783 2784 PUT32(sc, RADEON_DP_CNTL, 2785 RADEON_DST_X_LEFT_TO_RIGHT | 2786 RADEON_DST_Y_TOP_TO_BOTTOM); 2787 2788 PUT32(sc, RADEON_SRC_X_Y, 0); 2789 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2790 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2791 2792 rf = (fg >> 16) & 0xff; 2793 rb = (bg >> 16) & 0xff; 2794 gf = (fg >> 8) & 0xff; 2795 gb = (bg >> 8) & 0xff; 2796 bf = fg & 0xff; 2797 bb = bg & 0xff; 2798 2799 /* 2800 * I doubt we can upload data faster than even the slowest Radeon 2801 * could process them, especially when doing the alpha blending stuff 2802 * along the way, so just make sure there's some room in the FIFO and 2803 * then hammer away 2804 * As it turns out we can, so make periodic stops to let the FIFO 2805 * drain. 2806 */ 2807 radeonfb_wait_fifo(sc, 20); 2808 for (i = 0; i < ri->ri_fontscale; i++) { 2809 aval = *data; 2810 data++; 2811 if (aval == 0) { 2812 pixel = bg; 2813 } else if (aval == 255) { 2814 pixel = fg; 2815 } else { 2816 r = aval * rf + (255 - aval) * rb; 2817 g = aval * gf + (255 - aval) * gb; 2818 b = aval * bf + (255 - aval) * bb; 2819 pixel = (r & 0xff00) << 8 | 2820 (g & 0xff00) | 2821 (b & 0xff00) >> 8; 2822 } 2823 if (i & 16) 2824 radeonfb_wait_fifo(sc, 20); 2825 PUT32(sc, RADEON_HOST_DATA0, pixel); 2826 } 2827 if (rv == GC_ADD) { 2828 glyphcache_add(&dp->rd_gc, c, xd, yd); 2829 } else 2830 if (attr & 1) 2831 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2832 2833 } 2834 2835 static void 2836 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2837 { 2838 struct rasops_info *ri = cookie; 2839 struct vcons_screen *scr = ri->ri_hw; 2840 struct radeonfb_display *dp = scr->scr_cookie; 2841 struct radeonfb_softc *sc = dp->rd_softc; 2842 struct wsdisplay_font *font = PICK_FONT(ri, c); 2843 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2844 int i, x, y, wi, he, r, g, b, aval; 2845 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2846 uint8_t *data8; 2847 int rv, cnt; 2848 2849 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2850 return; 2851 2852 if (!CHAR_IN_FONT(c, font)) 2853 return; 2854 2855 wi = font->fontwidth; 2856 he = font->fontheight; 2857 2858 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2859 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2860 2861 x = ri->ri_xorigin + col * wi; 2862 y = ri->ri_yorigin + row * he; 2863 2864 if (c == 0x20) { 2865 radeonfb_rectfill(dp, x, y, wi, he, bg); 2866 if (attr & 1) 2867 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2868 return; 2869 } 2870 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2871 if (rv == GC_OK) 2872 return; 2873 2874 data8 = WSFONT_GLYPH(c, font); 2875 2876 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2877 2878 radeonfb_wait_fifo(sc, 5); 2879 2880 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2881 RADEON_GMC_BRUSH_NONE | 2882 RADEON_GMC_SRC_DATATYPE_COLOR | 2883 RADEON_ROP3_S | 2884 RADEON_DP_SRC_SOURCE_HOST_DATA | 2885 RADEON_GMC_CLR_CMP_CNTL_DIS | 2886 RADEON_GMC_WR_MSK_DIS | 2887 gmc); 2888 2889 PUT32(sc, RADEON_DP_CNTL, 2890 RADEON_DST_X_LEFT_TO_RIGHT | 2891 RADEON_DST_Y_TOP_TO_BOTTOM); 2892 2893 PUT32(sc, RADEON_SRC_X_Y, 0); 2894 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2895 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2896 2897 /* 2898 * we need the RGB colours here, so get offsets into rasops_cmap 2899 */ 2900 fgo = ((attr >> 24) & 0xf) * 3; 2901 bgo = ((attr >> 16) & 0xf) * 3; 2902 2903 r0 = rasops_cmap[bgo]; 2904 r1 = rasops_cmap[fgo]; 2905 g0 = rasops_cmap[bgo + 1]; 2906 g1 = rasops_cmap[fgo + 1]; 2907 b0 = rasops_cmap[bgo + 2]; 2908 b1 = rasops_cmap[fgo + 2]; 2909 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2910 bg8 = R3G3B2(r0, g0, b0); 2911 fg8 = R3G3B2(r1, g1, b1); 2912 2913 radeonfb_wait_fifo(sc, 20); 2914 cnt = 0; 2915 for (i = 0; i < ri->ri_fontscale; i++) { 2916 aval = *data8; 2917 if (aval == 0) { 2918 pixel = bg8; 2919 } else if (aval == 255) { 2920 pixel = fg8; 2921 } else { 2922 r = aval * r1 + (255 - aval) * r0; 2923 g = aval * g1 + (255 - aval) * g0; 2924 b = aval * b1 + (255 - aval) * b0; 2925 pixel = ((r & 0xe000) >> 8) | 2926 ((g & 0xe000) >> 11) | 2927 ((b & 0xc000) >> 14); 2928 } 2929 latch |= pixel << (8 * (i & 3)); 2930 /* write in 32bit chunks */ 2931 if ((i & 3) == 3) { 2932 PUT32(sc, RADEON_HOST_DATA0, latch); 2933 /* 2934 * not strictly necessary, old data should be shifted 2935 * out 2936 */ 2937 latch = 0; 2938 cnt++; 2939 if (cnt > 16) { 2940 cnt = 0; 2941 radeonfb_wait_fifo(sc, 20); 2942 } 2943 } 2944 data8++; 2945 } 2946 /* if we have pixels left in latch write them out */ 2947 if ((i & 3) != 0) { 2948 /* 2949 * radeon is weird - apparently leftover pixels are written 2950 * from the middle, not from the left as everything else 2951 */ 2952 PUT32(sc, RADEON_HOST_DATA0, latch); 2953 } 2954 2955 if (rv == GC_ADD) { 2956 glyphcache_add(&dp->rd_gc, c, x, y); 2957 } else 2958 if (attr & 1) 2959 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2960 2961 } 2962 2963 /* 2964 * wrapper for software character drawing 2965 * just sync the engine and call rasops*_putchar() 2966 */ 2967 2968 static void 2969 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2970 { 2971 struct rasops_info *ri = cookie; 2972 struct vcons_screen *scr = ri->ri_hw; 2973 struct radeonfb_display *dp = scr->scr_cookie; 2974 2975 radeonfb_engine_idle(dp->rd_softc); 2976 dp->rd_putchar(ri, row, col, c, attr); 2977 } 2978 2979 static void 2980 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2981 { 2982 struct rasops_info *ri = cookie; 2983 struct vcons_screen *scr = ri->ri_hw; 2984 struct radeonfb_display *dp = scr->scr_cookie; 2985 uint32_t x, y, w, h, fg, bg, ul; 2986 2987 /* XXX: check for full emulation mode? */ 2988 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2989 x = ri->ri_xorigin; 2990 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2991 w = ri->ri_emuwidth; 2992 h = ri->ri_font->fontheight * nrows; 2993 2994 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2995 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2996 } 2997 } 2998 2999 static void 3000 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3001 { 3002 struct rasops_info *ri = cookie; 3003 struct vcons_screen *scr = ri->ri_hw; 3004 struct radeonfb_display *dp = scr->scr_cookie; 3005 uint32_t x, ys, yd, w, h; 3006 3007 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3008 x = ri->ri_xorigin; 3009 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3010 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3011 w = ri->ri_emuwidth; 3012 h = ri->ri_font->fontheight * nrows; 3013 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3014 RADEON_ROP3_S); 3015 } 3016 } 3017 3018 static void 3019 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3020 { 3021 struct rasops_info *ri = cookie; 3022 struct vcons_screen *scr = ri->ri_hw; 3023 struct radeonfb_display *dp = scr->scr_cookie; 3024 uint32_t xs, xd, y, w, h; 3025 3026 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3027 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3028 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3029 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3030 w = ri->ri_font->fontwidth * ncols; 3031 h = ri->ri_font->fontheight; 3032 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3033 RADEON_ROP3_S); 3034 } 3035 } 3036 3037 static void 3038 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3039 long fillattr) 3040 { 3041 struct rasops_info *ri = cookie; 3042 struct vcons_screen *scr = ri->ri_hw; 3043 struct radeonfb_display *dp = scr->scr_cookie; 3044 uint32_t x, y, w, h, fg, bg, ul; 3045 3046 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3047 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3048 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3049 w = ri->ri_font->fontwidth * ncols; 3050 h = ri->ri_font->fontheight; 3051 3052 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3053 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3054 } 3055 } 3056 3057 static void 3058 radeonfb_cursor(void *cookie, int on, int row, int col) 3059 { 3060 struct rasops_info *ri = cookie; 3061 struct vcons_screen *scr = ri->ri_hw; 3062 struct radeonfb_display *dp = scr->scr_cookie; 3063 int x, y, wi, he; 3064 3065 wi = ri->ri_font->fontwidth; 3066 he = ri->ri_font->fontheight; 3067 3068 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3069 x = ri->ri_ccol * wi + ri->ri_xorigin; 3070 y = ri->ri_crow * he + ri->ri_yorigin; 3071 /* first turn off the old cursor */ 3072 if (ri->ri_flg & RI_CURSOR) { 3073 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3074 RADEON_ROP3_Dn); 3075 ri->ri_flg &= ~RI_CURSOR; 3076 } 3077 ri->ri_crow = row; 3078 ri->ri_ccol = col; 3079 /* then (possibly) turn on the new one */ 3080 if (on) { 3081 x = ri->ri_ccol * wi + ri->ri_xorigin; 3082 y = ri->ri_crow * he + ri->ri_yorigin; 3083 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3084 RADEON_ROP3_Dn); 3085 ri->ri_flg |= RI_CURSOR; 3086 } 3087 } else { 3088 scr->scr_ri.ri_crow = row; 3089 scr->scr_ri.ri_ccol = col; 3090 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3091 } 3092 } 3093 3094 /* 3095 * Underlying acceleration support. 3096 */ 3097 3098 static void 3099 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3100 int width, int height, uint32_t color) 3101 { 3102 struct radeonfb_softc *sc = dp->rd_softc; 3103 uint32_t gmc; 3104 3105 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3106 3107 radeonfb_wait_fifo(sc, 6); 3108 3109 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3110 RADEON_GMC_BRUSH_SOLID_COLOR | 3111 RADEON_GMC_SRC_DATATYPE_COLOR | 3112 RADEON_GMC_CLR_CMP_CNTL_DIS | 3113 RADEON_ROP3_P | gmc); 3114 3115 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3116 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3117 PUT32(sc, RADEON_DP_CNTL, 3118 RADEON_DST_X_LEFT_TO_RIGHT | 3119 RADEON_DST_Y_TOP_TO_BOTTOM); 3120 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3121 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3122 3123 } 3124 3125 static void 3126 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3127 int width, int height, long attr) 3128 { 3129 struct radeonfb_display *dp = cookie; 3130 3131 radeonfb_rectfill(dp, dstx, dsty, width, height, 3132 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3133 } 3134 3135 static void 3136 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3137 int dstx, int dsty, int width, int height, int rop) 3138 { 3139 struct radeonfb_display *dp = cookie; 3140 struct radeonfb_softc *sc = dp->rd_softc; 3141 uint32_t gmc; 3142 uint32_t dir; 3143 3144 if (dsty < srcy) { 3145 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3146 } else { 3147 srcy += height - 1; 3148 dsty += height - 1; 3149 dir = 0; 3150 } 3151 if (dstx < srcx) { 3152 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3153 } else { 3154 srcx += width - 1; 3155 dstx += width - 1; 3156 } 3157 3158 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3159 3160 radeonfb_wait_fifo(sc, 6); 3161 3162 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3163 RADEON_GMC_BRUSH_SOLID_COLOR | 3164 RADEON_GMC_SRC_DATATYPE_COLOR | 3165 RADEON_GMC_CLR_CMP_CNTL_DIS | 3166 RADEON_DP_SRC_SOURCE_MEMORY | 3167 rop | gmc); 3168 3169 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3170 PUT32(sc, RADEON_DP_CNTL, dir); 3171 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3172 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3173 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3174 } 3175 3176 static void 3177 radeonfb_engine_idle(struct radeonfb_softc *sc) 3178 { 3179 3180 radeonfb_wait_fifo(sc, 64); 3181 while ((GET32(sc, RADEON_RBBM_STATUS) & 3182 RADEON_RBBM_ACTIVE) != 0); 3183 radeonfb_engine_flush(sc); 3184 } 3185 3186 static inline void 3187 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3188 { 3189 int i; 3190 3191 for (i = RADEON_TIMEOUT; i; i--) { 3192 if ((GET32(sc, RADEON_RBBM_STATUS) & 3193 RADEON_RBBM_FIFOCNT_MASK) >= n) 3194 return; 3195 } 3196 #ifdef DIAGNOSTIC 3197 if (!i) 3198 printf("%s: timed out waiting for fifo (%x)\n", 3199 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3200 #endif 3201 } 3202 3203 static void 3204 radeonfb_engine_flush(struct radeonfb_softc *sc) 3205 { 3206 int i = 0; 3207 3208 if (IS_R300(sc)) { 3209 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3210 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3211 i++; 3212 } 3213 } else { 3214 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3215 RADEON_RB2D_DC_FLUSH_ALL); 3216 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3217 RADEON_RB2D_DC_BUSY) { 3218 i++; 3219 } 3220 } 3221 #ifdef DIAGNOSTIC 3222 if (i > RADEON_TIMEOUT) 3223 printf("%s: engine flush timed out!\n", XNAME(sc)); 3224 #endif 3225 } 3226 3227 static inline void 3228 radeonfb_unclip(struct radeonfb_softc *sc) 3229 { 3230 3231 radeonfb_wait_fifo(sc, 2); 3232 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3233 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3234 } 3235 3236 static void 3237 radeonfb_engine_init(struct radeonfb_display *dp) 3238 { 3239 struct radeonfb_softc *sc = dp->rd_softc; 3240 uint32_t pitch; 3241 volatile uint32_t junk; 3242 3243 /* no 3D */ 3244 PUT32(sc, RADEON_RB3D_CNTL, 0); 3245 3246 radeonfb_engine_reset(sc); 3247 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3248 3249 radeonfb_wait_fifo(sc, 1); 3250 if (!IS_R300(sc)) 3251 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3252 3253 radeonfb_wait_fifo(sc, 3); 3254 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3255 (pitch << 22) | (sc->sc_aperbase >> 10)); 3256 3257 3258 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3259 (pitch << 22) | (sc->sc_aperbase >> 10)); 3260 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3261 (pitch << 22) | (sc->sc_aperbase >> 10)); 3262 3263 junk = GET32(sc, RADEON_DP_DATATYPE); 3264 3265 /* default scissors -- no clipping */ 3266 radeonfb_wait_fifo(sc, 1); 3267 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3268 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3269 3270 radeonfb_wait_fifo(sc, 1); 3271 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3272 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3273 RADEON_GMC_CLR_CMP_CNTL_DIS | 3274 RADEON_GMC_BRUSH_SOLID_COLOR | 3275 RADEON_GMC_SRC_DATATYPE_COLOR); 3276 3277 radeonfb_wait_fifo(sc, 10); 3278 PUT32(sc, RADEON_DST_LINE_START, 0); 3279 PUT32(sc, RADEON_DST_LINE_END, 0); 3280 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3281 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3282 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3283 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3284 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3285 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3286 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3287 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3288 radeonfb_engine_idle(sc); 3289 } 3290 3291 static void 3292 radeonfb_engine_reset(struct radeonfb_softc *sc) 3293 { 3294 uint32_t hpc, rbbm, mclkcntl, clkindex; 3295 3296 radeonfb_engine_flush(sc); 3297 3298 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3299 if (HAS_R300CG(sc)) 3300 radeonfb_r300cg_workaround(sc); 3301 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3302 3303 /* 3304 * According to comments in XFree code, resetting the HDP via 3305 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3306 * So we use HOST_PATH_CNTL instead. 3307 */ 3308 3309 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3310 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3311 if (IS_R300(sc)) { 3312 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3313 RADEON_SOFT_RESET_CP | 3314 RADEON_SOFT_RESET_HI | 3315 RADEON_SOFT_RESET_E2); 3316 GET32(sc, RADEON_RBBM_SOFT_RESET); 3317 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3318 /* 3319 * XXX: this bit is not defined in any ATI docs I have, 3320 * nor in the XFree code, but XFree does it. Why? 3321 */ 3322 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3323 } else { 3324 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3325 RADEON_SOFT_RESET_CP | 3326 RADEON_SOFT_RESET_SE | 3327 RADEON_SOFT_RESET_RE | 3328 RADEON_SOFT_RESET_PP | 3329 RADEON_SOFT_RESET_E2 | 3330 RADEON_SOFT_RESET_RB); 3331 GET32(sc, RADEON_RBBM_SOFT_RESET); 3332 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3333 ~(RADEON_SOFT_RESET_CP | 3334 RADEON_SOFT_RESET_SE | 3335 RADEON_SOFT_RESET_RE | 3336 RADEON_SOFT_RESET_PP | 3337 RADEON_SOFT_RESET_E2 | 3338 RADEON_SOFT_RESET_RB)); 3339 GET32(sc, RADEON_RBBM_SOFT_RESET); 3340 } 3341 3342 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3343 GET32(sc, RADEON_HOST_PATH_CNTL); 3344 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3345 3346 if (IS_R300(sc)) 3347 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3348 3349 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3350 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3351 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3352 3353 if (HAS_R300CG(sc)) 3354 radeonfb_r300cg_workaround(sc); 3355 } 3356 3357 static int 3358 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3359 { 3360 int x, y; 3361 3362 x = pos->x; 3363 y = pos->y; 3364 3365 /* 3366 * This doesn't let a cursor move off the screen. I'm not 3367 * sure if this will have negative effects for e.g. Xinerama. 3368 * I'd guess Xinerama handles it by changing the cursor shape, 3369 * but that needs verification. 3370 */ 3371 if (x >= dp->rd_virtx) 3372 x = dp->rd_virtx - 1; 3373 if (x < 0) 3374 x = 0; 3375 if (y >= dp->rd_virty) 3376 y = dp->rd_virty - 1; 3377 if (y < 0) 3378 y = 0; 3379 3380 dp->rd_cursor.rc_pos.x = x; 3381 dp->rd_cursor.rc_pos.y = y; 3382 3383 radeonfb_cursor_position(dp); 3384 return 0; 3385 } 3386 3387 static int 3388 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3389 { 3390 unsigned flags; 3391 3392 uint8_t r[2], g[2], b[2]; 3393 unsigned index, count; 3394 int i, err; 3395 int pitch, size; 3396 struct radeonfb_cursor nc; 3397 3398 flags = wc->which; 3399 3400 /* copy old values */ 3401 nc = dp->rd_cursor; 3402 3403 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3404 index = wc->cmap.index; 3405 count = wc->cmap.count; 3406 3407 if (index >= 2 || (index + count) > 2) 3408 return EINVAL; 3409 3410 err = copyin(wc->cmap.red, &r[index], count); 3411 if (err) 3412 return err; 3413 err = copyin(wc->cmap.green, &g[index], count); 3414 if (err) 3415 return err; 3416 err = copyin(wc->cmap.blue, &b[index], count); 3417 if (err) 3418 return err; 3419 3420 for (i = index; i < index + count; i++) { 3421 nc.rc_cmap[i] = 3422 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3423 } 3424 } 3425 3426 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3427 if ((wc->size.x > RADEON_CURSORMAXX) || 3428 (wc->size.y > RADEON_CURSORMAXY)) 3429 return EINVAL; 3430 3431 /* figure bytes per line */ 3432 pitch = (wc->size.x + 7) / 8; 3433 size = pitch * wc->size.y; 3434 3435 /* clear the old cursor and mask */ 3436 memset(nc.rc_image, 0, 512); 3437 memset(nc.rc_mask, 0, 512); 3438 3439 nc.rc_size = wc->size; 3440 3441 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3442 return err; 3443 3444 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3445 return err; 3446 } 3447 3448 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3449 nc.rc_hot = wc->hot; 3450 if (nc.rc_hot.x >= nc.rc_size.x) 3451 nc.rc_hot.x = nc.rc_size.x - 1; 3452 if (nc.rc_hot.y >= nc.rc_size.y) 3453 nc.rc_hot.y = nc.rc_size.y - 1; 3454 } 3455 3456 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3457 nc.rc_pos = wc->pos; 3458 if (nc.rc_pos.x >= dp->rd_virtx) 3459 nc.rc_pos.x = dp->rd_virtx - 1; 3460 #if 0 3461 if (nc.rc_pos.x < 0) 3462 nc.rc_pos.x = 0; 3463 #endif 3464 if (nc.rc_pos.y >= dp->rd_virty) 3465 nc.rc_pos.y = dp->rd_virty - 1; 3466 #if 0 3467 if (nc.rc_pos.y < 0) 3468 nc.rc_pos.y = 0; 3469 #endif 3470 } 3471 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3472 nc.rc_visible = wc->enable; 3473 } 3474 3475 dp->rd_cursor = nc; 3476 radeonfb_cursor_update(dp, wc->which); 3477 3478 return 0; 3479 } 3480 3481 /* 3482 * Change the cursor shape. Call this with the cursor locked to avoid 3483 * flickering/tearing. 3484 */ 3485 static void 3486 radeonfb_cursor_shape(struct radeonfb_display *dp) 3487 { 3488 uint8_t and[512], xor[512]; 3489 int i, j, src, dst, pitch; 3490 const uint8_t *msk = dp->rd_cursor.rc_mask; 3491 const uint8_t *img = dp->rd_cursor.rc_image; 3492 3493 /* 3494 * Radeon cursor data interleaves one line of AND data followed 3495 * by a line of XOR data. (Each line corresponds to a whole hardware 3496 * pitch - i.e. 64 pixels or 8 bytes.) 3497 * 3498 * The cursor is displayed using the following table: 3499 * 3500 * AND XOR Result 3501 * ---------------------- 3502 * 0 0 Cursor color 0 3503 * 0 1 Cursor color 1 3504 * 1 0 Transparent 3505 * 1 1 Complement of background 3506 * 3507 * Our masks are therefore different from what we were passed. 3508 * Passed in, I'm assuming the data represents either color 0 or 1, 3509 * and a mask, so the passed in table looks like: 3510 * 3511 * IMG Mask Result 3512 * ----------------------- 3513 * 0 0 Transparent 3514 * 0 1 Cursor color 0 3515 * 1 0 Transparent 3516 * 1 1 Cursor color 1 3517 * 3518 * IF mask bit == 1, AND = 0, XOR = color. 3519 * IF mask bit == 0, AND = 1, XOR = 0. 3520 * 3521 * hence: AND = ~(mask); XOR = color & ~(mask); 3522 */ 3523 3524 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3525 3526 /* start by assuming all bits are transparent */ 3527 memset(and, 0xff, 512); 3528 memset(xor, 0x00, 512); 3529 3530 src = 0; 3531 dst = 0; 3532 for (i = 0; i < 64; i++) { 3533 for (j = 0; j < 64; j += 8) { 3534 if ((i < dp->rd_cursor.rc_size.y) && 3535 (j < dp->rd_cursor.rc_size.x)) { 3536 3537 /* take care to leave odd bits alone */ 3538 and[dst] &= ~(msk[src]); 3539 xor[dst] = img[src] & msk[src]; 3540 src++; 3541 } 3542 dst++; 3543 } 3544 } 3545 3546 /* copy the image into place */ 3547 for (i = 0; i < 64; i++) { 3548 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3549 &and[i * 8], 8); 3550 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3551 &xor[i * 8], 8); 3552 } 3553 } 3554 3555 static void 3556 radeonfb_cursor_position(struct radeonfb_display *dp) 3557 { 3558 struct radeonfb_softc *sc = dp->rd_softc; 3559 uint32_t offset, hvoff, hvpos; /* registers */ 3560 uint32_t coff; /* cursor offset */ 3561 int i, x, y, xoff, yoff, crtcoff; 3562 3563 /* 3564 * XXX: this also needs to handle pan/scan 3565 */ 3566 for (i = 0; i < dp->rd_ncrtcs; i++) { 3567 3568 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3569 3570 if (rcp->rc_number) { 3571 offset = RADEON_CUR2_OFFSET; 3572 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3573 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3574 crtcoff = RADEON_CRTC2_OFFSET; 3575 } else { 3576 offset = RADEON_CUR_OFFSET; 3577 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3578 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3579 crtcoff = RADEON_CRTC_OFFSET; 3580 } 3581 3582 x = dp->rd_cursor.rc_pos.x; 3583 y = dp->rd_cursor.rc_pos.y; 3584 3585 while (y < rcp->rc_yoffset) { 3586 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3587 } 3588 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3589 rcp->rc_yoffset += RADEON_PANINCREMENT; 3590 } 3591 while (x < rcp->rc_xoffset) { 3592 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3593 } 3594 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3595 rcp->rc_xoffset += RADEON_PANINCREMENT; 3596 } 3597 3598 /* adjust for the cursor's hotspot */ 3599 x -= dp->rd_cursor.rc_hot.x; 3600 y -= dp->rd_cursor.rc_hot.y; 3601 xoff = yoff = 0; 3602 3603 if (x >= dp->rd_virtx) 3604 x = dp->rd_virtx - 1; 3605 if (y >= dp->rd_virty) 3606 y = dp->rd_virty - 1; 3607 3608 /* now adjust cursor so it is relative to viewport */ 3609 x -= rcp->rc_xoffset; 3610 y -= rcp->rc_yoffset; 3611 3612 /* 3613 * no need to check for fall off, because we should 3614 * never move off the screen entirely! 3615 */ 3616 coff = 0; 3617 if (x < 0) { 3618 xoff = -x; 3619 x = 0; 3620 } 3621 if (y < 0) { 3622 yoff = -y; 3623 y = 0; 3624 coff = (yoff * 2) * 8; 3625 } 3626 3627 /* pan the display */ 3628 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3629 rcp->rc_xoffset); 3630 3631 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3632 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3633 /* NB: this unlocks the cursor */ 3634 PUT32(sc, hvpos, (x << 16) | y); 3635 } 3636 } 3637 3638 static void 3639 radeonfb_cursor_visible(struct radeonfb_display *dp) 3640 { 3641 int i; 3642 uint32_t gencntl, bit; 3643 3644 for (i = 0; i < dp->rd_ncrtcs; i++) { 3645 if (dp->rd_crtcs[i].rc_number) { 3646 gencntl = RADEON_CRTC2_GEN_CNTL; 3647 bit = RADEON_CRTC2_CUR_EN; 3648 } else { 3649 gencntl = RADEON_CRTC_GEN_CNTL; 3650 bit = RADEON_CRTC_CUR_EN; 3651 } 3652 3653 if (dp->rd_cursor.rc_visible) 3654 SET32(dp->rd_softc, gencntl, bit); 3655 else 3656 CLR32(dp->rd_softc, gencntl, bit); 3657 } 3658 } 3659 3660 static void 3661 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3662 { 3663 int i; 3664 uint32_t c0reg, c1reg; 3665 struct radeonfb_softc *sc = dp->rd_softc; 3666 3667 for (i = 0; i < dp->rd_ncrtcs; i++) { 3668 if (dp->rd_crtcs[i].rc_number) { 3669 c0reg = RADEON_CUR2_CLR0; 3670 c1reg = RADEON_CUR2_CLR1; 3671 } else { 3672 c0reg = RADEON_CUR_CLR0; 3673 c1reg = RADEON_CUR_CLR1; 3674 } 3675 3676 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3677 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3678 } 3679 } 3680 3681 static void 3682 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3683 { 3684 struct radeonfb_softc *sc; 3685 int i; 3686 3687 sc = dp->rd_softc; 3688 for (i = 0; i < dp->rd_ncrtcs; i++) { 3689 if (dp->rd_crtcs[i].rc_number) { 3690 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3691 } else { 3692 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3693 } 3694 } 3695 3696 if (which & WSDISPLAY_CURSOR_DOCMAP) 3697 radeonfb_cursor_cmap(dp); 3698 3699 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3700 radeonfb_cursor_shape(dp); 3701 3702 if (which & WSDISPLAY_CURSOR_DOCUR) 3703 radeonfb_cursor_visible(dp); 3704 3705 /* this one is unconditional, because it updates other stuff */ 3706 radeonfb_cursor_position(dp); 3707 } 3708 3709 static struct videomode * 3710 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3711 { 3712 int r1, r2; 3713 3714 /* otherwise pick the higher refresh rate */ 3715 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3716 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3717 3718 return (r1 < r2 ? m2 : m1); 3719 } 3720 3721 static const struct videomode * 3722 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3723 int x, int y) 3724 { 3725 struct edid_info *ep = &rp->rp_edid; 3726 struct videomode *vmp = NULL; 3727 int i; 3728 3729 if (!rp->rp_edid_valid) { 3730 /* fallback to safe mode */ 3731 return radeonfb_modelookup(sc->sc_defaultmode); 3732 } 3733 3734 /* always choose the preferred mode first! */ 3735 if (ep->edid_preferred_mode) { 3736 3737 /* XXX: add auto-stretching support for native mode */ 3738 3739 /* this may want panning to occur, btw */ 3740 if ((ep->edid_preferred_mode->hdisplay <= x) && 3741 (ep->edid_preferred_mode->vdisplay <= y)) 3742 return ep->edid_preferred_mode; 3743 } 3744 3745 for (i = 0; i < ep->edid_nmodes; i++) { 3746 /* 3747 * We elect to pick a resolution that is too large for 3748 * the monitor than one that is too small. This means 3749 * that we will prefer to pan rather than to try to 3750 * center a smaller display on a larger screen. In 3751 * practice, this shouldn't matter because if a 3752 * monitor can support a larger resolution, it can 3753 * probably also support the smaller. A specific 3754 * exception is fixed format panels, but hopefully 3755 * they are properly dealt with by the "autostretch" 3756 * logic above. 3757 */ 3758 if ((ep->edid_modes[i].hdisplay > x) || 3759 (ep->edid_modes[i].vdisplay > y)) { 3760 continue; 3761 } 3762 3763 /* 3764 * at this point, the display mode is no larger than 3765 * what we've requested. 3766 */ 3767 if (vmp == NULL) 3768 vmp = &ep->edid_modes[i]; 3769 3770 /* eliminate smaller modes */ 3771 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3772 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3773 continue; 3774 3775 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3776 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3777 vmp = &ep->edid_modes[i]; 3778 continue; 3779 } 3780 3781 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3782 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3783 3784 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3785 } 3786 3787 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3788 } 3789 3790 static int 3791 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3792 { 3793 int i; 3794 3795 for (i = 0; i < nlist; i++) { 3796 if ((x == list[i].hdisplay) && 3797 (y == list[i].vdisplay)) { 3798 return 1; 3799 } 3800 } 3801 return 0; 3802 } 3803 3804 static void 3805 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3806 int pan) 3807 { 3808 struct radeonfb_port *rp; 3809 struct edid_info *ep; 3810 int i, j; 3811 3812 *x = 0; 3813 *y = 0; 3814 3815 if (pan) { 3816 for (i = 0; i < dp->rd_ncrtcs; i++) { 3817 rp = dp->rd_crtcs[i].rc_port; 3818 ep = &rp->rp_edid; 3819 if (!rp->rp_edid_valid) { 3820 /* monitor not present */ 3821 continue; 3822 } 3823 3824 /* 3825 * For now we are ignoring "conflict" that 3826 * could occur when mixing some modes like 3827 * 1280x1024 and 1400x800. It isn't clear 3828 * which is better, so the first one wins. 3829 */ 3830 for (j = 0; j < ep->edid_nmodes; j++) { 3831 /* 3832 * ignore resolutions that are too big for 3833 * the radeon 3834 */ 3835 if (ep->edid_modes[j].hdisplay > 3836 dp->rd_softc->sc_maxx) 3837 continue; 3838 if (ep->edid_modes[j].vdisplay > 3839 dp->rd_softc->sc_maxy) 3840 continue; 3841 3842 /* 3843 * pick largest resolution, the 3844 * smaller monitor will pan 3845 */ 3846 if ((ep->edid_modes[j].hdisplay >= *x) && 3847 (ep->edid_modes[j].vdisplay >= *y)) { 3848 *x = ep->edid_modes[j].hdisplay; 3849 *y = ep->edid_modes[j].vdisplay; 3850 } 3851 } 3852 } 3853 3854 } else { 3855 struct videomode modes[64]; 3856 int nmodes = 0; 3857 int valid = 0; 3858 3859 for (i = 0; i < dp->rd_ncrtcs; i++) { 3860 /* 3861 * pick the largest resolution in common. 3862 */ 3863 rp = dp->rd_crtcs[i].rc_port; 3864 ep = &rp->rp_edid; 3865 3866 if (!rp->rp_edid_valid) 3867 continue; 3868 3869 if (!valid) { 3870 /* 3871 * Pick the preferred mode for this port 3872 * if available. 3873 */ 3874 if (ep->edid_preferred_mode) { 3875 struct videomode *vmp = 3876 ep->edid_preferred_mode; 3877 3878 if ((vmp->hdisplay <= 3879 dp->rd_softc->sc_maxx) && 3880 (vmp->vdisplay <= 3881 dp->rd_softc->sc_maxy)) 3882 modes[nmodes++] = *vmp; 3883 } else { 3884 3885 /* initialize starting list */ 3886 for (j = 0; j < ep->edid_nmodes; j++) { 3887 /* 3888 * ignore resolutions that are 3889 * too big for the radeon 3890 */ 3891 if (ep->edid_modes[j].hdisplay > 3892 dp->rd_softc->sc_maxx) 3893 continue; 3894 if (ep->edid_modes[j].vdisplay > 3895 dp->rd_softc->sc_maxy) 3896 continue; 3897 3898 modes[nmodes] = 3899 ep->edid_modes[j]; 3900 nmodes++; 3901 } 3902 } 3903 valid = 1; 3904 } else { 3905 /* merge into preexisting list */ 3906 for (j = 0; j < nmodes; j++) { 3907 if (!radeonfb_hasres(ep->edid_modes, 3908 ep->edid_nmodes, 3909 modes[j].hdisplay, 3910 modes[j].vdisplay)) { 3911 modes[j] = modes[nmodes]; 3912 j--; 3913 nmodes--; 3914 } 3915 } 3916 } 3917 } 3918 3919 /* now we have to pick from the merged list */ 3920 for (i = 0; i < nmodes; i++) { 3921 if ((modes[i].hdisplay >= *x) && 3922 (modes[i].vdisplay >= *y)) { 3923 *x = modes[i].hdisplay; 3924 *y = modes[i].vdisplay; 3925 } 3926 } 3927 } 3928 3929 if ((*x == 0) || (*y == 0)) { 3930 /* fallback to safe mode */ 3931 *x = 640; 3932 *y = 480; 3933 } 3934 } 3935 3936 /* 3937 * backlight levels are linear on: 3938 * - RV200, RV250, RV280, RV350 3939 * - but NOT on PowerBook4,3 6,3 6,5 3940 * according to Linux' radeonfb 3941 */ 3942 3943 /* Get the current backlight level for the display. */ 3944 3945 static int 3946 radeonfb_get_backlight(struct radeonfb_display *dp) 3947 { 3948 int s; 3949 uint32_t level; 3950 3951 s = spltty(); 3952 3953 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3954 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3955 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3956 3957 /* 3958 * On some chips, we should negate the backlight level. 3959 * XXX Find out on which chips. 3960 */ 3961 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3962 level = RADEONFB_BACKLIGHT_MAX - level; 3963 3964 splx(s); 3965 3966 return level; 3967 } 3968 3969 /* Set the backlight to the given level for the display. */ 3970 static void 3971 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3972 { 3973 if (dp->rd_bl_on == on) 3974 return; 3975 dp->rd_bl_on = on; 3976 radeonfb_set_backlight(dp, dp->rd_bl_level); 3977 } 3978 3979 static int 3980 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3981 { 3982 struct radeonfb_softc *sc; 3983 int rlevel, s; 3984 uint32_t lvds; 3985 3986 s = spltty(); 3987 3988 dp->rd_bl_level = level; 3989 if (dp->rd_bl_on == 0) 3990 level = 0; 3991 3992 if (level < 0) 3993 level = 0; 3994 else if (level >= RADEONFB_BACKLIGHT_MAX) 3995 level = RADEONFB_BACKLIGHT_MAX; 3996 3997 sc = dp->rd_softc; 3998 3999 /* On some chips, we should negate the backlight level. */ 4000 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4001 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4002 } else 4003 rlevel = level; 4004 4005 callout_stop(&dp->rd_bl_lvds_co); 4006 radeonfb_engine_idle(sc); 4007 4008 /* 4009 * Turn off the display if the backlight is set to 0, since the 4010 * display is useless without backlight anyway. 4011 */ 4012 if (level == 0) 4013 radeonfb_blank(dp, 1); 4014 else if (radeonfb_get_backlight(dp) == 0) 4015 radeonfb_blank(dp, 0); 4016 4017 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4018 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4019 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4020 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4021 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4022 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4023 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4024 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4025 lvds |= RADEON_LVDS_ON; 4026 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4027 } else { 4028 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4029 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4030 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4031 } 4032 4033 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4034 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4035 /* XXX What is the correct delay? */ 4036 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4037 4038 splx(s); 4039 4040 return 0; 4041 } 4042 4043 /* 4044 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4045 * Set the delayed bits in the register, and clear the stored delayed 4046 * value. 4047 */ 4048 4049 static void radeonfb_lvds_callout(void *arg) 4050 { 4051 struct radeonfb_display *dp = arg; 4052 int s; 4053 4054 s = splhigh(); 4055 4056 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4057 dp->rd_bl_lvds_val); 4058 dp->rd_bl_lvds_val = 0; 4059 4060 splx(s); 4061 } 4062 4063 static void 4064 radeonfb_brightness_up(device_t dev) 4065 { 4066 struct radeonfb_softc *sc = device_private(dev); 4067 struct radeonfb_display *dp = &sc->sc_displays[0]; 4068 int level; 4069 4070 /* we assume the main display is the first one - need a better way */ 4071 if (sc->sc_ndisplays < 1) return; 4072 /* make sure pushing the hotkeys always has an effect */ 4073 dp->rd_bl_on = 1; 4074 level = dp->rd_bl_level; 4075 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4076 radeonfb_set_backlight(dp, level); 4077 } 4078 4079 static void 4080 radeonfb_brightness_down(device_t dev) 4081 { 4082 struct radeonfb_softc *sc = device_private(dev); 4083 struct radeonfb_display *dp = &sc->sc_displays[0]; 4084 int level; 4085 4086 /* we assume the main display is the first one - need a better way */ 4087 if (sc->sc_ndisplays < 1) return; 4088 /* make sure pushing the hotkeys always has an effect */ 4089 dp->rd_bl_on = 1; 4090 level = dp->rd_bl_level; 4091 level = max(0, level - 5); 4092 radeonfb_set_backlight(dp, level); 4093 } 4094
Indexes created Wed Oct 22 13:09:56 GMT 2025