radeonfb.c revision 1.73
1 /* $NetBSD: radeonfb.c,v 1.73 2013/01/01 12:13:28 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.73 2013/01/01 12:13:28 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 174 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 175 #endif 176 177 static int radeonfb_set_backlight(struct radeonfb_display *, int); 178 static int radeonfb_get_backlight(struct radeonfb_display *); 179 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 180 static void radeonfb_lvds_callout(void *); 181 182 static void radeonfb_brightness_up(device_t); 183 static void radeonfb_brightness_down(device_t); 184 185 static struct videomode *radeonfb_best_refresh(struct videomode *, 186 struct videomode *); 187 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 188 uint16_t *, int); 189 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 190 struct radeonfb_port *, int, int); 191 192 static int radeonfb_drm_print(void *, const char *); 193 194 #ifdef RADEONFB_DEBUG 195 int radeon_debug = 1; 196 #define DPRINTF(x) \ 197 if (radeon_debug) printf x 198 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 199 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 200 #else 201 #define DPRINTF(x) 202 #define PRINTREG(r) 203 #define PRINTPLL(r) 204 #endif 205 206 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 207 208 #ifndef RADEON_DEFAULT_MODE 209 /* any reasonably modern display should handle this */ 210 #define RADEON_DEFAULT_MODE "1024x768x60" 211 #endif 212 213 extern const u_char rasops_cmap[768]; 214 215 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 216 217 static struct { 218 int size; /* minimum memory size (MB) */ 219 int maxx; /* maximum x dimension */ 220 int maxy; /* maximum y dimension */ 221 int maxbpp; /* maximum bpp */ 222 int maxdisp; /* maximum logical display count */ 223 } radeonfb_limits[] = { 224 { 32, 2048, 1536, 32, 2 }, 225 { 16, 1600, 1200, 32, 2 }, 226 { 8, 1600, 1200, 32, 1 }, 227 { 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct wsscreen_descr radeonfb_stdscreen = { 231 "fb", /* name */ 232 0, 0, /* ncols, nrows */ 233 NULL, /* textops */ 234 8, 16, /* fontwidth, fontheight */ 235 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 236 0, /* modecookie */ 237 }; 238 239 struct wsdisplay_accessops radeonfb_accessops = { 240 radeonfb_ioctl, 241 radeonfb_mmap, 242 NULL, /* vcons_alloc_screen */ 243 NULL, /* vcons_free_screen */ 244 NULL, /* vcons_show_screen */ 245 NULL, /* load_font */ 246 NULL, /* pollc */ 247 NULL, /* scroll */ 248 }; 249 250 static struct { 251 uint16_t devid; 252 uint16_t family; 253 uint16_t flags; 254 } radeonfb_devices[] = 255 { 256 /* R100 family */ 257 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 261 262 /* RV100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 267 268 /* RS100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 271 272 /* RS200/RS250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 277 278 /* R200 family */ 279 /* add more R200 products? , 5148 */ 280 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 285 286 /* RV200 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 291 292 /* RV250 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 298 299 /* RS300 family */ 300 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 304 305 /* RV280 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 313 314 /* R300 family */ 315 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 323 324 /* RV350/RV360 family */ 325 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 337 338 /* R350/R360 family */ 339 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 347 348 /* RV380/RV370 family */ 349 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 358 359 #if notyet 360 /* R420/R423 family */ 361 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 378 #endif 379 { 0, 0, 0 } 380 }; 381 382 static struct { 383 int divider; 384 int mask; 385 } radeonfb_dividers[] = { 386 { 16, 5 }, 387 { 12, 7 }, 388 { 8, 3 }, 389 { 6, 6 }, 390 { 4, 2 }, 391 { 3, 4 }, 392 { 2, 1 }, 393 { 1, 0 }, 394 { 0, 0 } 395 }; 396 397 /* 398 * This table taken from X11. 399 */ 400 static const struct { 401 int family; 402 struct radeon_tmds_pll plls[4]; 403 } radeonfb_tmds_pll[] = { 404 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 405 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RS100, {{0, 0}}}, 407 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 408 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 411 { RADEON_RS300, {{0, 0}}}, 412 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 413 { RADEON_R300, {{-1, 0xb01cb}}}, 414 { RADEON_R350, {{-1, 0xb01cb}}}, 415 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 416 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 417 { RADEON_R420, {{-1, 0xb01cb}}}, 418 }; 419 420 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 421 422 423 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 424 radeonfb_match, radeonfb_attach, NULL, NULL); 425 426 static int 427 radeonfb_match(device_t parent, cfdata_t match, void *aux) 428 { 429 const struct pci_attach_args *pa = aux; 430 int i; 431 432 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 433 return 0; 434 435 for (i = 0; radeonfb_devices[i].devid; i++) { 436 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 437 return 100; /* high to defeat VGA/VESA */ 438 } 439 440 return 0; 441 } 442 443 static void 444 radeonfb_attach(device_t parent, device_t dev, void *aux) 445 { 446 struct radeonfb_softc *sc = device_private(dev); 447 const struct pci_attach_args *pa = aux; 448 const char *mptr; 449 bus_size_t bsz; 450 pcireg_t screg; 451 int i, j, fg, bg, ul, flags; 452 uint32_t v; 453 454 sc->sc_dev = dev; 455 sc->sc_id = pa->pa_id; 456 for (i = 0; radeonfb_devices[i].devid; i++) { 457 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 458 break; 459 } 460 461 pci_aprint_devinfo(pa, NULL); 462 463 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 464 465 KASSERT(radeonfb_devices[i].devid != 0); 466 sc->sc_pt = pa->pa_tag; 467 sc->sc_iot = pa->pa_iot; 468 sc->sc_pc = pa->pa_pc; 469 sc->sc_family = radeonfb_devices[i].family; 470 sc->sc_flags = radeonfb_devices[i].flags; 471 472 /* enable memory and IO access */ 473 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 474 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 475 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 476 477 /* 478 * Some flags are general to entire chip families, and rather 479 * than clutter up the table with them, we go ahead and set 480 * them here. 481 */ 482 switch (sc->sc_family) { 483 case RADEON_RS100: 484 case RADEON_RS200: 485 sc->sc_flags |= RFB_IGP | RFB_RV100; 486 break; 487 488 case RADEON_RV100: 489 case RADEON_RV200: 490 case RADEON_RV250: 491 case RADEON_RV280: 492 sc->sc_flags |= RFB_RV100; 493 break; 494 495 case RADEON_RS300: 496 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 497 break; 498 499 case RADEON_R300: 500 case RADEON_RV350: 501 case RADEON_R350: 502 case RADEON_RV380: 503 case RADEON_R420: 504 /* newer chips */ 505 sc->sc_flags |= RFB_R300; 506 break; 507 508 case RADEON_R100: 509 sc->sc_flags |= RFB_NCRTC2; 510 break; 511 } 512 513 if ((sc->sc_family == RADEON_RV200) || 514 (sc->sc_family == RADEON_RV250) || 515 (sc->sc_family == RADEON_RV280) || 516 (sc->sc_family == RADEON_RV350)) { 517 bool inverted = 0; 518 /* backlight level is linear */ 519 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 520 prop_dictionary_get_bool(device_properties(sc->sc_dev), 521 "backlight_level_reverted", &inverted); 522 if (inverted) { 523 DPRINTF(("nope, it's inverted\n")); 524 sc->sc_flags |= RFB_INV_BLIGHT; 525 } 526 } else 527 sc->sc_flags |= RFB_INV_BLIGHT; 528 529 /* 530 * XXX: to support true multihead, this must change. 531 */ 532 sc->sc_ndisplays = 1; 533 534 /* XXX: */ 535 if (!HAS_CRTC2(sc)) { 536 sc->sc_ndisplays = 1; 537 } 538 539 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 540 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 541 &sc->sc_regsz) != 0) { 542 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 543 goto error; 544 } 545 546 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 547 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 548 { 549 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 550 goto error; 551 } 552 sc->sc_romt = sc->sc_memt; 553 554 sc->sc_mapped = TRUE; 555 556 /* scratch register test... */ 557 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 558 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 559 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 560 goto error; 561 } 562 563 PRINTREG(RADEON_CRTC_EXT_CNTL); 564 PRINTREG(RADEON_CRTC_GEN_CNTL); 565 PRINTREG(RADEON_CRTC2_GEN_CNTL); 566 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 567 PRINTREG(RADEON_DAC_CNTL2); 568 PRINTREG(RADEON_FP_GEN_CNTL); 569 PRINTREG(RADEON_FP2_GEN_CNTL); 570 571 PRINTREG(RADEON_BIOS_4_SCRATCH); 572 PRINTREG(RADEON_FP_GEN_CNTL); 573 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 574 PRINTREG(RADEON_FP2_GEN_CNTL); 575 PRINTREG(RADEON_TMDS_CNTL); 576 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 577 PRINTREG(RADEON_TMDS_PLL_CNTL); 578 PRINTREG(RADEON_LVDS_GEN_CNTL); 579 PRINTREG(RADEON_FP_HORZ_STRETCH); 580 PRINTREG(RADEON_FP_VERT_STRETCH); 581 582 if (IS_RV100(sc)) 583 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 584 585 /* XXX 586 * according to xf86-video-radeon R3xx has this bit backwards 587 */ 588 if (IS_R300(sc)) { 589 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 590 0, 591 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 592 } else { 593 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 594 RADEON_TMDS_TRANSMITTER_PLLEN, 595 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 596 } 597 598 radeonfb_i2c_init(sc); 599 600 radeonfb_loadbios(sc, pa); 601 602 #ifdef RADEONFB_BIOS_INIT 603 if (radeonfb_bios_init(sc)) { 604 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 605 } 606 #endif 607 608 if (radeonfb_getclocks(sc)) { 609 aprint_error("%s: Unable to get reference clocks from BIOS\n", 610 XNAME(sc)); 611 goto error; 612 } 613 614 if (radeonfb_gettmds(sc)) { 615 aprint_error("%s: Unable to identify TMDS PLL settings\n", 616 XNAME(sc)); 617 goto error; 618 } 619 620 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 621 "minpll = %d, maxpll = %d\n", XNAME(sc), 622 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 623 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 624 625 radeonfb_getconnectors(sc); 626 627 radeonfb_set_fbloc(sc); 628 629 for (i = 0; radeonfb_limits[i].size; i++) { 630 if (sc->sc_memsz >= radeonfb_limits[i].size) { 631 sc->sc_maxx = radeonfb_limits[i].maxx; 632 sc->sc_maxy = radeonfb_limits[i].maxy; 633 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 634 /* framebuffer offset, start at a 4K page */ 635 sc->sc_fboffset = sc->sc_memsz / 636 radeonfb_limits[i].maxdisp; 637 /* 638 * we use the fbsize to figure out where we can store 639 * things like cursor data. 640 */ 641 sc->sc_fbsize = 642 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 643 RADEON_STRIDEALIGN) * sc->sc_maxy, 644 4096); 645 break; 646 } 647 } 648 649 650 radeonfb_init_misc(sc); 651 652 /* program the DAC wirings */ 653 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 654 switch (sc->sc_ports[i].rp_dac_type) { 655 case RADEON_DAC_PRIMARY: 656 PATCH32(sc, RADEON_DAC_CNTL2, 657 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 658 ~RADEON_DAC2_DAC_CLK_SEL); 659 break; 660 case RADEON_DAC_TVDAC: 661 /* we always use the TVDAC to drive a secondary analog 662 * CRT for now. if we ever support TV-out this will 663 * have to change. 664 */ 665 SET32(sc, RADEON_DAC_CNTL2, 666 RADEON_DAC2_DAC2_CLK_SEL); 667 PATCH32(sc, RADEON_DISP_HW_DEBUG, 668 i ? 0 : RADEON_CRT2_DISP1_SEL, 669 ~RADEON_CRT2_DISP1_SEL); 670 /* we're using CRTC2 for the 2nd port */ 671 if (sc->sc_ports[i].rp_number == 1) { 672 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 673 RADEON_DISP_DAC2_SOURCE_CRTC2, 674 ~RADEON_DISP_DAC2_SOURCE_MASK); 675 } 676 677 break; 678 } 679 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 680 sc->sc_ports[i].rp_tmds_type)); 681 switch (sc->sc_ports[i].rp_tmds_type) { 682 case RADEON_TMDS_INT: 683 /* point FP0 at the CRTC this port uses */ 684 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 685 __func__, sc->sc_ports[i].rp_number)); 686 if (IS_R300(sc)) { 687 PATCH32(sc, RADEON_FP_GEN_CNTL, 688 sc->sc_ports[i].rp_number ? 689 R200_FP_SOURCE_SEL_CRTC2 : 690 R200_FP_SOURCE_SEL_CRTC1, 691 ~R200_FP_SOURCE_SEL_MASK); 692 } else { 693 PATCH32(sc, RADEON_FP_GEN_CNTL, 694 sc->sc_ports[i].rp_number ? 695 RADEON_FP_SEL_CRTC2 : 696 RADEON_FP_SEL_CRTC1, 697 ~RADEON_FP_SEL_MASK); 698 } 699 } 700 } 701 PRINTREG(RADEON_DAC_CNTL2); 702 PRINTREG(RADEON_DISP_HW_DEBUG); 703 704 /* other DAC programming */ 705 v = GET32(sc, RADEON_DAC_CNTL); 706 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 707 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 708 PUT32(sc, RADEON_DAC_CNTL, v); 709 PRINTREG(RADEON_DAC_CNTL); 710 711 /* XXX: this may need more investigation */ 712 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 713 PRINTREG(RADEON_TV_DAC_CNTL); 714 715 /* enable TMDS */ 716 SET32(sc, RADEON_FP_GEN_CNTL, 717 RADEON_FP_TMDS_EN | 718 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 719 RADEON_FP_CRTC_DONT_SHADOW_HEND); 720 /* 721 * XXX 722 * no idea why this is necessary - if I do not clear this bit on my 723 * iBook G4 the screen remains black, even though it's already clear. 724 * It needs to be set on my Sun XVR-100 for the DVI port to work 725 * TODO: 726 * see if this is still necessary now that CRTCs, DACs and outputs are 727 * getting wired up in a halfway sane way 728 */ 729 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 730 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 731 } else { 732 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 733 } 734 735 /* 736 * we use bus_space_map instead of pci_mapreg, because we don't 737 * need the full aperature space. no point in wasting virtual 738 * address space we don't intend to use, right? 739 */ 740 if ((sc->sc_memsz < (4096 * 1024)) || 741 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 742 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 743 (bsz < sc->sc_memsz)) { 744 sc->sc_memsz = 0; 745 aprint_error("%s: Bad frame buffer configuration\n", 746 XNAME(sc)); 747 goto error; 748 } 749 750 /* 64 MB should be enough -- more just wastes map entries */ 751 if (sc->sc_memsz > (64 << 20)) 752 sc->sc_memsz = (64 << 20); 753 754 sc->sc_memt = pa->pa_memt; 755 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 756 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 757 sc->sc_memsz = 0; 758 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 759 goto error; 760 } 761 762 aprint_normal("%s: %d MB aperture at 0x%08x, " 763 "%d KB registers at 0x%08x\n", XNAME(sc), 764 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 765 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 766 767 /* setup default video mode from devprop (allows PROM override) */ 768 sc->sc_defaultmode = radeonfb_default_mode; 769 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 770 "videomode", &mptr)) { 771 772 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 773 sc->sc_defaultmode = sc->sc_modebuf; 774 } 775 776 /* initialize some basic display parameters */ 777 for (i = 0; i < sc->sc_ndisplays; i++) { 778 struct radeonfb_display *dp = &sc->sc_displays[i]; 779 struct rasops_info *ri; 780 long defattr; 781 struct wsemuldisplaydev_attach_args aa; 782 783 /* 784 * Figure out how many "displays" (desktops) we are going to 785 * support. If more than one, then each CRTC gets its own 786 * programming. 787 * 788 * XXX: this code needs to change to support mergedfb. 789 * XXX: would be nice to allow this to be overridden 790 */ 791 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 792 DPRINTF(("dual crtcs!\n")); 793 dp->rd_ncrtcs = 2; 794 dp->rd_crtcs[0].rc_port = 795 &sc->sc_ports[0]; 796 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 797 dp->rd_crtcs[1].rc_port = 798 &sc->sc_ports[1]; 799 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 800 } else { 801 dp->rd_ncrtcs = 1; 802 dp->rd_crtcs[0].rc_port = 803 &sc->sc_ports[i]; 804 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 805 } 806 807 dp->rd_softc = sc; 808 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 809 dp->rd_bg = WS_DEFAULT_BG; 810 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 811 812 /* for text mode, we pick a resolution that won't 813 * require panning */ 814 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 815 816 aprint_normal("%s: display %d: " 817 "initial virtual resolution %dx%d at %d bpp\n", 818 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 819 820 /* now select the *video mode* that we will use */ 821 for (j = 0; j < dp->rd_ncrtcs; j++) { 822 const struct videomode *vmp; 823 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 824 dp->rd_virtx, dp->rd_virty); 825 826 /* 827 * virtual resolution should be at least as high as 828 * physical 829 */ 830 if (dp->rd_virtx < vmp->hdisplay || 831 dp->rd_virty < vmp->vdisplay) { 832 dp->rd_virtx = vmp->hdisplay; 833 dp->rd_virty = vmp->vdisplay; 834 } 835 836 dp->rd_crtcs[j].rc_videomode = *vmp; 837 printf("%s: port %d: physical %dx%d %dHz\n", 838 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 839 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 840 vmp->htotal), vmp->vtotal)); 841 } 842 843 /* N.B.: radeon wants 64-byte aligned stride */ 844 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 845 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 846 DPRINTF(("stride: %d\n", dp->rd_stride)); 847 848 dp->rd_offset = sc->sc_fboffset * i; 849 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 850 sc->sc_memh) + dp->rd_offset; 851 dp->rd_curoff = sc->sc_fbsize; 852 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 853 854 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 855 856 switch (dp->rd_bpp) { 857 case 8: 858 dp->rd_format = 2; 859 break; 860 case 32: 861 dp->rd_format = 6; 862 break; 863 default: 864 aprint_error("%s: bad depth %d\n", XNAME(sc), 865 dp->rd_bpp); 866 goto error; 867 } 868 869 DPRINTF(("init engine\n")); 870 /* XXX: this seems suspicious - per display engine 871 initialization? */ 872 radeonfb_engine_init(dp); 873 874 /* copy the template into place */ 875 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 876 dp->rd_wsscreens = dp->rd_wsscreens_storage; 877 878 /* and make up the list */ 879 dp->rd_wsscreenlist.nscreens = 1; 880 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 881 882 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 883 &radeonfb_accessops); 884 885 dp->rd_vd.init_screen = radeonfb_init_screen; 886 887 #ifdef RADEONFB_DEBUG 888 dp->rd_virty -= 200; 889 #endif 890 891 dp->rd_console = 0; 892 prop_dictionary_get_bool(device_properties(sc->sc_dev), 893 "is_console", &dp->rd_console); 894 895 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 896 897 898 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 899 dp->rd_console, &defattr); 900 901 ri = &dp->rd_vscreen.scr_ri; 902 903 /* clear the screen */ 904 rasops_unpack_attr(defattr, &fg, &bg, &ul); 905 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 906 ri->ri_devcmap[bg & 0xf]); 907 908 dp->rd_wsscreens->textops = &ri->ri_ops; 909 dp->rd_wsscreens->capabilities = ri->ri_caps; 910 dp->rd_wsscreens->nrows = ri->ri_rows; 911 dp->rd_wsscreens->ncols = ri->ri_cols; 912 913 #ifdef SPLASHSCREEN 914 dp->rd_splash.si_depth = ri->ri_depth; 915 dp->rd_splash.si_bits = ri->ri_bits; 916 dp->rd_splash.si_hwbits = ri->ri_hwbits; 917 dp->rd_splash.si_width = ri->ri_width; 918 dp->rd_splash.si_height = ri->ri_height; 919 dp->rd_splash.si_stride = ri->ri_stride; 920 dp->rd_splash.si_fillrect = NULL; 921 #endif 922 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 923 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 924 dp->rd_gc.gc_rop = RADEON_ROP3_S; 925 dp->rd_gc.gc_blitcookie = dp; 926 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 927 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 928 dp->rd_virtx, 929 ri->ri_font->fontwidth, 930 ri->ri_font->fontheight, 931 defattr); 932 if (dp->rd_console) { 933 934 radeonfb_modeswitch(dp); 935 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 936 defattr); 937 #ifdef SPLASHSCREEN 938 if (splash_render(&dp->rd_splash, 939 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 940 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 941 else 942 #endif 943 vcons_replay_msgbuf(&dp->rd_vscreen); 944 } else { 945 946 /* 947 * since we're not the console we can postpone 948 * the rest until someone actually allocates a 949 * screen for us. but we do clear the screen 950 * at least. 951 */ 952 memset(ri->ri_bits, 0, 1024); 953 954 radeonfb_modeswitch(dp); 955 #ifdef SPLASHSCREEN 956 if (splash_render(&dp->rd_splash, 957 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 958 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 959 #endif 960 } 961 962 aa.console = dp->rd_console; 963 aa.scrdata = &dp->rd_wsscreenlist; 964 aa.accessops = &radeonfb_accessops; 965 aa.accesscookie = &dp->rd_vd; 966 967 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 968 969 radeonfb_blank(dp, 0); 970 971 /* Initialise delayed lvds operations for backlight. */ 972 callout_init(&dp->rd_bl_lvds_co, 0); 973 callout_setfunc(&dp->rd_bl_lvds_co, 974 radeonfb_lvds_callout, dp); 975 dp->rd_bl_on = 1; 976 dp->rd_bl_level = radeonfb_get_backlight(dp); 977 radeonfb_set_backlight(dp, dp->rd_bl_level); 978 } 979 980 for (i = 0; i < RADEON_NDISPLAYS; i++) 981 radeonfb_init_palette(&sc->sc_displays[i]); 982 983 if (HAS_CRTC2(sc)) { 984 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 985 } 986 987 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 988 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 989 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 990 radeonfb_brightness_up, TRUE); 991 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 992 radeonfb_brightness_down, TRUE); 993 994 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 995 996 PRINTREG(RADEON_CRTC_EXT_CNTL); 997 PRINTREG(RADEON_CRTC_GEN_CNTL); 998 PRINTREG(RADEON_CRTC2_GEN_CNTL); 999 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1000 PRINTREG(RADEON_DAC_CNTL2); 1001 PRINTREG(RADEON_FP_GEN_CNTL); 1002 PRINTREG(RADEON_FP2_GEN_CNTL); 1003 1004 return; 1005 1006 error: 1007 if (sc->sc_biossz) 1008 free(sc->sc_bios, M_DEVBUF); 1009 1010 if (sc->sc_regsz) 1011 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1012 1013 if (sc->sc_memsz) 1014 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1015 } 1016 1017 static void 1018 radeonfb_map(struct radeonfb_softc *sc) 1019 { 1020 if (!sc->sc_mapped) { 1021 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1022 &sc->sc_regh) != 0) { 1023 aprint_error_dev(sc->sc_dev, 1024 "unable to map registers!\n"); 1025 return; 1026 } 1027 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1028 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1029 sc->sc_memsz = 0; 1030 aprint_error_dev(sc->sc_dev, 1031 "Unable to map frame buffer\n"); 1032 return; 1033 } 1034 sc->sc_mapped = TRUE; 1035 } 1036 } 1037 1038 static void 1039 radeonfb_unmap(struct radeonfb_softc *sc) 1040 { 1041 if (sc->sc_mapped) { 1042 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1043 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1044 sc->sc_mapped = FALSE; 1045 } 1046 } 1047 1048 static int 1049 radeonfb_drm_print(void *aux, const char *pnp) 1050 { 1051 if (pnp) 1052 aprint_normal("drm at %s", pnp); 1053 return (UNCONF); 1054 } 1055 1056 int 1057 radeonfb_ioctl(void *v, void *vs, 1058 unsigned long cmd, void *d, int flag, struct lwp *l) 1059 { 1060 struct vcons_data *vd; 1061 struct radeonfb_display *dp; 1062 struct radeonfb_softc *sc; 1063 struct wsdisplay_param *param; 1064 1065 vd = (struct vcons_data *)v; 1066 dp = (struct radeonfb_display *)vd->cookie; 1067 sc = dp->rd_softc; 1068 1069 switch (cmd) { 1070 case WSDISPLAYIO_GTYPE: 1071 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1072 return 0; 1073 1074 case WSDISPLAYIO_GINFO: 1075 if (vd->active != NULL) { 1076 struct wsdisplay_fbinfo *fb; 1077 fb = (struct wsdisplay_fbinfo *)d; 1078 fb->width = dp->rd_virtx; 1079 fb->height = dp->rd_virty; 1080 fb->depth = dp->rd_bpp; 1081 fb->cmsize = 256; 1082 return 0; 1083 } else 1084 return ENODEV; 1085 case WSDISPLAYIO_GVIDEO: 1086 if (radeonfb_isblank(dp)) 1087 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1088 else 1089 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1090 return 0; 1091 1092 case WSDISPLAYIO_SVIDEO: 1093 radeonfb_blank(dp, 1094 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1095 return 0; 1096 1097 case WSDISPLAYIO_GETCMAP: 1098 #if 0 1099 if (dp->rd_bpp == 8) 1100 return radeonfb_getcmap(sc, 1101 (struct wsdisplay_cmap *)d); 1102 #endif 1103 return EINVAL; 1104 1105 case WSDISPLAYIO_PUTCMAP: 1106 #if 0 1107 if (dp->rd_bpp == 8) 1108 return radeonfb_putcmap(sc, 1109 (struct wsdisplay_cmap *)d); 1110 #endif 1111 return EINVAL; 1112 1113 case WSDISPLAYIO_LINEBYTES: 1114 *(unsigned *)d = dp->rd_stride; 1115 return 0; 1116 1117 case WSDISPLAYIO_SMODE: 1118 if (*(int *)d != dp->rd_wsmode) { 1119 dp->rd_wsmode = *(int *)d; 1120 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1121 (dp->rd_vd.active)) { 1122 radeonfb_map(sc); 1123 radeonfb_engine_init(dp); 1124 glyphcache_wipe(&dp->rd_gc); 1125 radeonfb_init_palette(dp); 1126 radeonfb_modeswitch(dp); 1127 vcons_redraw_screen(dp->rd_vd.active); 1128 } else { 1129 radeonfb_unmap(sc); 1130 } 1131 } 1132 return 0; 1133 1134 case WSDISPLAYIO_GCURMAX: 1135 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1136 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1137 return 0; 1138 1139 case WSDISPLAYIO_SCURSOR: 1140 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1141 1142 case WSDISPLAYIO_GCURSOR: 1143 return EPASSTHROUGH; 1144 1145 case WSDISPLAYIO_GCURPOS: 1146 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1147 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1148 return 0; 1149 1150 case WSDISPLAYIO_SCURPOS: 1151 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1152 1153 case WSDISPLAYIO_SSPLASH: 1154 #if defined(SPLASHSCREEN) 1155 if (*(int *)d == 1) { 1156 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1157 splash_render(&dp->rd_splash, 1158 SPLASH_F_CENTER|SPLASH_F_FILL); 1159 } else 1160 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1161 return 0; 1162 #else 1163 return ENODEV; 1164 #endif 1165 case WSDISPLAYIO_GETPARAM: 1166 param = (struct wsdisplay_param *)d; 1167 switch (param->param) { 1168 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1169 param->min = 0; 1170 param->max = 255; 1171 param->curval = dp->rd_bl_level; 1172 return 0; 1173 case WSDISPLAYIO_PARAM_BACKLIGHT: 1174 param->min = 0; 1175 param->max = RADEONFB_BACKLIGHT_MAX; 1176 param->curval = dp->rd_bl_on; 1177 return 0; 1178 } 1179 return EPASSTHROUGH; 1180 1181 case WSDISPLAYIO_SETPARAM: 1182 param = (struct wsdisplay_param *)d; 1183 switch (param->param) { 1184 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1185 radeonfb_set_backlight(dp, param->curval); 1186 return 0; 1187 case WSDISPLAYIO_PARAM_BACKLIGHT: 1188 radeonfb_switch_backlight(dp, param->curval); 1189 return 0; 1190 } 1191 return EPASSTHROUGH; 1192 1193 /* PCI config read/write passthrough. */ 1194 case PCI_IOC_CFGREAD: 1195 case PCI_IOC_CFGWRITE: 1196 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1197 1198 case WSDISPLAYIO_GET_BUSID: 1199 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1200 sc->sc_pt, d); 1201 1202 case WSDISPLAYIO_GET_EDID: { 1203 struct wsdisplayio_edid_info *ei = d; 1204 return wsdisplayio_get_edid(sc->sc_dev, ei); 1205 } 1206 1207 default: 1208 return EPASSTHROUGH; 1209 } 1210 } 1211 1212 paddr_t 1213 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1214 { 1215 struct vcons_data *vd; 1216 struct radeonfb_display *dp; 1217 struct radeonfb_softc *sc; 1218 paddr_t pa; 1219 1220 vd = (struct vcons_data *)v; 1221 dp = (struct radeonfb_display *)vd->cookie; 1222 sc = dp->rd_softc; 1223 1224 /* XXX: note that we don't allow mapping of registers right now */ 1225 /* XXX: this means that the XFree86 radeon driver won't work */ 1226 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1227 pa = bus_space_mmap(sc->sc_memt, 1228 sc->sc_memaddr + dp->rd_offset + offset, 0, 1229 prot, BUS_SPACE_MAP_LINEAR); 1230 return pa; 1231 } 1232 1233 #ifdef RADEONFB_MMAP_BARS 1234 /* 1235 * restrict all other mappings to processes with superuser privileges 1236 * or the kernel itself 1237 */ 1238 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1239 NULL, NULL, NULL, NULL) != 0) { 1240 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1241 return -1; 1242 } 1243 1244 if ((offset >= sc->sc_regaddr) && 1245 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1246 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1247 BUS_SPACE_MAP_LINEAR); 1248 } 1249 1250 if ((offset >= sc->sc_memaddr) && 1251 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1252 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1253 BUS_SPACE_MAP_LINEAR); 1254 } 1255 1256 if ((offset >= sc->sc_romaddr) && 1257 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1258 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1259 BUS_SPACE_MAP_LINEAR); 1260 } 1261 1262 #ifdef PCI_MAGIC_IO_RANGE 1263 /* allow mapping of IO space */ 1264 if ((offset >= PCI_MAGIC_IO_RANGE) && 1265 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1266 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1267 0, prot, 0); 1268 return pa; 1269 } 1270 #endif /* PCI_MAGIC_IO_RANGE */ 1271 1272 #endif /* RADEONFB_MMAP_BARS */ 1273 1274 return -1; 1275 } 1276 1277 static void 1278 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1279 { 1280 bus_space_tag_t romt; 1281 bus_space_handle_t romh, biosh; 1282 bus_size_t romsz; 1283 bus_addr_t ptr; 1284 1285 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1286 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1287 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1288 return; 1289 } 1290 1291 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1292 &sc->sc_biossz); 1293 if (sc->sc_biossz == 0) { 1294 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1295 return; 1296 } 1297 1298 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1299 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1300 1301 /* unmap the PCI expansion rom */ 1302 bus_space_unmap(romt, romh, romsz); 1303 1304 /* turn off rom decoder now */ 1305 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1306 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1307 ~PCI_MAPREG_ROM_ENABLE); 1308 1309 ptr = GETBIOS16(sc, 0x48); 1310 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1311 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1312 sc->sc_flags |= RFB_ATOM; 1313 } 1314 1315 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1316 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1317 } 1318 1319 1320 uint32_t 1321 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1322 { 1323 1324 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1325 } 1326 1327 void 1328 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1329 { 1330 1331 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1332 } 1333 1334 void 1335 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1336 { 1337 1338 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1339 } 1340 1341 void 1342 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1343 uint32_t andmask, uint32_t ormask) 1344 { 1345 int s; 1346 uint32_t val; 1347 1348 s = splhigh(); 1349 val = radeonfb_get32(sc, reg); 1350 val = (val & andmask) | ormask; 1351 radeonfb_put32(sc, reg, val); 1352 splx(s); 1353 } 1354 1355 uint32_t 1356 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1357 { 1358 int s; 1359 uint32_t val; 1360 1361 s = splhigh(); 1362 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1363 val = radeonfb_get32(sc, RADEON_MM_DATA); 1364 splx(s); 1365 1366 return (val); 1367 } 1368 1369 void 1370 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1371 { 1372 int s; 1373 1374 s = splhigh(); 1375 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1376 radeonfb_put32(sc, RADEON_MM_DATA, val); 1377 splx(s); 1378 } 1379 1380 void 1381 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1382 uint32_t andmask, uint32_t ormask) 1383 { 1384 int s; 1385 uint32_t val; 1386 1387 s = splhigh(); 1388 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1389 val = radeonfb_get32(sc, RADEON_MM_DATA); 1390 val = (val & andmask) | ormask; 1391 radeonfb_put32(sc, RADEON_MM_DATA, val); 1392 splx(s); 1393 } 1394 1395 uint32_t 1396 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1397 { 1398 int s; 1399 uint32_t val; 1400 1401 s = splhigh(); 1402 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1403 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1404 if (HAS_R300CG(sc)) 1405 radeonfb_r300cg_workaround(sc); 1406 splx(s); 1407 1408 return (val); 1409 } 1410 1411 void 1412 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1413 { 1414 int s; 1415 1416 s = splhigh(); 1417 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1418 RADEON_PLL_WR_EN); 1419 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1420 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1421 splx(s); 1422 } 1423 1424 void 1425 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1426 uint32_t andmask, uint32_t ormask) 1427 { 1428 int s; 1429 uint32_t val; 1430 1431 s = splhigh(); 1432 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1433 RADEON_PLL_WR_EN); 1434 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1435 val = (val & andmask) | ormask; 1436 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1437 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1438 splx(s); 1439 } 1440 1441 int 1442 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1443 { 1444 uint32_t saved; 1445 1446 saved = GET32(sc, reg); 1447 PUT32(sc, reg, v); 1448 if (GET32(sc, reg) != v) { 1449 return -1; 1450 } 1451 PUT32(sc, reg, saved); 1452 return 0; 1453 } 1454 1455 uintmax_t 1456 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1457 uintmax_t defval) 1458 { 1459 prop_number_t pn; 1460 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1461 if (pn == NULL) { 1462 return defval; 1463 } 1464 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1465 return (prop_number_integer_value(pn)); 1466 } 1467 1468 int 1469 radeonfb_getclocks(struct radeonfb_softc *sc) 1470 { 1471 bus_addr_t ptr; 1472 int refclk = 0; 1473 int refdiv = 0; 1474 int minpll = 0; 1475 int maxpll = 0; 1476 1477 /* load initial property values if port/board provides them */ 1478 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1479 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1480 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1481 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1482 1483 PRINTPLL(RADEON_PPLL_REF_DIV); 1484 PRINTPLL(RADEON_PPLL_DIV_0); 1485 PRINTPLL(RADEON_PPLL_DIV_1); 1486 PRINTPLL(RADEON_PPLL_DIV_2); 1487 PRINTPLL(RADEON_PPLL_DIV_3); 1488 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1489 PRINTPLL(RADEON_P2PLL_REF_DIV); 1490 PRINTPLL(RADEON_P2PLL_DIV_0); 1491 1492 if (refclk && refdiv && minpll && maxpll) 1493 goto dontprobe; 1494 1495 if (!sc->sc_biossz) { 1496 /* no BIOS */ 1497 aprint_verbose("%s: No video BIOS, using default clocks\n", 1498 XNAME(sc)); 1499 if (IS_IGP(sc)) 1500 refclk = refclk ? refclk : 1432; 1501 else 1502 refclk = refclk ? refclk : 2700; 1503 refdiv = refdiv ? refdiv : 12; 1504 minpll = minpll ? minpll : 12500; 1505 /* XXX 1506 * Need to check if the firmware or something programmed a 1507 * higher value than this, and if so, bump it. 1508 * The RV280 in my iBook is unhappy if the PLL input is less 1509 * than 360MHz 1510 */ 1511 maxpll = maxpll ? maxpll : 40000/*35000*/; 1512 } else if (IS_ATOM(sc)) { 1513 /* ATOM BIOS */ 1514 ptr = GETBIOS16(sc, 0x48); 1515 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1516 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1517 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1518 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1519 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1520 /* 1521 * ATOM BIOS doesn't supply a reference divider, so we 1522 * have to probe for it. 1523 */ 1524 if (refdiv < 2) 1525 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1526 RADEON_PPLL_REF_DIV_MASK; 1527 /* 1528 * if probe is zero, just assume one that should work 1529 * for most parts 1530 */ 1531 if (refdiv < 2) 1532 refdiv = 12; 1533 1534 } else { 1535 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1536 /* Legacy BIOS */ 1537 ptr = GETBIOS16(sc, 0x48); 1538 ptr = GETBIOS16(sc, ptr + 0x30); 1539 if (IS_R300(sc)) { 1540 refdiv = refdiv ? refdiv : 1541 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1542 R300_PPLL_REF_DIV_ACC_SHIFT; 1543 } else { 1544 refdiv = refdiv ? refdiv : 1545 tmp & RADEON_PPLL_REF_DIV_MASK; 1546 } 1547 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1548 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1549 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1550 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1551 } 1552 1553 1554 dontprobe: 1555 sc->sc_refclk = refclk * 10; 1556 sc->sc_refdiv = refdiv; 1557 sc->sc_minpll = minpll * 10; 1558 sc->sc_maxpll = maxpll * 10; 1559 return 0; 1560 } 1561 1562 int 1563 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1564 uint32_t *postdivbit, uint32_t *feedbackdiv) 1565 { 1566 int i; 1567 uint32_t outfreq; 1568 int div; 1569 1570 DPRINTF(("dot clock: %u\n", dotclock)); 1571 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1572 outfreq = div * dotclock; 1573 if ((outfreq >= sc->sc_minpll) && 1574 (outfreq <= sc->sc_maxpll)) { 1575 DPRINTF(("outfreq: %u\n", outfreq)); 1576 *postdivbit = 1577 ((uint32_t)radeonfb_dividers[i].mask << 16); 1578 DPRINTF(("post divider: %d (mask %x)\n", div, 1579 *postdivbit)); 1580 break; 1581 } 1582 } 1583 1584 if (div == 0) 1585 return 1; 1586 1587 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1588 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1589 return 0; 1590 } 1591 1592 #if 0 1593 #ifdef RADEONFB_DEBUG 1594 static void 1595 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1596 { 1597 char asc[17]; 1598 unsigned ptr = (unsigned)buffer; 1599 char *start = (char *)(ptr & ~0xf); 1600 char *end = (char *)(ptr + size); 1601 1602 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1603 1604 if (pfx == NULL) { 1605 pfx = ""; 1606 } 1607 1608 while (start < end) { 1609 unsigned offset = (unsigned)start & 0xf; 1610 if (offset == 0) { 1611 printf("%s%x: ", pfx, (unsigned)start); 1612 } 1613 if (((unsigned)start < ptr) || 1614 ((unsigned)start >= (ptr + size))) { 1615 printf(" "); 1616 asc[offset] = ' '; 1617 } else { 1618 printf("%02x", *(unsigned char *)start); 1619 if ((*start >= ' ') && (*start <= '~')) { 1620 asc[offset] = *start; 1621 } else { 1622 asc[offset] = '.'; 1623 } 1624 } 1625 asc[offset + 1] = 0; 1626 if (offset % 2) { 1627 printf(" "); 1628 } 1629 if (offset == 15) { 1630 printf(" %s\n", asc); 1631 } 1632 start++; 1633 } 1634 } 1635 #endif 1636 #endif 1637 1638 int 1639 radeonfb_getconnectors(struct radeonfb_softc *sc) 1640 { 1641 int i; 1642 int found = 0; 1643 1644 for (i = 0; i < 2; i++) { 1645 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1646 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1647 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1648 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1649 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1650 } 1651 1652 /* 1653 * This logic is borrowed from Xorg's radeon driver. 1654 */ 1655 if (!sc->sc_biossz) 1656 goto nobios; 1657 1658 if (IS_ATOM(sc)) { 1659 /* not done yet */ 1660 } else { 1661 uint16_t ptr; 1662 int port = 0; 1663 1664 ptr = GETBIOS16(sc, 0x48); 1665 ptr = GETBIOS16(sc, ptr + 0x50); 1666 for (i = 1; i < 4; i++) { 1667 uint16_t entry; 1668 uint8_t conn, ddc, dac, tmds; 1669 1670 /* 1671 * Parse the connector table. From reading the code, 1672 * it appears to made up of 16-bit entries for each 1673 * connector. The 16-bits are defined as: 1674 * 1675 * bits 12-15 - connector type (0 == end of table) 1676 * bits 8-11 - DDC type 1677 * bits 5-7 - ??? 1678 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1679 * bits 1-3 - ??? 1680 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1681 */ 1682 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1683 break; 1684 entry = GETBIOS16(sc, ptr + i * 2); 1685 1686 conn = (entry >> 12) & 0xf; 1687 ddc = (entry >> 8) & 0xf; 1688 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1689 RADEON_DAC_PRIMARY; 1690 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1691 RADEON_TMDS_INT; 1692 1693 if (conn == RADEON_CONN_NONE) 1694 continue; /* no connector */ 1695 1696 if ((found > 0) && 1697 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1698 /* duplicate entry for same connector */ 1699 continue; 1700 } 1701 1702 /* internal DDC_DVI port gets priority */ 1703 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1704 port = 0; 1705 else 1706 port = 1; 1707 1708 sc->sc_ports[port].rp_ddc_type = 1709 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1710 sc->sc_ports[port].rp_dac_type = dac; 1711 sc->sc_ports[port].rp_conn_type = 1712 min(conn, RADEON_CONN_UNSUPPORTED) ; 1713 1714 sc->sc_ports[port].rp_tmds_type = tmds; 1715 1716 if ((conn != RADEON_CONN_DVI_I) && 1717 (conn != RADEON_CONN_DVI_D) && 1718 (tmds == RADEON_TMDS_INT)) 1719 sc->sc_ports[port].rp_tmds_type = 1720 RADEON_TMDS_UNKNOWN; 1721 sc->sc_ports[port].rp_number = i - 1; 1722 1723 found += (port + 1); 1724 } 1725 } 1726 1727 nobios: 1728 if (!found) { 1729 DPRINTF(("No connector info in BIOS!\n")); 1730 if IS_MOBILITY(sc) { 1731 /* default, port 0 = internal TMDS, port 1 = CRT */ 1732 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1733 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1734 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1735 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1736 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1737 sc->sc_ports[0].rp_number = 0; 1738 1739 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1740 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1741 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1742 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1743 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1744 sc->sc_ports[1].rp_number = 1; 1745 } else { 1746 /* default, port 0 = DVI, port 1 = CRT */ 1747 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1748 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1749 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1750 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1751 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1752 sc->sc_ports[0].rp_number = 1; 1753 1754 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1755 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1756 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1757 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1758 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1759 sc->sc_ports[1].rp_number = 0; 1760 } 1761 } 1762 1763 /* 1764 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1765 * these chips should use TVDAC for the VGA port. 1766 */ 1767 if (HAS_SDAC(sc)) { 1768 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1769 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1770 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1771 } else { 1772 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1773 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1774 } 1775 } else if (!HAS_CRTC2(sc)) { 1776 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1777 } 1778 1779 for (i = 0; i < 2; i++) { 1780 char edid[128]; 1781 uint8_t ddc; 1782 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1783 prop_data_t edid_data; 1784 1785 DPRINTF(("Port #%d:\n", i)); 1786 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1787 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1788 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1789 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1790 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1791 1792 sc->sc_ports[i].rp_edid_valid = 0; 1793 /* first look for static EDID data */ 1794 if ((edid_data = prop_dictionary_get(device_properties( 1795 sc->sc_dev), "EDID")) != NULL) { 1796 1797 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1798 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1799 if (edid_parse(edid, eip) == 0) { 1800 1801 sc->sc_ports[i].rp_edid_valid = 1; 1802 } 1803 } 1804 /* if we didn't find any we'll try to talk to the monitor */ 1805 if (sc->sc_ports[i].rp_edid_valid != 1) { 1806 1807 ddc = sc->sc_ports[i].rp_ddc_type; 1808 if (ddc != RADEON_DDC_NONE) { 1809 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1810 == 0) && (edid_parse(edid, eip) == 0)) { 1811 1812 sc->sc_ports[i].rp_edid_valid = 1; 1813 #ifdef RADEONFB_DEBUG 1814 edid_print(eip); 1815 #endif 1816 } 1817 } 1818 } 1819 } 1820 1821 return found; 1822 } 1823 1824 int 1825 radeonfb_gettmds(struct radeonfb_softc *sc) 1826 { 1827 int i; 1828 1829 if (!sc->sc_biossz) { 1830 goto nobios; 1831 } 1832 1833 if (IS_ATOM(sc)) { 1834 /* XXX: not done yet */ 1835 } else { 1836 uint16_t ptr; 1837 int n; 1838 1839 ptr = GETBIOS16(sc, 0x48); 1840 ptr = GETBIOS16(sc, ptr + 0x34); 1841 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1842 if (GETBIOS8(sc, ptr) == 3) { 1843 /* revision three table */ 1844 n = GETBIOS8(sc, ptr + 5) + 1; 1845 n = min(n, 4); 1846 1847 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1848 for (i = 0; i < n; i++) { 1849 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1850 ptr + i * 10 + 8); 1851 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1852 ptr + i * 10 + 0x10); 1853 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1854 sc->sc_tmds_pll[i].rtp_freq, 1855 sc->sc_tmds_pll[i].rtp_pll)); 1856 } 1857 return 0; 1858 } 1859 } 1860 1861 nobios: 1862 DPRINTF(("no suitable DFP table present\n")); 1863 for (i = 0; 1864 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1865 i++) { 1866 int j; 1867 1868 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1869 continue; 1870 1871 for (j = 0; j < 4; j++) { 1872 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1873 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1874 sc->sc_tmds_pll[j].rtp_freq, 1875 sc->sc_tmds_pll[j].rtp_pll)); 1876 } 1877 return 0; 1878 } 1879 1880 return -1; 1881 } 1882 1883 const struct videomode * 1884 radeonfb_modelookup(const char *name) 1885 { 1886 int i; 1887 1888 for (i = 0; i < videomode_count; i++) 1889 if (!strcmp(name, videomode_list[i].name)) 1890 return &videomode_list[i]; 1891 1892 return NULL; 1893 } 1894 1895 void 1896 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1897 { 1898 if (crtc) { 1899 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1900 RADEON_P2PLL_ATOMIC_UPDATE_R); 1901 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1902 } else { 1903 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1904 RADEON_PPLL_ATOMIC_UPDATE_R); 1905 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1906 } 1907 } 1908 1909 void 1910 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1911 { 1912 int i; 1913 1914 for (i = 10000; i; i--) { 1915 if (crtc) { 1916 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1917 RADEON_P2PLL_ATOMIC_UPDATE_R) 1918 break; 1919 } else { 1920 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1921 RADEON_PPLL_ATOMIC_UPDATE_R) 1922 break; 1923 } 1924 } 1925 } 1926 1927 void 1928 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1929 { 1930 uint32_t pbit = 0; 1931 uint32_t feed = 0; 1932 uint32_t data, refdiv, div0; 1933 1934 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1935 1936 if (crtc == 0) { 1937 1938 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1939 if (IS_R300(sc)) { 1940 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1941 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1942 } else { 1943 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1944 sc->sc_refdiv; 1945 } 1946 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1947 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1948 RADEON_PPLL_POST3_DIV_MASK); 1949 div0 |= pbit; 1950 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1951 1952 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1953 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1954 /* 1955 * nothing to do here, the PLL is already where we 1956 * want it 1957 */ 1958 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1959 ~RADEON_PLL_DIV_SEL); 1960 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1961 return; 1962 } 1963 1964 /* alright, we do need to reprogram stuff */ 1965 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1966 RADEON_VCLK_SRC_SEL_CPUCLK, 1967 ~RADEON_VCLK_SRC_SEL_MASK); 1968 1969 /* put vclk into reset, use atomic updates */ 1970 SETPLL(sc, RADEON_PPLL_CNTL, 1971 RADEON_PPLL_REFCLK_SEL | 1972 RADEON_PPLL_FBCLK_SEL | 1973 RADEON_PPLL_RESET | 1974 RADEON_PPLL_ATOMIC_UPDATE_EN | 1975 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1976 1977 /* select clock 0 */ 1978 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1979 ~RADEON_PLL_DIV_SEL); 1980 1981 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1982 1983 /* xf86-video-radeon does this, not sure why */ 1984 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1985 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1986 1987 /* use the atomic update */ 1988 radeonfb_pllwriteupdate(sc, crtc); 1989 1990 /* and wait for it to complete */ 1991 radeonfb_pllwaitatomicread(sc, crtc); 1992 1993 /* program HTOTAL (why?) */ 1994 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1995 1996 /* drop reset */ 1997 CLRPLL(sc, RADEON_PPLL_CNTL, 1998 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1999 RADEON_PPLL_ATOMIC_UPDATE_EN | 2000 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2001 2002 PRINTPLL(RADEON_PPLL_CNTL); 2003 PRINTPLL(RADEON_PPLL_REF_DIV); 2004 PRINTPLL(RADEON_PPLL_DIV_3); 2005 2006 /* give clock time to lock */ 2007 delay(50000); 2008 2009 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2010 RADEON_VCLK_SRC_SEL_PPLLCLK, 2011 ~RADEON_VCLK_SRC_SEL_MASK); 2012 2013 } else { 2014 2015 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2016 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2017 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2018 2019 /* put vclk into reset, use atomic updates */ 2020 SETPLL(sc, RADEON_P2PLL_CNTL, 2021 RADEON_P2PLL_RESET | 2022 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2023 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2024 2025 /* program reference divider */ 2026 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2027 ~RADEON_P2PLL_REF_DIV_MASK); 2028 2029 /* program feedback and post dividers */ 2030 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2031 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2032 RADEON_P2PLL_POST0_DIV_MASK); 2033 data |= pbit; 2034 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2035 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2036 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2037 2038 PRINTPLL(RADEON_P2PLL_REF_DIV); 2039 PRINTPLL(RADEON_P2PLL_DIV_0); 2040 2041 /* use the atomic update */ 2042 radeonfb_pllwriteupdate(sc, crtc); 2043 2044 /* and wait for it to complete */ 2045 radeonfb_pllwaitatomicread(sc, crtc); 2046 2047 /* program HTOTAL (why?) */ 2048 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2049 2050 /* drop reset */ 2051 CLRPLL(sc, RADEON_P2PLL_CNTL, 2052 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2053 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2054 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2055 2056 /* allow time for clock to lock */ 2057 delay(50000); 2058 2059 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2060 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2061 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2062 } 2063 PRINTREG(RADEON_CRTC_MORE_CNTL); 2064 } 2065 2066 void 2067 radeonfb_modeswitch(struct radeonfb_display *dp) 2068 { 2069 struct radeonfb_softc *sc = dp->rd_softc; 2070 int i; 2071 2072 /* blank the display while we switch modes */ 2073 radeonfb_blank(dp, 1); 2074 2075 #if 0 2076 SET32(sc, RADEON_CRTC_EXT_CNTL, 2077 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2078 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2079 #endif 2080 2081 /* these registers might get in the way... */ 2082 PUT32(sc, RADEON_OVR_CLR, 0); 2083 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2084 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2085 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2086 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2087 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2088 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2089 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2090 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2091 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2092 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2093 2094 for (i = 0; i < dp->rd_ncrtcs; i++) 2095 radeonfb_setcrtc(dp, i); 2096 2097 /* activate the display */ 2098 radeonfb_blank(dp, 0); 2099 } 2100 2101 void 2102 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2103 { 2104 int crtc; 2105 struct videomode *mode; 2106 struct radeonfb_softc *sc; 2107 struct radeonfb_crtc *cp; 2108 uint32_t v; 2109 uint32_t gencntl; 2110 uint32_t htotaldisp; 2111 uint32_t hsyncstrt; 2112 uint32_t vtotaldisp; 2113 uint32_t vsyncstrt; 2114 uint32_t fphsyncstrt; 2115 uint32_t fpvsyncstrt; 2116 uint32_t fphtotaldisp; 2117 uint32_t fpvtotaldisp; 2118 uint32_t pitch; 2119 2120 sc = dp->rd_softc; 2121 cp = &dp->rd_crtcs[index]; 2122 crtc = cp->rc_number; 2123 mode = &cp->rc_videomode; 2124 2125 #if 1 2126 pitch = dp->rd_stride / dp->rd_bpp; 2127 #else 2128 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2129 (sc->sc_maxbpp * 8)); 2130 #endif 2131 switch (crtc) { 2132 case 0: 2133 gencntl = RADEON_CRTC_GEN_CNTL; 2134 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2135 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2136 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2137 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2138 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2139 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2140 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2141 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2142 break; 2143 case 1: 2144 gencntl = RADEON_CRTC2_GEN_CNTL; 2145 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2146 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2147 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2148 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2149 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2150 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2151 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2152 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2153 break; 2154 default: 2155 panic("Bad CRTC!"); 2156 break; 2157 } 2158 2159 /* 2160 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2161 */ 2162 /* only bother with 32bpp and 8bpp */ 2163 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2164 2165 if (crtc == 1) { 2166 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2167 } else { 2168 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2169 } 2170 2171 if (mode->flags & VID_DBLSCAN) 2172 v |= RADEON_CRTC2_DBL_SCAN_EN; 2173 2174 if (mode->flags & VID_INTERLACE) 2175 v |= RADEON_CRTC2_INTERLACE_EN; 2176 2177 if (mode->flags & VID_CSYNC) { 2178 v |= RADEON_CRTC2_CSYNC_EN; 2179 if (crtc == 1) 2180 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2181 } 2182 2183 PUT32(sc, gencntl, v); 2184 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2185 2186 /* 2187 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2188 */ 2189 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2190 if (crtc == 0) { 2191 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2192 RADEON_CRTC_DISPLAY_DIS); 2193 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2194 if (mode->flags & VID_CSYNC) 2195 v |= RADEON_CRTC_VSYNC_TRISTAT; 2196 } 2197 /* unconditional turn on CRT, in case first CRTC is DFP */ 2198 v |= RADEON_CRTC_CRT_ON; 2199 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2200 PRINTREG(RADEON_CRTC_EXT_CNTL); 2201 2202 /* 2203 * H_TOTAL_DISP 2204 */ 2205 v = ((mode->hdisplay / 8) - 1) << 16; 2206 v |= (mode->htotal / 8) - 1; 2207 PUT32(sc, htotaldisp, v); 2208 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2209 PUT32(sc, fphtotaldisp, v); 2210 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2211 2212 /* 2213 * H_SYNC_STRT_WID 2214 */ 2215 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2216 v |= mode->hsync_start; 2217 if (mode->flags & VID_NHSYNC) 2218 v |= RADEON_CRTC_H_SYNC_POL; 2219 PUT32(sc, hsyncstrt, v); 2220 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2221 PUT32(sc, fphsyncstrt, v); 2222 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2223 2224 /* 2225 * V_TOTAL_DISP 2226 */ 2227 v = ((mode->vdisplay - 1) << 16); 2228 v |= (mode->vtotal - 1); 2229 PUT32(sc, vtotaldisp, v); 2230 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2231 PUT32(sc, fpvtotaldisp, v); 2232 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2233 2234 /* 2235 * V_SYNC_STRT_WID 2236 */ 2237 v = ((mode->vsync_end - mode->vsync_start) << 16); 2238 v |= (mode->vsync_start - 1); 2239 if (mode->flags & VID_NVSYNC) 2240 v |= RADEON_CRTC_V_SYNC_POL; 2241 PUT32(sc, vsyncstrt, v); 2242 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2243 PUT32(sc, fpvsyncstrt, v); 2244 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2245 2246 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2247 2248 switch (crtc) { 2249 case 0: 2250 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2251 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2252 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2253 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2254 2255 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2256 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2257 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2258 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2259 PRINTREG(RADEON_CRTC_EXT_CNTL); 2260 PRINTREG(RADEON_CRTC_GEN_CNTL); 2261 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2262 break; 2263 2264 case 1: 2265 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2266 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2267 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2268 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2269 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2270 RADEON_CRTC2_VSYNC_DIS | 2271 RADEON_CRTC2_HSYNC_DIS | 2272 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2273 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2274 break; 2275 } 2276 } 2277 2278 int 2279 radeonfb_isblank(struct radeonfb_display *dp) 2280 { 2281 uint32_t reg, mask; 2282 2283 if(!dp->rd_softc->sc_mapped) 2284 return 1; 2285 2286 if (dp->rd_crtcs[0].rc_number) { 2287 reg = RADEON_CRTC2_GEN_CNTL; 2288 mask = RADEON_CRTC2_DISP_DIS; 2289 } else { 2290 reg = RADEON_CRTC_EXT_CNTL; 2291 mask = RADEON_CRTC_DISPLAY_DIS; 2292 } 2293 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2294 } 2295 2296 void 2297 radeonfb_blank(struct radeonfb_display *dp, int blank) 2298 { 2299 struct radeonfb_softc *sc = dp->rd_softc; 2300 uint32_t reg, mask; 2301 uint32_t fpreg, fpval; 2302 int i; 2303 2304 if (!sc->sc_mapped) 2305 return; 2306 2307 for (i = 0; i < dp->rd_ncrtcs; i++) { 2308 2309 if (dp->rd_crtcs[i].rc_number) { 2310 reg = RADEON_CRTC2_GEN_CNTL; 2311 mask = RADEON_CRTC2_DISP_DIS; 2312 fpreg = RADEON_FP2_GEN_CNTL; 2313 fpval = RADEON_FP2_ON; 2314 } else { 2315 reg = RADEON_CRTC_EXT_CNTL; 2316 mask = RADEON_CRTC_DISPLAY_DIS; 2317 fpreg = RADEON_FP_GEN_CNTL; 2318 fpval = RADEON_FP_FPON; 2319 } 2320 2321 if (blank) { 2322 SET32(sc, reg, mask); 2323 CLR32(sc, fpreg, fpval); 2324 } else { 2325 CLR32(sc, reg, mask); 2326 SET32(sc, fpreg, fpval); 2327 } 2328 } 2329 PRINTREG(RADEON_FP_GEN_CNTL); 2330 PRINTREG(RADEON_FP2_GEN_CNTL); 2331 } 2332 2333 void 2334 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2335 long *defattr) 2336 { 2337 struct radeonfb_display *dp = cookie; 2338 struct rasops_info *ri = &scr->scr_ri; 2339 2340 /* initialize font subsystem */ 2341 wsfont_init(); 2342 2343 DPRINTF(("init screen called, existing %d\n", existing)); 2344 2345 ri->ri_depth = dp->rd_bpp; 2346 ri->ri_width = dp->rd_virtx; 2347 ri->ri_height = dp->rd_virty; 2348 ri->ri_stride = dp->rd_stride; 2349 ri->ri_flg = RI_CENTER; 2350 switch (ri->ri_depth) { 2351 case 8: 2352 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2353 break; 2354 case 32: 2355 ri->ri_flg |= RI_ENABLE_ALPHA; 2356 /* we run radeons in RGB even on SPARC hardware */ 2357 ri->ri_rnum = 8; 2358 ri->ri_gnum = 8; 2359 ri->ri_bnum = 8; 2360 ri->ri_rpos = 16; 2361 ri->ri_gpos = 8; 2362 ri->ri_bpos = 0; 2363 break; 2364 } 2365 2366 ri->ri_bits = (void *)dp->rd_fbptr; 2367 2368 #ifdef VCONS_DRAW_INTR 2369 scr->scr_flags |= VCONS_DONT_READ; 2370 #endif 2371 2372 if (existing) { 2373 ri->ri_flg |= RI_CLEAR; 2374 2375 /* start a modeswitch now */ 2376 radeonfb_modeswitch(dp); 2377 } 2378 2379 /* 2380 * XXX: font selection should be based on properties, with some 2381 * normal/reasonable default. 2382 */ 2383 2384 /* initialize and look for an initial font */ 2385 rasops_init(ri, 0, 0); 2386 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2387 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2388 2389 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2390 dp->rd_virtx / ri->ri_font->fontwidth); 2391 2392 /* enable acceleration */ 2393 dp->rd_putchar = ri->ri_ops.putchar; 2394 ri->ri_ops.copyrows = radeonfb_copyrows; 2395 ri->ri_ops.copycols = radeonfb_copycols; 2396 ri->ri_ops.eraserows = radeonfb_eraserows; 2397 ri->ri_ops.erasecols = radeonfb_erasecols; 2398 /* pick a putchar method based on font and Radeon model */ 2399 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2400 /* got a bitmap font */ 2401 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2402 if (IS_R300(dp->rd_softc)) { 2403 /* 2404 * radeonfb_putchar() doesn't work right on some R3xx 2405 * so we use software drawing here, the wrapper just 2406 * makes sure the engine is idle before scribbling 2407 * into vram 2408 */ 2409 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2410 } else 2411 #endif 2412 ri->ri_ops.putchar = radeonfb_putchar; 2413 } else { 2414 /* got an alpha font */ 2415 switch(ri->ri_depth) { 2416 case 32: 2417 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2418 break; 2419 case 8: 2420 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2421 break; 2422 default: 2423 /* XXX this should never happen */ 2424 panic("%s: depth is not 8 or 32 but we got an" \ 2425 " alpha font?!", __func__); 2426 } 2427 } 2428 ri->ri_ops.cursor = radeonfb_cursor; 2429 } 2430 2431 void 2432 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2433 { 2434 uint32_t gen, ext, gen2 = 0; 2435 uint32_t agploc, aperbase, apersize, mcfbloc; 2436 2437 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2438 /* XXX */ 2439 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2440 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2441 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2442 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2443 2444 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2445 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2446 #if 0 2447 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2448 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2449 #endif 2450 2451 if (HAS_CRTC2(sc)) { 2452 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2453 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2454 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2455 } 2456 2457 delay(100000); 2458 2459 mcfbloc = (aperbase >> 16) | 2460 ((aperbase + (apersize - 1)) & 0xffff0000); 2461 2462 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2463 sc->sc_memsz = apersize; 2464 2465 if (((agploc & 0xffff) << 16) != 2466 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2467 agploc = mcfbloc & 0xffff0000U; 2468 agploc |= ((agploc + 0x10000) >> 16); 2469 } 2470 2471 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2472 2473 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2474 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2475 2476 DPRINTF(("aperbase = %u\n", aperbase)); 2477 PRINTREG(RADEON_MC_FB_LOCATION); 2478 PRINTREG(RADEON_MC_AGP_LOCATION); 2479 2480 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2481 2482 if (HAS_CRTC2(sc)) 2483 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2484 2485 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2486 2487 #if 0 2488 /* XXX: what is this AGP garbage? :-) */ 2489 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2490 #endif 2491 2492 delay(100000); 2493 2494 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2495 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2496 2497 if (HAS_CRTC2(sc)) 2498 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2499 } 2500 2501 void 2502 radeonfb_init_misc(struct radeonfb_softc *sc) 2503 { 2504 PUT32(sc, RADEON_BUS_CNTL, 2505 RADEON_BUS_MASTER_DIS | 2506 RADEON_BUS_PREFETCH_MODE_ACT | 2507 RADEON_BUS_PCI_READ_RETRY_EN | 2508 RADEON_BUS_PCI_WRT_RETRY_EN | 2509 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2510 RADEON_BUS_MSTR_RD_MULT | 2511 RADEON_BUS_MSTR_RD_LINE | 2512 RADEON_BUS_RD_DISCARD_EN | 2513 RADEON_BUS_MSTR_DISCONNECT_EN | 2514 RADEON_BUS_READ_BURST); 2515 2516 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2517 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2518 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2519 PUT32(sc, RADEON_RBBM_CNTL, 2520 (3 << RADEON_RB_SETTLE_SHIFT) | 2521 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2522 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2523 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2524 2525 /* XXX: figure out what these mean! */ 2526 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2527 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2528 #if 0 2529 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2530 #endif 2531 2532 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2533 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2534 } 2535 2536 /* 2537 * This loads a linear color map for true color. 2538 */ 2539 void 2540 radeonfb_init_palette(struct radeonfb_display *dp) 2541 { 2542 struct radeonfb_softc *sc = dp->rd_softc; 2543 int i, cc; 2544 uint32_t vclk; 2545 int crtc; 2546 2547 #define DAC_WIDTH ((1 << 10) - 1) 2548 #define CLUT_WIDTH ((1 << 8) - 1) 2549 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2550 2551 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2552 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2553 2554 /* initialize the palette for every CRTC used by this display */ 2555 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2556 crtc = dp->rd_crtcs[cc].rc_number; 2557 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2558 2559 if (crtc) 2560 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2561 else 2562 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2563 2564 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2565 2566 if (dp->rd_bpp == 8) { 2567 2568 /* R3G3B2 palette */ 2569 int j = 0; 2570 uint32_t tmp, r, g, b; 2571 2572 for (i = 0; i <= CLUT_WIDTH; ++i) { 2573 tmp = i & 0xe0; 2574 /* 2575 * replicate bits so 0xe0 maps to a red value of 0xff 2576 * in order to make white look actually white 2577 */ 2578 tmp |= (tmp >> 3) | (tmp >> 6); 2579 r = tmp; 2580 2581 tmp = (i & 0x1c) << 3; 2582 tmp |= (tmp >> 3) | (tmp >> 6); 2583 g = tmp; 2584 2585 tmp = (i & 0x03) << 6; 2586 tmp |= tmp >> 2; 2587 tmp |= tmp >> 4; 2588 b = tmp; 2589 2590 PUT32(sc, RADEON_PALETTE_30_DATA, 2591 (r << 22) | 2592 (g << 12) | 2593 (b << 2)); 2594 j += 3; 2595 } 2596 } else { 2597 /* linear ramp */ 2598 for (i = 0; i <= CLUT_WIDTH; ++i) { 2599 PUT32(sc, RADEON_PALETTE_30_DATA, 2600 (CLUT_COLOR(i) << 10) | 2601 (CLUT_COLOR(i) << 20) | 2602 (CLUT_COLOR(i))); 2603 } 2604 } 2605 } 2606 2607 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2608 PRINTREG(RADEON_DAC_CNTL2); 2609 2610 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2611 } 2612 2613 /* 2614 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2615 */ 2616 void 2617 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2618 { 2619 uint32_t tmp, save; 2620 2621 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2622 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2623 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2624 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2625 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2626 } 2627 2628 /* 2629 * Acceleration entry points. 2630 */ 2631 2632 /* this one draws characters using bitmap fonts */ 2633 static void 2634 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2635 { 2636 struct rasops_info *ri = cookie; 2637 struct vcons_screen *scr = ri->ri_hw; 2638 struct radeonfb_display *dp = scr->scr_cookie; 2639 struct radeonfb_softc *sc = dp->rd_softc; 2640 struct wsdisplay_font *font = PICK_FONT(ri, c); 2641 uint32_t w, h; 2642 int xd, yd, offset, i; 2643 uint32_t bg, fg, gmc; 2644 uint32_t reg; 2645 uint8_t *data8; 2646 uint16_t *data16; 2647 void *data; 2648 2649 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2650 return; 2651 2652 if (!CHAR_IN_FONT(c, font)) 2653 return; 2654 2655 w = font->fontwidth; 2656 h = font->fontheight; 2657 2658 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2659 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2660 2661 xd = ri->ri_xorigin + col * w; 2662 yd = ri->ri_yorigin + row * h; 2663 2664 if (c == 0x20) { 2665 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2666 return; 2667 } 2668 data = WSFONT_GLYPH(c, font); 2669 2670 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2671 2672 radeonfb_wait_fifo(sc, 9); 2673 2674 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2675 RADEON_GMC_BRUSH_NONE | 2676 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2677 RADEON_GMC_DST_CLIPPING | 2678 RADEON_ROP3_S | 2679 RADEON_DP_SRC_SOURCE_HOST_DATA | 2680 RADEON_GMC_CLR_CMP_CNTL_DIS | 2681 RADEON_GMC_WR_MSK_DIS | 2682 gmc); 2683 2684 PUT32(sc, RADEON_SC_LEFT, xd); 2685 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2686 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2687 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2688 PUT32(sc, RADEON_DP_CNTL, 2689 RADEON_DST_X_LEFT_TO_RIGHT | 2690 RADEON_DST_Y_TOP_TO_BOTTOM); 2691 2692 PUT32(sc, RADEON_SRC_X_Y, 0); 2693 offset = 32 - (font->stride << 3); 2694 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2695 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2696 2697 radeonfb_wait_fifo(sc, h); 2698 switch (font->stride) { 2699 case 1: { 2700 data8 = data; 2701 for (i = 0; i < h; i++) { 2702 reg = *data8; 2703 #if BYTE_ORDER == LITTLE_ENDIAN 2704 reg = reg << 24; 2705 #endif 2706 bus_space_write_stream_4(sc->sc_regt, 2707 sc->sc_regh, RADEON_HOST_DATA0, reg); 2708 data8++; 2709 } 2710 break; 2711 } 2712 case 2: { 2713 data16 = data; 2714 for (i = 0; i < h; i++) { 2715 reg = *data16; 2716 #if BYTE_ORDER == LITTLE_ENDIAN 2717 reg = reg << 16; 2718 #endif 2719 bus_space_write_stream_4(sc->sc_regt, 2720 sc->sc_regh, RADEON_HOST_DATA0, reg); 2721 data16++; 2722 } 2723 break; 2724 } 2725 } 2726 if (attr & 1) 2727 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2728 } 2729 2730 /* ... while this one is for anti-aliased ones */ 2731 static void 2732 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2733 { 2734 struct rasops_info *ri = cookie; 2735 struct vcons_screen *scr = ri->ri_hw; 2736 struct radeonfb_display *dp = scr->scr_cookie; 2737 struct radeonfb_softc *sc = dp->rd_softc; 2738 struct wsdisplay_font *font = PICK_FONT(ri, c); 2739 uint32_t bg, fg, gmc; 2740 uint8_t *data; 2741 int w, h, xd, yd; 2742 int i, r, g, b, aval; 2743 int rf, gf, bf, rb, gb, bb; 2744 uint32_t pixel; 2745 int rv; 2746 2747 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2748 return; 2749 2750 if (!CHAR_IN_FONT(c, font)) 2751 return; 2752 2753 w = font->fontwidth; 2754 h = font->fontheight; 2755 2756 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2757 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2758 2759 xd = ri->ri_xorigin + col * w; 2760 yd = ri->ri_yorigin + row * h; 2761 2762 if (c == 0x20) { 2763 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2764 if (attr & 1) 2765 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2766 return; 2767 } 2768 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2769 if (rv == GC_OK) 2770 return; 2771 2772 data = WSFONT_GLYPH(c, font); 2773 2774 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2775 2776 radeonfb_wait_fifo(sc, 5); 2777 2778 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2779 RADEON_GMC_BRUSH_NONE | 2780 RADEON_GMC_SRC_DATATYPE_COLOR | 2781 RADEON_ROP3_S | 2782 RADEON_DP_SRC_SOURCE_HOST_DATA | 2783 RADEON_GMC_CLR_CMP_CNTL_DIS | 2784 RADEON_GMC_WR_MSK_DIS | 2785 gmc); 2786 2787 PUT32(sc, RADEON_DP_CNTL, 2788 RADEON_DST_X_LEFT_TO_RIGHT | 2789 RADEON_DST_Y_TOP_TO_BOTTOM); 2790 2791 PUT32(sc, RADEON_SRC_X_Y, 0); 2792 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2793 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2794 2795 rf = (fg >> 16) & 0xff; 2796 rb = (bg >> 16) & 0xff; 2797 gf = (fg >> 8) & 0xff; 2798 gb = (bg >> 8) & 0xff; 2799 bf = fg & 0xff; 2800 bb = bg & 0xff; 2801 2802 /* 2803 * I doubt we can upload data faster than even the slowest Radeon 2804 * could process them, especially when doing the alpha blending stuff 2805 * along the way, so just make sure there's some room in the FIFO and 2806 * then hammer away 2807 * As it turns out we can, so make periodic stops to let the FIFO 2808 * drain. 2809 */ 2810 radeonfb_wait_fifo(sc, 20); 2811 for (i = 0; i < ri->ri_fontscale; i++) { 2812 aval = *data; 2813 data++; 2814 if (aval == 0) { 2815 pixel = bg; 2816 } else if (aval == 255) { 2817 pixel = fg; 2818 } else { 2819 r = aval * rf + (255 - aval) * rb; 2820 g = aval * gf + (255 - aval) * gb; 2821 b = aval * bf + (255 - aval) * bb; 2822 pixel = (r & 0xff00) << 8 | 2823 (g & 0xff00) | 2824 (b & 0xff00) >> 8; 2825 } 2826 if (i & 16) 2827 radeonfb_wait_fifo(sc, 20); 2828 PUT32(sc, RADEON_HOST_DATA0, pixel); 2829 } 2830 if (rv == GC_ADD) { 2831 glyphcache_add(&dp->rd_gc, c, xd, yd); 2832 } else 2833 if (attr & 1) 2834 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2835 2836 } 2837 2838 static void 2839 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2840 { 2841 struct rasops_info *ri = cookie; 2842 struct vcons_screen *scr = ri->ri_hw; 2843 struct radeonfb_display *dp = scr->scr_cookie; 2844 struct radeonfb_softc *sc = dp->rd_softc; 2845 struct wsdisplay_font *font = PICK_FONT(ri, c); 2846 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2847 int i, x, y, wi, he, r, g, b, aval; 2848 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2849 uint8_t *data8; 2850 int rv, cnt; 2851 2852 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2853 return; 2854 2855 if (!CHAR_IN_FONT(c, font)) 2856 return; 2857 2858 wi = font->fontwidth; 2859 he = font->fontheight; 2860 2861 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2862 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2863 2864 x = ri->ri_xorigin + col * wi; 2865 y = ri->ri_yorigin + row * he; 2866 2867 if (c == 0x20) { 2868 radeonfb_rectfill(dp, x, y, wi, he, bg); 2869 if (attr & 1) 2870 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2871 return; 2872 } 2873 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2874 if (rv == GC_OK) 2875 return; 2876 2877 data8 = WSFONT_GLYPH(c, font); 2878 2879 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2880 2881 radeonfb_wait_fifo(sc, 5); 2882 2883 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2884 RADEON_GMC_BRUSH_NONE | 2885 RADEON_GMC_SRC_DATATYPE_COLOR | 2886 RADEON_ROP3_S | 2887 RADEON_DP_SRC_SOURCE_HOST_DATA | 2888 RADEON_GMC_CLR_CMP_CNTL_DIS | 2889 RADEON_GMC_WR_MSK_DIS | 2890 gmc); 2891 2892 PUT32(sc, RADEON_DP_CNTL, 2893 RADEON_DST_X_LEFT_TO_RIGHT | 2894 RADEON_DST_Y_TOP_TO_BOTTOM); 2895 2896 PUT32(sc, RADEON_SRC_X_Y, 0); 2897 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2898 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2899 2900 /* 2901 * we need the RGB colours here, so get offsets into rasops_cmap 2902 */ 2903 fgo = ((attr >> 24) & 0xf) * 3; 2904 bgo = ((attr >> 16) & 0xf) * 3; 2905 2906 r0 = rasops_cmap[bgo]; 2907 r1 = rasops_cmap[fgo]; 2908 g0 = rasops_cmap[bgo + 1]; 2909 g1 = rasops_cmap[fgo + 1]; 2910 b0 = rasops_cmap[bgo + 2]; 2911 b1 = rasops_cmap[fgo + 2]; 2912 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2913 bg8 = R3G3B2(r0, g0, b0); 2914 fg8 = R3G3B2(r1, g1, b1); 2915 2916 radeonfb_wait_fifo(sc, 20); 2917 cnt = 0; 2918 for (i = 0; i < ri->ri_fontscale; i++) { 2919 aval = *data8; 2920 if (aval == 0) { 2921 pixel = bg8; 2922 } else if (aval == 255) { 2923 pixel = fg8; 2924 } else { 2925 r = aval * r1 + (255 - aval) * r0; 2926 g = aval * g1 + (255 - aval) * g0; 2927 b = aval * b1 + (255 - aval) * b0; 2928 pixel = ((r & 0xe000) >> 8) | 2929 ((g & 0xe000) >> 11) | 2930 ((b & 0xc000) >> 14); 2931 } 2932 latch |= pixel << (8 * (i & 3)); 2933 /* write in 32bit chunks */ 2934 if ((i & 3) == 3) { 2935 PUT32(sc, RADEON_HOST_DATA0, latch); 2936 /* 2937 * not strictly necessary, old data should be shifted 2938 * out 2939 */ 2940 latch = 0; 2941 cnt++; 2942 if (cnt > 16) { 2943 cnt = 0; 2944 radeonfb_wait_fifo(sc, 20); 2945 } 2946 } 2947 data8++; 2948 } 2949 /* if we have pixels left in latch write them out */ 2950 if ((i & 3) != 0) { 2951 /* 2952 * radeon is weird - apparently leftover pixels are written 2953 * from the middle, not from the left as everything else 2954 */ 2955 PUT32(sc, RADEON_HOST_DATA0, latch); 2956 } 2957 2958 if (rv == GC_ADD) { 2959 glyphcache_add(&dp->rd_gc, c, x, y); 2960 } else 2961 if (attr & 1) 2962 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2963 2964 } 2965 2966 /* 2967 * wrapper for software character drawing 2968 * just sync the engine and call rasops*_putchar() 2969 */ 2970 2971 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2972 static void 2973 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2974 { 2975 struct rasops_info *ri = cookie; 2976 struct vcons_screen *scr = ri->ri_hw; 2977 struct radeonfb_display *dp = scr->scr_cookie; 2978 2979 radeonfb_engine_idle(dp->rd_softc); 2980 dp->rd_putchar(ri, row, col, c, attr); 2981 } 2982 #endif 2983 2984 static void 2985 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2986 { 2987 struct rasops_info *ri = cookie; 2988 struct vcons_screen *scr = ri->ri_hw; 2989 struct radeonfb_display *dp = scr->scr_cookie; 2990 uint32_t x, y, w, h, fg, bg, ul; 2991 2992 /* XXX: check for full emulation mode? */ 2993 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2994 x = ri->ri_xorigin; 2995 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2996 w = ri->ri_emuwidth; 2997 h = ri->ri_font->fontheight * nrows; 2998 2999 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3000 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3001 } 3002 } 3003 3004 static void 3005 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3006 { 3007 struct rasops_info *ri = cookie; 3008 struct vcons_screen *scr = ri->ri_hw; 3009 struct radeonfb_display *dp = scr->scr_cookie; 3010 uint32_t x, ys, yd, w, h; 3011 3012 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3013 x = ri->ri_xorigin; 3014 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3015 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3016 w = ri->ri_emuwidth; 3017 h = ri->ri_font->fontheight * nrows; 3018 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3019 RADEON_ROP3_S); 3020 } 3021 } 3022 3023 static void 3024 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3025 { 3026 struct rasops_info *ri = cookie; 3027 struct vcons_screen *scr = ri->ri_hw; 3028 struct radeonfb_display *dp = scr->scr_cookie; 3029 uint32_t xs, xd, y, w, h; 3030 3031 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3032 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3033 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3034 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3035 w = ri->ri_font->fontwidth * ncols; 3036 h = ri->ri_font->fontheight; 3037 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3038 RADEON_ROP3_S); 3039 } 3040 } 3041 3042 static void 3043 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3044 long fillattr) 3045 { 3046 struct rasops_info *ri = cookie; 3047 struct vcons_screen *scr = ri->ri_hw; 3048 struct radeonfb_display *dp = scr->scr_cookie; 3049 uint32_t x, y, w, h, fg, bg, ul; 3050 3051 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3052 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3053 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3054 w = ri->ri_font->fontwidth * ncols; 3055 h = ri->ri_font->fontheight; 3056 3057 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3058 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3059 } 3060 } 3061 3062 static void 3063 radeonfb_cursor(void *cookie, int on, int row, int col) 3064 { 3065 struct rasops_info *ri = cookie; 3066 struct vcons_screen *scr = ri->ri_hw; 3067 struct radeonfb_display *dp = scr->scr_cookie; 3068 int x, y, wi, he; 3069 3070 wi = ri->ri_font->fontwidth; 3071 he = ri->ri_font->fontheight; 3072 3073 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3074 x = ri->ri_ccol * wi + ri->ri_xorigin; 3075 y = ri->ri_crow * he + ri->ri_yorigin; 3076 /* first turn off the old cursor */ 3077 if (ri->ri_flg & RI_CURSOR) { 3078 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3079 RADEON_ROP3_Dn); 3080 ri->ri_flg &= ~RI_CURSOR; 3081 } 3082 ri->ri_crow = row; 3083 ri->ri_ccol = col; 3084 /* then (possibly) turn on the new one */ 3085 if (on) { 3086 x = ri->ri_ccol * wi + ri->ri_xorigin; 3087 y = ri->ri_crow * he + ri->ri_yorigin; 3088 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3089 RADEON_ROP3_Dn); 3090 ri->ri_flg |= RI_CURSOR; 3091 } 3092 } else { 3093 scr->scr_ri.ri_crow = row; 3094 scr->scr_ri.ri_ccol = col; 3095 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3096 } 3097 } 3098 3099 /* 3100 * Underlying acceleration support. 3101 */ 3102 3103 static void 3104 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3105 int width, int height, uint32_t color) 3106 { 3107 struct radeonfb_softc *sc = dp->rd_softc; 3108 uint32_t gmc; 3109 3110 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3111 3112 radeonfb_wait_fifo(sc, 6); 3113 3114 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3115 RADEON_GMC_BRUSH_SOLID_COLOR | 3116 RADEON_GMC_SRC_DATATYPE_COLOR | 3117 RADEON_GMC_CLR_CMP_CNTL_DIS | 3118 RADEON_ROP3_P | gmc); 3119 3120 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3121 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3122 PUT32(sc, RADEON_DP_CNTL, 3123 RADEON_DST_X_LEFT_TO_RIGHT | 3124 RADEON_DST_Y_TOP_TO_BOTTOM); 3125 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3126 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3127 3128 } 3129 3130 static void 3131 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3132 int width, int height, long attr) 3133 { 3134 struct radeonfb_display *dp = cookie; 3135 3136 radeonfb_rectfill(dp, dstx, dsty, width, height, 3137 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3138 } 3139 3140 static void 3141 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3142 int dstx, int dsty, int width, int height, int rop) 3143 { 3144 struct radeonfb_display *dp = cookie; 3145 struct radeonfb_softc *sc = dp->rd_softc; 3146 uint32_t gmc; 3147 uint32_t dir; 3148 3149 if (dsty < srcy) { 3150 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3151 } else { 3152 srcy += height - 1; 3153 dsty += height - 1; 3154 dir = 0; 3155 } 3156 if (dstx < srcx) { 3157 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3158 } else { 3159 srcx += width - 1; 3160 dstx += width - 1; 3161 } 3162 3163 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3164 3165 radeonfb_wait_fifo(sc, 6); 3166 3167 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3168 RADEON_GMC_BRUSH_SOLID_COLOR | 3169 RADEON_GMC_SRC_DATATYPE_COLOR | 3170 RADEON_GMC_CLR_CMP_CNTL_DIS | 3171 RADEON_DP_SRC_SOURCE_MEMORY | 3172 rop | gmc); 3173 3174 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3175 PUT32(sc, RADEON_DP_CNTL, dir); 3176 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3177 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3178 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3179 } 3180 3181 static void 3182 radeonfb_engine_idle(struct radeonfb_softc *sc) 3183 { 3184 3185 radeonfb_wait_fifo(sc, 64); 3186 while ((GET32(sc, RADEON_RBBM_STATUS) & 3187 RADEON_RBBM_ACTIVE) != 0); 3188 radeonfb_engine_flush(sc); 3189 } 3190 3191 static inline void 3192 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3193 { 3194 int i; 3195 3196 for (i = RADEON_TIMEOUT; i; i--) { 3197 if ((GET32(sc, RADEON_RBBM_STATUS) & 3198 RADEON_RBBM_FIFOCNT_MASK) >= n) 3199 return; 3200 } 3201 #ifdef DIAGNOSTIC 3202 if (!i) 3203 printf("%s: timed out waiting for fifo (%x)\n", 3204 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3205 #endif 3206 } 3207 3208 static void 3209 radeonfb_engine_flush(struct radeonfb_softc *sc) 3210 { 3211 int i = 0; 3212 3213 if (IS_R300(sc)) { 3214 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3215 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3216 i++; 3217 } 3218 } else { 3219 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3220 RADEON_RB2D_DC_FLUSH_ALL); 3221 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3222 RADEON_RB2D_DC_BUSY) { 3223 i++; 3224 } 3225 } 3226 #ifdef DIAGNOSTIC 3227 if (i > RADEON_TIMEOUT) 3228 printf("%s: engine flush timed out!\n", XNAME(sc)); 3229 #endif 3230 } 3231 3232 static inline void 3233 radeonfb_unclip(struct radeonfb_softc *sc) 3234 { 3235 3236 radeonfb_wait_fifo(sc, 2); 3237 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3238 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3239 } 3240 3241 static void 3242 radeonfb_engine_init(struct radeonfb_display *dp) 3243 { 3244 struct radeonfb_softc *sc = dp->rd_softc; 3245 uint32_t pitch; 3246 volatile uint32_t junk; 3247 3248 /* no 3D */ 3249 PUT32(sc, RADEON_RB3D_CNTL, 0); 3250 3251 radeonfb_engine_reset(sc); 3252 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3253 3254 radeonfb_wait_fifo(sc, 1); 3255 if (!IS_R300(sc)) 3256 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3257 3258 radeonfb_wait_fifo(sc, 3); 3259 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3260 (pitch << 22) | (sc->sc_aperbase >> 10)); 3261 3262 3263 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3264 (pitch << 22) | (sc->sc_aperbase >> 10)); 3265 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3266 (pitch << 22) | (sc->sc_aperbase >> 10)); 3267 3268 junk = GET32(sc, RADEON_DP_DATATYPE); 3269 3270 /* default scissors -- no clipping */ 3271 radeonfb_wait_fifo(sc, 1); 3272 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3273 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3274 3275 radeonfb_wait_fifo(sc, 1); 3276 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3277 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3278 RADEON_GMC_CLR_CMP_CNTL_DIS | 3279 RADEON_GMC_BRUSH_SOLID_COLOR | 3280 RADEON_GMC_SRC_DATATYPE_COLOR); 3281 3282 radeonfb_wait_fifo(sc, 10); 3283 PUT32(sc, RADEON_DST_LINE_START, 0); 3284 PUT32(sc, RADEON_DST_LINE_END, 0); 3285 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3286 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3287 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3288 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3289 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3290 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3291 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3292 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3293 radeonfb_engine_idle(sc); 3294 } 3295 3296 static void 3297 radeonfb_engine_reset(struct radeonfb_softc *sc) 3298 { 3299 uint32_t hpc, rbbm, mclkcntl, clkindex; 3300 3301 radeonfb_engine_flush(sc); 3302 3303 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3304 if (HAS_R300CG(sc)) 3305 radeonfb_r300cg_workaround(sc); 3306 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3307 3308 /* 3309 * According to comments in XFree code, resetting the HDP via 3310 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3311 * So we use HOST_PATH_CNTL instead. 3312 */ 3313 3314 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3315 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3316 if (IS_R300(sc)) { 3317 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3318 RADEON_SOFT_RESET_CP | 3319 RADEON_SOFT_RESET_HI | 3320 RADEON_SOFT_RESET_E2); 3321 GET32(sc, RADEON_RBBM_SOFT_RESET); 3322 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3323 /* 3324 * XXX: this bit is not defined in any ATI docs I have, 3325 * nor in the XFree code, but XFree does it. Why? 3326 */ 3327 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3328 } else { 3329 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3330 RADEON_SOFT_RESET_CP | 3331 RADEON_SOFT_RESET_SE | 3332 RADEON_SOFT_RESET_RE | 3333 RADEON_SOFT_RESET_PP | 3334 RADEON_SOFT_RESET_E2 | 3335 RADEON_SOFT_RESET_RB); 3336 GET32(sc, RADEON_RBBM_SOFT_RESET); 3337 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3338 ~(RADEON_SOFT_RESET_CP | 3339 RADEON_SOFT_RESET_SE | 3340 RADEON_SOFT_RESET_RE | 3341 RADEON_SOFT_RESET_PP | 3342 RADEON_SOFT_RESET_E2 | 3343 RADEON_SOFT_RESET_RB)); 3344 GET32(sc, RADEON_RBBM_SOFT_RESET); 3345 } 3346 3347 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3348 GET32(sc, RADEON_HOST_PATH_CNTL); 3349 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3350 3351 if (IS_R300(sc)) 3352 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3353 3354 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3355 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3356 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3357 3358 if (HAS_R300CG(sc)) 3359 radeonfb_r300cg_workaround(sc); 3360 } 3361 3362 static int 3363 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3364 { 3365 int x, y; 3366 3367 x = pos->x; 3368 y = pos->y; 3369 3370 /* 3371 * This doesn't let a cursor move off the screen. I'm not 3372 * sure if this will have negative effects for e.g. Xinerama. 3373 * I'd guess Xinerama handles it by changing the cursor shape, 3374 * but that needs verification. 3375 */ 3376 if (x >= dp->rd_virtx) 3377 x = dp->rd_virtx - 1; 3378 if (x < 0) 3379 x = 0; 3380 if (y >= dp->rd_virty) 3381 y = dp->rd_virty - 1; 3382 if (y < 0) 3383 y = 0; 3384 3385 dp->rd_cursor.rc_pos.x = x; 3386 dp->rd_cursor.rc_pos.y = y; 3387 3388 radeonfb_cursor_position(dp); 3389 return 0; 3390 } 3391 3392 static int 3393 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3394 { 3395 unsigned flags; 3396 3397 uint8_t r[2], g[2], b[2]; 3398 unsigned index, count; 3399 int i, err; 3400 int pitch, size; 3401 struct radeonfb_cursor nc; 3402 3403 flags = wc->which; 3404 3405 /* copy old values */ 3406 nc = dp->rd_cursor; 3407 3408 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3409 index = wc->cmap.index; 3410 count = wc->cmap.count; 3411 3412 if (index >= 2 || (index + count) > 2) 3413 return EINVAL; 3414 3415 err = copyin(wc->cmap.red, &r[index], count); 3416 if (err) 3417 return err; 3418 err = copyin(wc->cmap.green, &g[index], count); 3419 if (err) 3420 return err; 3421 err = copyin(wc->cmap.blue, &b[index], count); 3422 if (err) 3423 return err; 3424 3425 for (i = index; i < index + count; i++) { 3426 nc.rc_cmap[i] = 3427 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3428 } 3429 } 3430 3431 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3432 if ((wc->size.x > RADEON_CURSORMAXX) || 3433 (wc->size.y > RADEON_CURSORMAXY)) 3434 return EINVAL; 3435 3436 /* figure bytes per line */ 3437 pitch = (wc->size.x + 7) / 8; 3438 size = pitch * wc->size.y; 3439 3440 /* clear the old cursor and mask */ 3441 memset(nc.rc_image, 0, 512); 3442 memset(nc.rc_mask, 0, 512); 3443 3444 nc.rc_size = wc->size; 3445 3446 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3447 return err; 3448 3449 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3450 return err; 3451 } 3452 3453 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3454 nc.rc_hot = wc->hot; 3455 if (nc.rc_hot.x >= nc.rc_size.x) 3456 nc.rc_hot.x = nc.rc_size.x - 1; 3457 if (nc.rc_hot.y >= nc.rc_size.y) 3458 nc.rc_hot.y = nc.rc_size.y - 1; 3459 } 3460 3461 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3462 nc.rc_pos = wc->pos; 3463 if (nc.rc_pos.x >= dp->rd_virtx) 3464 nc.rc_pos.x = dp->rd_virtx - 1; 3465 #if 0 3466 if (nc.rc_pos.x < 0) 3467 nc.rc_pos.x = 0; 3468 #endif 3469 if (nc.rc_pos.y >= dp->rd_virty) 3470 nc.rc_pos.y = dp->rd_virty - 1; 3471 #if 0 3472 if (nc.rc_pos.y < 0) 3473 nc.rc_pos.y = 0; 3474 #endif 3475 } 3476 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3477 nc.rc_visible = wc->enable; 3478 } 3479 3480 dp->rd_cursor = nc; 3481 radeonfb_cursor_update(dp, wc->which); 3482 3483 return 0; 3484 } 3485 3486 /* 3487 * Change the cursor shape. Call this with the cursor locked to avoid 3488 * flickering/tearing. 3489 */ 3490 static void 3491 radeonfb_cursor_shape(struct radeonfb_display *dp) 3492 { 3493 uint8_t and[512], xor[512]; 3494 int i, j, src, dst, pitch; 3495 const uint8_t *msk = dp->rd_cursor.rc_mask; 3496 const uint8_t *img = dp->rd_cursor.rc_image; 3497 3498 /* 3499 * Radeon cursor data interleaves one line of AND data followed 3500 * by a line of XOR data. (Each line corresponds to a whole hardware 3501 * pitch - i.e. 64 pixels or 8 bytes.) 3502 * 3503 * The cursor is displayed using the following table: 3504 * 3505 * AND XOR Result 3506 * ---------------------- 3507 * 0 0 Cursor color 0 3508 * 0 1 Cursor color 1 3509 * 1 0 Transparent 3510 * 1 1 Complement of background 3511 * 3512 * Our masks are therefore different from what we were passed. 3513 * Passed in, I'm assuming the data represents either color 0 or 1, 3514 * and a mask, so the passed in table looks like: 3515 * 3516 * IMG Mask Result 3517 * ----------------------- 3518 * 0 0 Transparent 3519 * 0 1 Cursor color 0 3520 * 1 0 Transparent 3521 * 1 1 Cursor color 1 3522 * 3523 * IF mask bit == 1, AND = 0, XOR = color. 3524 * IF mask bit == 0, AND = 1, XOR = 0. 3525 * 3526 * hence: AND = ~(mask); XOR = color & ~(mask); 3527 */ 3528 3529 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3530 3531 /* start by assuming all bits are transparent */ 3532 memset(and, 0xff, 512); 3533 memset(xor, 0x00, 512); 3534 3535 src = 0; 3536 dst = 0; 3537 for (i = 0; i < 64; i++) { 3538 for (j = 0; j < 64; j += 8) { 3539 if ((i < dp->rd_cursor.rc_size.y) && 3540 (j < dp->rd_cursor.rc_size.x)) { 3541 3542 /* take care to leave odd bits alone */ 3543 and[dst] &= ~(msk[src]); 3544 xor[dst] = img[src] & msk[src]; 3545 src++; 3546 } 3547 dst++; 3548 } 3549 } 3550 3551 /* copy the image into place */ 3552 for (i = 0; i < 64; i++) { 3553 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3554 &and[i * 8], 8); 3555 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3556 &xor[i * 8], 8); 3557 } 3558 } 3559 3560 static void 3561 radeonfb_cursor_position(struct radeonfb_display *dp) 3562 { 3563 struct radeonfb_softc *sc = dp->rd_softc; 3564 uint32_t offset, hvoff, hvpos; /* registers */ 3565 uint32_t coff; /* cursor offset */ 3566 int i, x, y, xoff, yoff, crtcoff; 3567 3568 /* 3569 * XXX: this also needs to handle pan/scan 3570 */ 3571 for (i = 0; i < dp->rd_ncrtcs; i++) { 3572 3573 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3574 3575 if (rcp->rc_number) { 3576 offset = RADEON_CUR2_OFFSET; 3577 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3578 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3579 crtcoff = RADEON_CRTC2_OFFSET; 3580 } else { 3581 offset = RADEON_CUR_OFFSET; 3582 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3583 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3584 crtcoff = RADEON_CRTC_OFFSET; 3585 } 3586 3587 x = dp->rd_cursor.rc_pos.x; 3588 y = dp->rd_cursor.rc_pos.y; 3589 3590 while (y < rcp->rc_yoffset) { 3591 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3592 } 3593 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3594 rcp->rc_yoffset += RADEON_PANINCREMENT; 3595 } 3596 while (x < rcp->rc_xoffset) { 3597 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3598 } 3599 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3600 rcp->rc_xoffset += RADEON_PANINCREMENT; 3601 } 3602 3603 /* adjust for the cursor's hotspot */ 3604 x -= dp->rd_cursor.rc_hot.x; 3605 y -= dp->rd_cursor.rc_hot.y; 3606 xoff = yoff = 0; 3607 3608 if (x >= dp->rd_virtx) 3609 x = dp->rd_virtx - 1; 3610 if (y >= dp->rd_virty) 3611 y = dp->rd_virty - 1; 3612 3613 /* now adjust cursor so it is relative to viewport */ 3614 x -= rcp->rc_xoffset; 3615 y -= rcp->rc_yoffset; 3616 3617 /* 3618 * no need to check for fall off, because we should 3619 * never move off the screen entirely! 3620 */ 3621 coff = 0; 3622 if (x < 0) { 3623 xoff = -x; 3624 x = 0; 3625 } 3626 if (y < 0) { 3627 yoff = -y; 3628 y = 0; 3629 coff = (yoff * 2) * 8; 3630 } 3631 3632 /* pan the display */ 3633 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3634 rcp->rc_xoffset); 3635 3636 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3637 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3638 /* NB: this unlocks the cursor */ 3639 PUT32(sc, hvpos, (x << 16) | y); 3640 } 3641 } 3642 3643 static void 3644 radeonfb_cursor_visible(struct radeonfb_display *dp) 3645 { 3646 int i; 3647 uint32_t gencntl, bit; 3648 3649 for (i = 0; i < dp->rd_ncrtcs; i++) { 3650 if (dp->rd_crtcs[i].rc_number) { 3651 gencntl = RADEON_CRTC2_GEN_CNTL; 3652 bit = RADEON_CRTC2_CUR_EN; 3653 } else { 3654 gencntl = RADEON_CRTC_GEN_CNTL; 3655 bit = RADEON_CRTC_CUR_EN; 3656 } 3657 3658 if (dp->rd_cursor.rc_visible) 3659 SET32(dp->rd_softc, gencntl, bit); 3660 else 3661 CLR32(dp->rd_softc, gencntl, bit); 3662 } 3663 } 3664 3665 static void 3666 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3667 { 3668 int i; 3669 uint32_t c0reg, c1reg; 3670 struct radeonfb_softc *sc = dp->rd_softc; 3671 3672 for (i = 0; i < dp->rd_ncrtcs; i++) { 3673 if (dp->rd_crtcs[i].rc_number) { 3674 c0reg = RADEON_CUR2_CLR0; 3675 c1reg = RADEON_CUR2_CLR1; 3676 } else { 3677 c0reg = RADEON_CUR_CLR0; 3678 c1reg = RADEON_CUR_CLR1; 3679 } 3680 3681 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3682 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3683 } 3684 } 3685 3686 static void 3687 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3688 { 3689 struct radeonfb_softc *sc; 3690 int i; 3691 3692 sc = dp->rd_softc; 3693 for (i = 0; i < dp->rd_ncrtcs; i++) { 3694 if (dp->rd_crtcs[i].rc_number) { 3695 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3696 } else { 3697 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3698 } 3699 } 3700 3701 if (which & WSDISPLAY_CURSOR_DOCMAP) 3702 radeonfb_cursor_cmap(dp); 3703 3704 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3705 radeonfb_cursor_shape(dp); 3706 3707 if (which & WSDISPLAY_CURSOR_DOCUR) 3708 radeonfb_cursor_visible(dp); 3709 3710 /* this one is unconditional, because it updates other stuff */ 3711 radeonfb_cursor_position(dp); 3712 } 3713 3714 static struct videomode * 3715 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3716 { 3717 int r1, r2; 3718 3719 /* otherwise pick the higher refresh rate */ 3720 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3721 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3722 3723 return (r1 < r2 ? m2 : m1); 3724 } 3725 3726 static const struct videomode * 3727 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3728 int x, int y) 3729 { 3730 struct edid_info *ep = &rp->rp_edid; 3731 struct videomode *vmp = NULL; 3732 int i; 3733 3734 if (!rp->rp_edid_valid) { 3735 /* fallback to safe mode */ 3736 return radeonfb_modelookup(sc->sc_defaultmode); 3737 } 3738 3739 /* always choose the preferred mode first! */ 3740 if (ep->edid_preferred_mode) { 3741 3742 /* XXX: add auto-stretching support for native mode */ 3743 3744 /* this may want panning to occur, btw */ 3745 if ((ep->edid_preferred_mode->hdisplay <= x) && 3746 (ep->edid_preferred_mode->vdisplay <= y)) 3747 return ep->edid_preferred_mode; 3748 } 3749 3750 for (i = 0; i < ep->edid_nmodes; i++) { 3751 /* 3752 * We elect to pick a resolution that is too large for 3753 * the monitor than one that is too small. This means 3754 * that we will prefer to pan rather than to try to 3755 * center a smaller display on a larger screen. In 3756 * practice, this shouldn't matter because if a 3757 * monitor can support a larger resolution, it can 3758 * probably also support the smaller. A specific 3759 * exception is fixed format panels, but hopefully 3760 * they are properly dealt with by the "autostretch" 3761 * logic above. 3762 */ 3763 if ((ep->edid_modes[i].hdisplay > x) || 3764 (ep->edid_modes[i].vdisplay > y)) { 3765 continue; 3766 } 3767 3768 /* 3769 * at this point, the display mode is no larger than 3770 * what we've requested. 3771 */ 3772 if (vmp == NULL) 3773 vmp = &ep->edid_modes[i]; 3774 3775 /* eliminate smaller modes */ 3776 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3777 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3778 continue; 3779 3780 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3781 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3782 vmp = &ep->edid_modes[i]; 3783 continue; 3784 } 3785 3786 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3787 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3788 3789 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3790 } 3791 3792 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3793 } 3794 3795 static int 3796 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3797 { 3798 int i; 3799 3800 for (i = 0; i < nlist; i++) { 3801 if ((x == list[i].hdisplay) && 3802 (y == list[i].vdisplay)) { 3803 return 1; 3804 } 3805 } 3806 return 0; 3807 } 3808 3809 static void 3810 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3811 int pan) 3812 { 3813 struct radeonfb_port *rp; 3814 struct edid_info *ep; 3815 int i, j; 3816 3817 *x = 0; 3818 *y = 0; 3819 3820 if (pan) { 3821 for (i = 0; i < dp->rd_ncrtcs; i++) { 3822 rp = dp->rd_crtcs[i].rc_port; 3823 ep = &rp->rp_edid; 3824 if (!rp->rp_edid_valid) { 3825 /* monitor not present */ 3826 continue; 3827 } 3828 3829 /* 3830 * For now we are ignoring "conflict" that 3831 * could occur when mixing some modes like 3832 * 1280x1024 and 1400x800. It isn't clear 3833 * which is better, so the first one wins. 3834 */ 3835 for (j = 0; j < ep->edid_nmodes; j++) { 3836 /* 3837 * ignore resolutions that are too big for 3838 * the radeon 3839 */ 3840 if (ep->edid_modes[j].hdisplay > 3841 dp->rd_softc->sc_maxx) 3842 continue; 3843 if (ep->edid_modes[j].vdisplay > 3844 dp->rd_softc->sc_maxy) 3845 continue; 3846 3847 /* 3848 * pick largest resolution, the 3849 * smaller monitor will pan 3850 */ 3851 if ((ep->edid_modes[j].hdisplay >= *x) && 3852 (ep->edid_modes[j].vdisplay >= *y)) { 3853 *x = ep->edid_modes[j].hdisplay; 3854 *y = ep->edid_modes[j].vdisplay; 3855 } 3856 } 3857 } 3858 3859 } else { 3860 struct videomode modes[64]; 3861 int nmodes = 0; 3862 int valid = 0; 3863 3864 for (i = 0; i < dp->rd_ncrtcs; i++) { 3865 /* 3866 * pick the largest resolution in common. 3867 */ 3868 rp = dp->rd_crtcs[i].rc_port; 3869 ep = &rp->rp_edid; 3870 3871 if (!rp->rp_edid_valid) 3872 continue; 3873 3874 if (!valid) { 3875 /* 3876 * Pick the preferred mode for this port 3877 * if available. 3878 */ 3879 if (ep->edid_preferred_mode) { 3880 struct videomode *vmp = 3881 ep->edid_preferred_mode; 3882 3883 if ((vmp->hdisplay <= 3884 dp->rd_softc->sc_maxx) && 3885 (vmp->vdisplay <= 3886 dp->rd_softc->sc_maxy)) 3887 modes[nmodes++] = *vmp; 3888 } else { 3889 3890 /* initialize starting list */ 3891 for (j = 0; j < ep->edid_nmodes; j++) { 3892 /* 3893 * ignore resolutions that are 3894 * too big for the radeon 3895 */ 3896 if (ep->edid_modes[j].hdisplay > 3897 dp->rd_softc->sc_maxx) 3898 continue; 3899 if (ep->edid_modes[j].vdisplay > 3900 dp->rd_softc->sc_maxy) 3901 continue; 3902 3903 modes[nmodes] = 3904 ep->edid_modes[j]; 3905 nmodes++; 3906 } 3907 } 3908 valid = 1; 3909 } else { 3910 /* merge into preexisting list */ 3911 for (j = 0; j < nmodes; j++) { 3912 if (!radeonfb_hasres(ep->edid_modes, 3913 ep->edid_nmodes, 3914 modes[j].hdisplay, 3915 modes[j].vdisplay)) { 3916 modes[j] = modes[nmodes]; 3917 j--; 3918 nmodes--; 3919 } 3920 } 3921 } 3922 } 3923 3924 /* now we have to pick from the merged list */ 3925 for (i = 0; i < nmodes; i++) { 3926 if ((modes[i].hdisplay >= *x) && 3927 (modes[i].vdisplay >= *y)) { 3928 *x = modes[i].hdisplay; 3929 *y = modes[i].vdisplay; 3930 } 3931 } 3932 } 3933 3934 if ((*x == 0) || (*y == 0)) { 3935 /* fallback to safe mode */ 3936 *x = 640; 3937 *y = 480; 3938 } 3939 } 3940 3941 /* 3942 * backlight levels are linear on: 3943 * - RV200, RV250, RV280, RV350 3944 * - but NOT on PowerBook4,3 6,3 6,5 3945 * according to Linux' radeonfb 3946 */ 3947 3948 /* Get the current backlight level for the display. */ 3949 3950 static int 3951 radeonfb_get_backlight(struct radeonfb_display *dp) 3952 { 3953 int s; 3954 uint32_t level; 3955 3956 s = spltty(); 3957 3958 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3959 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3960 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3961 3962 /* 3963 * On some chips, we should negate the backlight level. 3964 * XXX Find out on which chips. 3965 */ 3966 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3967 level = RADEONFB_BACKLIGHT_MAX - level; 3968 3969 splx(s); 3970 3971 return level; 3972 } 3973 3974 /* Set the backlight to the given level for the display. */ 3975 static void 3976 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3977 { 3978 if (dp->rd_bl_on == on) 3979 return; 3980 dp->rd_bl_on = on; 3981 radeonfb_set_backlight(dp, dp->rd_bl_level); 3982 } 3983 3984 static int 3985 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3986 { 3987 struct radeonfb_softc *sc; 3988 int rlevel, s; 3989 uint32_t lvds; 3990 3991 s = spltty(); 3992 3993 dp->rd_bl_level = level; 3994 if (dp->rd_bl_on == 0) 3995 level = 0; 3996 3997 if (level < 0) 3998 level = 0; 3999 else if (level >= RADEONFB_BACKLIGHT_MAX) 4000 level = RADEONFB_BACKLIGHT_MAX; 4001 4002 sc = dp->rd_softc; 4003 4004 /* On some chips, we should negate the backlight level. */ 4005 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4006 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4007 } else 4008 rlevel = level; 4009 4010 callout_stop(&dp->rd_bl_lvds_co); 4011 radeonfb_engine_idle(sc); 4012 4013 /* 4014 * Turn off the display if the backlight is set to 0, since the 4015 * display is useless without backlight anyway. 4016 */ 4017 if (level == 0) 4018 radeonfb_blank(dp, 1); 4019 else if (radeonfb_get_backlight(dp) == 0) 4020 radeonfb_blank(dp, 0); 4021 4022 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4023 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4024 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4025 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4026 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4027 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4028 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4029 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4030 lvds |= RADEON_LVDS_ON; 4031 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4032 } else { 4033 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4034 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4035 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4036 } 4037 4038 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4039 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4040 /* XXX What is the correct delay? */ 4041 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4042 4043 splx(s); 4044 4045 return 0; 4046 } 4047 4048 /* 4049 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4050 * Set the delayed bits in the register, and clear the stored delayed 4051 * value. 4052 */ 4053 4054 static void radeonfb_lvds_callout(void *arg) 4055 { 4056 struct radeonfb_display *dp = arg; 4057 int s; 4058 4059 s = splhigh(); 4060 4061 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4062 dp->rd_bl_lvds_val); 4063 dp->rd_bl_lvds_val = 0; 4064 4065 splx(s); 4066 } 4067 4068 static void 4069 radeonfb_brightness_up(device_t dev) 4070 { 4071 struct radeonfb_softc *sc = device_private(dev); 4072 struct radeonfb_display *dp = &sc->sc_displays[0]; 4073 int level; 4074 4075 /* we assume the main display is the first one - need a better way */ 4076 if (sc->sc_ndisplays < 1) return; 4077 /* make sure pushing the hotkeys always has an effect */ 4078 dp->rd_bl_on = 1; 4079 level = dp->rd_bl_level; 4080 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4081 radeonfb_set_backlight(dp, level); 4082 } 4083 4084 static void 4085 radeonfb_brightness_down(device_t dev) 4086 { 4087 struct radeonfb_softc *sc = device_private(dev); 4088 struct radeonfb_display *dp = &sc->sc_displays[0]; 4089 int level; 4090 4091 /* we assume the main display is the first one - need a better way */ 4092 if (sc->sc_ndisplays < 1) return; 4093 /* make sure pushing the hotkeys always has an effect */ 4094 dp->rd_bl_on = 1; 4095 level = dp->rd_bl_level; 4096 level = max(0, level - 5); 4097 radeonfb_set_backlight(dp, level); 4098 } 4099
Indexes created Fri Sep 26 20:09:58 GMT 2025