radeonfb.c revision 1.75
1 /* $NetBSD: radeonfb.c,v 1.75 2013/03/25 17:35:51 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.75 2013/03/25 17:35:51 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 174 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 175 #endif 176 177 static int radeonfb_set_backlight(struct radeonfb_display *, int); 178 static int radeonfb_get_backlight(struct radeonfb_display *); 179 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 180 static void radeonfb_lvds_callout(void *); 181 182 static void radeonfb_brightness_up(device_t); 183 static void radeonfb_brightness_down(device_t); 184 185 static struct videomode *radeonfb_best_refresh(struct videomode *, 186 struct videomode *); 187 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 188 uint16_t *, int); 189 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 190 struct radeonfb_port *, int, int); 191 192 static int radeonfb_drm_print(void *, const char *); 193 194 #ifdef RADEONFB_DEBUG 195 int radeon_debug = 1; 196 #define DPRINTF(x) \ 197 if (radeon_debug) printf x 198 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 199 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 200 #else 201 #define DPRINTF(x) 202 #define PRINTREG(r) 203 #define PRINTPLL(r) 204 #endif 205 206 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 207 208 #ifndef RADEON_DEFAULT_MODE 209 /* any reasonably modern display should handle this */ 210 #define RADEON_DEFAULT_MODE "1024x768x60" 211 #endif 212 213 extern const u_char rasops_cmap[768]; 214 215 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 216 217 static struct { 218 int size; /* minimum memory size (MB) */ 219 int maxx; /* maximum x dimension */ 220 int maxy; /* maximum y dimension */ 221 int maxbpp; /* maximum bpp */ 222 int maxdisp; /* maximum logical display count */ 223 } radeonfb_limits[] = { 224 { 32, 2048, 1536, 32, 2 }, 225 { 16, 1600, 1200, 32, 2 }, 226 { 8, 1600, 1200, 32, 1 }, 227 { 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct wsscreen_descr radeonfb_stdscreen = { 231 "fb", /* name */ 232 0, 0, /* ncols, nrows */ 233 NULL, /* textops */ 234 8, 16, /* fontwidth, fontheight */ 235 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 236 0, /* modecookie */ 237 }; 238 239 struct wsdisplay_accessops radeonfb_accessops = { 240 radeonfb_ioctl, 241 radeonfb_mmap, 242 NULL, /* vcons_alloc_screen */ 243 NULL, /* vcons_free_screen */ 244 NULL, /* vcons_show_screen */ 245 NULL, /* load_font */ 246 NULL, /* pollc */ 247 NULL, /* scroll */ 248 }; 249 250 static struct { 251 uint16_t devid; 252 uint16_t family; 253 uint16_t flags; 254 } radeonfb_devices[] = 255 { 256 /* R100 family */ 257 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 261 262 /* RV100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 267 268 /* RS100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 271 272 /* RS200/RS250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 277 278 /* R200 family */ 279 /* add more R200 products? , 5148 */ 280 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 285 286 /* RV200 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 291 292 /* RV250 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 298 299 /* RS300 family */ 300 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 304 305 /* RV280 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 313 314 /* R300 family */ 315 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 323 324 /* RV350/RV360 family */ 325 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 337 338 /* R350/R360 family */ 339 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 347 348 /* RV380/RV370 family */ 349 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 359 360 #if notyet 361 /* R420/R423 family */ 362 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 379 #endif 380 { 0, 0, 0 } 381 }; 382 383 static struct { 384 int divider; 385 int mask; 386 } radeonfb_dividers[] = { 387 { 16, 5 }, 388 { 12, 7 }, 389 { 8, 3 }, 390 { 6, 6 }, 391 { 4, 2 }, 392 { 3, 4 }, 393 { 2, 1 }, 394 { 1, 0 }, 395 { 0, 0 } 396 }; 397 398 /* 399 * This table taken from X11. 400 */ 401 static const struct { 402 int family; 403 struct radeon_tmds_pll plls[4]; 404 } radeonfb_tmds_pll[] = { 405 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RS100, {{0, 0}}}, 408 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 411 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 412 { RADEON_RS300, {{0, 0}}}, 413 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 414 { RADEON_R300, {{-1, 0xb01cb}}}, 415 { RADEON_R350, {{-1, 0xb01cb}}}, 416 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 417 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 418 { RADEON_R420, {{-1, 0xb01cb}}}, 419 }; 420 421 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 422 423 424 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 425 radeonfb_match, radeonfb_attach, NULL, NULL); 426 427 static int 428 radeonfb_match(device_t parent, cfdata_t match, void *aux) 429 { 430 const struct pci_attach_args *pa = aux; 431 int i; 432 433 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 434 return 0; 435 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 438 return 100; /* high to defeat VGA/VESA */ 439 } 440 441 return 0; 442 } 443 444 static void 445 radeonfb_attach(device_t parent, device_t dev, void *aux) 446 { 447 struct radeonfb_softc *sc = device_private(dev); 448 const struct pci_attach_args *pa = aux; 449 const char *mptr; 450 bus_size_t bsz; 451 pcireg_t screg; 452 int i, j, fg, bg, ul, flags; 453 uint32_t v; 454 455 sc->sc_dev = dev; 456 sc->sc_id = pa->pa_id; 457 for (i = 0; radeonfb_devices[i].devid; i++) { 458 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 459 break; 460 } 461 462 pci_aprint_devinfo(pa, NULL); 463 464 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 465 466 KASSERT(radeonfb_devices[i].devid != 0); 467 sc->sc_pt = pa->pa_tag; 468 sc->sc_iot = pa->pa_iot; 469 sc->sc_pc = pa->pa_pc; 470 sc->sc_family = radeonfb_devices[i].family; 471 sc->sc_flags = radeonfb_devices[i].flags; 472 473 /* enable memory and IO access */ 474 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 475 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 476 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 477 478 /* 479 * Some flags are general to entire chip families, and rather 480 * than clutter up the table with them, we go ahead and set 481 * them here. 482 */ 483 switch (sc->sc_family) { 484 case RADEON_RS100: 485 case RADEON_RS200: 486 sc->sc_flags |= RFB_IGP | RFB_RV100; 487 break; 488 489 case RADEON_RV100: 490 case RADEON_RV200: 491 case RADEON_RV250: 492 case RADEON_RV280: 493 sc->sc_flags |= RFB_RV100; 494 break; 495 496 case RADEON_RS300: 497 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_R300: 501 case RADEON_RV350: 502 case RADEON_R350: 503 case RADEON_RV380: 504 case RADEON_R420: 505 /* newer chips */ 506 sc->sc_flags |= RFB_R300; 507 break; 508 509 case RADEON_R100: 510 sc->sc_flags |= RFB_NCRTC2; 511 break; 512 } 513 514 if ((sc->sc_family == RADEON_RV200) || 515 (sc->sc_family == RADEON_RV250) || 516 (sc->sc_family == RADEON_RV280) || 517 (sc->sc_family == RADEON_RV350)) { 518 bool inverted = 0; 519 /* backlight level is linear */ 520 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 521 prop_dictionary_get_bool(device_properties(sc->sc_dev), 522 "backlight_level_reverted", &inverted); 523 if (inverted) { 524 DPRINTF(("nope, it's inverted\n")); 525 sc->sc_flags |= RFB_INV_BLIGHT; 526 } 527 } else 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 530 /* 531 * XXX: to support true multihead, this must change. 532 */ 533 sc->sc_ndisplays = 1; 534 535 /* XXX: */ 536 if (!HAS_CRTC2(sc)) { 537 sc->sc_ndisplays = 1; 538 } 539 540 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 541 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 542 &sc->sc_regsz) != 0) { 543 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 544 goto error; 545 } 546 547 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 548 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 549 { 550 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 551 goto error; 552 } 553 sc->sc_romt = sc->sc_memt; 554 555 sc->sc_mapped = TRUE; 556 557 /* scratch register test... */ 558 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 559 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 560 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 561 goto error; 562 } 563 564 PRINTREG(RADEON_CRTC_EXT_CNTL); 565 PRINTREG(RADEON_CRTC_GEN_CNTL); 566 PRINTREG(RADEON_CRTC2_GEN_CNTL); 567 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 568 PRINTREG(RADEON_DAC_CNTL2); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 PRINTREG(RADEON_FP2_GEN_CNTL); 571 572 PRINTREG(RADEON_BIOS_4_SCRATCH); 573 PRINTREG(RADEON_FP_GEN_CNTL); 574 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 575 PRINTREG(RADEON_FP2_GEN_CNTL); 576 PRINTREG(RADEON_TMDS_CNTL); 577 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 578 PRINTREG(RADEON_TMDS_PLL_CNTL); 579 PRINTREG(RADEON_LVDS_GEN_CNTL); 580 PRINTREG(RADEON_FP_HORZ_STRETCH); 581 PRINTREG(RADEON_FP_VERT_STRETCH); 582 583 if (IS_RV100(sc)) 584 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 585 586 /* XXX 587 * according to xf86-video-radeon R3xx has this bit backwards 588 */ 589 if (IS_R300(sc)) { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 0, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } else { 594 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 595 RADEON_TMDS_TRANSMITTER_PLLEN, 596 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 597 } 598 599 radeonfb_i2c_init(sc); 600 601 radeonfb_loadbios(sc, pa); 602 603 #ifdef RADEONFB_BIOS_INIT 604 if (radeonfb_bios_init(sc)) { 605 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 606 } 607 #endif 608 609 if (radeonfb_getclocks(sc)) { 610 aprint_error("%s: Unable to get reference clocks from BIOS\n", 611 XNAME(sc)); 612 goto error; 613 } 614 615 if (radeonfb_gettmds(sc)) { 616 aprint_error("%s: Unable to identify TMDS PLL settings\n", 617 XNAME(sc)); 618 goto error; 619 } 620 621 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 622 "minpll = %d, maxpll = %d\n", XNAME(sc), 623 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 624 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 625 626 radeonfb_getconnectors(sc); 627 628 radeonfb_set_fbloc(sc); 629 630 for (i = 0; radeonfb_limits[i].size; i++) { 631 if (sc->sc_memsz >= radeonfb_limits[i].size) { 632 sc->sc_maxx = radeonfb_limits[i].maxx; 633 sc->sc_maxy = radeonfb_limits[i].maxy; 634 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 635 /* framebuffer offset, start at a 4K page */ 636 sc->sc_fboffset = sc->sc_memsz / 637 radeonfb_limits[i].maxdisp; 638 /* 639 * we use the fbsize to figure out where we can store 640 * things like cursor data. 641 */ 642 sc->sc_fbsize = 643 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 644 RADEON_STRIDEALIGN) * sc->sc_maxy, 645 4096); 646 break; 647 } 648 } 649 650 651 radeonfb_init_misc(sc); 652 653 /* program the DAC wirings */ 654 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 655 switch (sc->sc_ports[i].rp_dac_type) { 656 case RADEON_DAC_PRIMARY: 657 PATCH32(sc, RADEON_DAC_CNTL2, 658 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 659 ~RADEON_DAC2_DAC_CLK_SEL); 660 break; 661 case RADEON_DAC_TVDAC: 662 /* we always use the TVDAC to drive a secondary analog 663 * CRT for now. if we ever support TV-out this will 664 * have to change. 665 */ 666 SET32(sc, RADEON_DAC_CNTL2, 667 RADEON_DAC2_DAC2_CLK_SEL); 668 PATCH32(sc, RADEON_DISP_HW_DEBUG, 669 i ? 0 : RADEON_CRT2_DISP1_SEL, 670 ~RADEON_CRT2_DISP1_SEL); 671 /* we're using CRTC2 for the 2nd port */ 672 if (sc->sc_ports[i].rp_number == 1) { 673 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 674 RADEON_DISP_DAC2_SOURCE_CRTC2, 675 ~RADEON_DISP_DAC2_SOURCE_MASK); 676 } 677 678 break; 679 } 680 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 681 sc->sc_ports[i].rp_tmds_type)); 682 switch (sc->sc_ports[i].rp_tmds_type) { 683 case RADEON_TMDS_INT: 684 /* point FP0 at the CRTC this port uses */ 685 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 686 __func__, sc->sc_ports[i].rp_number)); 687 if (IS_R300(sc)) { 688 PATCH32(sc, RADEON_FP_GEN_CNTL, 689 sc->sc_ports[i].rp_number ? 690 R200_FP_SOURCE_SEL_CRTC2 : 691 R200_FP_SOURCE_SEL_CRTC1, 692 ~R200_FP_SOURCE_SEL_MASK); 693 } else { 694 PATCH32(sc, RADEON_FP_GEN_CNTL, 695 sc->sc_ports[i].rp_number ? 696 RADEON_FP_SEL_CRTC2 : 697 RADEON_FP_SEL_CRTC1, 698 ~RADEON_FP_SEL_MASK); 699 } 700 } 701 } 702 PRINTREG(RADEON_DAC_CNTL2); 703 PRINTREG(RADEON_DISP_HW_DEBUG); 704 705 /* other DAC programming */ 706 v = GET32(sc, RADEON_DAC_CNTL); 707 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 708 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 709 PUT32(sc, RADEON_DAC_CNTL, v); 710 PRINTREG(RADEON_DAC_CNTL); 711 712 /* XXX: this may need more investigation */ 713 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 714 PRINTREG(RADEON_TV_DAC_CNTL); 715 716 /* enable TMDS */ 717 SET32(sc, RADEON_FP_GEN_CNTL, 718 RADEON_FP_TMDS_EN | 719 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 720 RADEON_FP_CRTC_DONT_SHADOW_HEND); 721 /* 722 * XXX 723 * no idea why this is necessary - if I do not clear this bit on my 724 * iBook G4 the screen remains black, even though it's already clear. 725 * It needs to be set on my Sun XVR-100 for the DVI port to work 726 * TODO: 727 * see if this is still necessary now that CRTCs, DACs and outputs are 728 * getting wired up in a halfway sane way 729 */ 730 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 731 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 732 } else { 733 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 734 } 735 736 /* 737 * we use bus_space_map instead of pci_mapreg, because we don't 738 * need the full aperature space. no point in wasting virtual 739 * address space we don't intend to use, right? 740 */ 741 if ((sc->sc_memsz < (4096 * 1024)) || 742 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 743 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 744 (bsz < sc->sc_memsz)) { 745 sc->sc_memsz = 0; 746 aprint_error("%s: Bad frame buffer configuration\n", 747 XNAME(sc)); 748 goto error; 749 } 750 751 /* 64 MB should be enough -- more just wastes map entries */ 752 if (sc->sc_memsz > (64 << 20)) 753 sc->sc_memsz = (64 << 20); 754 755 sc->sc_memt = pa->pa_memt; 756 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 757 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 758 sc->sc_memsz = 0; 759 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 760 goto error; 761 } 762 763 aprint_normal("%s: %d MB aperture at 0x%08x, " 764 "%d KB registers at 0x%08x\n", XNAME(sc), 765 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 766 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 767 768 /* setup default video mode from devprop (allows PROM override) */ 769 sc->sc_defaultmode = radeonfb_default_mode; 770 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 771 "videomode", &mptr)) { 772 773 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 774 sc->sc_defaultmode = sc->sc_modebuf; 775 } 776 777 /* initialize some basic display parameters */ 778 for (i = 0; i < sc->sc_ndisplays; i++) { 779 struct radeonfb_display *dp = &sc->sc_displays[i]; 780 struct rasops_info *ri; 781 long defattr; 782 struct wsemuldisplaydev_attach_args aa; 783 784 /* 785 * Figure out how many "displays" (desktops) we are going to 786 * support. If more than one, then each CRTC gets its own 787 * programming. 788 * 789 * XXX: this code needs to change to support mergedfb. 790 * XXX: would be nice to allow this to be overridden 791 */ 792 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 793 DPRINTF(("dual crtcs!\n")); 794 dp->rd_ncrtcs = 2; 795 dp->rd_crtcs[0].rc_port = 796 &sc->sc_ports[0]; 797 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 798 dp->rd_crtcs[1].rc_port = 799 &sc->sc_ports[1]; 800 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 801 } else { 802 dp->rd_ncrtcs = 1; 803 dp->rd_crtcs[0].rc_port = 804 &sc->sc_ports[i]; 805 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 806 } 807 808 dp->rd_softc = sc; 809 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 810 dp->rd_bg = WS_DEFAULT_BG; 811 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 812 813 /* for text mode, we pick a resolution that won't 814 * require panning */ 815 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 816 817 aprint_normal("%s: display %d: " 818 "initial virtual resolution %dx%d at %d bpp\n", 819 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 820 821 /* now select the *video mode* that we will use */ 822 for (j = 0; j < dp->rd_ncrtcs; j++) { 823 const struct videomode *vmp; 824 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 825 dp->rd_virtx, dp->rd_virty); 826 827 /* 828 * virtual resolution should be at least as high as 829 * physical 830 */ 831 if (dp->rd_virtx < vmp->hdisplay || 832 dp->rd_virty < vmp->vdisplay) { 833 dp->rd_virtx = vmp->hdisplay; 834 dp->rd_virty = vmp->vdisplay; 835 } 836 837 dp->rd_crtcs[j].rc_videomode = *vmp; 838 printf("%s: port %d: physical %dx%d %dHz\n", 839 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 840 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 841 vmp->htotal), vmp->vtotal)); 842 } 843 844 /* N.B.: radeon wants 64-byte aligned stride */ 845 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 846 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 847 DPRINTF(("stride: %d\n", dp->rd_stride)); 848 849 dp->rd_offset = sc->sc_fboffset * i; 850 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 851 sc->sc_memh) + dp->rd_offset; 852 dp->rd_curoff = sc->sc_fbsize; 853 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 854 855 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 856 857 switch (dp->rd_bpp) { 858 case 8: 859 dp->rd_format = 2; 860 break; 861 case 32: 862 dp->rd_format = 6; 863 break; 864 default: 865 aprint_error("%s: bad depth %d\n", XNAME(sc), 866 dp->rd_bpp); 867 goto error; 868 } 869 870 DPRINTF(("init engine\n")); 871 /* XXX: this seems suspicious - per display engine 872 initialization? */ 873 radeonfb_engine_init(dp); 874 875 /* copy the template into place */ 876 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 877 dp->rd_wsscreens = dp->rd_wsscreens_storage; 878 879 /* and make up the list */ 880 dp->rd_wsscreenlist.nscreens = 1; 881 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 882 883 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 884 &radeonfb_accessops); 885 886 dp->rd_vd.init_screen = radeonfb_init_screen; 887 888 #ifdef RADEONFB_DEBUG 889 dp->rd_virty -= 200; 890 #endif 891 892 dp->rd_console = 0; 893 prop_dictionary_get_bool(device_properties(sc->sc_dev), 894 "is_console", &dp->rd_console); 895 896 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 897 898 899 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 900 dp->rd_console, &defattr); 901 902 ri = &dp->rd_vscreen.scr_ri; 903 904 /* clear the screen */ 905 rasops_unpack_attr(defattr, &fg, &bg, &ul); 906 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 907 ri->ri_devcmap[bg & 0xf]); 908 909 dp->rd_wsscreens->textops = &ri->ri_ops; 910 dp->rd_wsscreens->capabilities = ri->ri_caps; 911 dp->rd_wsscreens->nrows = ri->ri_rows; 912 dp->rd_wsscreens->ncols = ri->ri_cols; 913 914 #ifdef SPLASHSCREEN 915 dp->rd_splash.si_depth = ri->ri_depth; 916 dp->rd_splash.si_bits = ri->ri_bits; 917 dp->rd_splash.si_hwbits = ri->ri_hwbits; 918 dp->rd_splash.si_width = ri->ri_width; 919 dp->rd_splash.si_height = ri->ri_height; 920 dp->rd_splash.si_stride = ri->ri_stride; 921 dp->rd_splash.si_fillrect = NULL; 922 #endif 923 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 924 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 925 dp->rd_gc.gc_rop = RADEON_ROP3_S; 926 dp->rd_gc.gc_blitcookie = dp; 927 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 928 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 929 dp->rd_virtx, 930 ri->ri_font->fontwidth, 931 ri->ri_font->fontheight, 932 defattr); 933 if (dp->rd_console) { 934 935 radeonfb_modeswitch(dp); 936 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 937 defattr); 938 #ifdef SPLASHSCREEN 939 if (splash_render(&dp->rd_splash, 940 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 941 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 942 else 943 #endif 944 vcons_replay_msgbuf(&dp->rd_vscreen); 945 } else { 946 947 /* 948 * since we're not the console we can postpone 949 * the rest until someone actually allocates a 950 * screen for us. but we do clear the screen 951 * at least. 952 */ 953 memset(ri->ri_bits, 0, 1024); 954 955 radeonfb_modeswitch(dp); 956 #ifdef SPLASHSCREEN 957 if (splash_render(&dp->rd_splash, 958 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 959 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 960 #endif 961 } 962 963 aa.console = dp->rd_console; 964 aa.scrdata = &dp->rd_wsscreenlist; 965 aa.accessops = &radeonfb_accessops; 966 aa.accesscookie = &dp->rd_vd; 967 968 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 969 970 radeonfb_blank(dp, 0); 971 972 /* Initialise delayed lvds operations for backlight. */ 973 callout_init(&dp->rd_bl_lvds_co, 0); 974 callout_setfunc(&dp->rd_bl_lvds_co, 975 radeonfb_lvds_callout, dp); 976 dp->rd_bl_on = 1; 977 dp->rd_bl_level = radeonfb_get_backlight(dp); 978 radeonfb_set_backlight(dp, dp->rd_bl_level); 979 } 980 981 for (i = 0; i < RADEON_NDISPLAYS; i++) 982 radeonfb_init_palette(&sc->sc_displays[i]); 983 984 if (HAS_CRTC2(sc)) { 985 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 986 } 987 988 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 989 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 990 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 991 radeonfb_brightness_up, TRUE); 992 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 993 radeonfb_brightness_down, TRUE); 994 995 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 996 997 PRINTREG(RADEON_CRTC_EXT_CNTL); 998 PRINTREG(RADEON_CRTC_GEN_CNTL); 999 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1000 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1001 PRINTREG(RADEON_DAC_CNTL2); 1002 PRINTREG(RADEON_FP_GEN_CNTL); 1003 PRINTREG(RADEON_FP2_GEN_CNTL); 1004 1005 return; 1006 1007 error: 1008 if (sc->sc_biossz) 1009 free(sc->sc_bios, M_DEVBUF); 1010 1011 if (sc->sc_regsz) 1012 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1013 1014 if (sc->sc_memsz) 1015 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1016 } 1017 1018 static void 1019 radeonfb_map(struct radeonfb_softc *sc) 1020 { 1021 if (!sc->sc_mapped) { 1022 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1023 &sc->sc_regh) != 0) { 1024 aprint_error_dev(sc->sc_dev, 1025 "unable to map registers!\n"); 1026 return; 1027 } 1028 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1029 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1030 sc->sc_memsz = 0; 1031 aprint_error_dev(sc->sc_dev, 1032 "Unable to map frame buffer\n"); 1033 return; 1034 } 1035 sc->sc_mapped = TRUE; 1036 } 1037 } 1038 1039 static void 1040 radeonfb_unmap(struct radeonfb_softc *sc) 1041 { 1042 if (sc->sc_mapped) { 1043 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1044 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1045 sc->sc_mapped = FALSE; 1046 } 1047 } 1048 1049 static int 1050 radeonfb_drm_print(void *aux, const char *pnp) 1051 { 1052 if (pnp) 1053 aprint_normal("drm at %s", pnp); 1054 return (UNCONF); 1055 } 1056 1057 int 1058 radeonfb_ioctl(void *v, void *vs, 1059 unsigned long cmd, void *d, int flag, struct lwp *l) 1060 { 1061 struct vcons_data *vd; 1062 struct radeonfb_display *dp; 1063 struct radeonfb_softc *sc; 1064 struct wsdisplay_param *param; 1065 1066 vd = (struct vcons_data *)v; 1067 dp = (struct radeonfb_display *)vd->cookie; 1068 sc = dp->rd_softc; 1069 1070 switch (cmd) { 1071 case WSDISPLAYIO_GTYPE: 1072 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1073 return 0; 1074 1075 case WSDISPLAYIO_GINFO: 1076 if (vd->active != NULL) { 1077 struct wsdisplay_fbinfo *fb; 1078 fb = (struct wsdisplay_fbinfo *)d; 1079 fb->width = dp->rd_virtx; 1080 fb->height = dp->rd_virty; 1081 fb->depth = dp->rd_bpp; 1082 fb->cmsize = 256; 1083 return 0; 1084 } else 1085 return ENODEV; 1086 case WSDISPLAYIO_GVIDEO: 1087 if (radeonfb_isblank(dp)) 1088 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1089 else 1090 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1091 return 0; 1092 1093 case WSDISPLAYIO_SVIDEO: 1094 radeonfb_blank(dp, 1095 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1096 return 0; 1097 1098 case WSDISPLAYIO_GETCMAP: 1099 #if 0 1100 if (dp->rd_bpp == 8) 1101 return radeonfb_getcmap(sc, 1102 (struct wsdisplay_cmap *)d); 1103 #endif 1104 return EINVAL; 1105 1106 case WSDISPLAYIO_PUTCMAP: 1107 #if 0 1108 if (dp->rd_bpp == 8) 1109 return radeonfb_putcmap(sc, 1110 (struct wsdisplay_cmap *)d); 1111 #endif 1112 return EINVAL; 1113 1114 case WSDISPLAYIO_LINEBYTES: 1115 *(unsigned *)d = dp->rd_stride; 1116 return 0; 1117 1118 case WSDISPLAYIO_SMODE: 1119 if (*(int *)d != dp->rd_wsmode) { 1120 dp->rd_wsmode = *(int *)d; 1121 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1122 (dp->rd_vd.active)) { 1123 radeonfb_map(sc); 1124 radeonfb_engine_init(dp); 1125 glyphcache_wipe(&dp->rd_gc); 1126 radeonfb_init_palette(dp); 1127 radeonfb_modeswitch(dp); 1128 vcons_redraw_screen(dp->rd_vd.active); 1129 } else { 1130 radeonfb_unmap(sc); 1131 } 1132 } 1133 return 0; 1134 1135 case WSDISPLAYIO_GCURMAX: 1136 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1137 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1138 return 0; 1139 1140 case WSDISPLAYIO_SCURSOR: 1141 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1142 1143 case WSDISPLAYIO_GCURSOR: 1144 return EPASSTHROUGH; 1145 1146 case WSDISPLAYIO_GCURPOS: 1147 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1148 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1149 return 0; 1150 1151 case WSDISPLAYIO_SCURPOS: 1152 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1153 1154 case WSDISPLAYIO_SSPLASH: 1155 #if defined(SPLASHSCREEN) 1156 if (*(int *)d == 1) { 1157 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1158 splash_render(&dp->rd_splash, 1159 SPLASH_F_CENTER|SPLASH_F_FILL); 1160 } else 1161 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1162 return 0; 1163 #else 1164 return ENODEV; 1165 #endif 1166 case WSDISPLAYIO_GETPARAM: 1167 param = (struct wsdisplay_param *)d; 1168 switch (param->param) { 1169 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1170 param->min = 0; 1171 param->max = 255; 1172 param->curval = dp->rd_bl_level; 1173 return 0; 1174 case WSDISPLAYIO_PARAM_BACKLIGHT: 1175 param->min = 0; 1176 param->max = RADEONFB_BACKLIGHT_MAX; 1177 param->curval = dp->rd_bl_on; 1178 return 0; 1179 } 1180 return EPASSTHROUGH; 1181 1182 case WSDISPLAYIO_SETPARAM: 1183 param = (struct wsdisplay_param *)d; 1184 switch (param->param) { 1185 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1186 radeonfb_set_backlight(dp, param->curval); 1187 return 0; 1188 case WSDISPLAYIO_PARAM_BACKLIGHT: 1189 radeonfb_switch_backlight(dp, param->curval); 1190 return 0; 1191 } 1192 return EPASSTHROUGH; 1193 1194 /* PCI config read/write passthrough. */ 1195 case PCI_IOC_CFGREAD: 1196 case PCI_IOC_CFGWRITE: 1197 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1198 1199 case WSDISPLAYIO_GET_BUSID: 1200 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1201 sc->sc_pt, d); 1202 1203 case WSDISPLAYIO_GET_EDID: { 1204 struct wsdisplayio_edid_info *ei = d; 1205 return wsdisplayio_get_edid(sc->sc_dev, ei); 1206 } 1207 1208 default: 1209 return EPASSTHROUGH; 1210 } 1211 } 1212 1213 paddr_t 1214 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1215 { 1216 struct vcons_data *vd; 1217 struct radeonfb_display *dp; 1218 struct radeonfb_softc *sc; 1219 paddr_t pa; 1220 1221 vd = (struct vcons_data *)v; 1222 dp = (struct radeonfb_display *)vd->cookie; 1223 sc = dp->rd_softc; 1224 1225 /* XXX: note that we don't allow mapping of registers right now */ 1226 /* XXX: this means that the XFree86 radeon driver won't work */ 1227 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1228 pa = bus_space_mmap(sc->sc_memt, 1229 sc->sc_memaddr + dp->rd_offset + offset, 0, 1230 prot, BUS_SPACE_MAP_LINEAR); 1231 return pa; 1232 } 1233 1234 #ifdef RADEONFB_MMAP_BARS 1235 /* 1236 * restrict all other mappings to processes with superuser privileges 1237 * or the kernel itself 1238 */ 1239 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1240 NULL, NULL, NULL, NULL) != 0) { 1241 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1242 return -1; 1243 } 1244 1245 if ((offset >= sc->sc_regaddr) && 1246 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1247 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1248 BUS_SPACE_MAP_LINEAR); 1249 } 1250 1251 if ((offset >= sc->sc_memaddr) && 1252 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1253 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1254 BUS_SPACE_MAP_LINEAR); 1255 } 1256 1257 if ((offset >= sc->sc_romaddr) && 1258 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1259 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1260 BUS_SPACE_MAP_LINEAR); 1261 } 1262 1263 #ifdef PCI_MAGIC_IO_RANGE 1264 /* allow mapping of IO space */ 1265 if ((offset >= PCI_MAGIC_IO_RANGE) && 1266 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1267 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1268 0, prot, 0); 1269 return pa; 1270 } 1271 #endif /* PCI_MAGIC_IO_RANGE */ 1272 1273 #endif /* RADEONFB_MMAP_BARS */ 1274 1275 return -1; 1276 } 1277 1278 static void 1279 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1280 { 1281 bus_space_tag_t romt; 1282 bus_space_handle_t romh, biosh; 1283 bus_size_t romsz; 1284 bus_addr_t ptr; 1285 1286 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1287 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1288 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1289 return; 1290 } 1291 1292 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1293 &sc->sc_biossz); 1294 if (sc->sc_biossz == 0) { 1295 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1296 return; 1297 } 1298 1299 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1300 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1301 1302 /* unmap the PCI expansion rom */ 1303 bus_space_unmap(romt, romh, romsz); 1304 1305 /* turn off rom decoder now */ 1306 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1307 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1308 ~PCI_MAPREG_ROM_ENABLE); 1309 1310 ptr = GETBIOS16(sc, 0x48); 1311 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1312 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1313 sc->sc_flags |= RFB_ATOM; 1314 } 1315 1316 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1317 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1318 } 1319 1320 1321 uint32_t 1322 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1323 { 1324 1325 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1326 } 1327 1328 void 1329 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1330 { 1331 1332 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1333 } 1334 1335 void 1336 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1337 { 1338 1339 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1340 } 1341 1342 void 1343 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1344 uint32_t andmask, uint32_t ormask) 1345 { 1346 int s; 1347 uint32_t val; 1348 1349 s = splhigh(); 1350 val = radeonfb_get32(sc, reg); 1351 val = (val & andmask) | ormask; 1352 radeonfb_put32(sc, reg, val); 1353 splx(s); 1354 } 1355 1356 uint32_t 1357 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1358 { 1359 int s; 1360 uint32_t val; 1361 1362 s = splhigh(); 1363 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1364 val = radeonfb_get32(sc, RADEON_MM_DATA); 1365 splx(s); 1366 1367 return (val); 1368 } 1369 1370 void 1371 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1372 { 1373 int s; 1374 1375 s = splhigh(); 1376 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1377 radeonfb_put32(sc, RADEON_MM_DATA, val); 1378 splx(s); 1379 } 1380 1381 void 1382 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1383 uint32_t andmask, uint32_t ormask) 1384 { 1385 int s; 1386 uint32_t val; 1387 1388 s = splhigh(); 1389 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1390 val = radeonfb_get32(sc, RADEON_MM_DATA); 1391 val = (val & andmask) | ormask; 1392 radeonfb_put32(sc, RADEON_MM_DATA, val); 1393 splx(s); 1394 } 1395 1396 uint32_t 1397 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1398 { 1399 int s; 1400 uint32_t val; 1401 1402 s = splhigh(); 1403 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1404 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1405 if (HAS_R300CG(sc)) 1406 radeonfb_r300cg_workaround(sc); 1407 splx(s); 1408 1409 return (val); 1410 } 1411 1412 void 1413 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1414 { 1415 int s; 1416 1417 s = splhigh(); 1418 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1419 RADEON_PLL_WR_EN); 1420 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1421 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1422 splx(s); 1423 } 1424 1425 void 1426 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1427 uint32_t andmask, uint32_t ormask) 1428 { 1429 int s; 1430 uint32_t val; 1431 1432 s = splhigh(); 1433 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1434 RADEON_PLL_WR_EN); 1435 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1436 val = (val & andmask) | ormask; 1437 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1438 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1439 splx(s); 1440 } 1441 1442 int 1443 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1444 { 1445 uint32_t saved; 1446 1447 saved = GET32(sc, reg); 1448 PUT32(sc, reg, v); 1449 if (GET32(sc, reg) != v) { 1450 return -1; 1451 } 1452 PUT32(sc, reg, saved); 1453 return 0; 1454 } 1455 1456 uintmax_t 1457 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1458 uintmax_t defval) 1459 { 1460 prop_number_t pn; 1461 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1462 if (pn == NULL) { 1463 return defval; 1464 } 1465 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1466 return (prop_number_integer_value(pn)); 1467 } 1468 1469 int 1470 radeonfb_getclocks(struct radeonfb_softc *sc) 1471 { 1472 bus_addr_t ptr; 1473 int refclk = 0; 1474 int refdiv = 0; 1475 int minpll = 0; 1476 int maxpll = 0; 1477 1478 /* load initial property values if port/board provides them */ 1479 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1480 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1481 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1482 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1483 1484 PRINTPLL(RADEON_PPLL_REF_DIV); 1485 PRINTPLL(RADEON_PPLL_DIV_0); 1486 PRINTPLL(RADEON_PPLL_DIV_1); 1487 PRINTPLL(RADEON_PPLL_DIV_2); 1488 PRINTPLL(RADEON_PPLL_DIV_3); 1489 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1490 PRINTPLL(RADEON_P2PLL_REF_DIV); 1491 PRINTPLL(RADEON_P2PLL_DIV_0); 1492 1493 if (refclk && refdiv && minpll && maxpll) 1494 goto dontprobe; 1495 1496 if (!sc->sc_biossz) { 1497 /* no BIOS */ 1498 aprint_verbose("%s: No video BIOS, using default clocks\n", 1499 XNAME(sc)); 1500 if (IS_IGP(sc)) 1501 refclk = refclk ? refclk : 1432; 1502 else 1503 refclk = refclk ? refclk : 2700; 1504 refdiv = refdiv ? refdiv : 12; 1505 minpll = minpll ? minpll : 12500; 1506 /* XXX 1507 * Need to check if the firmware or something programmed a 1508 * higher value than this, and if so, bump it. 1509 * The RV280 in my iBook is unhappy if the PLL input is less 1510 * than 360MHz 1511 */ 1512 maxpll = maxpll ? maxpll : 40000/*35000*/; 1513 } else if (IS_ATOM(sc)) { 1514 /* ATOM BIOS */ 1515 ptr = GETBIOS16(sc, 0x48); 1516 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1517 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1518 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1519 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1520 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1521 /* 1522 * ATOM BIOS doesn't supply a reference divider, so we 1523 * have to probe for it. 1524 */ 1525 if (refdiv < 2) 1526 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1527 RADEON_PPLL_REF_DIV_MASK; 1528 /* 1529 * if probe is zero, just assume one that should work 1530 * for most parts 1531 */ 1532 if (refdiv < 2) 1533 refdiv = 12; 1534 1535 } else { 1536 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1537 /* Legacy BIOS */ 1538 ptr = GETBIOS16(sc, 0x48); 1539 ptr = GETBIOS16(sc, ptr + 0x30); 1540 if (IS_R300(sc)) { 1541 refdiv = refdiv ? refdiv : 1542 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1543 R300_PPLL_REF_DIV_ACC_SHIFT; 1544 } else { 1545 refdiv = refdiv ? refdiv : 1546 tmp & RADEON_PPLL_REF_DIV_MASK; 1547 } 1548 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1549 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1550 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1551 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1552 } 1553 1554 1555 dontprobe: 1556 sc->sc_refclk = refclk * 10; 1557 sc->sc_refdiv = refdiv; 1558 sc->sc_minpll = minpll * 10; 1559 sc->sc_maxpll = maxpll * 10; 1560 return 0; 1561 } 1562 1563 int 1564 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1565 uint32_t *postdivbit, uint32_t *feedbackdiv) 1566 { 1567 int i; 1568 uint32_t outfreq; 1569 int div; 1570 1571 DPRINTF(("dot clock: %u\n", dotclock)); 1572 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1573 outfreq = div * dotclock; 1574 if ((outfreq >= sc->sc_minpll) && 1575 (outfreq <= sc->sc_maxpll)) { 1576 DPRINTF(("outfreq: %u\n", outfreq)); 1577 *postdivbit = 1578 ((uint32_t)radeonfb_dividers[i].mask << 16); 1579 DPRINTF(("post divider: %d (mask %x)\n", div, 1580 *postdivbit)); 1581 break; 1582 } 1583 } 1584 1585 if (div == 0) 1586 return 1; 1587 1588 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1589 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1590 return 0; 1591 } 1592 1593 #if 0 1594 #ifdef RADEONFB_DEBUG 1595 static void 1596 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1597 { 1598 char asc[17]; 1599 unsigned ptr = (unsigned)buffer; 1600 char *start = (char *)(ptr & ~0xf); 1601 char *end = (char *)(ptr + size); 1602 1603 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1604 1605 if (pfx == NULL) { 1606 pfx = ""; 1607 } 1608 1609 while (start < end) { 1610 unsigned offset = (unsigned)start & 0xf; 1611 if (offset == 0) { 1612 printf("%s%x: ", pfx, (unsigned)start); 1613 } 1614 if (((unsigned)start < ptr) || 1615 ((unsigned)start >= (ptr + size))) { 1616 printf(" "); 1617 asc[offset] = ' '; 1618 } else { 1619 printf("%02x", *(unsigned char *)start); 1620 if ((*start >= ' ') && (*start <= '~')) { 1621 asc[offset] = *start; 1622 } else { 1623 asc[offset] = '.'; 1624 } 1625 } 1626 asc[offset + 1] = 0; 1627 if (offset % 2) { 1628 printf(" "); 1629 } 1630 if (offset == 15) { 1631 printf(" %s\n", asc); 1632 } 1633 start++; 1634 } 1635 } 1636 #endif 1637 #endif 1638 1639 int 1640 radeonfb_getconnectors(struct radeonfb_softc *sc) 1641 { 1642 int i; 1643 int found = 0; 1644 1645 for (i = 0; i < 2; i++) { 1646 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1647 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1648 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1649 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1650 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1651 } 1652 1653 /* 1654 * This logic is borrowed from Xorg's radeon driver. 1655 */ 1656 if (!sc->sc_biossz) 1657 goto nobios; 1658 1659 if (IS_ATOM(sc)) { 1660 /* not done yet */ 1661 } else { 1662 uint16_t ptr; 1663 int port = 0; 1664 1665 ptr = GETBIOS16(sc, 0x48); 1666 ptr = GETBIOS16(sc, ptr + 0x50); 1667 for (i = 1; i < 4; i++) { 1668 uint16_t entry; 1669 uint8_t conn, ddc, dac, tmds; 1670 1671 /* 1672 * Parse the connector table. From reading the code, 1673 * it appears to made up of 16-bit entries for each 1674 * connector. The 16-bits are defined as: 1675 * 1676 * bits 12-15 - connector type (0 == end of table) 1677 * bits 8-11 - DDC type 1678 * bits 5-7 - ??? 1679 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1680 * bits 1-3 - ??? 1681 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1682 */ 1683 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1684 break; 1685 entry = GETBIOS16(sc, ptr + i * 2); 1686 1687 conn = (entry >> 12) & 0xf; 1688 ddc = (entry >> 8) & 0xf; 1689 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1690 RADEON_DAC_PRIMARY; 1691 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1692 RADEON_TMDS_INT; 1693 1694 if (conn == RADEON_CONN_NONE) 1695 continue; /* no connector */ 1696 1697 if ((found > 0) && 1698 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1699 /* duplicate entry for same connector */ 1700 continue; 1701 } 1702 1703 /* internal DDC_DVI port gets priority */ 1704 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1705 port = 0; 1706 else 1707 port = 1; 1708 1709 sc->sc_ports[port].rp_ddc_type = 1710 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1711 sc->sc_ports[port].rp_dac_type = dac; 1712 sc->sc_ports[port].rp_conn_type = 1713 min(conn, RADEON_CONN_UNSUPPORTED) ; 1714 1715 sc->sc_ports[port].rp_tmds_type = tmds; 1716 1717 if ((conn != RADEON_CONN_DVI_I) && 1718 (conn != RADEON_CONN_DVI_D) && 1719 (tmds == RADEON_TMDS_INT)) 1720 sc->sc_ports[port].rp_tmds_type = 1721 RADEON_TMDS_UNKNOWN; 1722 sc->sc_ports[port].rp_number = i - 1; 1723 1724 found += (port + 1); 1725 } 1726 } 1727 1728 nobios: 1729 if (!found) { 1730 DPRINTF(("No connector info in BIOS!\n")); 1731 if IS_MOBILITY(sc) { 1732 /* default, port 0 = internal TMDS, port 1 = CRT */ 1733 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1734 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1735 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1736 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1737 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1738 sc->sc_ports[0].rp_number = 0; 1739 1740 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1741 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1742 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1743 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1744 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1745 sc->sc_ports[1].rp_number = 1; 1746 } else { 1747 /* default, port 0 = DVI, port 1 = CRT */ 1748 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1749 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1750 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1751 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1752 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1753 sc->sc_ports[0].rp_number = 1; 1754 1755 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1756 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1757 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1758 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1759 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1760 sc->sc_ports[1].rp_number = 0; 1761 } 1762 } 1763 1764 /* 1765 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1766 * these chips should use TVDAC for the VGA port. 1767 */ 1768 if (HAS_SDAC(sc)) { 1769 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1770 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1771 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1772 } else { 1773 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1774 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1775 } 1776 } else if (!HAS_CRTC2(sc)) { 1777 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1778 } 1779 1780 for (i = 0; i < 2; i++) { 1781 char edid[128]; 1782 uint8_t ddc; 1783 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1784 prop_data_t edid_data; 1785 1786 DPRINTF(("Port #%d:\n", i)); 1787 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1788 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1789 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1790 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1791 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1792 1793 sc->sc_ports[i].rp_edid_valid = 0; 1794 /* first look for static EDID data */ 1795 if ((edid_data = prop_dictionary_get(device_properties( 1796 sc->sc_dev), "EDID")) != NULL) { 1797 1798 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1799 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1800 if (edid_parse(edid, eip) == 0) { 1801 1802 sc->sc_ports[i].rp_edid_valid = 1; 1803 } 1804 } 1805 /* if we didn't find any we'll try to talk to the monitor */ 1806 if (sc->sc_ports[i].rp_edid_valid != 1) { 1807 1808 ddc = sc->sc_ports[i].rp_ddc_type; 1809 if (ddc != RADEON_DDC_NONE) { 1810 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1811 == 0) && (edid_parse(edid, eip) == 0)) { 1812 1813 sc->sc_ports[i].rp_edid_valid = 1; 1814 #ifdef RADEONFB_DEBUG 1815 edid_print(eip); 1816 #endif 1817 } 1818 } 1819 } 1820 } 1821 1822 return found; 1823 } 1824 1825 int 1826 radeonfb_gettmds(struct radeonfb_softc *sc) 1827 { 1828 int i; 1829 1830 if (!sc->sc_biossz) { 1831 goto nobios; 1832 } 1833 1834 if (IS_ATOM(sc)) { 1835 /* XXX: not done yet */ 1836 } else { 1837 uint16_t ptr; 1838 int n; 1839 1840 ptr = GETBIOS16(sc, 0x48); 1841 ptr = GETBIOS16(sc, ptr + 0x34); 1842 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1843 if (GETBIOS8(sc, ptr) == 3) { 1844 /* revision three table */ 1845 n = GETBIOS8(sc, ptr + 5) + 1; 1846 n = min(n, 4); 1847 1848 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1849 for (i = 0; i < n; i++) { 1850 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1851 ptr + i * 10 + 8); 1852 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1853 ptr + i * 10 + 0x10); 1854 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1855 sc->sc_tmds_pll[i].rtp_freq, 1856 sc->sc_tmds_pll[i].rtp_pll)); 1857 } 1858 return 0; 1859 } 1860 } 1861 1862 nobios: 1863 DPRINTF(("no suitable DFP table present\n")); 1864 for (i = 0; 1865 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1866 i++) { 1867 int j; 1868 1869 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1870 continue; 1871 1872 for (j = 0; j < 4; j++) { 1873 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1874 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1875 sc->sc_tmds_pll[j].rtp_freq, 1876 sc->sc_tmds_pll[j].rtp_pll)); 1877 } 1878 return 0; 1879 } 1880 1881 return -1; 1882 } 1883 1884 const struct videomode * 1885 radeonfb_modelookup(const char *name) 1886 { 1887 int i; 1888 1889 for (i = 0; i < videomode_count; i++) 1890 if (!strcmp(name, videomode_list[i].name)) 1891 return &videomode_list[i]; 1892 1893 return NULL; 1894 } 1895 1896 void 1897 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1898 { 1899 if (crtc) { 1900 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1901 RADEON_P2PLL_ATOMIC_UPDATE_R); 1902 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1903 } else { 1904 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1905 RADEON_PPLL_ATOMIC_UPDATE_R); 1906 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1907 } 1908 } 1909 1910 void 1911 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1912 { 1913 int i; 1914 1915 for (i = 10000; i; i--) { 1916 if (crtc) { 1917 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1918 RADEON_P2PLL_ATOMIC_UPDATE_R) 1919 break; 1920 } else { 1921 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1922 RADEON_PPLL_ATOMIC_UPDATE_R) 1923 break; 1924 } 1925 } 1926 } 1927 1928 void 1929 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1930 { 1931 uint32_t pbit = 0; 1932 uint32_t feed = 0; 1933 uint32_t data, refdiv, div0; 1934 1935 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1936 1937 if (crtc == 0) { 1938 1939 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1940 if (IS_R300(sc)) { 1941 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1942 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1943 } else { 1944 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1945 sc->sc_refdiv; 1946 } 1947 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1948 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1949 RADEON_PPLL_POST3_DIV_MASK); 1950 div0 |= pbit; 1951 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1952 1953 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1954 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1955 /* 1956 * nothing to do here, the PLL is already where we 1957 * want it 1958 */ 1959 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1960 ~RADEON_PLL_DIV_SEL); 1961 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1962 return; 1963 } 1964 1965 /* alright, we do need to reprogram stuff */ 1966 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1967 RADEON_VCLK_SRC_SEL_CPUCLK, 1968 ~RADEON_VCLK_SRC_SEL_MASK); 1969 1970 /* put vclk into reset, use atomic updates */ 1971 SETPLL(sc, RADEON_PPLL_CNTL, 1972 RADEON_PPLL_REFCLK_SEL | 1973 RADEON_PPLL_FBCLK_SEL | 1974 RADEON_PPLL_RESET | 1975 RADEON_PPLL_ATOMIC_UPDATE_EN | 1976 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1977 1978 /* select clock 0 */ 1979 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1980 ~RADEON_PLL_DIV_SEL); 1981 1982 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1983 1984 /* xf86-video-radeon does this, not sure why */ 1985 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1986 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1987 1988 /* use the atomic update */ 1989 radeonfb_pllwriteupdate(sc, crtc); 1990 1991 /* and wait for it to complete */ 1992 radeonfb_pllwaitatomicread(sc, crtc); 1993 1994 /* program HTOTAL (why?) */ 1995 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1996 1997 /* drop reset */ 1998 CLRPLL(sc, RADEON_PPLL_CNTL, 1999 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2000 RADEON_PPLL_ATOMIC_UPDATE_EN | 2001 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2002 2003 PRINTPLL(RADEON_PPLL_CNTL); 2004 PRINTPLL(RADEON_PPLL_REF_DIV); 2005 PRINTPLL(RADEON_PPLL_DIV_3); 2006 2007 /* give clock time to lock */ 2008 delay(50000); 2009 2010 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2011 RADEON_VCLK_SRC_SEL_PPLLCLK, 2012 ~RADEON_VCLK_SRC_SEL_MASK); 2013 2014 } else { 2015 2016 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2017 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2018 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2019 2020 /* put vclk into reset, use atomic updates */ 2021 SETPLL(sc, RADEON_P2PLL_CNTL, 2022 RADEON_P2PLL_RESET | 2023 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2024 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2025 2026 /* program reference divider */ 2027 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2028 ~RADEON_P2PLL_REF_DIV_MASK); 2029 2030 /* program feedback and post dividers */ 2031 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2032 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2033 RADEON_P2PLL_POST0_DIV_MASK); 2034 data |= pbit; 2035 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2036 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2037 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2038 2039 PRINTPLL(RADEON_P2PLL_REF_DIV); 2040 PRINTPLL(RADEON_P2PLL_DIV_0); 2041 2042 /* use the atomic update */ 2043 radeonfb_pllwriteupdate(sc, crtc); 2044 2045 /* and wait for it to complete */ 2046 radeonfb_pllwaitatomicread(sc, crtc); 2047 2048 /* program HTOTAL (why?) */ 2049 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2050 2051 /* drop reset */ 2052 CLRPLL(sc, RADEON_P2PLL_CNTL, 2053 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2054 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2055 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2056 2057 /* allow time for clock to lock */ 2058 delay(50000); 2059 2060 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2061 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2062 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2063 } 2064 PRINTREG(RADEON_CRTC_MORE_CNTL); 2065 } 2066 2067 void 2068 radeonfb_modeswitch(struct radeonfb_display *dp) 2069 { 2070 struct radeonfb_softc *sc = dp->rd_softc; 2071 int i; 2072 2073 /* blank the display while we switch modes */ 2074 radeonfb_blank(dp, 1); 2075 2076 #if 0 2077 SET32(sc, RADEON_CRTC_EXT_CNTL, 2078 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2079 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2080 #endif 2081 2082 /* these registers might get in the way... */ 2083 PUT32(sc, RADEON_OVR_CLR, 0); 2084 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2085 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2086 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2087 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2088 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2089 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2090 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2091 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2092 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2093 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2094 2095 for (i = 0; i < dp->rd_ncrtcs; i++) 2096 radeonfb_setcrtc(dp, i); 2097 2098 /* activate the display */ 2099 radeonfb_blank(dp, 0); 2100 } 2101 2102 void 2103 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2104 { 2105 int crtc; 2106 struct videomode *mode; 2107 struct radeonfb_softc *sc; 2108 struct radeonfb_crtc *cp; 2109 uint32_t v; 2110 uint32_t gencntl; 2111 uint32_t htotaldisp; 2112 uint32_t hsyncstrt; 2113 uint32_t vtotaldisp; 2114 uint32_t vsyncstrt; 2115 uint32_t fphsyncstrt; 2116 uint32_t fpvsyncstrt; 2117 uint32_t fphtotaldisp; 2118 uint32_t fpvtotaldisp; 2119 uint32_t pitch; 2120 2121 sc = dp->rd_softc; 2122 cp = &dp->rd_crtcs[index]; 2123 crtc = cp->rc_number; 2124 mode = &cp->rc_videomode; 2125 2126 #if 1 2127 pitch = dp->rd_stride / dp->rd_bpp; 2128 #else 2129 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2130 (sc->sc_maxbpp * 8)); 2131 #endif 2132 switch (crtc) { 2133 case 0: 2134 gencntl = RADEON_CRTC_GEN_CNTL; 2135 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2136 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2137 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2138 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2139 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2140 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2141 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2142 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2143 break; 2144 case 1: 2145 gencntl = RADEON_CRTC2_GEN_CNTL; 2146 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2147 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2148 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2149 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2150 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2151 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2152 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2153 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2154 break; 2155 default: 2156 panic("Bad CRTC!"); 2157 break; 2158 } 2159 2160 /* 2161 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2162 */ 2163 /* only bother with 32bpp and 8bpp */ 2164 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2165 2166 if (crtc == 1) { 2167 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2168 } else { 2169 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2170 } 2171 2172 if (mode->flags & VID_DBLSCAN) 2173 v |= RADEON_CRTC2_DBL_SCAN_EN; 2174 2175 if (mode->flags & VID_INTERLACE) 2176 v |= RADEON_CRTC2_INTERLACE_EN; 2177 2178 if (mode->flags & VID_CSYNC) { 2179 v |= RADEON_CRTC2_CSYNC_EN; 2180 if (crtc == 1) 2181 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2182 } 2183 2184 PUT32(sc, gencntl, v); 2185 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2186 2187 /* 2188 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2189 */ 2190 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2191 if (crtc == 0) { 2192 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2193 RADEON_CRTC_DISPLAY_DIS); 2194 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2195 if (mode->flags & VID_CSYNC) 2196 v |= RADEON_CRTC_VSYNC_TRISTAT; 2197 } 2198 /* unconditional turn on CRT, in case first CRTC is DFP */ 2199 v |= RADEON_CRTC_CRT_ON; 2200 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2201 PRINTREG(RADEON_CRTC_EXT_CNTL); 2202 2203 /* 2204 * H_TOTAL_DISP 2205 */ 2206 v = ((mode->hdisplay / 8) - 1) << 16; 2207 v |= (mode->htotal / 8) - 1; 2208 PUT32(sc, htotaldisp, v); 2209 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2210 PUT32(sc, fphtotaldisp, v); 2211 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2212 2213 /* 2214 * H_SYNC_STRT_WID 2215 */ 2216 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2217 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2218 if (mode->flags & VID_NHSYNC) 2219 v |= RADEON_CRTC_H_SYNC_POL; 2220 PUT32(sc, hsyncstrt, v); 2221 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2222 PUT32(sc, fphsyncstrt, v); 2223 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2224 2225 /* 2226 * V_TOTAL_DISP 2227 */ 2228 v = ((mode->vdisplay - 1) << 16); 2229 v |= (mode->vtotal - 1); 2230 PUT32(sc, vtotaldisp, v); 2231 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2232 PUT32(sc, fpvtotaldisp, v); 2233 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2234 2235 /* 2236 * V_SYNC_STRT_WID 2237 */ 2238 v = ((mode->vsync_end - mode->vsync_start) << 16); 2239 v |= (mode->vsync_start - 1); 2240 if (mode->flags & VID_NVSYNC) 2241 v |= RADEON_CRTC_V_SYNC_POL; 2242 PUT32(sc, vsyncstrt, v); 2243 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2244 PUT32(sc, fpvsyncstrt, v); 2245 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2246 2247 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2248 2249 switch (crtc) { 2250 case 0: 2251 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2252 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2253 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2254 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2255 2256 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2257 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2258 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2259 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2260 PRINTREG(RADEON_CRTC_EXT_CNTL); 2261 PRINTREG(RADEON_CRTC_GEN_CNTL); 2262 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2263 break; 2264 2265 case 1: 2266 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2267 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2268 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2269 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2270 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2271 RADEON_CRTC2_VSYNC_DIS | 2272 RADEON_CRTC2_HSYNC_DIS | 2273 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2274 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2275 break; 2276 } 2277 } 2278 2279 int 2280 radeonfb_isblank(struct radeonfb_display *dp) 2281 { 2282 uint32_t reg, mask; 2283 2284 if(!dp->rd_softc->sc_mapped) 2285 return 1; 2286 2287 if (dp->rd_crtcs[0].rc_number) { 2288 reg = RADEON_CRTC2_GEN_CNTL; 2289 mask = RADEON_CRTC2_DISP_DIS; 2290 } else { 2291 reg = RADEON_CRTC_EXT_CNTL; 2292 mask = RADEON_CRTC_DISPLAY_DIS; 2293 } 2294 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2295 } 2296 2297 void 2298 radeonfb_blank(struct radeonfb_display *dp, int blank) 2299 { 2300 struct radeonfb_softc *sc = dp->rd_softc; 2301 uint32_t reg, mask; 2302 uint32_t fpreg, fpval; 2303 int i; 2304 2305 if (!sc->sc_mapped) 2306 return; 2307 2308 for (i = 0; i < dp->rd_ncrtcs; i++) { 2309 2310 if (dp->rd_crtcs[i].rc_number) { 2311 reg = RADEON_CRTC2_GEN_CNTL; 2312 mask = RADEON_CRTC2_DISP_DIS; 2313 fpreg = RADEON_FP2_GEN_CNTL; 2314 fpval = RADEON_FP2_ON; 2315 } else { 2316 reg = RADEON_CRTC_EXT_CNTL; 2317 mask = RADEON_CRTC_DISPLAY_DIS; 2318 fpreg = RADEON_FP_GEN_CNTL; 2319 fpval = RADEON_FP_FPON; 2320 } 2321 2322 if (blank) { 2323 SET32(sc, reg, mask); 2324 CLR32(sc, fpreg, fpval); 2325 } else { 2326 CLR32(sc, reg, mask); 2327 SET32(sc, fpreg, fpval); 2328 } 2329 } 2330 PRINTREG(RADEON_FP_GEN_CNTL); 2331 PRINTREG(RADEON_FP2_GEN_CNTL); 2332 } 2333 2334 void 2335 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2336 long *defattr) 2337 { 2338 struct radeonfb_display *dp = cookie; 2339 struct rasops_info *ri = &scr->scr_ri; 2340 2341 /* initialize font subsystem */ 2342 wsfont_init(); 2343 2344 DPRINTF(("init screen called, existing %d\n", existing)); 2345 2346 ri->ri_depth = dp->rd_bpp; 2347 ri->ri_width = dp->rd_virtx; 2348 ri->ri_height = dp->rd_virty; 2349 ri->ri_stride = dp->rd_stride; 2350 ri->ri_flg = RI_CENTER; 2351 switch (ri->ri_depth) { 2352 case 8: 2353 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2354 break; 2355 case 32: 2356 ri->ri_flg |= RI_ENABLE_ALPHA; 2357 /* we run radeons in RGB even on SPARC hardware */ 2358 ri->ri_rnum = 8; 2359 ri->ri_gnum = 8; 2360 ri->ri_bnum = 8; 2361 ri->ri_rpos = 16; 2362 ri->ri_gpos = 8; 2363 ri->ri_bpos = 0; 2364 break; 2365 } 2366 2367 ri->ri_bits = (void *)dp->rd_fbptr; 2368 2369 #ifdef VCONS_DRAW_INTR 2370 scr->scr_flags |= VCONS_DONT_READ; 2371 #endif 2372 2373 if (existing) { 2374 ri->ri_flg |= RI_CLEAR; 2375 2376 /* start a modeswitch now */ 2377 radeonfb_modeswitch(dp); 2378 } 2379 2380 /* 2381 * XXX: font selection should be based on properties, with some 2382 * normal/reasonable default. 2383 */ 2384 2385 /* initialize and look for an initial font */ 2386 rasops_init(ri, 0, 0); 2387 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2388 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2389 2390 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2391 dp->rd_virtx / ri->ri_font->fontwidth); 2392 2393 /* enable acceleration */ 2394 dp->rd_putchar = ri->ri_ops.putchar; 2395 ri->ri_ops.copyrows = radeonfb_copyrows; 2396 ri->ri_ops.copycols = radeonfb_copycols; 2397 ri->ri_ops.eraserows = radeonfb_eraserows; 2398 ri->ri_ops.erasecols = radeonfb_erasecols; 2399 /* pick a putchar method based on font and Radeon model */ 2400 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2401 /* got a bitmap font */ 2402 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2403 if (IS_R300(dp->rd_softc)) { 2404 /* 2405 * radeonfb_putchar() doesn't work right on some R3xx 2406 * so we use software drawing here, the wrapper just 2407 * makes sure the engine is idle before scribbling 2408 * into vram 2409 */ 2410 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2411 } else 2412 #endif 2413 ri->ri_ops.putchar = radeonfb_putchar; 2414 } else { 2415 /* got an alpha font */ 2416 switch(ri->ri_depth) { 2417 case 32: 2418 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2419 break; 2420 case 8: 2421 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2422 break; 2423 default: 2424 /* XXX this should never happen */ 2425 panic("%s: depth is not 8 or 32 but we got an" \ 2426 " alpha font?!", __func__); 2427 } 2428 } 2429 ri->ri_ops.cursor = radeonfb_cursor; 2430 } 2431 2432 void 2433 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2434 { 2435 uint32_t gen, ext, gen2 = 0; 2436 uint32_t agploc, aperbase, apersize, mcfbloc; 2437 2438 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2439 /* XXX */ 2440 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2441 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2442 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2443 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2444 2445 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2446 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2447 #if 0 2448 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2449 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2450 #endif 2451 2452 if (HAS_CRTC2(sc)) { 2453 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2454 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2455 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2456 } 2457 2458 delay(100000); 2459 2460 mcfbloc = (aperbase >> 16) | 2461 ((aperbase + (apersize - 1)) & 0xffff0000); 2462 2463 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2464 sc->sc_memsz = apersize; 2465 2466 if (((agploc & 0xffff) << 16) != 2467 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2468 agploc = mcfbloc & 0xffff0000U; 2469 agploc |= ((agploc + 0x10000) >> 16); 2470 } 2471 2472 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2473 2474 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2475 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2476 2477 DPRINTF(("aperbase = %u\n", aperbase)); 2478 PRINTREG(RADEON_MC_FB_LOCATION); 2479 PRINTREG(RADEON_MC_AGP_LOCATION); 2480 2481 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2482 2483 if (HAS_CRTC2(sc)) 2484 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2485 2486 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2487 2488 #if 0 2489 /* XXX: what is this AGP garbage? :-) */ 2490 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2491 #endif 2492 2493 delay(100000); 2494 2495 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2496 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2497 2498 if (HAS_CRTC2(sc)) 2499 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2500 } 2501 2502 void 2503 radeonfb_init_misc(struct radeonfb_softc *sc) 2504 { 2505 PUT32(sc, RADEON_BUS_CNTL, 2506 RADEON_BUS_MASTER_DIS | 2507 RADEON_BUS_PREFETCH_MODE_ACT | 2508 RADEON_BUS_PCI_READ_RETRY_EN | 2509 RADEON_BUS_PCI_WRT_RETRY_EN | 2510 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2511 RADEON_BUS_MSTR_RD_MULT | 2512 RADEON_BUS_MSTR_RD_LINE | 2513 RADEON_BUS_RD_DISCARD_EN | 2514 RADEON_BUS_MSTR_DISCONNECT_EN | 2515 RADEON_BUS_READ_BURST); 2516 2517 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2518 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2519 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2520 PUT32(sc, RADEON_RBBM_CNTL, 2521 (3 << RADEON_RB_SETTLE_SHIFT) | 2522 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2523 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2524 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2525 2526 /* XXX: figure out what these mean! */ 2527 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2528 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2529 #if 0 2530 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2531 #endif 2532 2533 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2534 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2535 } 2536 2537 /* 2538 * This loads a linear color map for true color. 2539 */ 2540 void 2541 radeonfb_init_palette(struct radeonfb_display *dp) 2542 { 2543 struct radeonfb_softc *sc = dp->rd_softc; 2544 int i, cc; 2545 uint32_t vclk; 2546 int crtc; 2547 2548 #define DAC_WIDTH ((1 << 10) - 1) 2549 #define CLUT_WIDTH ((1 << 8) - 1) 2550 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2551 2552 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2553 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2554 2555 /* initialize the palette for every CRTC used by this display */ 2556 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2557 crtc = dp->rd_crtcs[cc].rc_number; 2558 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2559 2560 if (crtc) 2561 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2562 else 2563 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2564 2565 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2566 2567 if (dp->rd_bpp == 8) { 2568 2569 /* R3G3B2 palette */ 2570 int j = 0; 2571 uint32_t tmp, r, g, b; 2572 2573 for (i = 0; i <= CLUT_WIDTH; ++i) { 2574 tmp = i & 0xe0; 2575 /* 2576 * replicate bits so 0xe0 maps to a red value of 0xff 2577 * in order to make white look actually white 2578 */ 2579 tmp |= (tmp >> 3) | (tmp >> 6); 2580 r = tmp; 2581 2582 tmp = (i & 0x1c) << 3; 2583 tmp |= (tmp >> 3) | (tmp >> 6); 2584 g = tmp; 2585 2586 tmp = (i & 0x03) << 6; 2587 tmp |= tmp >> 2; 2588 tmp |= tmp >> 4; 2589 b = tmp; 2590 2591 PUT32(sc, RADEON_PALETTE_30_DATA, 2592 (r << 22) | 2593 (g << 12) | 2594 (b << 2)); 2595 j += 3; 2596 } 2597 } else { 2598 /* linear ramp */ 2599 for (i = 0; i <= CLUT_WIDTH; ++i) { 2600 PUT32(sc, RADEON_PALETTE_30_DATA, 2601 (CLUT_COLOR(i) << 10) | 2602 (CLUT_COLOR(i) << 20) | 2603 (CLUT_COLOR(i))); 2604 } 2605 } 2606 } 2607 2608 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2609 PRINTREG(RADEON_DAC_CNTL2); 2610 2611 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2612 } 2613 2614 /* 2615 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2616 */ 2617 void 2618 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2619 { 2620 uint32_t tmp, save; 2621 2622 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2623 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2624 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2625 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2626 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2627 } 2628 2629 /* 2630 * Acceleration entry points. 2631 */ 2632 2633 /* this one draws characters using bitmap fonts */ 2634 static void 2635 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2636 { 2637 struct rasops_info *ri = cookie; 2638 struct vcons_screen *scr = ri->ri_hw; 2639 struct radeonfb_display *dp = scr->scr_cookie; 2640 struct radeonfb_softc *sc = dp->rd_softc; 2641 struct wsdisplay_font *font = PICK_FONT(ri, c); 2642 uint32_t w, h; 2643 int xd, yd, offset, i; 2644 uint32_t bg, fg, gmc; 2645 uint32_t reg; 2646 uint8_t *data8; 2647 uint16_t *data16; 2648 void *data; 2649 2650 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2651 return; 2652 2653 if (!CHAR_IN_FONT(c, font)) 2654 return; 2655 2656 w = font->fontwidth; 2657 h = font->fontheight; 2658 2659 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2660 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2661 2662 xd = ri->ri_xorigin + col * w; 2663 yd = ri->ri_yorigin + row * h; 2664 2665 if (c == 0x20) { 2666 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2667 return; 2668 } 2669 data = WSFONT_GLYPH(c, font); 2670 2671 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2672 2673 radeonfb_wait_fifo(sc, 9); 2674 2675 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2676 RADEON_GMC_BRUSH_NONE | 2677 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2678 RADEON_GMC_DST_CLIPPING | 2679 RADEON_ROP3_S | 2680 RADEON_DP_SRC_SOURCE_HOST_DATA | 2681 RADEON_GMC_CLR_CMP_CNTL_DIS | 2682 RADEON_GMC_WR_MSK_DIS | 2683 gmc); 2684 2685 PUT32(sc, RADEON_SC_LEFT, xd); 2686 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2687 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2688 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2689 PUT32(sc, RADEON_DP_CNTL, 2690 RADEON_DST_X_LEFT_TO_RIGHT | 2691 RADEON_DST_Y_TOP_TO_BOTTOM); 2692 2693 PUT32(sc, RADEON_SRC_X_Y, 0); 2694 offset = 32 - (font->stride << 3); 2695 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2696 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2697 2698 radeonfb_wait_fifo(sc, h); 2699 switch (font->stride) { 2700 case 1: { 2701 data8 = data; 2702 for (i = 0; i < h; i++) { 2703 reg = *data8; 2704 #if BYTE_ORDER == LITTLE_ENDIAN 2705 reg = reg << 24; 2706 #endif 2707 bus_space_write_stream_4(sc->sc_regt, 2708 sc->sc_regh, RADEON_HOST_DATA0, reg); 2709 data8++; 2710 } 2711 break; 2712 } 2713 case 2: { 2714 data16 = data; 2715 for (i = 0; i < h; i++) { 2716 reg = *data16; 2717 #if BYTE_ORDER == LITTLE_ENDIAN 2718 reg = reg << 16; 2719 #endif 2720 bus_space_write_stream_4(sc->sc_regt, 2721 sc->sc_regh, RADEON_HOST_DATA0, reg); 2722 data16++; 2723 } 2724 break; 2725 } 2726 } 2727 if (attr & 1) 2728 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2729 } 2730 2731 /* ... while this one is for anti-aliased ones */ 2732 static void 2733 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2734 { 2735 struct rasops_info *ri = cookie; 2736 struct vcons_screen *scr = ri->ri_hw; 2737 struct radeonfb_display *dp = scr->scr_cookie; 2738 struct radeonfb_softc *sc = dp->rd_softc; 2739 struct wsdisplay_font *font = PICK_FONT(ri, c); 2740 uint32_t bg, fg, gmc; 2741 uint8_t *data; 2742 int w, h, xd, yd; 2743 int i, r, g, b, aval; 2744 int rf, gf, bf, rb, gb, bb; 2745 uint32_t pixel; 2746 int rv; 2747 2748 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2749 return; 2750 2751 if (!CHAR_IN_FONT(c, font)) 2752 return; 2753 2754 w = font->fontwidth; 2755 h = font->fontheight; 2756 2757 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2758 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2759 2760 xd = ri->ri_xorigin + col * w; 2761 yd = ri->ri_yorigin + row * h; 2762 2763 if (c == 0x20) { 2764 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2765 if (attr & 1) 2766 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2767 return; 2768 } 2769 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2770 if (rv == GC_OK) 2771 return; 2772 2773 data = WSFONT_GLYPH(c, font); 2774 2775 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2776 2777 radeonfb_wait_fifo(sc, 5); 2778 2779 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2780 RADEON_GMC_BRUSH_NONE | 2781 RADEON_GMC_SRC_DATATYPE_COLOR | 2782 RADEON_ROP3_S | 2783 RADEON_DP_SRC_SOURCE_HOST_DATA | 2784 RADEON_GMC_CLR_CMP_CNTL_DIS | 2785 RADEON_GMC_WR_MSK_DIS | 2786 gmc); 2787 2788 PUT32(sc, RADEON_DP_CNTL, 2789 RADEON_DST_X_LEFT_TO_RIGHT | 2790 RADEON_DST_Y_TOP_TO_BOTTOM); 2791 2792 PUT32(sc, RADEON_SRC_X_Y, 0); 2793 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2794 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2795 2796 rf = (fg >> 16) & 0xff; 2797 rb = (bg >> 16) & 0xff; 2798 gf = (fg >> 8) & 0xff; 2799 gb = (bg >> 8) & 0xff; 2800 bf = fg & 0xff; 2801 bb = bg & 0xff; 2802 2803 /* 2804 * I doubt we can upload data faster than even the slowest Radeon 2805 * could process them, especially when doing the alpha blending stuff 2806 * along the way, so just make sure there's some room in the FIFO and 2807 * then hammer away 2808 * As it turns out we can, so make periodic stops to let the FIFO 2809 * drain. 2810 */ 2811 radeonfb_wait_fifo(sc, 20); 2812 for (i = 0; i < ri->ri_fontscale; i++) { 2813 aval = *data; 2814 data++; 2815 if (aval == 0) { 2816 pixel = bg; 2817 } else if (aval == 255) { 2818 pixel = fg; 2819 } else { 2820 r = aval * rf + (255 - aval) * rb; 2821 g = aval * gf + (255 - aval) * gb; 2822 b = aval * bf + (255 - aval) * bb; 2823 pixel = (r & 0xff00) << 8 | 2824 (g & 0xff00) | 2825 (b & 0xff00) >> 8; 2826 } 2827 if (i & 16) 2828 radeonfb_wait_fifo(sc, 20); 2829 PUT32(sc, RADEON_HOST_DATA0, pixel); 2830 } 2831 if (rv == GC_ADD) { 2832 glyphcache_add(&dp->rd_gc, c, xd, yd); 2833 } else 2834 if (attr & 1) 2835 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2836 2837 } 2838 2839 static void 2840 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2841 { 2842 struct rasops_info *ri = cookie; 2843 struct vcons_screen *scr = ri->ri_hw; 2844 struct radeonfb_display *dp = scr->scr_cookie; 2845 struct radeonfb_softc *sc = dp->rd_softc; 2846 struct wsdisplay_font *font = PICK_FONT(ri, c); 2847 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2848 int i, x, y, wi, he, r, g, b, aval; 2849 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2850 uint8_t *data8; 2851 int rv, cnt; 2852 2853 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2854 return; 2855 2856 if (!CHAR_IN_FONT(c, font)) 2857 return; 2858 2859 wi = font->fontwidth; 2860 he = font->fontheight; 2861 2862 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2863 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2864 2865 x = ri->ri_xorigin + col * wi; 2866 y = ri->ri_yorigin + row * he; 2867 2868 if (c == 0x20) { 2869 radeonfb_rectfill(dp, x, y, wi, he, bg); 2870 if (attr & 1) 2871 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2872 return; 2873 } 2874 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2875 if (rv == GC_OK) 2876 return; 2877 2878 data8 = WSFONT_GLYPH(c, font); 2879 2880 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2881 2882 radeonfb_wait_fifo(sc, 5); 2883 2884 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2885 RADEON_GMC_BRUSH_NONE | 2886 RADEON_GMC_SRC_DATATYPE_COLOR | 2887 RADEON_ROP3_S | 2888 RADEON_DP_SRC_SOURCE_HOST_DATA | 2889 RADEON_GMC_CLR_CMP_CNTL_DIS | 2890 RADEON_GMC_WR_MSK_DIS | 2891 gmc); 2892 2893 PUT32(sc, RADEON_DP_CNTL, 2894 RADEON_DST_X_LEFT_TO_RIGHT | 2895 RADEON_DST_Y_TOP_TO_BOTTOM); 2896 2897 PUT32(sc, RADEON_SRC_X_Y, 0); 2898 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2899 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2900 2901 /* 2902 * we need the RGB colours here, so get offsets into rasops_cmap 2903 */ 2904 fgo = ((attr >> 24) & 0xf) * 3; 2905 bgo = ((attr >> 16) & 0xf) * 3; 2906 2907 r0 = rasops_cmap[bgo]; 2908 r1 = rasops_cmap[fgo]; 2909 g0 = rasops_cmap[bgo + 1]; 2910 g1 = rasops_cmap[fgo + 1]; 2911 b0 = rasops_cmap[bgo + 2]; 2912 b1 = rasops_cmap[fgo + 2]; 2913 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2914 bg8 = R3G3B2(r0, g0, b0); 2915 fg8 = R3G3B2(r1, g1, b1); 2916 2917 radeonfb_wait_fifo(sc, 20); 2918 cnt = 0; 2919 for (i = 0; i < ri->ri_fontscale; i++) { 2920 aval = *data8; 2921 if (aval == 0) { 2922 pixel = bg8; 2923 } else if (aval == 255) { 2924 pixel = fg8; 2925 } else { 2926 r = aval * r1 + (255 - aval) * r0; 2927 g = aval * g1 + (255 - aval) * g0; 2928 b = aval * b1 + (255 - aval) * b0; 2929 pixel = ((r & 0xe000) >> 8) | 2930 ((g & 0xe000) >> 11) | 2931 ((b & 0xc000) >> 14); 2932 } 2933 latch |= pixel << (8 * (i & 3)); 2934 /* write in 32bit chunks */ 2935 if ((i & 3) == 3) { 2936 PUT32(sc, RADEON_HOST_DATA0, latch); 2937 /* 2938 * not strictly necessary, old data should be shifted 2939 * out 2940 */ 2941 latch = 0; 2942 cnt++; 2943 if (cnt > 16) { 2944 cnt = 0; 2945 radeonfb_wait_fifo(sc, 20); 2946 } 2947 } 2948 data8++; 2949 } 2950 /* if we have pixels left in latch write them out */ 2951 if ((i & 3) != 0) { 2952 /* 2953 * radeon is weird - apparently leftover pixels are written 2954 * from the middle, not from the left as everything else 2955 */ 2956 PUT32(sc, RADEON_HOST_DATA0, latch); 2957 } 2958 2959 if (rv == GC_ADD) { 2960 glyphcache_add(&dp->rd_gc, c, x, y); 2961 } else 2962 if (attr & 1) 2963 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2964 2965 } 2966 2967 /* 2968 * wrapper for software character drawing 2969 * just sync the engine and call rasops*_putchar() 2970 */ 2971 2972 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2973 static void 2974 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2975 { 2976 struct rasops_info *ri = cookie; 2977 struct vcons_screen *scr = ri->ri_hw; 2978 struct radeonfb_display *dp = scr->scr_cookie; 2979 2980 radeonfb_engine_idle(dp->rd_softc); 2981 dp->rd_putchar(ri, row, col, c, attr); 2982 } 2983 #endif 2984 2985 static void 2986 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2987 { 2988 struct rasops_info *ri = cookie; 2989 struct vcons_screen *scr = ri->ri_hw; 2990 struct radeonfb_display *dp = scr->scr_cookie; 2991 uint32_t x, y, w, h, fg, bg, ul; 2992 2993 /* XXX: check for full emulation mode? */ 2994 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2995 x = ri->ri_xorigin; 2996 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2997 w = ri->ri_emuwidth; 2998 h = ri->ri_font->fontheight * nrows; 2999 3000 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3001 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3002 } 3003 } 3004 3005 static void 3006 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3007 { 3008 struct rasops_info *ri = cookie; 3009 struct vcons_screen *scr = ri->ri_hw; 3010 struct radeonfb_display *dp = scr->scr_cookie; 3011 uint32_t x, ys, yd, w, h; 3012 3013 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3014 x = ri->ri_xorigin; 3015 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3016 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3017 w = ri->ri_emuwidth; 3018 h = ri->ri_font->fontheight * nrows; 3019 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3020 RADEON_ROP3_S); 3021 } 3022 } 3023 3024 static void 3025 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3026 { 3027 struct rasops_info *ri = cookie; 3028 struct vcons_screen *scr = ri->ri_hw; 3029 struct radeonfb_display *dp = scr->scr_cookie; 3030 uint32_t xs, xd, y, w, h; 3031 3032 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3033 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3034 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3035 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3036 w = ri->ri_font->fontwidth * ncols; 3037 h = ri->ri_font->fontheight; 3038 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3039 RADEON_ROP3_S); 3040 } 3041 } 3042 3043 static void 3044 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3045 long fillattr) 3046 { 3047 struct rasops_info *ri = cookie; 3048 struct vcons_screen *scr = ri->ri_hw; 3049 struct radeonfb_display *dp = scr->scr_cookie; 3050 uint32_t x, y, w, h, fg, bg, ul; 3051 3052 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3053 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3054 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3055 w = ri->ri_font->fontwidth * ncols; 3056 h = ri->ri_font->fontheight; 3057 3058 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3059 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3060 } 3061 } 3062 3063 static void 3064 radeonfb_cursor(void *cookie, int on, int row, int col) 3065 { 3066 struct rasops_info *ri = cookie; 3067 struct vcons_screen *scr = ri->ri_hw; 3068 struct radeonfb_display *dp = scr->scr_cookie; 3069 int x, y, wi, he; 3070 3071 wi = ri->ri_font->fontwidth; 3072 he = ri->ri_font->fontheight; 3073 3074 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3075 x = ri->ri_ccol * wi + ri->ri_xorigin; 3076 y = ri->ri_crow * he + ri->ri_yorigin; 3077 /* first turn off the old cursor */ 3078 if (ri->ri_flg & RI_CURSOR) { 3079 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3080 RADEON_ROP3_Dn); 3081 ri->ri_flg &= ~RI_CURSOR; 3082 } 3083 ri->ri_crow = row; 3084 ri->ri_ccol = col; 3085 /* then (possibly) turn on the new one */ 3086 if (on) { 3087 x = ri->ri_ccol * wi + ri->ri_xorigin; 3088 y = ri->ri_crow * he + ri->ri_yorigin; 3089 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3090 RADEON_ROP3_Dn); 3091 ri->ri_flg |= RI_CURSOR; 3092 } 3093 } else { 3094 scr->scr_ri.ri_crow = row; 3095 scr->scr_ri.ri_ccol = col; 3096 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3097 } 3098 } 3099 3100 /* 3101 * Underlying acceleration support. 3102 */ 3103 3104 static void 3105 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3106 int width, int height, uint32_t color) 3107 { 3108 struct radeonfb_softc *sc = dp->rd_softc; 3109 uint32_t gmc; 3110 3111 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3112 3113 radeonfb_wait_fifo(sc, 6); 3114 3115 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3116 RADEON_GMC_BRUSH_SOLID_COLOR | 3117 RADEON_GMC_SRC_DATATYPE_COLOR | 3118 RADEON_GMC_CLR_CMP_CNTL_DIS | 3119 RADEON_ROP3_P | gmc); 3120 3121 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3122 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3123 PUT32(sc, RADEON_DP_CNTL, 3124 RADEON_DST_X_LEFT_TO_RIGHT | 3125 RADEON_DST_Y_TOP_TO_BOTTOM); 3126 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3127 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3128 3129 } 3130 3131 static void 3132 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3133 int width, int height, long attr) 3134 { 3135 struct radeonfb_display *dp = cookie; 3136 3137 radeonfb_rectfill(dp, dstx, dsty, width, height, 3138 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3139 } 3140 3141 static void 3142 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3143 int dstx, int dsty, int width, int height, int rop) 3144 { 3145 struct radeonfb_display *dp = cookie; 3146 struct radeonfb_softc *sc = dp->rd_softc; 3147 uint32_t gmc; 3148 uint32_t dir; 3149 3150 if (dsty < srcy) { 3151 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3152 } else { 3153 srcy += height - 1; 3154 dsty += height - 1; 3155 dir = 0; 3156 } 3157 if (dstx < srcx) { 3158 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3159 } else { 3160 srcx += width - 1; 3161 dstx += width - 1; 3162 } 3163 3164 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3165 3166 radeonfb_wait_fifo(sc, 6); 3167 3168 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3169 RADEON_GMC_BRUSH_SOLID_COLOR | 3170 RADEON_GMC_SRC_DATATYPE_COLOR | 3171 RADEON_GMC_CLR_CMP_CNTL_DIS | 3172 RADEON_DP_SRC_SOURCE_MEMORY | 3173 rop | gmc); 3174 3175 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3176 PUT32(sc, RADEON_DP_CNTL, dir); 3177 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3178 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3179 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3180 } 3181 3182 static void 3183 radeonfb_engine_idle(struct radeonfb_softc *sc) 3184 { 3185 3186 radeonfb_wait_fifo(sc, 64); 3187 while ((GET32(sc, RADEON_RBBM_STATUS) & 3188 RADEON_RBBM_ACTIVE) != 0); 3189 radeonfb_engine_flush(sc); 3190 } 3191 3192 static inline void 3193 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3194 { 3195 int i; 3196 3197 for (i = RADEON_TIMEOUT; i; i--) { 3198 if ((GET32(sc, RADEON_RBBM_STATUS) & 3199 RADEON_RBBM_FIFOCNT_MASK) >= n) 3200 return; 3201 } 3202 #ifdef DIAGNOSTIC 3203 if (!i) 3204 printf("%s: timed out waiting for fifo (%x)\n", 3205 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3206 #endif 3207 } 3208 3209 static void 3210 radeonfb_engine_flush(struct radeonfb_softc *sc) 3211 { 3212 int i = 0; 3213 3214 if (IS_R300(sc)) { 3215 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3216 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3217 i++; 3218 } 3219 } else { 3220 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3221 RADEON_RB2D_DC_FLUSH_ALL); 3222 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3223 RADEON_RB2D_DC_BUSY) { 3224 i++; 3225 } 3226 } 3227 #ifdef DIAGNOSTIC 3228 if (i > RADEON_TIMEOUT) 3229 printf("%s: engine flush timed out!\n", XNAME(sc)); 3230 #endif 3231 } 3232 3233 static inline void 3234 radeonfb_unclip(struct radeonfb_softc *sc) 3235 { 3236 3237 radeonfb_wait_fifo(sc, 2); 3238 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3239 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3240 } 3241 3242 static void 3243 radeonfb_engine_init(struct radeonfb_display *dp) 3244 { 3245 struct radeonfb_softc *sc = dp->rd_softc; 3246 uint32_t pitch; 3247 volatile uint32_t junk; 3248 3249 /* no 3D */ 3250 PUT32(sc, RADEON_RB3D_CNTL, 0); 3251 3252 radeonfb_engine_reset(sc); 3253 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3254 3255 radeonfb_wait_fifo(sc, 1); 3256 if (!IS_R300(sc)) 3257 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3258 3259 radeonfb_wait_fifo(sc, 3); 3260 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3261 (pitch << 22) | (sc->sc_aperbase >> 10)); 3262 3263 3264 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3265 (pitch << 22) | (sc->sc_aperbase >> 10)); 3266 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3267 (pitch << 22) | (sc->sc_aperbase >> 10)); 3268 3269 junk = GET32(sc, RADEON_DP_DATATYPE); 3270 3271 /* default scissors -- no clipping */ 3272 radeonfb_wait_fifo(sc, 1); 3273 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3274 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3275 3276 radeonfb_wait_fifo(sc, 1); 3277 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3278 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3279 RADEON_GMC_CLR_CMP_CNTL_DIS | 3280 RADEON_GMC_BRUSH_SOLID_COLOR | 3281 RADEON_GMC_SRC_DATATYPE_COLOR); 3282 3283 radeonfb_wait_fifo(sc, 10); 3284 PUT32(sc, RADEON_DST_LINE_START, 0); 3285 PUT32(sc, RADEON_DST_LINE_END, 0); 3286 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3287 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3288 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3289 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3290 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3291 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3292 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3293 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3294 radeonfb_engine_idle(sc); 3295 } 3296 3297 static void 3298 radeonfb_engine_reset(struct radeonfb_softc *sc) 3299 { 3300 uint32_t hpc, rbbm, mclkcntl, clkindex; 3301 3302 radeonfb_engine_flush(sc); 3303 3304 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3305 if (HAS_R300CG(sc)) 3306 radeonfb_r300cg_workaround(sc); 3307 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3308 3309 /* 3310 * According to comments in XFree code, resetting the HDP via 3311 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3312 * So we use HOST_PATH_CNTL instead. 3313 */ 3314 3315 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3316 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3317 if (IS_R300(sc)) { 3318 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3319 RADEON_SOFT_RESET_CP | 3320 RADEON_SOFT_RESET_HI | 3321 RADEON_SOFT_RESET_E2); 3322 GET32(sc, RADEON_RBBM_SOFT_RESET); 3323 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3324 /* 3325 * XXX: this bit is not defined in any ATI docs I have, 3326 * nor in the XFree code, but XFree does it. Why? 3327 */ 3328 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3329 } else { 3330 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3331 RADEON_SOFT_RESET_CP | 3332 RADEON_SOFT_RESET_SE | 3333 RADEON_SOFT_RESET_RE | 3334 RADEON_SOFT_RESET_PP | 3335 RADEON_SOFT_RESET_E2 | 3336 RADEON_SOFT_RESET_RB); 3337 GET32(sc, RADEON_RBBM_SOFT_RESET); 3338 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3339 ~(RADEON_SOFT_RESET_CP | 3340 RADEON_SOFT_RESET_SE | 3341 RADEON_SOFT_RESET_RE | 3342 RADEON_SOFT_RESET_PP | 3343 RADEON_SOFT_RESET_E2 | 3344 RADEON_SOFT_RESET_RB)); 3345 GET32(sc, RADEON_RBBM_SOFT_RESET); 3346 } 3347 3348 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3349 GET32(sc, RADEON_HOST_PATH_CNTL); 3350 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3351 3352 if (IS_R300(sc)) 3353 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3354 3355 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3356 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3357 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3358 3359 if (HAS_R300CG(sc)) 3360 radeonfb_r300cg_workaround(sc); 3361 } 3362 3363 static int 3364 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3365 { 3366 int x, y; 3367 3368 x = pos->x; 3369 y = pos->y; 3370 3371 /* 3372 * This doesn't let a cursor move off the screen. I'm not 3373 * sure if this will have negative effects for e.g. Xinerama. 3374 * I'd guess Xinerama handles it by changing the cursor shape, 3375 * but that needs verification. 3376 */ 3377 if (x >= dp->rd_virtx) 3378 x = dp->rd_virtx - 1; 3379 if (x < 0) 3380 x = 0; 3381 if (y >= dp->rd_virty) 3382 y = dp->rd_virty - 1; 3383 if (y < 0) 3384 y = 0; 3385 3386 dp->rd_cursor.rc_pos.x = x; 3387 dp->rd_cursor.rc_pos.y = y; 3388 3389 radeonfb_cursor_position(dp); 3390 return 0; 3391 } 3392 3393 static int 3394 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3395 { 3396 unsigned flags; 3397 3398 uint8_t r[2], g[2], b[2]; 3399 unsigned index, count; 3400 int i, err; 3401 int pitch, size; 3402 struct radeonfb_cursor nc; 3403 3404 flags = wc->which; 3405 3406 /* copy old values */ 3407 nc = dp->rd_cursor; 3408 3409 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3410 index = wc->cmap.index; 3411 count = wc->cmap.count; 3412 3413 if (index >= 2 || (index + count) > 2) 3414 return EINVAL; 3415 3416 err = copyin(wc->cmap.red, &r[index], count); 3417 if (err) 3418 return err; 3419 err = copyin(wc->cmap.green, &g[index], count); 3420 if (err) 3421 return err; 3422 err = copyin(wc->cmap.blue, &b[index], count); 3423 if (err) 3424 return err; 3425 3426 for (i = index; i < index + count; i++) { 3427 nc.rc_cmap[i] = 3428 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3429 } 3430 } 3431 3432 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3433 if ((wc->size.x > RADEON_CURSORMAXX) || 3434 (wc->size.y > RADEON_CURSORMAXY)) 3435 return EINVAL; 3436 3437 /* figure bytes per line */ 3438 pitch = (wc->size.x + 7) / 8; 3439 size = pitch * wc->size.y; 3440 3441 /* clear the old cursor and mask */ 3442 memset(nc.rc_image, 0, 512); 3443 memset(nc.rc_mask, 0, 512); 3444 3445 nc.rc_size = wc->size; 3446 3447 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3448 return err; 3449 3450 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3451 return err; 3452 } 3453 3454 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3455 nc.rc_hot = wc->hot; 3456 if (nc.rc_hot.x >= nc.rc_size.x) 3457 nc.rc_hot.x = nc.rc_size.x - 1; 3458 if (nc.rc_hot.y >= nc.rc_size.y) 3459 nc.rc_hot.y = nc.rc_size.y - 1; 3460 } 3461 3462 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3463 nc.rc_pos = wc->pos; 3464 if (nc.rc_pos.x >= dp->rd_virtx) 3465 nc.rc_pos.x = dp->rd_virtx - 1; 3466 #if 0 3467 if (nc.rc_pos.x < 0) 3468 nc.rc_pos.x = 0; 3469 #endif 3470 if (nc.rc_pos.y >= dp->rd_virty) 3471 nc.rc_pos.y = dp->rd_virty - 1; 3472 #if 0 3473 if (nc.rc_pos.y < 0) 3474 nc.rc_pos.y = 0; 3475 #endif 3476 } 3477 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3478 nc.rc_visible = wc->enable; 3479 } 3480 3481 dp->rd_cursor = nc; 3482 radeonfb_cursor_update(dp, wc->which); 3483 3484 return 0; 3485 } 3486 3487 /* 3488 * Change the cursor shape. Call this with the cursor locked to avoid 3489 * flickering/tearing. 3490 */ 3491 static void 3492 radeonfb_cursor_shape(struct radeonfb_display *dp) 3493 { 3494 uint8_t and[512], xor[512]; 3495 int i, j, src, dst, pitch; 3496 const uint8_t *msk = dp->rd_cursor.rc_mask; 3497 const uint8_t *img = dp->rd_cursor.rc_image; 3498 3499 /* 3500 * Radeon cursor data interleaves one line of AND data followed 3501 * by a line of XOR data. (Each line corresponds to a whole hardware 3502 * pitch - i.e. 64 pixels or 8 bytes.) 3503 * 3504 * The cursor is displayed using the following table: 3505 * 3506 * AND XOR Result 3507 * ---------------------- 3508 * 0 0 Cursor color 0 3509 * 0 1 Cursor color 1 3510 * 1 0 Transparent 3511 * 1 1 Complement of background 3512 * 3513 * Our masks are therefore different from what we were passed. 3514 * Passed in, I'm assuming the data represents either color 0 or 1, 3515 * and a mask, so the passed in table looks like: 3516 * 3517 * IMG Mask Result 3518 * ----------------------- 3519 * 0 0 Transparent 3520 * 0 1 Cursor color 0 3521 * 1 0 Transparent 3522 * 1 1 Cursor color 1 3523 * 3524 * IF mask bit == 1, AND = 0, XOR = color. 3525 * IF mask bit == 0, AND = 1, XOR = 0. 3526 * 3527 * hence: AND = ~(mask); XOR = color & ~(mask); 3528 */ 3529 3530 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 3531 3532 /* start by assuming all bits are transparent */ 3533 memset(and, 0xff, 512); 3534 memset(xor, 0x00, 512); 3535 3536 src = 0; 3537 dst = 0; 3538 for (i = 0; i < 64; i++) { 3539 for (j = 0; j < 64; j += 8) { 3540 if ((i < dp->rd_cursor.rc_size.y) && 3541 (j < dp->rd_cursor.rc_size.x)) { 3542 3543 /* take care to leave odd bits alone */ 3544 and[dst] &= ~(msk[src]); 3545 xor[dst] = img[src] & msk[src]; 3546 src++; 3547 } 3548 dst++; 3549 } 3550 } 3551 3552 /* copy the image into place */ 3553 for (i = 0; i < 64; i++) { 3554 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3555 &and[i * 8], 8); 3556 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3557 &xor[i * 8], 8); 3558 } 3559 } 3560 3561 static void 3562 radeonfb_cursor_position(struct radeonfb_display *dp) 3563 { 3564 struct radeonfb_softc *sc = dp->rd_softc; 3565 uint32_t offset, hvoff, hvpos; /* registers */ 3566 uint32_t coff; /* cursor offset */ 3567 int i, x, y, xoff, yoff, crtcoff; 3568 3569 /* 3570 * XXX: this also needs to handle pan/scan 3571 */ 3572 for (i = 0; i < dp->rd_ncrtcs; i++) { 3573 3574 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3575 3576 if (rcp->rc_number) { 3577 offset = RADEON_CUR2_OFFSET; 3578 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3579 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3580 crtcoff = RADEON_CRTC2_OFFSET; 3581 } else { 3582 offset = RADEON_CUR_OFFSET; 3583 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3584 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3585 crtcoff = RADEON_CRTC_OFFSET; 3586 } 3587 3588 x = dp->rd_cursor.rc_pos.x; 3589 y = dp->rd_cursor.rc_pos.y; 3590 3591 while (y < rcp->rc_yoffset) { 3592 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3593 } 3594 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3595 rcp->rc_yoffset += RADEON_PANINCREMENT; 3596 } 3597 while (x < rcp->rc_xoffset) { 3598 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3599 } 3600 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3601 rcp->rc_xoffset += RADEON_PANINCREMENT; 3602 } 3603 3604 /* adjust for the cursor's hotspot */ 3605 x -= dp->rd_cursor.rc_hot.x; 3606 y -= dp->rd_cursor.rc_hot.y; 3607 xoff = yoff = 0; 3608 3609 if (x >= dp->rd_virtx) 3610 x = dp->rd_virtx - 1; 3611 if (y >= dp->rd_virty) 3612 y = dp->rd_virty - 1; 3613 3614 /* now adjust cursor so it is relative to viewport */ 3615 x -= rcp->rc_xoffset; 3616 y -= rcp->rc_yoffset; 3617 3618 /* 3619 * no need to check for fall off, because we should 3620 * never move off the screen entirely! 3621 */ 3622 coff = 0; 3623 if (x < 0) { 3624 xoff = -x; 3625 x = 0; 3626 } 3627 if (y < 0) { 3628 yoff = -y; 3629 y = 0; 3630 coff = (yoff * 2) * 8; 3631 } 3632 3633 /* pan the display */ 3634 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3635 rcp->rc_xoffset); 3636 3637 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3638 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3639 /* NB: this unlocks the cursor */ 3640 PUT32(sc, hvpos, (x << 16) | y); 3641 } 3642 } 3643 3644 static void 3645 radeonfb_cursor_visible(struct radeonfb_display *dp) 3646 { 3647 int i; 3648 uint32_t gencntl, bit; 3649 3650 for (i = 0; i < dp->rd_ncrtcs; i++) { 3651 if (dp->rd_crtcs[i].rc_number) { 3652 gencntl = RADEON_CRTC2_GEN_CNTL; 3653 bit = RADEON_CRTC2_CUR_EN; 3654 } else { 3655 gencntl = RADEON_CRTC_GEN_CNTL; 3656 bit = RADEON_CRTC_CUR_EN; 3657 } 3658 3659 if (dp->rd_cursor.rc_visible) 3660 SET32(dp->rd_softc, gencntl, bit); 3661 else 3662 CLR32(dp->rd_softc, gencntl, bit); 3663 } 3664 } 3665 3666 static void 3667 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3668 { 3669 int i; 3670 uint32_t c0reg, c1reg; 3671 struct radeonfb_softc *sc = dp->rd_softc; 3672 3673 for (i = 0; i < dp->rd_ncrtcs; i++) { 3674 if (dp->rd_crtcs[i].rc_number) { 3675 c0reg = RADEON_CUR2_CLR0; 3676 c1reg = RADEON_CUR2_CLR1; 3677 } else { 3678 c0reg = RADEON_CUR_CLR0; 3679 c1reg = RADEON_CUR_CLR1; 3680 } 3681 3682 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3683 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3684 } 3685 } 3686 3687 static void 3688 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3689 { 3690 struct radeonfb_softc *sc; 3691 int i; 3692 3693 sc = dp->rd_softc; 3694 for (i = 0; i < dp->rd_ncrtcs; i++) { 3695 if (dp->rd_crtcs[i].rc_number) { 3696 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3697 } else { 3698 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3699 } 3700 } 3701 3702 if (which & WSDISPLAY_CURSOR_DOCMAP) 3703 radeonfb_cursor_cmap(dp); 3704 3705 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3706 radeonfb_cursor_shape(dp); 3707 3708 if (which & WSDISPLAY_CURSOR_DOCUR) 3709 radeonfb_cursor_visible(dp); 3710 3711 /* this one is unconditional, because it updates other stuff */ 3712 radeonfb_cursor_position(dp); 3713 } 3714 3715 static struct videomode * 3716 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3717 { 3718 int r1, r2; 3719 3720 /* otherwise pick the higher refresh rate */ 3721 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3722 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3723 3724 return (r1 < r2 ? m2 : m1); 3725 } 3726 3727 static const struct videomode * 3728 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3729 int x, int y) 3730 { 3731 struct edid_info *ep = &rp->rp_edid; 3732 struct videomode *vmp = NULL; 3733 int i; 3734 3735 if (!rp->rp_edid_valid) { 3736 /* fallback to safe mode */ 3737 return radeonfb_modelookup(sc->sc_defaultmode); 3738 } 3739 3740 /* always choose the preferred mode first! */ 3741 if (ep->edid_preferred_mode) { 3742 3743 /* XXX: add auto-stretching support for native mode */ 3744 3745 /* this may want panning to occur, btw */ 3746 if ((ep->edid_preferred_mode->hdisplay <= x) && 3747 (ep->edid_preferred_mode->vdisplay <= y)) 3748 return ep->edid_preferred_mode; 3749 } 3750 3751 for (i = 0; i < ep->edid_nmodes; i++) { 3752 /* 3753 * We elect to pick a resolution that is too large for 3754 * the monitor than one that is too small. This means 3755 * that we will prefer to pan rather than to try to 3756 * center a smaller display on a larger screen. In 3757 * practice, this shouldn't matter because if a 3758 * monitor can support a larger resolution, it can 3759 * probably also support the smaller. A specific 3760 * exception is fixed format panels, but hopefully 3761 * they are properly dealt with by the "autostretch" 3762 * logic above. 3763 */ 3764 if ((ep->edid_modes[i].hdisplay > x) || 3765 (ep->edid_modes[i].vdisplay > y)) { 3766 continue; 3767 } 3768 3769 /* 3770 * at this point, the display mode is no larger than 3771 * what we've requested. 3772 */ 3773 if (vmp == NULL) 3774 vmp = &ep->edid_modes[i]; 3775 3776 /* eliminate smaller modes */ 3777 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3778 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3779 continue; 3780 3781 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3782 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3783 vmp = &ep->edid_modes[i]; 3784 continue; 3785 } 3786 3787 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3788 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3789 3790 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3791 } 3792 3793 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3794 } 3795 3796 static int 3797 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3798 { 3799 int i; 3800 3801 for (i = 0; i < nlist; i++) { 3802 if ((x == list[i].hdisplay) && 3803 (y == list[i].vdisplay)) { 3804 return 1; 3805 } 3806 } 3807 return 0; 3808 } 3809 3810 static void 3811 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3812 int pan) 3813 { 3814 struct radeonfb_port *rp; 3815 struct edid_info *ep; 3816 int i, j; 3817 3818 *x = 0; 3819 *y = 0; 3820 3821 if (pan) { 3822 for (i = 0; i < dp->rd_ncrtcs; i++) { 3823 rp = dp->rd_crtcs[i].rc_port; 3824 ep = &rp->rp_edid; 3825 if (!rp->rp_edid_valid) { 3826 /* monitor not present */ 3827 continue; 3828 } 3829 3830 /* 3831 * For now we are ignoring "conflict" that 3832 * could occur when mixing some modes like 3833 * 1280x1024 and 1400x800. It isn't clear 3834 * which is better, so the first one wins. 3835 */ 3836 for (j = 0; j < ep->edid_nmodes; j++) { 3837 /* 3838 * ignore resolutions that are too big for 3839 * the radeon 3840 */ 3841 if (ep->edid_modes[j].hdisplay > 3842 dp->rd_softc->sc_maxx) 3843 continue; 3844 if (ep->edid_modes[j].vdisplay > 3845 dp->rd_softc->sc_maxy) 3846 continue; 3847 3848 /* 3849 * pick largest resolution, the 3850 * smaller monitor will pan 3851 */ 3852 if ((ep->edid_modes[j].hdisplay >= *x) && 3853 (ep->edid_modes[j].vdisplay >= *y)) { 3854 *x = ep->edid_modes[j].hdisplay; 3855 *y = ep->edid_modes[j].vdisplay; 3856 } 3857 } 3858 } 3859 3860 } else { 3861 struct videomode modes[64]; 3862 int nmodes = 0; 3863 int valid = 0; 3864 3865 for (i = 0; i < dp->rd_ncrtcs; i++) { 3866 /* 3867 * pick the largest resolution in common. 3868 */ 3869 rp = dp->rd_crtcs[i].rc_port; 3870 ep = &rp->rp_edid; 3871 3872 if (!rp->rp_edid_valid) 3873 continue; 3874 3875 if (!valid) { 3876 /* 3877 * Pick the preferred mode for this port 3878 * if available. 3879 */ 3880 if (ep->edid_preferred_mode) { 3881 struct videomode *vmp = 3882 ep->edid_preferred_mode; 3883 3884 if ((vmp->hdisplay <= 3885 dp->rd_softc->sc_maxx) && 3886 (vmp->vdisplay <= 3887 dp->rd_softc->sc_maxy)) 3888 modes[nmodes++] = *vmp; 3889 } else { 3890 3891 /* initialize starting list */ 3892 for (j = 0; j < ep->edid_nmodes; j++) { 3893 /* 3894 * ignore resolutions that are 3895 * too big for the radeon 3896 */ 3897 if (ep->edid_modes[j].hdisplay > 3898 dp->rd_softc->sc_maxx) 3899 continue; 3900 if (ep->edid_modes[j].vdisplay > 3901 dp->rd_softc->sc_maxy) 3902 continue; 3903 3904 modes[nmodes] = 3905 ep->edid_modes[j]; 3906 nmodes++; 3907 } 3908 } 3909 valid = 1; 3910 } else { 3911 /* merge into preexisting list */ 3912 for (j = 0; j < nmodes; j++) { 3913 if (!radeonfb_hasres(ep->edid_modes, 3914 ep->edid_nmodes, 3915 modes[j].hdisplay, 3916 modes[j].vdisplay)) { 3917 modes[j] = modes[nmodes]; 3918 j--; 3919 nmodes--; 3920 } 3921 } 3922 } 3923 } 3924 3925 /* now we have to pick from the merged list */ 3926 for (i = 0; i < nmodes; i++) { 3927 if ((modes[i].hdisplay >= *x) && 3928 (modes[i].vdisplay >= *y)) { 3929 *x = modes[i].hdisplay; 3930 *y = modes[i].vdisplay; 3931 } 3932 } 3933 } 3934 3935 if ((*x == 0) || (*y == 0)) { 3936 /* fallback to safe mode */ 3937 *x = 640; 3938 *y = 480; 3939 } 3940 } 3941 3942 /* 3943 * backlight levels are linear on: 3944 * - RV200, RV250, RV280, RV350 3945 * - but NOT on PowerBook4,3 6,3 6,5 3946 * according to Linux' radeonfb 3947 */ 3948 3949 /* Get the current backlight level for the display. */ 3950 3951 static int 3952 radeonfb_get_backlight(struct radeonfb_display *dp) 3953 { 3954 int s; 3955 uint32_t level; 3956 3957 s = spltty(); 3958 3959 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3960 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3961 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3962 3963 /* 3964 * On some chips, we should negate the backlight level. 3965 * XXX Find out on which chips. 3966 */ 3967 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3968 level = RADEONFB_BACKLIGHT_MAX - level; 3969 3970 splx(s); 3971 3972 return level; 3973 } 3974 3975 /* Set the backlight to the given level for the display. */ 3976 static void 3977 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3978 { 3979 if (dp->rd_bl_on == on) 3980 return; 3981 dp->rd_bl_on = on; 3982 radeonfb_set_backlight(dp, dp->rd_bl_level); 3983 } 3984 3985 static int 3986 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3987 { 3988 struct radeonfb_softc *sc; 3989 int rlevel, s; 3990 uint32_t lvds; 3991 3992 s = spltty(); 3993 3994 dp->rd_bl_level = level; 3995 if (dp->rd_bl_on == 0) 3996 level = 0; 3997 3998 if (level < 0) 3999 level = 0; 4000 else if (level >= RADEONFB_BACKLIGHT_MAX) 4001 level = RADEONFB_BACKLIGHT_MAX; 4002 4003 sc = dp->rd_softc; 4004 4005 /* On some chips, we should negate the backlight level. */ 4006 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4007 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4008 } else 4009 rlevel = level; 4010 4011 callout_stop(&dp->rd_bl_lvds_co); 4012 radeonfb_engine_idle(sc); 4013 4014 /* 4015 * Turn off the display if the backlight is set to 0, since the 4016 * display is useless without backlight anyway. 4017 */ 4018 if (level == 0) 4019 radeonfb_blank(dp, 1); 4020 else if (radeonfb_get_backlight(dp) == 0) 4021 radeonfb_blank(dp, 0); 4022 4023 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4024 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4025 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4026 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4027 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4028 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4029 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4030 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4031 lvds |= RADEON_LVDS_ON; 4032 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4033 } else { 4034 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4035 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4036 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4037 } 4038 4039 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4040 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4041 /* XXX What is the correct delay? */ 4042 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4043 4044 splx(s); 4045 4046 return 0; 4047 } 4048 4049 /* 4050 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4051 * Set the delayed bits in the register, and clear the stored delayed 4052 * value. 4053 */ 4054 4055 static void radeonfb_lvds_callout(void *arg) 4056 { 4057 struct radeonfb_display *dp = arg; 4058 int s; 4059 4060 s = splhigh(); 4061 4062 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4063 dp->rd_bl_lvds_val); 4064 dp->rd_bl_lvds_val = 0; 4065 4066 splx(s); 4067 } 4068 4069 static void 4070 radeonfb_brightness_up(device_t dev) 4071 { 4072 struct radeonfb_softc *sc = device_private(dev); 4073 struct radeonfb_display *dp = &sc->sc_displays[0]; 4074 int level; 4075 4076 /* we assume the main display is the first one - need a better way */ 4077 if (sc->sc_ndisplays < 1) return; 4078 /* make sure pushing the hotkeys always has an effect */ 4079 dp->rd_bl_on = 1; 4080 level = dp->rd_bl_level; 4081 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4082 radeonfb_set_backlight(dp, level); 4083 } 4084 4085 static void 4086 radeonfb_brightness_down(device_t dev) 4087 { 4088 struct radeonfb_softc *sc = device_private(dev); 4089 struct radeonfb_display *dp = &sc->sc_displays[0]; 4090 int level; 4091 4092 /* we assume the main display is the first one - need a better way */ 4093 if (sc->sc_ndisplays < 1) return; 4094 /* make sure pushing the hotkeys always has an effect */ 4095 dp->rd_bl_on = 1; 4096 level = dp->rd_bl_level; 4097 level = max(0, level - 5); 4098 radeonfb_set_backlight(dp, level); 4099 } 4100
Indexes created Fri Sep 26 08:10:20 GMT 2025