radeonfb.c revision 1.77
1 /* $NetBSD: radeonfb.c,v 1.77 2013/09/15 09:36:02 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.77 2013/09/15 09:36:02 martin Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 174 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 175 #endif 176 177 static int radeonfb_set_backlight(struct radeonfb_display *, int); 178 static int radeonfb_get_backlight(struct radeonfb_display *); 179 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 180 static void radeonfb_lvds_callout(void *); 181 182 static void radeonfb_brightness_up(device_t); 183 static void radeonfb_brightness_down(device_t); 184 185 static struct videomode *radeonfb_best_refresh(struct videomode *, 186 struct videomode *); 187 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 188 uint16_t *, int); 189 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 190 struct radeonfb_port *, int, int); 191 192 static int radeonfb_drm_print(void *, const char *); 193 194 #ifdef RADEONFB_DEBUG 195 int radeon_debug = 1; 196 #define DPRINTF(x) \ 197 if (radeon_debug) printf x 198 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 199 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 200 #else 201 #define DPRINTF(x) 202 #define PRINTREG(r) 203 #define PRINTPLL(r) 204 #endif 205 206 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 207 208 #ifndef RADEON_DEFAULT_MODE 209 /* any reasonably modern display should handle this */ 210 #define RADEON_DEFAULT_MODE "1024x768x60" 211 #endif 212 213 extern const u_char rasops_cmap[768]; 214 215 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 216 217 static struct { 218 int size; /* minimum memory size (MB) */ 219 int maxx; /* maximum x dimension */ 220 int maxy; /* maximum y dimension */ 221 int maxbpp; /* maximum bpp */ 222 int maxdisp; /* maximum logical display count */ 223 } radeonfb_limits[] = { 224 { 32, 2048, 1536, 32, 2 }, 225 { 16, 1600, 1200, 32, 2 }, 226 { 8, 1600, 1200, 32, 1 }, 227 { 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct wsscreen_descr radeonfb_stdscreen = { 231 "fb", /* name */ 232 0, 0, /* ncols, nrows */ 233 NULL, /* textops */ 234 8, 16, /* fontwidth, fontheight */ 235 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 236 0, /* modecookie */ 237 }; 238 239 struct wsdisplay_accessops radeonfb_accessops = { 240 radeonfb_ioctl, 241 radeonfb_mmap, 242 NULL, /* vcons_alloc_screen */ 243 NULL, /* vcons_free_screen */ 244 NULL, /* vcons_show_screen */ 245 NULL, /* load_font */ 246 NULL, /* pollc */ 247 NULL, /* scroll */ 248 }; 249 250 static struct { 251 uint16_t devid; 252 uint16_t family; 253 uint16_t flags; 254 } radeonfb_devices[] = 255 { 256 /* R100 family */ 257 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 261 262 /* RV100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 267 268 /* RS100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 271 272 /* RS200/RS250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 277 278 /* R200 family */ 279 /* add more R200 products? , 5148 */ 280 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 285 286 /* RV200 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 291 292 /* RV250 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 298 299 /* RS300 family */ 300 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 304 305 /* RV280 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 313 314 /* R300 family */ 315 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 323 324 /* RV350/RV360 family */ 325 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 337 338 /* R350/R360 family */ 339 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 347 348 /* RV380/RV370 family */ 349 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 359 360 #if notyet 361 /* R420/R423 family */ 362 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 379 #endif 380 { 0, 0, 0 } 381 }; 382 383 static struct { 384 int divider; 385 int mask; 386 } radeonfb_dividers[] = { 387 { 16, 5 }, 388 { 12, 7 }, 389 { 8, 3 }, 390 { 6, 6 }, 391 { 4, 2 }, 392 { 3, 4 }, 393 { 2, 1 }, 394 { 1, 0 }, 395 { 0, 0 } 396 }; 397 398 /* 399 * This table taken from X11. 400 */ 401 static const struct { 402 int family; 403 struct radeon_tmds_pll plls[4]; 404 } radeonfb_tmds_pll[] = { 405 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RS100, {{0, 0}}}, 408 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 411 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 412 { RADEON_RS300, {{0, 0}}}, 413 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 414 { RADEON_R300, {{-1, 0xb01cb}}}, 415 { RADEON_R350, {{-1, 0xb01cb}}}, 416 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 417 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 418 { RADEON_R420, {{-1, 0xb01cb}}}, 419 }; 420 421 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 422 423 424 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 425 radeonfb_match, radeonfb_attach, NULL, NULL); 426 427 static int 428 radeonfb_match(device_t parent, cfdata_t match, void *aux) 429 { 430 const struct pci_attach_args *pa = aux; 431 int i; 432 433 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 434 return 0; 435 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 438 return 100; /* high to defeat VGA/VESA */ 439 } 440 441 return 0; 442 } 443 444 static void 445 radeonfb_attach(device_t parent, device_t dev, void *aux) 446 { 447 struct radeonfb_softc *sc = device_private(dev); 448 const struct pci_attach_args *pa = aux; 449 const char *mptr; 450 bus_size_t bsz; 451 pcireg_t screg; 452 int i, j, fg, bg, ul, flags; 453 uint32_t v; 454 455 sc->sc_dev = dev; 456 sc->sc_id = pa->pa_id; 457 for (i = 0; radeonfb_devices[i].devid; i++) { 458 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 459 break; 460 } 461 462 pci_aprint_devinfo(pa, NULL); 463 464 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 465 466 KASSERT(radeonfb_devices[i].devid != 0); 467 sc->sc_pt = pa->pa_tag; 468 sc->sc_iot = pa->pa_iot; 469 sc->sc_pc = pa->pa_pc; 470 sc->sc_family = radeonfb_devices[i].family; 471 sc->sc_flags = radeonfb_devices[i].flags; 472 473 /* enable memory and IO access */ 474 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 475 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 476 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 477 478 /* 479 * Some flags are general to entire chip families, and rather 480 * than clutter up the table with them, we go ahead and set 481 * them here. 482 */ 483 switch (sc->sc_family) { 484 case RADEON_RS100: 485 case RADEON_RS200: 486 sc->sc_flags |= RFB_IGP | RFB_RV100; 487 break; 488 489 case RADEON_RV100: 490 case RADEON_RV200: 491 case RADEON_RV250: 492 case RADEON_RV280: 493 sc->sc_flags |= RFB_RV100; 494 break; 495 496 case RADEON_RS300: 497 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_R300: 501 case RADEON_RV350: 502 case RADEON_R350: 503 case RADEON_RV380: 504 case RADEON_R420: 505 /* newer chips */ 506 sc->sc_flags |= RFB_R300; 507 break; 508 509 case RADEON_R100: 510 sc->sc_flags |= RFB_NCRTC2; 511 break; 512 } 513 514 if ((sc->sc_family == RADEON_RV200) || 515 (sc->sc_family == RADEON_RV250) || 516 (sc->sc_family == RADEON_RV280) || 517 (sc->sc_family == RADEON_RV350)) { 518 bool inverted = 0; 519 /* backlight level is linear */ 520 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 521 prop_dictionary_get_bool(device_properties(sc->sc_dev), 522 "backlight_level_reverted", &inverted); 523 if (inverted) { 524 DPRINTF(("nope, it's inverted\n")); 525 sc->sc_flags |= RFB_INV_BLIGHT; 526 } 527 } else 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 530 /* 531 * XXX: to support true multihead, this must change. 532 */ 533 sc->sc_ndisplays = 1; 534 535 /* XXX: */ 536 if (!HAS_CRTC2(sc)) { 537 sc->sc_ndisplays = 1; 538 } 539 540 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 541 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 542 &sc->sc_regsz) != 0) { 543 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 544 goto error; 545 } 546 547 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 548 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 549 { 550 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 551 goto error; 552 } 553 sc->sc_romt = sc->sc_memt; 554 555 sc->sc_mapped = TRUE; 556 557 /* scratch register test... */ 558 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 559 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 560 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 561 goto error; 562 } 563 564 PRINTREG(RADEON_CRTC_EXT_CNTL); 565 PRINTREG(RADEON_CRTC_GEN_CNTL); 566 PRINTREG(RADEON_CRTC2_GEN_CNTL); 567 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 568 PRINTREG(RADEON_DAC_CNTL2); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 PRINTREG(RADEON_FP2_GEN_CNTL); 571 572 PRINTREG(RADEON_BIOS_4_SCRATCH); 573 PRINTREG(RADEON_FP_GEN_CNTL); 574 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 575 PRINTREG(RADEON_FP2_GEN_CNTL); 576 PRINTREG(RADEON_TMDS_CNTL); 577 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 578 PRINTREG(RADEON_TMDS_PLL_CNTL); 579 PRINTREG(RADEON_LVDS_GEN_CNTL); 580 PRINTREG(RADEON_FP_HORZ_STRETCH); 581 PRINTREG(RADEON_FP_VERT_STRETCH); 582 583 if (IS_RV100(sc)) 584 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 585 586 /* XXX 587 * according to xf86-video-radeon R3xx has this bit backwards 588 */ 589 if (IS_R300(sc)) { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 0, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } else { 594 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 595 RADEON_TMDS_TRANSMITTER_PLLEN, 596 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 597 } 598 599 radeonfb_i2c_init(sc); 600 601 radeonfb_loadbios(sc, pa); 602 603 #ifdef RADEONFB_BIOS_INIT 604 if (radeonfb_bios_init(sc)) { 605 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 606 } 607 #endif 608 609 if (radeonfb_getclocks(sc)) { 610 aprint_error("%s: Unable to get reference clocks from BIOS\n", 611 XNAME(sc)); 612 goto error; 613 } 614 615 if (radeonfb_gettmds(sc)) { 616 aprint_error("%s: Unable to identify TMDS PLL settings\n", 617 XNAME(sc)); 618 goto error; 619 } 620 621 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 622 "minpll = %d, maxpll = %d\n", XNAME(sc), 623 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 624 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 625 626 radeonfb_getconnectors(sc); 627 628 radeonfb_set_fbloc(sc); 629 630 for (i = 0; radeonfb_limits[i].size; i++) { 631 if (sc->sc_memsz >= radeonfb_limits[i].size) { 632 sc->sc_maxx = radeonfb_limits[i].maxx; 633 sc->sc_maxy = radeonfb_limits[i].maxy; 634 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 635 /* framebuffer offset, start at a 4K page */ 636 sc->sc_fboffset = sc->sc_memsz / 637 radeonfb_limits[i].maxdisp; 638 /* 639 * we use the fbsize to figure out where we can store 640 * things like cursor data. 641 */ 642 sc->sc_fbsize = 643 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 644 RADEON_STRIDEALIGN) * sc->sc_maxy, 645 4096); 646 break; 647 } 648 } 649 650 651 radeonfb_init_misc(sc); 652 653 /* program the DAC wirings */ 654 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 655 switch (sc->sc_ports[i].rp_dac_type) { 656 case RADEON_DAC_PRIMARY: 657 PATCH32(sc, RADEON_DAC_CNTL2, 658 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 659 ~RADEON_DAC2_DAC_CLK_SEL); 660 break; 661 case RADEON_DAC_TVDAC: 662 /* we always use the TVDAC to drive a secondary analog 663 * CRT for now. if we ever support TV-out this will 664 * have to change. 665 */ 666 SET32(sc, RADEON_DAC_CNTL2, 667 RADEON_DAC2_DAC2_CLK_SEL); 668 PATCH32(sc, RADEON_DISP_HW_DEBUG, 669 i ? 0 : RADEON_CRT2_DISP1_SEL, 670 ~RADEON_CRT2_DISP1_SEL); 671 /* we're using CRTC2 for the 2nd port */ 672 if (sc->sc_ports[i].rp_number == 1) { 673 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 674 RADEON_DISP_DAC2_SOURCE_CRTC2, 675 ~RADEON_DISP_DAC2_SOURCE_MASK); 676 } 677 678 break; 679 } 680 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 681 sc->sc_ports[i].rp_tmds_type)); 682 switch (sc->sc_ports[i].rp_tmds_type) { 683 case RADEON_TMDS_INT: 684 /* point FP0 at the CRTC this port uses */ 685 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 686 __func__, sc->sc_ports[i].rp_number)); 687 if (IS_R300(sc)) { 688 PATCH32(sc, RADEON_FP_GEN_CNTL, 689 sc->sc_ports[i].rp_number ? 690 R200_FP_SOURCE_SEL_CRTC2 : 691 R200_FP_SOURCE_SEL_CRTC1, 692 ~R200_FP_SOURCE_SEL_MASK); 693 } else { 694 PATCH32(sc, RADEON_FP_GEN_CNTL, 695 sc->sc_ports[i].rp_number ? 696 RADEON_FP_SEL_CRTC2 : 697 RADEON_FP_SEL_CRTC1, 698 ~RADEON_FP_SEL_MASK); 699 } 700 } 701 } 702 PRINTREG(RADEON_DAC_CNTL2); 703 PRINTREG(RADEON_DISP_HW_DEBUG); 704 705 /* other DAC programming */ 706 v = GET32(sc, RADEON_DAC_CNTL); 707 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 708 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 709 PUT32(sc, RADEON_DAC_CNTL, v); 710 PRINTREG(RADEON_DAC_CNTL); 711 712 /* XXX: this may need more investigation */ 713 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 714 PRINTREG(RADEON_TV_DAC_CNTL); 715 716 /* enable TMDS */ 717 SET32(sc, RADEON_FP_GEN_CNTL, 718 RADEON_FP_TMDS_EN | 719 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 720 RADEON_FP_CRTC_DONT_SHADOW_HEND); 721 /* 722 * XXX 723 * no idea why this is necessary - if I do not clear this bit on my 724 * iBook G4 the screen remains black, even though it's already clear. 725 * It needs to be set on my Sun XVR-100 for the DVI port to work 726 * TODO: 727 * see if this is still necessary now that CRTCs, DACs and outputs are 728 * getting wired up in a halfway sane way 729 */ 730 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 731 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 732 } else { 733 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 734 } 735 736 /* 737 * we use bus_space_map instead of pci_mapreg, because we don't 738 * need the full aperature space. no point in wasting virtual 739 * address space we don't intend to use, right? 740 */ 741 if ((sc->sc_memsz < (4096 * 1024)) || 742 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 743 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 744 (bsz < sc->sc_memsz)) { 745 sc->sc_memsz = 0; 746 aprint_error("%s: Bad frame buffer configuration\n", 747 XNAME(sc)); 748 goto error; 749 } 750 751 /* 64 MB should be enough -- more just wastes map entries */ 752 if (sc->sc_memsz > (64 << 20)) 753 sc->sc_memsz = (64 << 20); 754 755 sc->sc_memt = pa->pa_memt; 756 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 757 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 758 sc->sc_memsz = 0; 759 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 760 goto error; 761 } 762 763 aprint_normal("%s: %d MB aperture at 0x%08x, " 764 "%d KB registers at 0x%08x\n", XNAME(sc), 765 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 766 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 767 768 /* setup default video mode from devprop (allows PROM override) */ 769 sc->sc_defaultmode = radeonfb_default_mode; 770 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 771 "videomode", &mptr)) { 772 773 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 774 sc->sc_defaultmode = sc->sc_modebuf; 775 } 776 777 /* initialize some basic display parameters */ 778 for (i = 0; i < sc->sc_ndisplays; i++) { 779 struct radeonfb_display *dp = &sc->sc_displays[i]; 780 struct rasops_info *ri; 781 long defattr; 782 struct wsemuldisplaydev_attach_args aa; 783 784 /* 785 * Figure out how many "displays" (desktops) we are going to 786 * support. If more than one, then each CRTC gets its own 787 * programming. 788 * 789 * XXX: this code needs to change to support mergedfb. 790 * XXX: would be nice to allow this to be overridden 791 */ 792 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 793 DPRINTF(("dual crtcs!\n")); 794 dp->rd_ncrtcs = 2; 795 dp->rd_crtcs[0].rc_port = 796 &sc->sc_ports[0]; 797 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 798 dp->rd_crtcs[1].rc_port = 799 &sc->sc_ports[1]; 800 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 801 } else { 802 dp->rd_ncrtcs = 1; 803 dp->rd_crtcs[0].rc_port = 804 &sc->sc_ports[i]; 805 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 806 } 807 808 dp->rd_softc = sc; 809 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 810 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 811 812 /* for text mode, we pick a resolution that won't 813 * require panning */ 814 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 815 816 aprint_normal("%s: display %d: " 817 "initial virtual resolution %dx%d at %d bpp\n", 818 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 819 820 /* now select the *video mode* that we will use */ 821 for (j = 0; j < dp->rd_ncrtcs; j++) { 822 const struct videomode *vmp; 823 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 824 dp->rd_virtx, dp->rd_virty); 825 826 /* 827 * virtual resolution should be at least as high as 828 * physical 829 */ 830 if (dp->rd_virtx < vmp->hdisplay || 831 dp->rd_virty < vmp->vdisplay) { 832 dp->rd_virtx = vmp->hdisplay; 833 dp->rd_virty = vmp->vdisplay; 834 } 835 836 dp->rd_crtcs[j].rc_videomode = *vmp; 837 printf("%s: port %d: physical %dx%d %dHz\n", 838 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 839 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 840 vmp->htotal), vmp->vtotal)); 841 } 842 843 /* N.B.: radeon wants 64-byte aligned stride */ 844 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 845 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 846 DPRINTF(("stride: %d\n", dp->rd_stride)); 847 848 dp->rd_offset = sc->sc_fboffset * i; 849 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 850 sc->sc_memh) + dp->rd_offset; 851 dp->rd_curoff = sc->sc_fbsize; 852 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 853 854 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 855 856 switch (dp->rd_bpp) { 857 case 8: 858 dp->rd_format = 2; 859 break; 860 case 32: 861 dp->rd_format = 6; 862 break; 863 default: 864 aprint_error("%s: bad depth %d\n", XNAME(sc), 865 dp->rd_bpp); 866 goto error; 867 } 868 869 DPRINTF(("init engine\n")); 870 /* XXX: this seems suspicious - per display engine 871 initialization? */ 872 radeonfb_engine_init(dp); 873 874 /* copy the template into place */ 875 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 876 dp->rd_wsscreens = dp->rd_wsscreens_storage; 877 878 /* and make up the list */ 879 dp->rd_wsscreenlist.nscreens = 1; 880 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 881 882 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 883 &radeonfb_accessops); 884 885 dp->rd_vd.init_screen = radeonfb_init_screen; 886 887 #ifdef RADEONFB_DEBUG 888 dp->rd_virty -= 200; 889 #endif 890 891 dp->rd_console = 0; 892 prop_dictionary_get_bool(device_properties(sc->sc_dev), 893 "is_console", &dp->rd_console); 894 895 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 896 897 898 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 899 dp->rd_console, &defattr); 900 901 ri = &dp->rd_vscreen.scr_ri; 902 903 /* clear the screen */ 904 rasops_unpack_attr(defattr, &fg, &bg, &ul); 905 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 906 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 907 dp->rd_bg); 908 909 dp->rd_wsscreens->textops = &ri->ri_ops; 910 dp->rd_wsscreens->capabilities = ri->ri_caps; 911 dp->rd_wsscreens->nrows = ri->ri_rows; 912 dp->rd_wsscreens->ncols = ri->ri_cols; 913 914 #ifdef SPLASHSCREEN 915 dp->rd_splash.si_depth = ri->ri_depth; 916 dp->rd_splash.si_bits = ri->ri_bits; 917 dp->rd_splash.si_hwbits = ri->ri_hwbits; 918 dp->rd_splash.si_width = ri->ri_width; 919 dp->rd_splash.si_height = ri->ri_height; 920 dp->rd_splash.si_stride = ri->ri_stride; 921 dp->rd_splash.si_fillrect = NULL; 922 #endif 923 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 924 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 925 dp->rd_gc.gc_rop = RADEON_ROP3_S; 926 dp->rd_gc.gc_blitcookie = dp; 927 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 928 (0x800000 / dp->rd_stride) - (dp->rd_virty + 4), 929 dp->rd_virtx, 930 ri->ri_font->fontwidth, 931 ri->ri_font->fontheight, 932 defattr); 933 if (dp->rd_console) { 934 935 radeonfb_modeswitch(dp); 936 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 937 defattr); 938 #ifdef SPLASHSCREEN 939 if (splash_render(&dp->rd_splash, 940 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 941 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 942 else 943 #endif 944 vcons_replay_msgbuf(&dp->rd_vscreen); 945 } else { 946 947 /* 948 * since we're not the console we can postpone 949 * the rest until someone actually allocates a 950 * screen for us. but we do clear the screen 951 * at least. 952 */ 953 memset(ri->ri_bits, 0, 1024); 954 955 radeonfb_modeswitch(dp); 956 #ifdef SPLASHSCREEN 957 if (splash_render(&dp->rd_splash, 958 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 959 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 960 #endif 961 } 962 963 aa.console = dp->rd_console; 964 aa.scrdata = &dp->rd_wsscreenlist; 965 aa.accessops = &radeonfb_accessops; 966 aa.accesscookie = &dp->rd_vd; 967 968 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 969 970 radeonfb_blank(dp, 0); 971 972 /* Initialise delayed lvds operations for backlight. */ 973 callout_init(&dp->rd_bl_lvds_co, 0); 974 callout_setfunc(&dp->rd_bl_lvds_co, 975 radeonfb_lvds_callout, dp); 976 dp->rd_bl_on = 1; 977 dp->rd_bl_level = radeonfb_get_backlight(dp); 978 radeonfb_set_backlight(dp, dp->rd_bl_level); 979 } 980 981 for (i = 0; i < RADEON_NDISPLAYS; i++) 982 radeonfb_init_palette(&sc->sc_displays[i]); 983 984 if (HAS_CRTC2(sc)) { 985 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 986 } 987 988 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 989 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 990 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 991 radeonfb_brightness_up, TRUE); 992 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 993 radeonfb_brightness_down, TRUE); 994 995 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 996 997 PRINTREG(RADEON_CRTC_EXT_CNTL); 998 PRINTREG(RADEON_CRTC_GEN_CNTL); 999 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1000 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1001 PRINTREG(RADEON_DAC_CNTL2); 1002 PRINTREG(RADEON_FP_GEN_CNTL); 1003 PRINTREG(RADEON_FP2_GEN_CNTL); 1004 1005 return; 1006 1007 error: 1008 if (sc->sc_biossz) 1009 free(sc->sc_bios, M_DEVBUF); 1010 1011 if (sc->sc_regsz) 1012 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1013 1014 if (sc->sc_memsz) 1015 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1016 } 1017 1018 static void 1019 radeonfb_map(struct radeonfb_softc *sc) 1020 { 1021 if (!sc->sc_mapped) { 1022 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1023 &sc->sc_regh) != 0) { 1024 aprint_error_dev(sc->sc_dev, 1025 "unable to map registers!\n"); 1026 return; 1027 } 1028 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1029 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1030 sc->sc_memsz = 0; 1031 aprint_error_dev(sc->sc_dev, 1032 "Unable to map frame buffer\n"); 1033 return; 1034 } 1035 sc->sc_mapped = TRUE; 1036 } 1037 } 1038 1039 static void 1040 radeonfb_unmap(struct radeonfb_softc *sc) 1041 { 1042 if (sc->sc_mapped) { 1043 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1044 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1045 sc->sc_mapped = FALSE; 1046 } 1047 } 1048 1049 static int 1050 radeonfb_drm_print(void *aux, const char *pnp) 1051 { 1052 if (pnp) 1053 aprint_normal("drm at %s", pnp); 1054 return (UNCONF); 1055 } 1056 1057 int 1058 radeonfb_ioctl(void *v, void *vs, 1059 unsigned long cmd, void *d, int flag, struct lwp *l) 1060 { 1061 struct vcons_data *vd; 1062 struct radeonfb_display *dp; 1063 struct radeonfb_softc *sc; 1064 struct wsdisplay_param *param; 1065 1066 vd = (struct vcons_data *)v; 1067 dp = (struct radeonfb_display *)vd->cookie; 1068 sc = dp->rd_softc; 1069 1070 switch (cmd) { 1071 case WSDISPLAYIO_GTYPE: 1072 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1073 return 0; 1074 1075 case WSDISPLAYIO_GINFO: 1076 if (vd->active != NULL) { 1077 struct wsdisplay_fbinfo *fb; 1078 fb = (struct wsdisplay_fbinfo *)d; 1079 fb->width = dp->rd_virtx; 1080 fb->height = dp->rd_virty; 1081 fb->depth = dp->rd_bpp; 1082 fb->cmsize = 256; 1083 return 0; 1084 } else 1085 return ENODEV; 1086 case WSDISPLAYIO_GVIDEO: 1087 if (radeonfb_isblank(dp)) 1088 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1089 else 1090 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1091 return 0; 1092 1093 case WSDISPLAYIO_SVIDEO: 1094 radeonfb_blank(dp, 1095 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1096 return 0; 1097 1098 case WSDISPLAYIO_GETCMAP: 1099 #if 0 1100 if (dp->rd_bpp == 8) 1101 return radeonfb_getcmap(sc, 1102 (struct wsdisplay_cmap *)d); 1103 #endif 1104 return EINVAL; 1105 1106 case WSDISPLAYIO_PUTCMAP: 1107 #if 0 1108 if (dp->rd_bpp == 8) 1109 return radeonfb_putcmap(sc, 1110 (struct wsdisplay_cmap *)d); 1111 #endif 1112 return EINVAL; 1113 1114 case WSDISPLAYIO_LINEBYTES: 1115 *(unsigned *)d = dp->rd_stride; 1116 return 0; 1117 1118 case WSDISPLAYIO_SMODE: 1119 if (*(int *)d != dp->rd_wsmode) { 1120 dp->rd_wsmode = *(int *)d; 1121 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1122 (dp->rd_vd.active)) { 1123 radeonfb_map(sc); 1124 radeonfb_engine_init(dp); 1125 glyphcache_wipe(&dp->rd_gc); 1126 radeonfb_init_palette(dp); 1127 radeonfb_modeswitch(dp); 1128 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1129 dp->rd_virty, dp->rd_bg); 1130 vcons_redraw_screen(dp->rd_vd.active); 1131 } else { 1132 radeonfb_unmap(sc); 1133 } 1134 } 1135 return 0; 1136 1137 case WSDISPLAYIO_GCURMAX: 1138 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1139 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1140 return 0; 1141 1142 case WSDISPLAYIO_SCURSOR: 1143 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1144 1145 case WSDISPLAYIO_GCURSOR: 1146 return EPASSTHROUGH; 1147 1148 case WSDISPLAYIO_GCURPOS: 1149 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1150 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1151 return 0; 1152 1153 case WSDISPLAYIO_SCURPOS: 1154 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1155 1156 case WSDISPLAYIO_SSPLASH: 1157 #if defined(SPLASHSCREEN) 1158 if (*(int *)d == 1) { 1159 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1160 splash_render(&dp->rd_splash, 1161 SPLASH_F_CENTER|SPLASH_F_FILL); 1162 } else 1163 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1164 return 0; 1165 #else 1166 return ENODEV; 1167 #endif 1168 case WSDISPLAYIO_GETPARAM: 1169 param = (struct wsdisplay_param *)d; 1170 switch (param->param) { 1171 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1172 param->min = 0; 1173 param->max = 255; 1174 param->curval = dp->rd_bl_level; 1175 return 0; 1176 case WSDISPLAYIO_PARAM_BACKLIGHT: 1177 param->min = 0; 1178 param->max = RADEONFB_BACKLIGHT_MAX; 1179 param->curval = dp->rd_bl_on; 1180 return 0; 1181 } 1182 return EPASSTHROUGH; 1183 1184 case WSDISPLAYIO_SETPARAM: 1185 param = (struct wsdisplay_param *)d; 1186 switch (param->param) { 1187 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1188 radeonfb_set_backlight(dp, param->curval); 1189 return 0; 1190 case WSDISPLAYIO_PARAM_BACKLIGHT: 1191 radeonfb_switch_backlight(dp, param->curval); 1192 return 0; 1193 } 1194 return EPASSTHROUGH; 1195 1196 /* PCI config read/write passthrough. */ 1197 case PCI_IOC_CFGREAD: 1198 case PCI_IOC_CFGWRITE: 1199 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1200 1201 case WSDISPLAYIO_GET_BUSID: 1202 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1203 sc->sc_pt, d); 1204 1205 case WSDISPLAYIO_GET_EDID: { 1206 struct wsdisplayio_edid_info *ei = d; 1207 return wsdisplayio_get_edid(sc->sc_dev, ei); 1208 } 1209 1210 default: 1211 return EPASSTHROUGH; 1212 } 1213 } 1214 1215 paddr_t 1216 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1217 { 1218 struct vcons_data *vd; 1219 struct radeonfb_display *dp; 1220 struct radeonfb_softc *sc; 1221 paddr_t pa; 1222 1223 vd = (struct vcons_data *)v; 1224 dp = (struct radeonfb_display *)vd->cookie; 1225 sc = dp->rd_softc; 1226 1227 /* XXX: note that we don't allow mapping of registers right now */ 1228 /* XXX: this means that the XFree86 radeon driver won't work */ 1229 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1230 pa = bus_space_mmap(sc->sc_memt, 1231 sc->sc_memaddr + dp->rd_offset + offset, 0, 1232 prot, BUS_SPACE_MAP_LINEAR); 1233 return pa; 1234 } 1235 1236 #ifdef RADEONFB_MMAP_BARS 1237 /* 1238 * restrict all other mappings to processes with superuser privileges 1239 * or the kernel itself 1240 */ 1241 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1242 NULL, NULL, NULL, NULL) != 0) { 1243 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1244 return -1; 1245 } 1246 1247 if ((offset >= sc->sc_regaddr) && 1248 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1249 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1250 BUS_SPACE_MAP_LINEAR); 1251 } 1252 1253 if ((offset >= sc->sc_memaddr) && 1254 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1255 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1256 BUS_SPACE_MAP_LINEAR); 1257 } 1258 1259 if ((offset >= sc->sc_romaddr) && 1260 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1261 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1262 BUS_SPACE_MAP_LINEAR); 1263 } 1264 1265 #ifdef PCI_MAGIC_IO_RANGE 1266 /* allow mapping of IO space */ 1267 if ((offset >= PCI_MAGIC_IO_RANGE) && 1268 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1269 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1270 0, prot, 0); 1271 return pa; 1272 } 1273 #endif /* PCI_MAGIC_IO_RANGE */ 1274 1275 #endif /* RADEONFB_MMAP_BARS */ 1276 1277 return -1; 1278 } 1279 1280 static void 1281 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1282 { 1283 bus_space_tag_t romt; 1284 bus_space_handle_t romh, biosh; 1285 bus_size_t romsz; 1286 bus_addr_t ptr; 1287 1288 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1289 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1290 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1291 return; 1292 } 1293 1294 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1295 &sc->sc_biossz); 1296 if (sc->sc_biossz == 0) { 1297 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1298 return; 1299 } 1300 1301 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1302 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1303 1304 /* unmap the PCI expansion rom */ 1305 bus_space_unmap(romt, romh, romsz); 1306 1307 /* turn off rom decoder now */ 1308 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1309 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1310 ~PCI_MAPREG_ROM_ENABLE); 1311 1312 ptr = GETBIOS16(sc, 0x48); 1313 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1314 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1315 sc->sc_flags |= RFB_ATOM; 1316 } 1317 1318 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1319 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1320 } 1321 1322 1323 uint32_t 1324 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1325 { 1326 1327 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1328 } 1329 1330 void 1331 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1332 { 1333 1334 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1335 } 1336 1337 void 1338 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1339 { 1340 1341 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1342 } 1343 1344 void 1345 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1346 uint32_t andmask, uint32_t ormask) 1347 { 1348 int s; 1349 uint32_t val; 1350 1351 s = splhigh(); 1352 val = radeonfb_get32(sc, reg); 1353 val = (val & andmask) | ormask; 1354 radeonfb_put32(sc, reg, val); 1355 splx(s); 1356 } 1357 1358 uint32_t 1359 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1360 { 1361 int s; 1362 uint32_t val; 1363 1364 s = splhigh(); 1365 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1366 val = radeonfb_get32(sc, RADEON_MM_DATA); 1367 splx(s); 1368 1369 return (val); 1370 } 1371 1372 void 1373 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1374 { 1375 int s; 1376 1377 s = splhigh(); 1378 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1379 radeonfb_put32(sc, RADEON_MM_DATA, val); 1380 splx(s); 1381 } 1382 1383 void 1384 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1385 uint32_t andmask, uint32_t ormask) 1386 { 1387 int s; 1388 uint32_t val; 1389 1390 s = splhigh(); 1391 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1392 val = radeonfb_get32(sc, RADEON_MM_DATA); 1393 val = (val & andmask) | ormask; 1394 radeonfb_put32(sc, RADEON_MM_DATA, val); 1395 splx(s); 1396 } 1397 1398 uint32_t 1399 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1400 { 1401 int s; 1402 uint32_t val; 1403 1404 s = splhigh(); 1405 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1406 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1407 if (HAS_R300CG(sc)) 1408 radeonfb_r300cg_workaround(sc); 1409 splx(s); 1410 1411 return (val); 1412 } 1413 1414 void 1415 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1416 { 1417 int s; 1418 1419 s = splhigh(); 1420 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1421 RADEON_PLL_WR_EN); 1422 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1423 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1424 splx(s); 1425 } 1426 1427 void 1428 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1429 uint32_t andmask, uint32_t ormask) 1430 { 1431 int s; 1432 uint32_t val; 1433 1434 s = splhigh(); 1435 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1436 RADEON_PLL_WR_EN); 1437 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1438 val = (val & andmask) | ormask; 1439 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1440 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1441 splx(s); 1442 } 1443 1444 int 1445 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1446 { 1447 uint32_t saved; 1448 1449 saved = GET32(sc, reg); 1450 PUT32(sc, reg, v); 1451 if (GET32(sc, reg) != v) { 1452 return -1; 1453 } 1454 PUT32(sc, reg, saved); 1455 return 0; 1456 } 1457 1458 uintmax_t 1459 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1460 uintmax_t defval) 1461 { 1462 prop_number_t pn; 1463 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1464 if (pn == NULL) { 1465 return defval; 1466 } 1467 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1468 return (prop_number_integer_value(pn)); 1469 } 1470 1471 int 1472 radeonfb_getclocks(struct radeonfb_softc *sc) 1473 { 1474 bus_addr_t ptr; 1475 int refclk = 0; 1476 int refdiv = 0; 1477 int minpll = 0; 1478 int maxpll = 0; 1479 1480 /* load initial property values if port/board provides them */ 1481 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1482 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1483 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1484 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1485 1486 PRINTPLL(RADEON_PPLL_REF_DIV); 1487 PRINTPLL(RADEON_PPLL_DIV_0); 1488 PRINTPLL(RADEON_PPLL_DIV_1); 1489 PRINTPLL(RADEON_PPLL_DIV_2); 1490 PRINTPLL(RADEON_PPLL_DIV_3); 1491 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1492 PRINTPLL(RADEON_P2PLL_REF_DIV); 1493 PRINTPLL(RADEON_P2PLL_DIV_0); 1494 1495 if (refclk && refdiv && minpll && maxpll) 1496 goto dontprobe; 1497 1498 if (!sc->sc_biossz) { 1499 /* no BIOS */ 1500 aprint_verbose("%s: No video BIOS, using default clocks\n", 1501 XNAME(sc)); 1502 if (IS_IGP(sc)) 1503 refclk = refclk ? refclk : 1432; 1504 else 1505 refclk = refclk ? refclk : 2700; 1506 refdiv = refdiv ? refdiv : 12; 1507 minpll = minpll ? minpll : 12500; 1508 /* XXX 1509 * Need to check if the firmware or something programmed a 1510 * higher value than this, and if so, bump it. 1511 * The RV280 in my iBook is unhappy if the PLL input is less 1512 * than 360MHz 1513 */ 1514 maxpll = maxpll ? maxpll : 40000/*35000*/; 1515 } else if (IS_ATOM(sc)) { 1516 /* ATOM BIOS */ 1517 ptr = GETBIOS16(sc, 0x48); 1518 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1519 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1520 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1521 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1522 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1523 /* 1524 * ATOM BIOS doesn't supply a reference divider, so we 1525 * have to probe for it. 1526 */ 1527 if (refdiv < 2) 1528 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1529 RADEON_PPLL_REF_DIV_MASK; 1530 /* 1531 * if probe is zero, just assume one that should work 1532 * for most parts 1533 */ 1534 if (refdiv < 2) 1535 refdiv = 12; 1536 1537 } else { 1538 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1539 /* Legacy BIOS */ 1540 ptr = GETBIOS16(sc, 0x48); 1541 ptr = GETBIOS16(sc, ptr + 0x30); 1542 if (IS_R300(sc)) { 1543 refdiv = refdiv ? refdiv : 1544 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1545 R300_PPLL_REF_DIV_ACC_SHIFT; 1546 } else { 1547 refdiv = refdiv ? refdiv : 1548 tmp & RADEON_PPLL_REF_DIV_MASK; 1549 } 1550 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1551 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1552 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1553 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1554 } 1555 1556 1557 dontprobe: 1558 sc->sc_refclk = refclk * 10; 1559 sc->sc_refdiv = refdiv; 1560 sc->sc_minpll = minpll * 10; 1561 sc->sc_maxpll = maxpll * 10; 1562 return 0; 1563 } 1564 1565 int 1566 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1567 uint32_t *postdivbit, uint32_t *feedbackdiv) 1568 { 1569 int i; 1570 uint32_t outfreq; 1571 int div; 1572 1573 DPRINTF(("dot clock: %u\n", dotclock)); 1574 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1575 outfreq = div * dotclock; 1576 if ((outfreq >= sc->sc_minpll) && 1577 (outfreq <= sc->sc_maxpll)) { 1578 DPRINTF(("outfreq: %u\n", outfreq)); 1579 *postdivbit = 1580 ((uint32_t)radeonfb_dividers[i].mask << 16); 1581 DPRINTF(("post divider: %d (mask %x)\n", div, 1582 *postdivbit)); 1583 break; 1584 } 1585 } 1586 1587 if (div == 0) 1588 return 1; 1589 1590 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1591 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1592 return 0; 1593 } 1594 1595 #if 0 1596 #ifdef RADEONFB_DEBUG 1597 static void 1598 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1599 { 1600 char asc[17]; 1601 unsigned ptr = (unsigned)buffer; 1602 char *start = (char *)(ptr & ~0xf); 1603 char *end = (char *)(ptr + size); 1604 1605 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1606 1607 if (pfx == NULL) { 1608 pfx = ""; 1609 } 1610 1611 while (start < end) { 1612 unsigned offset = (unsigned)start & 0xf; 1613 if (offset == 0) { 1614 printf("%s%x: ", pfx, (unsigned)start); 1615 } 1616 if (((unsigned)start < ptr) || 1617 ((unsigned)start >= (ptr + size))) { 1618 printf(" "); 1619 asc[offset] = ' '; 1620 } else { 1621 printf("%02x", *(unsigned char *)start); 1622 if ((*start >= ' ') && (*start <= '~')) { 1623 asc[offset] = *start; 1624 } else { 1625 asc[offset] = '.'; 1626 } 1627 } 1628 asc[offset + 1] = 0; 1629 if (offset % 2) { 1630 printf(" "); 1631 } 1632 if (offset == 15) { 1633 printf(" %s\n", asc); 1634 } 1635 start++; 1636 } 1637 } 1638 #endif 1639 #endif 1640 1641 int 1642 radeonfb_getconnectors(struct radeonfb_softc *sc) 1643 { 1644 int i; 1645 int found = 0; 1646 1647 for (i = 0; i < 2; i++) { 1648 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1649 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1650 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1651 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1652 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1653 } 1654 1655 /* 1656 * This logic is borrowed from Xorg's radeon driver. 1657 */ 1658 if (!sc->sc_biossz) 1659 goto nobios; 1660 1661 if (IS_ATOM(sc)) { 1662 /* not done yet */ 1663 } else { 1664 uint16_t ptr; 1665 int port = 0; 1666 1667 ptr = GETBIOS16(sc, 0x48); 1668 ptr = GETBIOS16(sc, ptr + 0x50); 1669 for (i = 1; i < 4; i++) { 1670 uint16_t entry; 1671 uint8_t conn, ddc, dac, tmds; 1672 1673 /* 1674 * Parse the connector table. From reading the code, 1675 * it appears to made up of 16-bit entries for each 1676 * connector. The 16-bits are defined as: 1677 * 1678 * bits 12-15 - connector type (0 == end of table) 1679 * bits 8-11 - DDC type 1680 * bits 5-7 - ??? 1681 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1682 * bits 1-3 - ??? 1683 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1684 */ 1685 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1686 break; 1687 entry = GETBIOS16(sc, ptr + i * 2); 1688 1689 conn = (entry >> 12) & 0xf; 1690 ddc = (entry >> 8) & 0xf; 1691 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1692 RADEON_DAC_PRIMARY; 1693 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1694 RADEON_TMDS_INT; 1695 1696 if (conn == RADEON_CONN_NONE) 1697 continue; /* no connector */ 1698 1699 if ((found > 0) && 1700 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1701 /* duplicate entry for same connector */ 1702 continue; 1703 } 1704 1705 /* internal DDC_DVI port gets priority */ 1706 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1707 port = 0; 1708 else 1709 port = 1; 1710 1711 sc->sc_ports[port].rp_ddc_type = 1712 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1713 sc->sc_ports[port].rp_dac_type = dac; 1714 sc->sc_ports[port].rp_conn_type = 1715 min(conn, RADEON_CONN_UNSUPPORTED) ; 1716 1717 sc->sc_ports[port].rp_tmds_type = tmds; 1718 1719 if ((conn != RADEON_CONN_DVI_I) && 1720 (conn != RADEON_CONN_DVI_D) && 1721 (tmds == RADEON_TMDS_INT)) 1722 sc->sc_ports[port].rp_tmds_type = 1723 RADEON_TMDS_UNKNOWN; 1724 sc->sc_ports[port].rp_number = i - 1; 1725 1726 found += (port + 1); 1727 } 1728 } 1729 1730 nobios: 1731 if (!found) { 1732 DPRINTF(("No connector info in BIOS!\n")); 1733 if IS_MOBILITY(sc) { 1734 /* default, port 0 = internal TMDS, port 1 = CRT */ 1735 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1736 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1737 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1738 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1739 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1740 sc->sc_ports[0].rp_number = 0; 1741 1742 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1743 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1744 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1745 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1746 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1747 sc->sc_ports[1].rp_number = 1; 1748 } else { 1749 /* default, port 0 = DVI, port 1 = CRT */ 1750 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1751 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1752 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1753 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1754 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1755 sc->sc_ports[0].rp_number = 1; 1756 1757 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1758 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1759 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1760 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1761 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1762 sc->sc_ports[1].rp_number = 0; 1763 } 1764 } 1765 1766 /* 1767 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1768 * these chips should use TVDAC for the VGA port. 1769 */ 1770 if (HAS_SDAC(sc)) { 1771 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1772 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1773 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1774 } else { 1775 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1776 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1777 } 1778 } else if (!HAS_CRTC2(sc)) { 1779 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1780 } 1781 1782 for (i = 0; i < 2; i++) { 1783 char edid[128]; 1784 uint8_t ddc; 1785 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1786 prop_data_t edid_data; 1787 1788 DPRINTF(("Port #%d:\n", i)); 1789 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1790 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1791 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1792 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1793 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1794 1795 sc->sc_ports[i].rp_edid_valid = 0; 1796 /* first look for static EDID data */ 1797 if ((edid_data = prop_dictionary_get(device_properties( 1798 sc->sc_dev), "EDID")) != NULL) { 1799 1800 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1801 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1802 if (edid_parse(edid, eip) == 0) { 1803 1804 sc->sc_ports[i].rp_edid_valid = 1; 1805 } 1806 } 1807 /* if we didn't find any we'll try to talk to the monitor */ 1808 if (sc->sc_ports[i].rp_edid_valid != 1) { 1809 1810 ddc = sc->sc_ports[i].rp_ddc_type; 1811 if (ddc != RADEON_DDC_NONE) { 1812 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1813 == 0) && (edid_parse(edid, eip) == 0)) { 1814 1815 sc->sc_ports[i].rp_edid_valid = 1; 1816 #ifdef RADEONFB_DEBUG 1817 edid_print(eip); 1818 #endif 1819 } 1820 } 1821 } 1822 } 1823 1824 return found; 1825 } 1826 1827 int 1828 radeonfb_gettmds(struct radeonfb_softc *sc) 1829 { 1830 int i; 1831 1832 if (!sc->sc_biossz) { 1833 goto nobios; 1834 } 1835 1836 if (IS_ATOM(sc)) { 1837 /* XXX: not done yet */ 1838 } else { 1839 uint16_t ptr; 1840 int n; 1841 1842 ptr = GETBIOS16(sc, 0x48); 1843 ptr = GETBIOS16(sc, ptr + 0x34); 1844 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1845 if (GETBIOS8(sc, ptr) == 3) { 1846 /* revision three table */ 1847 n = GETBIOS8(sc, ptr + 5) + 1; 1848 n = min(n, 4); 1849 1850 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1851 for (i = 0; i < n; i++) { 1852 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1853 ptr + i * 10 + 8); 1854 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1855 ptr + i * 10 + 0x10); 1856 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1857 sc->sc_tmds_pll[i].rtp_freq, 1858 sc->sc_tmds_pll[i].rtp_pll)); 1859 } 1860 return 0; 1861 } 1862 } 1863 1864 nobios: 1865 DPRINTF(("no suitable DFP table present\n")); 1866 for (i = 0; 1867 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1868 i++) { 1869 int j; 1870 1871 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1872 continue; 1873 1874 for (j = 0; j < 4; j++) { 1875 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1876 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1877 sc->sc_tmds_pll[j].rtp_freq, 1878 sc->sc_tmds_pll[j].rtp_pll)); 1879 } 1880 return 0; 1881 } 1882 1883 return -1; 1884 } 1885 1886 const struct videomode * 1887 radeonfb_modelookup(const char *name) 1888 { 1889 int i; 1890 1891 for (i = 0; i < videomode_count; i++) 1892 if (!strcmp(name, videomode_list[i].name)) 1893 return &videomode_list[i]; 1894 1895 return NULL; 1896 } 1897 1898 void 1899 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1900 { 1901 if (crtc) { 1902 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1903 RADEON_P2PLL_ATOMIC_UPDATE_R); 1904 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1905 } else { 1906 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1907 RADEON_PPLL_ATOMIC_UPDATE_R); 1908 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1909 } 1910 } 1911 1912 void 1913 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1914 { 1915 int i; 1916 1917 for (i = 10000; i; i--) { 1918 if (crtc) { 1919 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1920 RADEON_P2PLL_ATOMIC_UPDATE_R) 1921 break; 1922 } else { 1923 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1924 RADEON_PPLL_ATOMIC_UPDATE_R) 1925 break; 1926 } 1927 } 1928 } 1929 1930 void 1931 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1932 { 1933 uint32_t pbit = 0; 1934 uint32_t feed = 0; 1935 uint32_t data, refdiv, div0; 1936 1937 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1938 1939 if (crtc == 0) { 1940 1941 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1942 if (IS_R300(sc)) { 1943 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1944 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1945 } else { 1946 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1947 sc->sc_refdiv; 1948 } 1949 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1950 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1951 RADEON_PPLL_POST3_DIV_MASK); 1952 div0 |= pbit; 1953 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1954 1955 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1956 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1957 /* 1958 * nothing to do here, the PLL is already where we 1959 * want it 1960 */ 1961 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1962 ~RADEON_PLL_DIV_SEL); 1963 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1964 return; 1965 } 1966 1967 /* alright, we do need to reprogram stuff */ 1968 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1969 RADEON_VCLK_SRC_SEL_CPUCLK, 1970 ~RADEON_VCLK_SRC_SEL_MASK); 1971 1972 /* put vclk into reset, use atomic updates */ 1973 SETPLL(sc, RADEON_PPLL_CNTL, 1974 RADEON_PPLL_REFCLK_SEL | 1975 RADEON_PPLL_FBCLK_SEL | 1976 RADEON_PPLL_RESET | 1977 RADEON_PPLL_ATOMIC_UPDATE_EN | 1978 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1979 1980 /* select clock 0 */ 1981 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1982 ~RADEON_PLL_DIV_SEL); 1983 1984 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1985 1986 /* xf86-video-radeon does this, not sure why */ 1987 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1988 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 1989 1990 /* use the atomic update */ 1991 radeonfb_pllwriteupdate(sc, crtc); 1992 1993 /* and wait for it to complete */ 1994 radeonfb_pllwaitatomicread(sc, crtc); 1995 1996 /* program HTOTAL (why?) */ 1997 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1998 1999 /* drop reset */ 2000 CLRPLL(sc, RADEON_PPLL_CNTL, 2001 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2002 RADEON_PPLL_ATOMIC_UPDATE_EN | 2003 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2004 2005 PRINTPLL(RADEON_PPLL_CNTL); 2006 PRINTPLL(RADEON_PPLL_REF_DIV); 2007 PRINTPLL(RADEON_PPLL_DIV_3); 2008 2009 /* give clock time to lock */ 2010 delay(50000); 2011 2012 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2013 RADEON_VCLK_SRC_SEL_PPLLCLK, 2014 ~RADEON_VCLK_SRC_SEL_MASK); 2015 2016 } else { 2017 2018 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2019 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2020 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2021 2022 /* put vclk into reset, use atomic updates */ 2023 SETPLL(sc, RADEON_P2PLL_CNTL, 2024 RADEON_P2PLL_RESET | 2025 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2026 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2027 2028 /* program reference divider */ 2029 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2030 ~RADEON_P2PLL_REF_DIV_MASK); 2031 2032 /* program feedback and post dividers */ 2033 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2034 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2035 RADEON_P2PLL_POST0_DIV_MASK); 2036 data |= pbit; 2037 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2038 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2039 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2040 2041 PRINTPLL(RADEON_P2PLL_REF_DIV); 2042 PRINTPLL(RADEON_P2PLL_DIV_0); 2043 2044 /* use the atomic update */ 2045 radeonfb_pllwriteupdate(sc, crtc); 2046 2047 /* and wait for it to complete */ 2048 radeonfb_pllwaitatomicread(sc, crtc); 2049 2050 /* program HTOTAL (why?) */ 2051 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2052 2053 /* drop reset */ 2054 CLRPLL(sc, RADEON_P2PLL_CNTL, 2055 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2056 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2057 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2058 2059 /* allow time for clock to lock */ 2060 delay(50000); 2061 2062 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2063 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2064 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2065 } 2066 PRINTREG(RADEON_CRTC_MORE_CNTL); 2067 } 2068 2069 void 2070 radeonfb_modeswitch(struct radeonfb_display *dp) 2071 { 2072 struct radeonfb_softc *sc = dp->rd_softc; 2073 int i; 2074 2075 /* blank the display while we switch modes */ 2076 radeonfb_blank(dp, 1); 2077 2078 #if 0 2079 SET32(sc, RADEON_CRTC_EXT_CNTL, 2080 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2081 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2082 #endif 2083 2084 /* these registers might get in the way... */ 2085 PUT32(sc, RADEON_OVR_CLR, 0); 2086 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2087 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2088 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2089 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2090 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2091 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2092 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2093 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2094 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2095 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2096 2097 for (i = 0; i < dp->rd_ncrtcs; i++) 2098 radeonfb_setcrtc(dp, i); 2099 2100 /* activate the display */ 2101 radeonfb_blank(dp, 0); 2102 } 2103 2104 void 2105 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2106 { 2107 int crtc; 2108 struct videomode *mode; 2109 struct radeonfb_softc *sc; 2110 struct radeonfb_crtc *cp; 2111 uint32_t v; 2112 uint32_t gencntl; 2113 uint32_t htotaldisp; 2114 uint32_t hsyncstrt; 2115 uint32_t vtotaldisp; 2116 uint32_t vsyncstrt; 2117 uint32_t fphsyncstrt; 2118 uint32_t fpvsyncstrt; 2119 uint32_t fphtotaldisp; 2120 uint32_t fpvtotaldisp; 2121 uint32_t pitch; 2122 2123 sc = dp->rd_softc; 2124 cp = &dp->rd_crtcs[index]; 2125 crtc = cp->rc_number; 2126 mode = &cp->rc_videomode; 2127 2128 #if 1 2129 pitch = dp->rd_stride / dp->rd_bpp; 2130 #else 2131 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2132 (sc->sc_maxbpp * 8)); 2133 #endif 2134 switch (crtc) { 2135 case 0: 2136 gencntl = RADEON_CRTC_GEN_CNTL; 2137 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2138 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2139 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2140 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2141 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2142 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2143 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2144 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2145 break; 2146 case 1: 2147 gencntl = RADEON_CRTC2_GEN_CNTL; 2148 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2149 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2150 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2151 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2152 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2153 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2154 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2155 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2156 break; 2157 default: 2158 panic("Bad CRTC!"); 2159 break; 2160 } 2161 2162 /* 2163 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2164 */ 2165 /* only bother with 32bpp and 8bpp */ 2166 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2167 2168 if (crtc == 1) { 2169 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2170 } else { 2171 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2172 } 2173 2174 if (mode->flags & VID_DBLSCAN) 2175 v |= RADEON_CRTC2_DBL_SCAN_EN; 2176 2177 if (mode->flags & VID_INTERLACE) 2178 v |= RADEON_CRTC2_INTERLACE_EN; 2179 2180 if (mode->flags & VID_CSYNC) { 2181 v |= RADEON_CRTC2_CSYNC_EN; 2182 if (crtc == 1) 2183 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2184 } 2185 2186 PUT32(sc, gencntl, v); 2187 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2188 2189 /* 2190 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2191 */ 2192 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2193 if (crtc == 0) { 2194 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2195 RADEON_CRTC_DISPLAY_DIS); 2196 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2197 if (mode->flags & VID_CSYNC) 2198 v |= RADEON_CRTC_VSYNC_TRISTAT; 2199 } 2200 /* unconditional turn on CRT, in case first CRTC is DFP */ 2201 v |= RADEON_CRTC_CRT_ON; 2202 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2203 PRINTREG(RADEON_CRTC_EXT_CNTL); 2204 2205 /* 2206 * H_TOTAL_DISP 2207 */ 2208 v = ((mode->hdisplay / 8) - 1) << 16; 2209 v |= (mode->htotal / 8) - 1; 2210 PUT32(sc, htotaldisp, v); 2211 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2212 PUT32(sc, fphtotaldisp, v); 2213 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2214 2215 /* 2216 * H_SYNC_STRT_WID 2217 */ 2218 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2219 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2220 if (mode->flags & VID_NHSYNC) 2221 v |= RADEON_CRTC_H_SYNC_POL; 2222 PUT32(sc, hsyncstrt, v); 2223 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2224 PUT32(sc, fphsyncstrt, v); 2225 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2226 2227 /* 2228 * V_TOTAL_DISP 2229 */ 2230 v = ((mode->vdisplay - 1) << 16); 2231 v |= (mode->vtotal - 1); 2232 PUT32(sc, vtotaldisp, v); 2233 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2234 PUT32(sc, fpvtotaldisp, v); 2235 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2236 2237 /* 2238 * V_SYNC_STRT_WID 2239 */ 2240 v = ((mode->vsync_end - mode->vsync_start) << 16); 2241 v |= (mode->vsync_start - 1); 2242 if (mode->flags & VID_NVSYNC) 2243 v |= RADEON_CRTC_V_SYNC_POL; 2244 PUT32(sc, vsyncstrt, v); 2245 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2246 PUT32(sc, fpvsyncstrt, v); 2247 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2248 2249 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2250 2251 switch (crtc) { 2252 case 0: 2253 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2254 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2255 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2256 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2257 2258 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2259 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2260 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2261 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2262 PRINTREG(RADEON_CRTC_EXT_CNTL); 2263 PRINTREG(RADEON_CRTC_GEN_CNTL); 2264 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2265 break; 2266 2267 case 1: 2268 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2269 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2270 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2271 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2272 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2273 RADEON_CRTC2_VSYNC_DIS | 2274 RADEON_CRTC2_HSYNC_DIS | 2275 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2276 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2277 break; 2278 } 2279 } 2280 2281 int 2282 radeonfb_isblank(struct radeonfb_display *dp) 2283 { 2284 uint32_t reg, mask; 2285 2286 if(!dp->rd_softc->sc_mapped) 2287 return 1; 2288 2289 if (dp->rd_crtcs[0].rc_number) { 2290 reg = RADEON_CRTC2_GEN_CNTL; 2291 mask = RADEON_CRTC2_DISP_DIS; 2292 } else { 2293 reg = RADEON_CRTC_EXT_CNTL; 2294 mask = RADEON_CRTC_DISPLAY_DIS; 2295 } 2296 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2297 } 2298 2299 void 2300 radeonfb_blank(struct radeonfb_display *dp, int blank) 2301 { 2302 struct radeonfb_softc *sc = dp->rd_softc; 2303 uint32_t reg, mask; 2304 uint32_t fpreg, fpval; 2305 int i; 2306 2307 if (!sc->sc_mapped) 2308 return; 2309 2310 for (i = 0; i < dp->rd_ncrtcs; i++) { 2311 2312 if (dp->rd_crtcs[i].rc_number) { 2313 reg = RADEON_CRTC2_GEN_CNTL; 2314 mask = RADEON_CRTC2_DISP_DIS; 2315 fpreg = RADEON_FP2_GEN_CNTL; 2316 fpval = RADEON_FP2_ON; 2317 } else { 2318 reg = RADEON_CRTC_EXT_CNTL; 2319 mask = RADEON_CRTC_DISPLAY_DIS; 2320 fpreg = RADEON_FP_GEN_CNTL; 2321 fpval = RADEON_FP_FPON; 2322 } 2323 2324 if (blank) { 2325 SET32(sc, reg, mask); 2326 CLR32(sc, fpreg, fpval); 2327 } else { 2328 CLR32(sc, reg, mask); 2329 SET32(sc, fpreg, fpval); 2330 } 2331 } 2332 PRINTREG(RADEON_FP_GEN_CNTL); 2333 PRINTREG(RADEON_FP2_GEN_CNTL); 2334 } 2335 2336 void 2337 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2338 long *defattr) 2339 { 2340 struct radeonfb_display *dp = cookie; 2341 struct rasops_info *ri = &scr->scr_ri; 2342 2343 /* initialize font subsystem */ 2344 wsfont_init(); 2345 2346 DPRINTF(("init screen called, existing %d\n", existing)); 2347 2348 ri->ri_depth = dp->rd_bpp; 2349 ri->ri_width = dp->rd_virtx; 2350 ri->ri_height = dp->rd_virty; 2351 ri->ri_stride = dp->rd_stride; 2352 ri->ri_flg = RI_CENTER; 2353 switch (ri->ri_depth) { 2354 case 8: 2355 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2356 break; 2357 case 32: 2358 ri->ri_flg |= RI_ENABLE_ALPHA; 2359 /* we run radeons in RGB even on SPARC hardware */ 2360 ri->ri_rnum = 8; 2361 ri->ri_gnum = 8; 2362 ri->ri_bnum = 8; 2363 ri->ri_rpos = 16; 2364 ri->ri_gpos = 8; 2365 ri->ri_bpos = 0; 2366 break; 2367 } 2368 2369 ri->ri_bits = (void *)dp->rd_fbptr; 2370 2371 #ifdef VCONS_DRAW_INTR 2372 scr->scr_flags |= VCONS_DONT_READ; 2373 #endif 2374 2375 if (existing) { 2376 ri->ri_flg |= RI_CLEAR; 2377 2378 /* start a modeswitch now */ 2379 radeonfb_modeswitch(dp); 2380 } 2381 2382 /* 2383 * XXX: font selection should be based on properties, with some 2384 * normal/reasonable default. 2385 */ 2386 2387 /* initialize and look for an initial font */ 2388 rasops_init(ri, 0, 0); 2389 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2390 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2391 2392 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2393 dp->rd_virtx / ri->ri_font->fontwidth); 2394 2395 /* enable acceleration */ 2396 dp->rd_putchar = ri->ri_ops.putchar; 2397 ri->ri_ops.copyrows = radeonfb_copyrows; 2398 ri->ri_ops.copycols = radeonfb_copycols; 2399 ri->ri_ops.eraserows = radeonfb_eraserows; 2400 ri->ri_ops.erasecols = radeonfb_erasecols; 2401 /* pick a putchar method based on font and Radeon model */ 2402 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2403 /* got a bitmap font */ 2404 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2405 if (IS_R300(dp->rd_softc)) { 2406 /* 2407 * radeonfb_putchar() doesn't work right on some R3xx 2408 * so we use software drawing here, the wrapper just 2409 * makes sure the engine is idle before scribbling 2410 * into vram 2411 */ 2412 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2413 } else 2414 #endif 2415 ri->ri_ops.putchar = radeonfb_putchar; 2416 } else { 2417 /* got an alpha font */ 2418 switch(ri->ri_depth) { 2419 case 32: 2420 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2421 break; 2422 case 8: 2423 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2424 break; 2425 default: 2426 /* XXX this should never happen */ 2427 panic("%s: depth is not 8 or 32 but we got an" \ 2428 " alpha font?!", __func__); 2429 } 2430 } 2431 ri->ri_ops.cursor = radeonfb_cursor; 2432 } 2433 2434 void 2435 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2436 { 2437 uint32_t gen, ext, gen2 = 0; 2438 uint32_t agploc, aperbase, apersize, mcfbloc; 2439 2440 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2441 /* XXX */ 2442 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2443 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2444 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2445 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2446 2447 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2448 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2449 #if 0 2450 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2451 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2452 #endif 2453 2454 if (HAS_CRTC2(sc)) { 2455 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2456 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2457 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2458 } 2459 2460 delay(100000); 2461 2462 mcfbloc = (aperbase >> 16) | 2463 ((aperbase + (apersize - 1)) & 0xffff0000); 2464 2465 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2466 sc->sc_memsz = apersize; 2467 2468 if (((agploc & 0xffff) << 16) != 2469 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2470 agploc = mcfbloc & 0xffff0000U; 2471 agploc |= ((agploc + 0x10000) >> 16); 2472 } 2473 2474 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2475 2476 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2477 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2478 2479 DPRINTF(("aperbase = %u\n", aperbase)); 2480 PRINTREG(RADEON_MC_FB_LOCATION); 2481 PRINTREG(RADEON_MC_AGP_LOCATION); 2482 2483 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2484 2485 if (HAS_CRTC2(sc)) 2486 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2487 2488 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2489 2490 #if 0 2491 /* XXX: what is this AGP garbage? :-) */ 2492 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2493 #endif 2494 2495 delay(100000); 2496 2497 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2498 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2499 2500 if (HAS_CRTC2(sc)) 2501 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2502 } 2503 2504 void 2505 radeonfb_init_misc(struct radeonfb_softc *sc) 2506 { 2507 PUT32(sc, RADEON_BUS_CNTL, 2508 RADEON_BUS_MASTER_DIS | 2509 RADEON_BUS_PREFETCH_MODE_ACT | 2510 RADEON_BUS_PCI_READ_RETRY_EN | 2511 RADEON_BUS_PCI_WRT_RETRY_EN | 2512 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2513 RADEON_BUS_MSTR_RD_MULT | 2514 RADEON_BUS_MSTR_RD_LINE | 2515 RADEON_BUS_RD_DISCARD_EN | 2516 RADEON_BUS_MSTR_DISCONNECT_EN | 2517 RADEON_BUS_READ_BURST); 2518 2519 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2520 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2521 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2522 PUT32(sc, RADEON_RBBM_CNTL, 2523 (3 << RADEON_RB_SETTLE_SHIFT) | 2524 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2525 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2526 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2527 2528 /* XXX: figure out what these mean! */ 2529 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2530 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2531 #if 0 2532 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2533 #endif 2534 2535 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2536 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2537 } 2538 2539 /* 2540 * This loads a linear color map for true color. 2541 */ 2542 void 2543 radeonfb_init_palette(struct radeonfb_display *dp) 2544 { 2545 struct radeonfb_softc *sc = dp->rd_softc; 2546 int i, cc; 2547 uint32_t vclk; 2548 int crtc; 2549 2550 #define DAC_WIDTH ((1 << 10) - 1) 2551 #define CLUT_WIDTH ((1 << 8) - 1) 2552 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2553 2554 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2555 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2556 2557 /* initialize the palette for every CRTC used by this display */ 2558 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2559 crtc = dp->rd_crtcs[cc].rc_number; 2560 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2561 2562 if (crtc) 2563 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2564 else 2565 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2566 2567 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2568 2569 if (dp->rd_bpp == 8) { 2570 2571 /* R3G3B2 palette */ 2572 int j = 0; 2573 uint32_t tmp, r, g, b; 2574 2575 for (i = 0; i <= CLUT_WIDTH; ++i) { 2576 tmp = i & 0xe0; 2577 /* 2578 * replicate bits so 0xe0 maps to a red value of 0xff 2579 * in order to make white look actually white 2580 */ 2581 tmp |= (tmp >> 3) | (tmp >> 6); 2582 r = tmp; 2583 2584 tmp = (i & 0x1c) << 3; 2585 tmp |= (tmp >> 3) | (tmp >> 6); 2586 g = tmp; 2587 2588 tmp = (i & 0x03) << 6; 2589 tmp |= tmp >> 2; 2590 tmp |= tmp >> 4; 2591 b = tmp; 2592 2593 PUT32(sc, RADEON_PALETTE_30_DATA, 2594 (r << 22) | 2595 (g << 12) | 2596 (b << 2)); 2597 j += 3; 2598 } 2599 } else { 2600 /* linear ramp */ 2601 for (i = 0; i <= CLUT_WIDTH; ++i) { 2602 PUT32(sc, RADEON_PALETTE_30_DATA, 2603 (CLUT_COLOR(i) << 10) | 2604 (CLUT_COLOR(i) << 20) | 2605 (CLUT_COLOR(i))); 2606 } 2607 } 2608 } 2609 2610 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2611 PRINTREG(RADEON_DAC_CNTL2); 2612 2613 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2614 } 2615 2616 /* 2617 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2618 */ 2619 void 2620 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2621 { 2622 uint32_t tmp, save; 2623 2624 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2625 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2626 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2627 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2628 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2629 } 2630 2631 /* 2632 * Acceleration entry points. 2633 */ 2634 2635 /* this one draws characters using bitmap fonts */ 2636 static void 2637 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2638 { 2639 struct rasops_info *ri = cookie; 2640 struct vcons_screen *scr = ri->ri_hw; 2641 struct radeonfb_display *dp = scr->scr_cookie; 2642 struct radeonfb_softc *sc = dp->rd_softc; 2643 struct wsdisplay_font *font = PICK_FONT(ri, c); 2644 uint32_t w, h; 2645 int xd, yd, offset, i; 2646 uint32_t bg, fg, gmc; 2647 uint32_t reg; 2648 uint8_t *data8; 2649 uint16_t *data16; 2650 void *data; 2651 2652 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2653 return; 2654 2655 if (!CHAR_IN_FONT(c, font)) 2656 return; 2657 2658 w = font->fontwidth; 2659 h = font->fontheight; 2660 2661 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2662 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2663 2664 xd = ri->ri_xorigin + col * w; 2665 yd = ri->ri_yorigin + row * h; 2666 2667 if (c == 0x20) { 2668 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2669 return; 2670 } 2671 data = WSFONT_GLYPH(c, font); 2672 2673 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2674 2675 radeonfb_wait_fifo(sc, 9); 2676 2677 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2678 RADEON_GMC_BRUSH_NONE | 2679 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2680 RADEON_GMC_DST_CLIPPING | 2681 RADEON_ROP3_S | 2682 RADEON_DP_SRC_SOURCE_HOST_DATA | 2683 RADEON_GMC_CLR_CMP_CNTL_DIS | 2684 RADEON_GMC_WR_MSK_DIS | 2685 gmc); 2686 2687 PUT32(sc, RADEON_SC_LEFT, xd); 2688 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2689 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2690 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2691 PUT32(sc, RADEON_DP_CNTL, 2692 RADEON_DST_X_LEFT_TO_RIGHT | 2693 RADEON_DST_Y_TOP_TO_BOTTOM); 2694 2695 PUT32(sc, RADEON_SRC_X_Y, 0); 2696 offset = 32 - (font->stride << 3); 2697 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2698 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2699 2700 radeonfb_wait_fifo(sc, h); 2701 switch (font->stride) { 2702 case 1: { 2703 data8 = data; 2704 for (i = 0; i < h; i++) { 2705 reg = *data8; 2706 #if BYTE_ORDER == LITTLE_ENDIAN 2707 reg = reg << 24; 2708 #endif 2709 bus_space_write_stream_4(sc->sc_regt, 2710 sc->sc_regh, RADEON_HOST_DATA0, reg); 2711 data8++; 2712 } 2713 break; 2714 } 2715 case 2: { 2716 data16 = data; 2717 for (i = 0; i < h; i++) { 2718 reg = *data16; 2719 #if BYTE_ORDER == LITTLE_ENDIAN 2720 reg = reg << 16; 2721 #endif 2722 bus_space_write_stream_4(sc->sc_regt, 2723 sc->sc_regh, RADEON_HOST_DATA0, reg); 2724 data16++; 2725 } 2726 break; 2727 } 2728 } 2729 if (attr & 1) 2730 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2731 } 2732 2733 /* ... while this one is for anti-aliased ones */ 2734 static void 2735 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2736 { 2737 struct rasops_info *ri = cookie; 2738 struct vcons_screen *scr = ri->ri_hw; 2739 struct radeonfb_display *dp = scr->scr_cookie; 2740 struct radeonfb_softc *sc = dp->rd_softc; 2741 struct wsdisplay_font *font = PICK_FONT(ri, c); 2742 uint32_t bg, fg, gmc; 2743 uint8_t *data; 2744 int w, h, xd, yd; 2745 int i, r, g, b, aval; 2746 int rf, gf, bf, rb, gb, bb; 2747 uint32_t pixel; 2748 int rv; 2749 2750 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2751 return; 2752 2753 if (!CHAR_IN_FONT(c, font)) 2754 return; 2755 2756 w = font->fontwidth; 2757 h = font->fontheight; 2758 2759 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2760 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2761 2762 xd = ri->ri_xorigin + col * w; 2763 yd = ri->ri_yorigin + row * h; 2764 2765 if (c == 0x20) { 2766 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2767 if (attr & 1) 2768 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2769 return; 2770 } 2771 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2772 if (rv == GC_OK) 2773 return; 2774 2775 data = WSFONT_GLYPH(c, font); 2776 2777 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2778 2779 radeonfb_wait_fifo(sc, 5); 2780 2781 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2782 RADEON_GMC_BRUSH_NONE | 2783 RADEON_GMC_SRC_DATATYPE_COLOR | 2784 RADEON_ROP3_S | 2785 RADEON_DP_SRC_SOURCE_HOST_DATA | 2786 RADEON_GMC_CLR_CMP_CNTL_DIS | 2787 RADEON_GMC_WR_MSK_DIS | 2788 gmc); 2789 2790 PUT32(sc, RADEON_DP_CNTL, 2791 RADEON_DST_X_LEFT_TO_RIGHT | 2792 RADEON_DST_Y_TOP_TO_BOTTOM); 2793 2794 PUT32(sc, RADEON_SRC_X_Y, 0); 2795 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2796 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2797 2798 rf = (fg >> 16) & 0xff; 2799 rb = (bg >> 16) & 0xff; 2800 gf = (fg >> 8) & 0xff; 2801 gb = (bg >> 8) & 0xff; 2802 bf = fg & 0xff; 2803 bb = bg & 0xff; 2804 2805 /* 2806 * I doubt we can upload data faster than even the slowest Radeon 2807 * could process them, especially when doing the alpha blending stuff 2808 * along the way, so just make sure there's some room in the FIFO and 2809 * then hammer away 2810 * As it turns out we can, so make periodic stops to let the FIFO 2811 * drain. 2812 */ 2813 radeonfb_wait_fifo(sc, 20); 2814 for (i = 0; i < ri->ri_fontscale; i++) { 2815 aval = *data; 2816 data++; 2817 if (aval == 0) { 2818 pixel = bg; 2819 } else if (aval == 255) { 2820 pixel = fg; 2821 } else { 2822 r = aval * rf + (255 - aval) * rb; 2823 g = aval * gf + (255 - aval) * gb; 2824 b = aval * bf + (255 - aval) * bb; 2825 pixel = (r & 0xff00) << 8 | 2826 (g & 0xff00) | 2827 (b & 0xff00) >> 8; 2828 } 2829 if (i & 16) 2830 radeonfb_wait_fifo(sc, 20); 2831 PUT32(sc, RADEON_HOST_DATA0, pixel); 2832 } 2833 if (rv == GC_ADD) { 2834 glyphcache_add(&dp->rd_gc, c, xd, yd); 2835 } else 2836 if (attr & 1) 2837 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2838 2839 } 2840 2841 static void 2842 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2843 { 2844 struct rasops_info *ri = cookie; 2845 struct vcons_screen *scr = ri->ri_hw; 2846 struct radeonfb_display *dp = scr->scr_cookie; 2847 struct radeonfb_softc *sc = dp->rd_softc; 2848 struct wsdisplay_font *font = PICK_FONT(ri, c); 2849 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2850 int i, x, y, wi, he, r, g, b, aval; 2851 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2852 uint8_t *data8; 2853 int rv, cnt; 2854 2855 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2856 return; 2857 2858 if (!CHAR_IN_FONT(c, font)) 2859 return; 2860 2861 wi = font->fontwidth; 2862 he = font->fontheight; 2863 2864 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2865 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2866 2867 x = ri->ri_xorigin + col * wi; 2868 y = ri->ri_yorigin + row * he; 2869 2870 if (c == 0x20) { 2871 radeonfb_rectfill(dp, x, y, wi, he, bg); 2872 if (attr & 1) 2873 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2874 return; 2875 } 2876 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2877 if (rv == GC_OK) 2878 return; 2879 2880 data8 = WSFONT_GLYPH(c, font); 2881 2882 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2883 2884 radeonfb_wait_fifo(sc, 5); 2885 2886 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2887 RADEON_GMC_BRUSH_NONE | 2888 RADEON_GMC_SRC_DATATYPE_COLOR | 2889 RADEON_ROP3_S | 2890 RADEON_DP_SRC_SOURCE_HOST_DATA | 2891 RADEON_GMC_CLR_CMP_CNTL_DIS | 2892 RADEON_GMC_WR_MSK_DIS | 2893 gmc); 2894 2895 PUT32(sc, RADEON_DP_CNTL, 2896 RADEON_DST_X_LEFT_TO_RIGHT | 2897 RADEON_DST_Y_TOP_TO_BOTTOM); 2898 2899 PUT32(sc, RADEON_SRC_X_Y, 0); 2900 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2901 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2902 2903 /* 2904 * we need the RGB colours here, so get offsets into rasops_cmap 2905 */ 2906 fgo = ((attr >> 24) & 0xf) * 3; 2907 bgo = ((attr >> 16) & 0xf) * 3; 2908 2909 r0 = rasops_cmap[bgo]; 2910 r1 = rasops_cmap[fgo]; 2911 g0 = rasops_cmap[bgo + 1]; 2912 g1 = rasops_cmap[fgo + 1]; 2913 b0 = rasops_cmap[bgo + 2]; 2914 b1 = rasops_cmap[fgo + 2]; 2915 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2916 bg8 = R3G3B2(r0, g0, b0); 2917 fg8 = R3G3B2(r1, g1, b1); 2918 2919 radeonfb_wait_fifo(sc, 20); 2920 cnt = 0; 2921 for (i = 0; i < ri->ri_fontscale; i++) { 2922 aval = *data8; 2923 if (aval == 0) { 2924 pixel = bg8; 2925 } else if (aval == 255) { 2926 pixel = fg8; 2927 } else { 2928 r = aval * r1 + (255 - aval) * r0; 2929 g = aval * g1 + (255 - aval) * g0; 2930 b = aval * b1 + (255 - aval) * b0; 2931 pixel = ((r & 0xe000) >> 8) | 2932 ((g & 0xe000) >> 11) | 2933 ((b & 0xc000) >> 14); 2934 } 2935 latch |= pixel << (8 * (i & 3)); 2936 /* write in 32bit chunks */ 2937 if ((i & 3) == 3) { 2938 PUT32(sc, RADEON_HOST_DATA0, latch); 2939 /* 2940 * not strictly necessary, old data should be shifted 2941 * out 2942 */ 2943 latch = 0; 2944 cnt++; 2945 if (cnt > 16) { 2946 cnt = 0; 2947 radeonfb_wait_fifo(sc, 20); 2948 } 2949 } 2950 data8++; 2951 } 2952 /* if we have pixels left in latch write them out */ 2953 if ((i & 3) != 0) { 2954 /* 2955 * radeon is weird - apparently leftover pixels are written 2956 * from the middle, not from the left as everything else 2957 */ 2958 PUT32(sc, RADEON_HOST_DATA0, latch); 2959 } 2960 2961 if (rv == GC_ADD) { 2962 glyphcache_add(&dp->rd_gc, c, x, y); 2963 } else 2964 if (attr & 1) 2965 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2966 2967 } 2968 2969 /* 2970 * wrapper for software character drawing 2971 * just sync the engine and call rasops*_putchar() 2972 */ 2973 2974 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2975 static void 2976 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2977 { 2978 struct rasops_info *ri = cookie; 2979 struct vcons_screen *scr = ri->ri_hw; 2980 struct radeonfb_display *dp = scr->scr_cookie; 2981 2982 radeonfb_engine_idle(dp->rd_softc); 2983 dp->rd_putchar(ri, row, col, c, attr); 2984 } 2985 #endif 2986 2987 static void 2988 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2989 { 2990 struct rasops_info *ri = cookie; 2991 struct vcons_screen *scr = ri->ri_hw; 2992 struct radeonfb_display *dp = scr->scr_cookie; 2993 uint32_t x, y, w, h, fg, bg, ul; 2994 2995 /* XXX: check for full emulation mode? */ 2996 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2997 x = ri->ri_xorigin; 2998 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2999 w = ri->ri_emuwidth; 3000 h = ri->ri_font->fontheight * nrows; 3001 3002 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3003 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3004 } 3005 } 3006 3007 static void 3008 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3009 { 3010 struct rasops_info *ri = cookie; 3011 struct vcons_screen *scr = ri->ri_hw; 3012 struct radeonfb_display *dp = scr->scr_cookie; 3013 uint32_t x, ys, yd, w, h; 3014 3015 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3016 x = ri->ri_xorigin; 3017 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3018 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3019 w = ri->ri_emuwidth; 3020 h = ri->ri_font->fontheight * nrows; 3021 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3022 RADEON_ROP3_S); 3023 } 3024 } 3025 3026 static void 3027 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3028 { 3029 struct rasops_info *ri = cookie; 3030 struct vcons_screen *scr = ri->ri_hw; 3031 struct radeonfb_display *dp = scr->scr_cookie; 3032 uint32_t xs, xd, y, w, h; 3033 3034 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3035 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3036 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3037 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3038 w = ri->ri_font->fontwidth * ncols; 3039 h = ri->ri_font->fontheight; 3040 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3041 RADEON_ROP3_S); 3042 } 3043 } 3044 3045 static void 3046 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3047 long fillattr) 3048 { 3049 struct rasops_info *ri = cookie; 3050 struct vcons_screen *scr = ri->ri_hw; 3051 struct radeonfb_display *dp = scr->scr_cookie; 3052 uint32_t x, y, w, h, fg, bg, ul; 3053 3054 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3055 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3056 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3057 w = ri->ri_font->fontwidth * ncols; 3058 h = ri->ri_font->fontheight; 3059 3060 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3061 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3062 } 3063 } 3064 3065 static void 3066 radeonfb_cursor(void *cookie, int on, int row, int col) 3067 { 3068 struct rasops_info *ri = cookie; 3069 struct vcons_screen *scr = ri->ri_hw; 3070 struct radeonfb_display *dp = scr->scr_cookie; 3071 int x, y, wi, he; 3072 3073 wi = ri->ri_font->fontwidth; 3074 he = ri->ri_font->fontheight; 3075 3076 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3077 x = ri->ri_ccol * wi + ri->ri_xorigin; 3078 y = ri->ri_crow * he + ri->ri_yorigin; 3079 /* first turn off the old cursor */ 3080 if (ri->ri_flg & RI_CURSOR) { 3081 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3082 RADEON_ROP3_Dn); 3083 ri->ri_flg &= ~RI_CURSOR; 3084 } 3085 ri->ri_crow = row; 3086 ri->ri_ccol = col; 3087 /* then (possibly) turn on the new one */ 3088 if (on) { 3089 x = ri->ri_ccol * wi + ri->ri_xorigin; 3090 y = ri->ri_crow * he + ri->ri_yorigin; 3091 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3092 RADEON_ROP3_Dn); 3093 ri->ri_flg |= RI_CURSOR; 3094 } 3095 } else { 3096 scr->scr_ri.ri_crow = row; 3097 scr->scr_ri.ri_ccol = col; 3098 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3099 } 3100 } 3101 3102 /* 3103 * Underlying acceleration support. 3104 */ 3105 3106 static void 3107 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3108 int width, int height, uint32_t color) 3109 { 3110 struct radeonfb_softc *sc = dp->rd_softc; 3111 uint32_t gmc; 3112 3113 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3114 3115 radeonfb_wait_fifo(sc, 6); 3116 3117 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3118 RADEON_GMC_BRUSH_SOLID_COLOR | 3119 RADEON_GMC_SRC_DATATYPE_COLOR | 3120 RADEON_GMC_CLR_CMP_CNTL_DIS | 3121 RADEON_ROP3_P | gmc); 3122 3123 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3124 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3125 PUT32(sc, RADEON_DP_CNTL, 3126 RADEON_DST_X_LEFT_TO_RIGHT | 3127 RADEON_DST_Y_TOP_TO_BOTTOM); 3128 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3129 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3130 3131 } 3132 3133 static void 3134 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3135 int width, int height, long attr) 3136 { 3137 struct radeonfb_display *dp = cookie; 3138 3139 radeonfb_rectfill(dp, dstx, dsty, width, height, 3140 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3141 } 3142 3143 static void 3144 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3145 int dstx, int dsty, int width, int height, int rop) 3146 { 3147 struct radeonfb_display *dp = cookie; 3148 struct radeonfb_softc *sc = dp->rd_softc; 3149 uint32_t gmc; 3150 uint32_t dir; 3151 3152 if (dsty < srcy) { 3153 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3154 } else { 3155 srcy += height - 1; 3156 dsty += height - 1; 3157 dir = 0; 3158 } 3159 if (dstx < srcx) { 3160 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3161 } else { 3162 srcx += width - 1; 3163 dstx += width - 1; 3164 } 3165 3166 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3167 3168 radeonfb_wait_fifo(sc, 6); 3169 3170 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3171 RADEON_GMC_BRUSH_SOLID_COLOR | 3172 RADEON_GMC_SRC_DATATYPE_COLOR | 3173 RADEON_GMC_CLR_CMP_CNTL_DIS | 3174 RADEON_DP_SRC_SOURCE_MEMORY | 3175 rop | gmc); 3176 3177 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3178 PUT32(sc, RADEON_DP_CNTL, dir); 3179 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3180 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3181 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3182 } 3183 3184 static void 3185 radeonfb_engine_idle(struct radeonfb_softc *sc) 3186 { 3187 3188 radeonfb_wait_fifo(sc, 64); 3189 while ((GET32(sc, RADEON_RBBM_STATUS) & 3190 RADEON_RBBM_ACTIVE) != 0); 3191 radeonfb_engine_flush(sc); 3192 } 3193 3194 static inline void 3195 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3196 { 3197 int i; 3198 3199 for (i = RADEON_TIMEOUT; i; i--) { 3200 if ((GET32(sc, RADEON_RBBM_STATUS) & 3201 RADEON_RBBM_FIFOCNT_MASK) >= n) 3202 return; 3203 } 3204 #ifdef DIAGNOSTIC 3205 if (!i) 3206 printf("%s: timed out waiting for fifo (%x)\n", 3207 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3208 #endif 3209 } 3210 3211 static void 3212 radeonfb_engine_flush(struct radeonfb_softc *sc) 3213 { 3214 int i = 0; 3215 3216 if (IS_R300(sc)) { 3217 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3218 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3219 i++; 3220 } 3221 } else { 3222 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3223 RADEON_RB2D_DC_FLUSH_ALL); 3224 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3225 RADEON_RB2D_DC_BUSY) { 3226 i++; 3227 } 3228 } 3229 #ifdef DIAGNOSTIC 3230 if (i > RADEON_TIMEOUT) 3231 printf("%s: engine flush timed out!\n", XNAME(sc)); 3232 #endif 3233 } 3234 3235 static inline void 3236 radeonfb_unclip(struct radeonfb_softc *sc) 3237 { 3238 3239 radeonfb_wait_fifo(sc, 2); 3240 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3241 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3242 } 3243 3244 static void 3245 radeonfb_engine_init(struct radeonfb_display *dp) 3246 { 3247 struct radeonfb_softc *sc = dp->rd_softc; 3248 uint32_t pitch; 3249 volatile uint32_t junk; 3250 3251 /* no 3D */ 3252 PUT32(sc, RADEON_RB3D_CNTL, 0); 3253 3254 radeonfb_engine_reset(sc); 3255 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3256 3257 radeonfb_wait_fifo(sc, 1); 3258 if (!IS_R300(sc)) 3259 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3260 3261 radeonfb_wait_fifo(sc, 3); 3262 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3263 (pitch << 22) | (sc->sc_aperbase >> 10)); 3264 3265 3266 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3267 (pitch << 22) | (sc->sc_aperbase >> 10)); 3268 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3269 (pitch << 22) | (sc->sc_aperbase >> 10)); 3270 3271 junk = GET32(sc, RADEON_DP_DATATYPE); 3272 3273 /* default scissors -- no clipping */ 3274 radeonfb_wait_fifo(sc, 1); 3275 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3276 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3277 3278 radeonfb_wait_fifo(sc, 1); 3279 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3280 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3281 RADEON_GMC_CLR_CMP_CNTL_DIS | 3282 RADEON_GMC_BRUSH_SOLID_COLOR | 3283 RADEON_GMC_SRC_DATATYPE_COLOR); 3284 3285 radeonfb_wait_fifo(sc, 10); 3286 PUT32(sc, RADEON_DST_LINE_START, 0); 3287 PUT32(sc, RADEON_DST_LINE_END, 0); 3288 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3289 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3290 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3291 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3292 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3293 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3294 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3295 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3296 radeonfb_engine_idle(sc); 3297 } 3298 3299 static void 3300 radeonfb_engine_reset(struct radeonfb_softc *sc) 3301 { 3302 uint32_t hpc, rbbm, mclkcntl, clkindex; 3303 3304 radeonfb_engine_flush(sc); 3305 3306 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3307 if (HAS_R300CG(sc)) 3308 radeonfb_r300cg_workaround(sc); 3309 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3310 3311 /* 3312 * According to comments in XFree code, resetting the HDP via 3313 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3314 * So we use HOST_PATH_CNTL instead. 3315 */ 3316 3317 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3318 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3319 if (IS_R300(sc)) { 3320 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3321 RADEON_SOFT_RESET_CP | 3322 RADEON_SOFT_RESET_HI | 3323 RADEON_SOFT_RESET_E2); 3324 GET32(sc, RADEON_RBBM_SOFT_RESET); 3325 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3326 /* 3327 * XXX: this bit is not defined in any ATI docs I have, 3328 * nor in the XFree code, but XFree does it. Why? 3329 */ 3330 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3331 } else { 3332 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3333 RADEON_SOFT_RESET_CP | 3334 RADEON_SOFT_RESET_SE | 3335 RADEON_SOFT_RESET_RE | 3336 RADEON_SOFT_RESET_PP | 3337 RADEON_SOFT_RESET_E2 | 3338 RADEON_SOFT_RESET_RB); 3339 GET32(sc, RADEON_RBBM_SOFT_RESET); 3340 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3341 ~(RADEON_SOFT_RESET_CP | 3342 RADEON_SOFT_RESET_SE | 3343 RADEON_SOFT_RESET_RE | 3344 RADEON_SOFT_RESET_PP | 3345 RADEON_SOFT_RESET_E2 | 3346 RADEON_SOFT_RESET_RB)); 3347 GET32(sc, RADEON_RBBM_SOFT_RESET); 3348 } 3349 3350 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3351 GET32(sc, RADEON_HOST_PATH_CNTL); 3352 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3353 3354 if (IS_R300(sc)) 3355 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3356 3357 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3358 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3359 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3360 3361 if (HAS_R300CG(sc)) 3362 radeonfb_r300cg_workaround(sc); 3363 } 3364 3365 static int 3366 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3367 { 3368 int x, y; 3369 3370 x = pos->x; 3371 y = pos->y; 3372 3373 /* 3374 * This doesn't let a cursor move off the screen. I'm not 3375 * sure if this will have negative effects for e.g. Xinerama. 3376 * I'd guess Xinerama handles it by changing the cursor shape, 3377 * but that needs verification. 3378 */ 3379 if (x >= dp->rd_virtx) 3380 x = dp->rd_virtx - 1; 3381 if (x < 0) 3382 x = 0; 3383 if (y >= dp->rd_virty) 3384 y = dp->rd_virty - 1; 3385 if (y < 0) 3386 y = 0; 3387 3388 dp->rd_cursor.rc_pos.x = x; 3389 dp->rd_cursor.rc_pos.y = y; 3390 3391 radeonfb_cursor_position(dp); 3392 return 0; 3393 } 3394 3395 static int 3396 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3397 { 3398 unsigned flags; 3399 3400 uint8_t r[2], g[2], b[2]; 3401 unsigned index, count; 3402 int i, err; 3403 int pitch, size; 3404 struct radeonfb_cursor nc; 3405 3406 flags = wc->which; 3407 3408 /* copy old values */ 3409 nc = dp->rd_cursor; 3410 3411 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3412 index = wc->cmap.index; 3413 count = wc->cmap.count; 3414 3415 if (index >= 2 || (index + count) > 2) 3416 return EINVAL; 3417 3418 err = copyin(wc->cmap.red, &r[index], count); 3419 if (err) 3420 return err; 3421 err = copyin(wc->cmap.green, &g[index], count); 3422 if (err) 3423 return err; 3424 err = copyin(wc->cmap.blue, &b[index], count); 3425 if (err) 3426 return err; 3427 3428 for (i = index; i < index + count; i++) { 3429 nc.rc_cmap[i] = 3430 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3431 } 3432 } 3433 3434 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3435 if ((wc->size.x > RADEON_CURSORMAXX) || 3436 (wc->size.y > RADEON_CURSORMAXY)) 3437 return EINVAL; 3438 3439 /* figure bytes per line */ 3440 pitch = (wc->size.x + 7) / 8; 3441 size = pitch * wc->size.y; 3442 3443 /* clear the old cursor and mask */ 3444 memset(nc.rc_image, 0, 512); 3445 memset(nc.rc_mask, 0, 512); 3446 3447 nc.rc_size = wc->size; 3448 3449 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3450 return err; 3451 3452 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3453 return err; 3454 } 3455 3456 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3457 nc.rc_hot = wc->hot; 3458 if (nc.rc_hot.x >= nc.rc_size.x) 3459 nc.rc_hot.x = nc.rc_size.x - 1; 3460 if (nc.rc_hot.y >= nc.rc_size.y) 3461 nc.rc_hot.y = nc.rc_size.y - 1; 3462 } 3463 3464 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3465 nc.rc_pos = wc->pos; 3466 if (nc.rc_pos.x >= dp->rd_virtx) 3467 nc.rc_pos.x = dp->rd_virtx - 1; 3468 #if 0 3469 if (nc.rc_pos.x < 0) 3470 nc.rc_pos.x = 0; 3471 #endif 3472 if (nc.rc_pos.y >= dp->rd_virty) 3473 nc.rc_pos.y = dp->rd_virty - 1; 3474 #if 0 3475 if (nc.rc_pos.y < 0) 3476 nc.rc_pos.y = 0; 3477 #endif 3478 } 3479 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3480 nc.rc_visible = wc->enable; 3481 } 3482 3483 dp->rd_cursor = nc; 3484 radeonfb_cursor_update(dp, wc->which); 3485 3486 return 0; 3487 } 3488 3489 /* 3490 * Change the cursor shape. Call this with the cursor locked to avoid 3491 * flickering/tearing. 3492 */ 3493 static void 3494 radeonfb_cursor_shape(struct radeonfb_display *dp) 3495 { 3496 uint8_t and[512], xor[512]; 3497 int i, j, src, dst /* , pitch */; 3498 const uint8_t *msk = dp->rd_cursor.rc_mask; 3499 const uint8_t *img = dp->rd_cursor.rc_image; 3500 3501 /* 3502 * Radeon cursor data interleaves one line of AND data followed 3503 * by a line of XOR data. (Each line corresponds to a whole hardware 3504 * pitch - i.e. 64 pixels or 8 bytes.) 3505 * 3506 * The cursor is displayed using the following table: 3507 * 3508 * AND XOR Result 3509 * ---------------------- 3510 * 0 0 Cursor color 0 3511 * 0 1 Cursor color 1 3512 * 1 0 Transparent 3513 * 1 1 Complement of background 3514 * 3515 * Our masks are therefore different from what we were passed. 3516 * Passed in, I'm assuming the data represents either color 0 or 1, 3517 * and a mask, so the passed in table looks like: 3518 * 3519 * IMG Mask Result 3520 * ----------------------- 3521 * 0 0 Transparent 3522 * 0 1 Cursor color 0 3523 * 1 0 Transparent 3524 * 1 1 Cursor color 1 3525 * 3526 * IF mask bit == 1, AND = 0, XOR = color. 3527 * IF mask bit == 0, AND = 1, XOR = 0. 3528 * 3529 * hence: AND = ~(mask); XOR = color & ~(mask); 3530 */ 3531 3532 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3533 3534 /* start by assuming all bits are transparent */ 3535 memset(and, 0xff, 512); 3536 memset(xor, 0x00, 512); 3537 3538 src = 0; 3539 dst = 0; 3540 for (i = 0; i < 64; i++) { 3541 for (j = 0; j < 64; j += 8) { 3542 if ((i < dp->rd_cursor.rc_size.y) && 3543 (j < dp->rd_cursor.rc_size.x)) { 3544 3545 /* take care to leave odd bits alone */ 3546 and[dst] &= ~(msk[src]); 3547 xor[dst] = img[src] & msk[src]; 3548 src++; 3549 } 3550 dst++; 3551 } 3552 } 3553 3554 /* copy the image into place */ 3555 for (i = 0; i < 64; i++) { 3556 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3557 &and[i * 8], 8); 3558 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3559 &xor[i * 8], 8); 3560 } 3561 } 3562 3563 static void 3564 radeonfb_cursor_position(struct radeonfb_display *dp) 3565 { 3566 struct radeonfb_softc *sc = dp->rd_softc; 3567 uint32_t offset, hvoff, hvpos; /* registers */ 3568 uint32_t coff; /* cursor offset */ 3569 int i, x, y, xoff, yoff, crtcoff; 3570 3571 /* 3572 * XXX: this also needs to handle pan/scan 3573 */ 3574 for (i = 0; i < dp->rd_ncrtcs; i++) { 3575 3576 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3577 3578 if (rcp->rc_number) { 3579 offset = RADEON_CUR2_OFFSET; 3580 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3581 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3582 crtcoff = RADEON_CRTC2_OFFSET; 3583 } else { 3584 offset = RADEON_CUR_OFFSET; 3585 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3586 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3587 crtcoff = RADEON_CRTC_OFFSET; 3588 } 3589 3590 x = dp->rd_cursor.rc_pos.x; 3591 y = dp->rd_cursor.rc_pos.y; 3592 3593 while (y < rcp->rc_yoffset) { 3594 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3595 } 3596 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3597 rcp->rc_yoffset += RADEON_PANINCREMENT; 3598 } 3599 while (x < rcp->rc_xoffset) { 3600 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3601 } 3602 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3603 rcp->rc_xoffset += RADEON_PANINCREMENT; 3604 } 3605 3606 /* adjust for the cursor's hotspot */ 3607 x -= dp->rd_cursor.rc_hot.x; 3608 y -= dp->rd_cursor.rc_hot.y; 3609 xoff = yoff = 0; 3610 3611 if (x >= dp->rd_virtx) 3612 x = dp->rd_virtx - 1; 3613 if (y >= dp->rd_virty) 3614 y = dp->rd_virty - 1; 3615 3616 /* now adjust cursor so it is relative to viewport */ 3617 x -= rcp->rc_xoffset; 3618 y -= rcp->rc_yoffset; 3619 3620 /* 3621 * no need to check for fall off, because we should 3622 * never move off the screen entirely! 3623 */ 3624 coff = 0; 3625 if (x < 0) { 3626 xoff = -x; 3627 x = 0; 3628 } 3629 if (y < 0) { 3630 yoff = -y; 3631 y = 0; 3632 coff = (yoff * 2) * 8; 3633 } 3634 3635 /* pan the display */ 3636 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3637 rcp->rc_xoffset); 3638 3639 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3640 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3641 /* NB: this unlocks the cursor */ 3642 PUT32(sc, hvpos, (x << 16) | y); 3643 } 3644 } 3645 3646 static void 3647 radeonfb_cursor_visible(struct radeonfb_display *dp) 3648 { 3649 int i; 3650 uint32_t gencntl, bit; 3651 3652 for (i = 0; i < dp->rd_ncrtcs; i++) { 3653 if (dp->rd_crtcs[i].rc_number) { 3654 gencntl = RADEON_CRTC2_GEN_CNTL; 3655 bit = RADEON_CRTC2_CUR_EN; 3656 } else { 3657 gencntl = RADEON_CRTC_GEN_CNTL; 3658 bit = RADEON_CRTC_CUR_EN; 3659 } 3660 3661 if (dp->rd_cursor.rc_visible) 3662 SET32(dp->rd_softc, gencntl, bit); 3663 else 3664 CLR32(dp->rd_softc, gencntl, bit); 3665 } 3666 } 3667 3668 static void 3669 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3670 { 3671 int i; 3672 uint32_t c0reg, c1reg; 3673 struct radeonfb_softc *sc = dp->rd_softc; 3674 3675 for (i = 0; i < dp->rd_ncrtcs; i++) { 3676 if (dp->rd_crtcs[i].rc_number) { 3677 c0reg = RADEON_CUR2_CLR0; 3678 c1reg = RADEON_CUR2_CLR1; 3679 } else { 3680 c0reg = RADEON_CUR_CLR0; 3681 c1reg = RADEON_CUR_CLR1; 3682 } 3683 3684 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3685 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3686 } 3687 } 3688 3689 static void 3690 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3691 { 3692 struct radeonfb_softc *sc; 3693 int i; 3694 3695 sc = dp->rd_softc; 3696 for (i = 0; i < dp->rd_ncrtcs; i++) { 3697 if (dp->rd_crtcs[i].rc_number) { 3698 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3699 } else { 3700 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3701 } 3702 } 3703 3704 if (which & WSDISPLAY_CURSOR_DOCMAP) 3705 radeonfb_cursor_cmap(dp); 3706 3707 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3708 radeonfb_cursor_shape(dp); 3709 3710 if (which & WSDISPLAY_CURSOR_DOCUR) 3711 radeonfb_cursor_visible(dp); 3712 3713 /* this one is unconditional, because it updates other stuff */ 3714 radeonfb_cursor_position(dp); 3715 } 3716 3717 static struct videomode * 3718 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3719 { 3720 int r1, r2; 3721 3722 /* otherwise pick the higher refresh rate */ 3723 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3724 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3725 3726 return (r1 < r2 ? m2 : m1); 3727 } 3728 3729 static const struct videomode * 3730 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3731 int x, int y) 3732 { 3733 struct edid_info *ep = &rp->rp_edid; 3734 struct videomode *vmp = NULL; 3735 int i; 3736 3737 if (!rp->rp_edid_valid) { 3738 /* fallback to safe mode */ 3739 return radeonfb_modelookup(sc->sc_defaultmode); 3740 } 3741 3742 /* always choose the preferred mode first! */ 3743 if (ep->edid_preferred_mode) { 3744 3745 /* XXX: add auto-stretching support for native mode */ 3746 3747 /* this may want panning to occur, btw */ 3748 if ((ep->edid_preferred_mode->hdisplay <= x) && 3749 (ep->edid_preferred_mode->vdisplay <= y)) 3750 return ep->edid_preferred_mode; 3751 } 3752 3753 for (i = 0; i < ep->edid_nmodes; i++) { 3754 /* 3755 * We elect to pick a resolution that is too large for 3756 * the monitor than one that is too small. This means 3757 * that we will prefer to pan rather than to try to 3758 * center a smaller display on a larger screen. In 3759 * practice, this shouldn't matter because if a 3760 * monitor can support a larger resolution, it can 3761 * probably also support the smaller. A specific 3762 * exception is fixed format panels, but hopefully 3763 * they are properly dealt with by the "autostretch" 3764 * logic above. 3765 */ 3766 if ((ep->edid_modes[i].hdisplay > x) || 3767 (ep->edid_modes[i].vdisplay > y)) { 3768 continue; 3769 } 3770 3771 /* 3772 * at this point, the display mode is no larger than 3773 * what we've requested. 3774 */ 3775 if (vmp == NULL) 3776 vmp = &ep->edid_modes[i]; 3777 3778 /* eliminate smaller modes */ 3779 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3780 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3781 continue; 3782 3783 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3784 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3785 vmp = &ep->edid_modes[i]; 3786 continue; 3787 } 3788 3789 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3790 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3791 3792 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3793 } 3794 3795 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3796 } 3797 3798 static int 3799 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3800 { 3801 int i; 3802 3803 for (i = 0; i < nlist; i++) { 3804 if ((x == list[i].hdisplay) && 3805 (y == list[i].vdisplay)) { 3806 return 1; 3807 } 3808 } 3809 return 0; 3810 } 3811 3812 static void 3813 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3814 int pan) 3815 { 3816 struct radeonfb_port *rp; 3817 struct edid_info *ep; 3818 int i, j; 3819 3820 *x = 0; 3821 *y = 0; 3822 3823 if (pan) { 3824 for (i = 0; i < dp->rd_ncrtcs; i++) { 3825 rp = dp->rd_crtcs[i].rc_port; 3826 ep = &rp->rp_edid; 3827 if (!rp->rp_edid_valid) { 3828 /* monitor not present */ 3829 continue; 3830 } 3831 3832 /* 3833 * For now we are ignoring "conflict" that 3834 * could occur when mixing some modes like 3835 * 1280x1024 and 1400x800. It isn't clear 3836 * which is better, so the first one wins. 3837 */ 3838 for (j = 0; j < ep->edid_nmodes; j++) { 3839 /* 3840 * ignore resolutions that are too big for 3841 * the radeon 3842 */ 3843 if (ep->edid_modes[j].hdisplay > 3844 dp->rd_softc->sc_maxx) 3845 continue; 3846 if (ep->edid_modes[j].vdisplay > 3847 dp->rd_softc->sc_maxy) 3848 continue; 3849 3850 /* 3851 * pick largest resolution, the 3852 * smaller monitor will pan 3853 */ 3854 if ((ep->edid_modes[j].hdisplay >= *x) && 3855 (ep->edid_modes[j].vdisplay >= *y)) { 3856 *x = ep->edid_modes[j].hdisplay; 3857 *y = ep->edid_modes[j].vdisplay; 3858 } 3859 } 3860 } 3861 3862 } else { 3863 struct videomode modes[64]; 3864 int nmodes = 0; 3865 int valid = 0; 3866 3867 for (i = 0; i < dp->rd_ncrtcs; i++) { 3868 /* 3869 * pick the largest resolution in common. 3870 */ 3871 rp = dp->rd_crtcs[i].rc_port; 3872 ep = &rp->rp_edid; 3873 3874 if (!rp->rp_edid_valid) 3875 continue; 3876 3877 if (!valid) { 3878 /* 3879 * Pick the preferred mode for this port 3880 * if available. 3881 */ 3882 if (ep->edid_preferred_mode) { 3883 struct videomode *vmp = 3884 ep->edid_preferred_mode; 3885 3886 if ((vmp->hdisplay <= 3887 dp->rd_softc->sc_maxx) && 3888 (vmp->vdisplay <= 3889 dp->rd_softc->sc_maxy)) 3890 modes[nmodes++] = *vmp; 3891 } else { 3892 3893 /* initialize starting list */ 3894 for (j = 0; j < ep->edid_nmodes; j++) { 3895 /* 3896 * ignore resolutions that are 3897 * too big for the radeon 3898 */ 3899 if (ep->edid_modes[j].hdisplay > 3900 dp->rd_softc->sc_maxx) 3901 continue; 3902 if (ep->edid_modes[j].vdisplay > 3903 dp->rd_softc->sc_maxy) 3904 continue; 3905 3906 modes[nmodes] = 3907 ep->edid_modes[j]; 3908 nmodes++; 3909 } 3910 } 3911 valid = 1; 3912 } else { 3913 /* merge into preexisting list */ 3914 for (j = 0; j < nmodes; j++) { 3915 if (!radeonfb_hasres(ep->edid_modes, 3916 ep->edid_nmodes, 3917 modes[j].hdisplay, 3918 modes[j].vdisplay)) { 3919 modes[j] = modes[nmodes]; 3920 j--; 3921 nmodes--; 3922 } 3923 } 3924 } 3925 } 3926 3927 /* now we have to pick from the merged list */ 3928 for (i = 0; i < nmodes; i++) { 3929 if ((modes[i].hdisplay >= *x) && 3930 (modes[i].vdisplay >= *y)) { 3931 *x = modes[i].hdisplay; 3932 *y = modes[i].vdisplay; 3933 } 3934 } 3935 } 3936 3937 if ((*x == 0) || (*y == 0)) { 3938 /* fallback to safe mode */ 3939 *x = 640; 3940 *y = 480; 3941 } 3942 } 3943 3944 /* 3945 * backlight levels are linear on: 3946 * - RV200, RV250, RV280, RV350 3947 * - but NOT on PowerBook4,3 6,3 6,5 3948 * according to Linux' radeonfb 3949 */ 3950 3951 /* Get the current backlight level for the display. */ 3952 3953 static int 3954 radeonfb_get_backlight(struct radeonfb_display *dp) 3955 { 3956 int s; 3957 uint32_t level; 3958 3959 s = spltty(); 3960 3961 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3962 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3963 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3964 3965 /* 3966 * On some chips, we should negate the backlight level. 3967 * XXX Find out on which chips. 3968 */ 3969 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3970 level = RADEONFB_BACKLIGHT_MAX - level; 3971 3972 splx(s); 3973 3974 return level; 3975 } 3976 3977 /* Set the backlight to the given level for the display. */ 3978 static void 3979 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3980 { 3981 if (dp->rd_bl_on == on) 3982 return; 3983 dp->rd_bl_on = on; 3984 radeonfb_set_backlight(dp, dp->rd_bl_level); 3985 } 3986 3987 static int 3988 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3989 { 3990 struct radeonfb_softc *sc; 3991 int rlevel, s; 3992 uint32_t lvds; 3993 3994 s = spltty(); 3995 3996 dp->rd_bl_level = level; 3997 if (dp->rd_bl_on == 0) 3998 level = 0; 3999 4000 if (level < 0) 4001 level = 0; 4002 else if (level >= RADEONFB_BACKLIGHT_MAX) 4003 level = RADEONFB_BACKLIGHT_MAX; 4004 4005 sc = dp->rd_softc; 4006 4007 /* On some chips, we should negate the backlight level. */ 4008 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4009 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4010 } else 4011 rlevel = level; 4012 4013 callout_stop(&dp->rd_bl_lvds_co); 4014 radeonfb_engine_idle(sc); 4015 4016 /* 4017 * Turn off the display if the backlight is set to 0, since the 4018 * display is useless without backlight anyway. 4019 */ 4020 if (level == 0) 4021 radeonfb_blank(dp, 1); 4022 else if (radeonfb_get_backlight(dp) == 0) 4023 radeonfb_blank(dp, 0); 4024 4025 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4026 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4027 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4028 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4029 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4030 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4031 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4032 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4033 lvds |= RADEON_LVDS_ON; 4034 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4035 } else { 4036 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4037 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4038 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4039 } 4040 4041 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4042 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4043 /* XXX What is the correct delay? */ 4044 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4045 4046 splx(s); 4047 4048 return 0; 4049 } 4050 4051 /* 4052 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4053 * Set the delayed bits in the register, and clear the stored delayed 4054 * value. 4055 */ 4056 4057 static void radeonfb_lvds_callout(void *arg) 4058 { 4059 struct radeonfb_display *dp = arg; 4060 int s; 4061 4062 s = splhigh(); 4063 4064 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4065 dp->rd_bl_lvds_val); 4066 dp->rd_bl_lvds_val = 0; 4067 4068 splx(s); 4069 } 4070 4071 static void 4072 radeonfb_brightness_up(device_t dev) 4073 { 4074 struct radeonfb_softc *sc = device_private(dev); 4075 struct radeonfb_display *dp = &sc->sc_displays[0]; 4076 int level; 4077 4078 /* we assume the main display is the first one - need a better way */ 4079 if (sc->sc_ndisplays < 1) return; 4080 /* make sure pushing the hotkeys always has an effect */ 4081 dp->rd_bl_on = 1; 4082 level = dp->rd_bl_level; 4083 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4084 radeonfb_set_backlight(dp, level); 4085 } 4086 4087 static void 4088 radeonfb_brightness_down(device_t dev) 4089 { 4090 struct radeonfb_softc *sc = device_private(dev); 4091 struct radeonfb_display *dp = &sc->sc_displays[0]; 4092 int level; 4093 4094 /* we assume the main display is the first one - need a better way */ 4095 if (sc->sc_ndisplays < 1) return; 4096 /* make sure pushing the hotkeys always has an effect */ 4097 dp->rd_bl_on = 1; 4098 level = dp->rd_bl_level; 4099 level = max(0, level - 5); 4100 radeonfb_set_backlight(dp, level); 4101 } 4102
Indexes created Wed Sep 24 05:09:52 GMT 2025