radeonfb.c revision 1.8
1 /* $NetBSD: radeonfb.c,v 1.8 2006/12/13 00:19:01 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.8 2006/12/13 00:19:01 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static struct videomode *radeonfb_best_refresh(struct videomode *, 167 struct videomode *); 168 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 169 uint16_t *, int); 170 static const struct videomode *radeonfb_port_mode(struct radeonfb_port *, 171 int, int); 172 173 174 #define RADEON_DEBUG 175 #ifdef RADEON_DEBUG 176 int radeon_debug = 1; 177 #define DPRINTF(x) \ 178 if (radeon_debug) printf x 179 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 180 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 181 #else 182 #define DPRINTF(x) 183 #define PRINTREG(r) 184 #define PRINTPLL(r) 185 #endif 186 187 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 188 189 #ifndef RADEON_DEFAULT_MODE 190 /* any reasonably modern display should handle this */ 191 #define RADEON_DEFAULT_MODE "1024x768x60" 192 //#define RADEON_DEFAULT_MODE "1280x1024x60" 193 #endif 194 195 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 196 197 static struct { 198 int size; /* minimum memory size (MB) */ 199 int maxx; /* maximum x dimension */ 200 int maxy; /* maximum y dimension */ 201 int maxbpp; /* maximum bpp */ 202 int maxdisp; /* maximum logical display count */ 203 } radeonfb_limits[] = { 204 { 32, 2048, 1536, 32, 2 }, 205 { 16, 1600, 1200, 32, 2 }, 206 { 8, 1600, 1200, 32, 1 }, 207 { 0, 0, 0, 0, 0 }, 208 }; 209 210 static struct wsscreen_descr radeonfb_stdscreen = { 211 "fb", /* name */ 212 0, 0, /* ncols, nrows */ 213 NULL, /* textops */ 214 8, 16, /* fontwidth, fontheight */ 215 WSSCREEN_WSCOLORS, /* capabilities */ 216 0, /* modecookie */ 217 }; 218 219 struct wsdisplay_accessops radeonfb_accessops = { 220 radeonfb_ioctl, 221 radeonfb_mmap, 222 NULL, /* vcons_alloc_screen */ 223 NULL, /* vcons_free_screen */ 224 NULL, /* vcons_show_screen */ 225 NULL, /* load_font */ 226 NULL, /* pollc */ 227 NULL, /* scroll */ 228 }; 229 230 static struct { 231 uint16_t devid; 232 uint16_t family; 233 uint16_t flags; 234 } radeonfb_devices[] = 235 { 236 /* R100 family */ 237 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 238 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 239 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 240 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 241 242 /* RV100 family */ 243 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 244 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 245 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 246 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 247 248 /* RS100 family */ 249 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 251 252 /* RS200/RS250 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 254 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 255 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 256 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 257 258 /* R200 family */ 259 /* add more R200 products? , 5148 */ 260 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 265 266 /* RV200 family */ 267 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 269 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 271 272 /* RV250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 278 279 /* RS300 family */ 280 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 284 285 /* RV280 family */ 286 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 293 294 /* R300 family */ 295 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 299 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 303 304 /* RV350/RV360 family */ 305 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 317 318 /* R350/R360 family */ 319 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 327 328 /* RV380/RV370 family */ 329 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 330 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 331 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 338 339 /* R420/R423 family */ 340 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 356 357 { 0, 0, 0 } 358 }; 359 360 static struct { 361 int divider; 362 int mask; 363 } radeonfb_dividers[] = { 364 { 1, 0 }, 365 { 2, 1 }, 366 { 3, 4 }, 367 { 4, 2 }, 368 { 6, 6 }, 369 { 8, 3 }, 370 { 12, 7 }, 371 { 0, 0 } 372 }; 373 374 /* 375 * This table taken from X11. 376 */ 377 static const struct { 378 int family; 379 struct radeon_tmds_pll plls[4]; 380 } radeonfb_tmds_pll[] = { 381 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 382 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 383 { RADEON_RS100, {{0, 0}}}, 384 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 385 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 388 { RADEON_RS300, {{0, 0}}}, 389 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 390 { RADEON_R300, {{-1, 0xb01cb}}}, 391 { RADEON_R350, {{-1, 0xb01cb}}}, 392 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 393 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 394 { RADEON_R420, {{-1, 0xb01cb}}}, 395 }; 396 397 398 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 399 radeonfb_match, radeonfb_attach, NULL, NULL); 400 401 static int 402 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 403 { 404 struct pci_attach_args *pa = aux; 405 int i; 406 407 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 408 return 0; 409 410 for (i = 0; radeonfb_devices[i].devid; i++) { 411 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 412 return 100; /* high to defeat VGA/VESA */ 413 } 414 415 return 0; 416 } 417 418 static void 419 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 420 { 421 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 422 struct pci_attach_args *pa = aux; 423 bus_size_t bsz; 424 pcireg_t screg; 425 int i, j, fg, bg, ul; 426 uint32_t v; 427 428 sc->sc_id = pa->pa_id; 429 for (i = 0; radeonfb_devices[i].devid; i++) { 430 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 431 break; 432 } 433 434 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 435 sizeof(sc->sc_devinfo)); 436 437 aprint_naive("\n"); 438 aprint_normal(": %s\n", sc->sc_devinfo); 439 440 KASSERT(radeonfb_devices[i].devid != 0); 441 sc->sc_pt = pa->pa_tag; 442 sc->sc_pc = pa->pa_pc; 443 sc->sc_family = radeonfb_devices[i].family; 444 sc->sc_flags = radeonfb_devices[i].flags; 445 446 /* enable memory and IO access */ 447 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 448 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 449 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 450 451 /* 452 * Some flags are general to entire chip families, and rather 453 * than clutter up the table with them, we go ahead and set 454 * them here. 455 */ 456 switch (sc->sc_family) { 457 case RADEON_RS100: 458 case RADEON_RS200: 459 sc->sc_flags |= RFB_IGP | RFB_RV100; 460 break; 461 462 case RADEON_RV100: 463 case RADEON_RV200: 464 case RADEON_RV250: 465 case RADEON_RV280: 466 sc->sc_flags |= RFB_RV100; 467 break; 468 469 case RADEON_RS300: 470 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 471 break; 472 473 case RADEON_R300: 474 case RADEON_RV350: 475 case RADEON_R350: 476 case RADEON_RV380: 477 case RADEON_R420: 478 /* newer chips */ 479 sc->sc_flags |= RFB_R300; 480 break; 481 482 case RADEON_R100: 483 sc->sc_flags |= RFB_NCRTC2; 484 break; 485 } 486 487 /* 488 * XXX: to support true multihead, this must change. 489 */ 490 sc->sc_ndisplays = 1; 491 492 /* XXX: */ 493 if (!HAS_CRTC2(sc)) { 494 sc->sc_ndisplays = 1; 495 } 496 497 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 498 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 499 &sc->sc_regsz) != 0) { 500 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 501 goto error; 502 } 503 504 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 505 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 506 &sc->sc_iosz) != 0) { 507 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 508 } 509 510 /* scratch register test... */ 511 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 512 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 513 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 514 goto error; 515 } 516 517 PRINTREG(RADEON_BIOS_4_SCRATCH); 518 PRINTREG(RADEON_FP_GEN_CNTL); 519 PRINTREG(RADEON_FP2_GEN_CNTL); 520 PRINTREG(RADEON_TMDS_CNTL); 521 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 522 PRINTREG(RADEON_TMDS_PLL_CNTL); 523 PRINTREG(RADEON_LVDS_GEN_CNTL); 524 PRINTREG(RADEON_FP_HORZ_STRETCH); 525 PRINTREG(RADEON_FP_VERT_STRETCH); 526 527 /* XXX: RV100 specific */ 528 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 529 530 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 531 RADEON_TMDS_TRANSMITTER_PLLEN, 532 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 533 534 radeonfb_i2c_init(sc); 535 536 radeonfb_loadbios(sc, pa); 537 538 #ifdef RADEON_BIOS_INIT 539 if (radeonfb_bios_init(sc)) { 540 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 541 goto error; 542 } 543 #endif 544 545 if (radeonfb_getclocks(sc)) { 546 aprint_error("%s: Unable to get reference clocks from BIOS\n", 547 XNAME(sc)); 548 goto error; 549 } 550 551 if (radeonfb_gettmds(sc)) { 552 aprint_error("%s: Unable to identify TMDS PLL settings\n", 553 XNAME(sc)); 554 goto error; 555 } 556 557 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 558 "minpll = %d, maxpll = %d\n", XNAME(sc), 559 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 560 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 561 562 radeonfb_getconnectors(sc); 563 564 radeonfb_set_fbloc(sc); 565 566 for (i = 0; radeonfb_limits[i].size; i++) { 567 if (sc->sc_memsz >= radeonfb_limits[i].size) { 568 sc->sc_maxx = radeonfb_limits[i].maxx; 569 sc->sc_maxy = radeonfb_limits[i].maxy; 570 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 571 /* framebuffer offset, start at a 4K page */ 572 sc->sc_fboffset = sc->sc_memsz / 573 radeonfb_limits[i].maxdisp; 574 /* 575 * we use the fbsize to figure out where we can store 576 * things like cursor data. 577 */ 578 sc->sc_fbsize = 579 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 580 RADEON_STRIDEALIGN) * sc->sc_maxy, 581 4096); 582 break; 583 } 584 } 585 586 587 radeonfb_init_misc(sc); 588 radeonfb_init_palette(sc, 0); 589 if (HAS_CRTC2(sc)) 590 radeonfb_init_palette(sc, 1); 591 592 /* program the DAC wirings */ 593 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 594 switch (sc->sc_ports[i].rp_dac_type) { 595 case RADEON_DAC_PRIMARY: 596 PATCH32(sc, RADEON_DAC_CNTL2, 597 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 598 ~RADEON_DAC2_DAC_CLK_SEL); 599 break; 600 case RADEON_DAC_TVDAC: 601 /* we always use the TVDAC to drive a secondary analog 602 * CRT for now. if we ever support TV-out this will 603 * have to change. 604 */ 605 SET32(sc, RADEON_DAC_CNTL2, 606 RADEON_DAC2_DAC2_CLK_SEL); 607 PATCH32(sc, RADEON_DISP_HW_DEBUG, 608 i ? 0 : RADEON_CRT2_DISP1_SEL, 609 ~RADEON_CRT2_DISP1_SEL); 610 break; 611 } 612 } 613 PRINTREG(RADEON_DAC_CNTL2); 614 PRINTREG(RADEON_DISP_HW_DEBUG); 615 616 /* other DAC programming */ 617 v = GET32(sc, RADEON_DAC_CNTL); 618 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 619 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 620 PUT32(sc, RADEON_DAC_CNTL, v); 621 PRINTREG(RADEON_DAC_CNTL); 622 623 /* XXX: this may need more investigation */ 624 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 625 PRINTREG(RADEON_TV_DAC_CNTL); 626 627 /* enable TMDS */ 628 SET32(sc, RADEON_FP_GEN_CNTL, 629 RADEON_FP_TMDS_EN | 630 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 631 RADEON_FP_CRTC_DONT_SHADOW_HEND); 632 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 633 if (HAS_CRTC2(sc)) 634 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 635 636 /* 637 * we use bus_space_map instead of pci_mapreg, because we don't 638 * need the full aperature space. no point in wasting virtual 639 * address space we don't intend to use, right? 640 */ 641 if ((sc->sc_memsz < (4096 * 1024)) || 642 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 643 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 644 (bsz < sc->sc_memsz)) { 645 sc->sc_memsz = 0; 646 aprint_error("%s: Bad frame buffer configuration\n", 647 XNAME(sc)); 648 goto error; 649 } 650 651 /* 64 MB should be enough -- more just wastes map entries */ 652 if (sc->sc_memsz > (64 << 20)) 653 sc->sc_memsz = (64 << 20); 654 655 sc->sc_memt = pa->pa_memt; 656 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 657 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 658 sc->sc_memsz = 0; 659 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 660 goto error; 661 } 662 663 aprint_normal("%s: %d MB aperture at 0x%08x, " 664 "%d KB registers at 0x%08x\n", XNAME(sc), 665 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 666 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 667 668 #if 0 669 /* setup default video mode from devprop (allows PROM override) */ 670 sc->sc_defaultmode = radeonfb_default_mode; 671 ps = prop_dictionary_get(device_properties(&sc->sc_dev), 672 "videomode"); 673 if (ps != NULL) { 674 sc->sc_modebuf = prop_string_cstring(ps); 675 if (sc->sc_modebuf) 676 sc->sc_defaultmode = sc->sc_modebuf; 677 } 678 #endif 679 680 /* initialize some basic display parameters */ 681 for (i = 0; i < sc->sc_ndisplays; i++) { 682 struct radeonfb_display *dp = &sc->sc_displays[i]; 683 struct rasops_info *ri; 684 long defattr; 685 struct wsemuldisplaydev_attach_args aa; 686 687 /* 688 * Figure out how many "displays" (desktops) we are going to 689 * support. If more than one, then each CRTC gets its own 690 * programming. 691 * 692 * XXX: this code needs to change to support mergedfb. 693 * XXX: would be nice to allow this to be overridden 694 */ 695 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 696 DPRINTF(("dual crtcs!\n")); 697 dp->rd_ncrtcs = 2; 698 dp->rd_crtcs[0].rc_number = 0; 699 dp->rd_crtcs[1].rc_number = 1; 700 } else { 701 dp->rd_ncrtcs = 1; 702 dp->rd_crtcs[0].rc_number = i; 703 } 704 705 /* set up port pointer */ 706 for (j = 0; j < dp->rd_ncrtcs; j++) { 707 dp->rd_crtcs[j].rc_port = 708 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 709 } 710 711 dp->rd_softc = sc; 712 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 713 dp->rd_bg = WS_DEFAULT_BG; 714 #if 0 715 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 716 #else 717 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 718 #endif 719 /* for text mode, we pick a resolution that won't 720 * require panning */ 721 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 722 723 aprint_normal("%s: display %d: " 724 "initial virtual resolution %dx%d at %d bpp\n", 725 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 726 727 /* now select the *video mode* that we will use */ 728 for (j = 0; j < dp->rd_ncrtcs; j++) { 729 const struct videomode *vmp; 730 vmp = radeonfb_port_mode(dp->rd_crtcs[j].rc_port, 731 dp->rd_virtx, dp->rd_virty); 732 733 /* 734 * virtual resolution should be at least as high as 735 * physical 736 */ 737 if (dp->rd_virtx < vmp->hdisplay || 738 dp->rd_virty < vmp->vdisplay) { 739 dp->rd_virtx = vmp->hdisplay; 740 dp->rd_virty = vmp->vdisplay; 741 } 742 743 dp->rd_crtcs[j].rc_videomode = *vmp; 744 printf("%s: port %d: physical %dx%d %dHz\n", 745 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 746 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 747 vmp->htotal), vmp->vtotal)); 748 } 749 750 /* N.B.: radeon wants 64-byte aligned stride */ 751 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 752 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 753 754 dp->rd_offset = sc->sc_fboffset * i; 755 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 756 sc->sc_memh) + dp->rd_offset; 757 dp->rd_curoff = sc->sc_fbsize; 758 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 759 760 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 761 762 switch (dp->rd_bpp) { 763 case 8: 764 dp->rd_format = 2; 765 break; 766 case 32: 767 dp->rd_format = 6; 768 break; 769 default: 770 aprint_error("%s: bad depth %d\n", XNAME(sc), 771 dp->rd_bpp); 772 goto error; 773 } 774 775 printf("init engine\n"); 776 /* XXX: this seems suspicious - per display engine 777 initialization? */ 778 radeonfb_engine_init(dp); 779 780 /* copy the template into place */ 781 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 782 dp->rd_wsscreens = dp->rd_wsscreens_storage; 783 784 /* and make up the list */ 785 dp->rd_wsscreenlist.nscreens = 1; 786 dp->rd_wsscreenlist.screens = 787 (const struct wsscreen_descr **)&dp->rd_wsscreens; 788 789 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 790 &radeonfb_accessops); 791 792 dp->rd_vd.init_screen = radeonfb_init_screen; 793 794 dp->rd_console = 1; 795 796 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 797 798 799 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 800 dp->rd_console, &defattr); 801 802 ri = &dp->rd_vscreen.scr_ri; 803 804 /* clear the screen */ 805 rasops_unpack_attr(defattr, &fg, &bg, &ul); 806 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 807 ri->ri_devcmap[bg & 0xf]); 808 809 dp->rd_wsscreens->textops = &ri->ri_ops; 810 dp->rd_wsscreens->capabilities = ri->ri_caps; 811 dp->rd_wsscreens->nrows = ri->ri_rows; 812 dp->rd_wsscreens->ncols = ri->ri_cols; 813 814 #ifdef SPLASHSCREEN 815 dp->rd_splash.si_depth = ri->ri_depth; 816 dp->rd_splash.si_bits = ri->ri_bits; 817 dp->rd_splash.si_hwbits = ri->ri_hwbits; 818 dp->rd_splash.si_width = ri->ri_width; 819 dp->rd_splash.si_height = ri->ri_height; 820 dp->rd_splash.si_stride = ri->ri_stride; 821 dp->rd_splash.si_fillrect = NULL; 822 #endif 823 if (dp->rd_console) { 824 825 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 826 defattr); 827 #ifdef SPLASHSCREEN 828 splash_render(&dp->rd_splash, 829 SPLASH_F_CENTER|SPLASH_F_FILL); 830 #endif 831 832 #ifdef SPLASHSCREEN_PROGRESS 833 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 834 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 835 dp->rd_progress.sp_left = (dp->rd_virtx - 836 dp->rd_progress.sp_width) / 2; 837 dp->rd_progress.sp_height = 20; 838 dp->rd_progress.sp_state = -1; 839 dp->rd_progress.sp_si = &dp->rd_splash; 840 splash_progress_init(&dp->rd_progress); 841 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 842 #endif 843 844 } else { 845 846 /* 847 * since we're not the console we can postpone 848 * the rest until someone actually allocates a 849 * screen for us. but we do clear the screen 850 * at least. 851 */ 852 memset(ri->ri_bits, 0, 1024); 853 854 radeonfb_modeswitch(dp); 855 #ifdef SPLASHSCREEN 856 splash_render(&dp->rd_splash, 857 SPLASH_F_CENTER|SPLASH_F_FILL); 858 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 859 #endif 860 } 861 862 aa.console = dp->rd_console; 863 aa.scrdata = &dp->rd_wsscreenlist; 864 aa.accessops = &radeonfb_accessops; 865 aa.accesscookie = &dp->rd_vd; 866 867 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 868 radeonfb_blank(dp, 0); 869 } 870 871 return; 872 873 error: 874 if (sc->sc_biossz) 875 free(sc->sc_bios, M_DEVBUF); 876 877 if (sc->sc_regsz) 878 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 879 880 if (sc->sc_memsz) 881 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 882 } 883 884 int 885 radeonfb_ioctl(void *v, void *vs, 886 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 887 { 888 struct vcons_data *vd; 889 struct radeonfb_display *dp; 890 struct radeonfb_softc *sc; 891 892 vd = (struct vcons_data *)v; 893 dp = (struct radeonfb_display *)vd->cookie; 894 sc = dp->rd_softc; 895 896 switch (cmd) { 897 case WSDISPLAYIO_GTYPE: 898 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 899 return 0; 900 901 case WSDISPLAYIO_GINFO: 902 if (vd->active != NULL) { 903 struct wsdisplay_fbinfo *fb; 904 fb = (struct wsdisplay_fbinfo *)d; 905 fb->width = dp->rd_virtx; 906 fb->height = dp->rd_virty; 907 fb->depth = dp->rd_bpp; 908 fb->cmsize = 256; 909 return 0; 910 } else 911 return ENODEV; 912 case WSDISPLAYIO_GVIDEO: 913 if (radeonfb_isblank(dp)) 914 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 915 else 916 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 917 return 0; 918 919 case WSDISPLAYIO_SVIDEO: 920 radeonfb_blank(dp, 921 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 922 return 0; 923 924 case WSDISPLAYIO_GETCMAP: 925 #if 0 926 if (dp->rd_bpp == 8) 927 return radeonfb_getcmap(sc, 928 (struct wsdisplay_cmap *)d); 929 #endif 930 return EINVAL; 931 932 case WSDISPLAYIO_PUTCMAP: 933 #if 0 934 if (dp->rd_bpp == 8) 935 return radeonfb_putcmap(sc, 936 (struct wsdisplay_cmap *)d); 937 #endif 938 return EINVAL; 939 940 case WSDISPLAYIO_LINEBYTES: 941 *(unsigned *)d = dp->rd_stride; 942 return 0; 943 944 case WSDISPLAYIO_SMODE: 945 if (*(int *)d != dp->rd_wsmode) { 946 dp->rd_wsmode = *(int *)d; 947 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 948 (dp->rd_vd.active)) { 949 vcons_redraw_screen(dp->rd_vd.active); 950 } 951 } 952 return 0; 953 954 case WSDISPLAYIO_GCURMAX: 955 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 956 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 957 return 0; 958 959 case WSDISPLAYIO_SCURSOR: 960 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 961 962 case WSDISPLAYIO_GCURSOR: 963 return EPASSTHROUGH; 964 965 case WSDISPLAYIO_GCURPOS: 966 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 967 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 968 return 0; 969 970 case WSDISPLAYIO_SCURPOS: 971 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 972 973 case WSDISPLAYIO_SSPLASH: 974 #if defined(SPLASHSCREEN) 975 if (*(int *)d == 1) { 976 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 977 splash_render(&dp->rd_splash, 978 SPLASH_F_CENTER|SPLASH_F_FILL); 979 } else 980 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 981 return 0; 982 #else 983 return ENODEV; 984 #endif 985 case WSDISPLAYIO_SPROGRESS: 986 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 987 dp->rd_progress.sp_force = 1; 988 splash_progress_update(&dp->rd_progress); 989 dp->rd_progress.sp_force = 0; 990 return 0; 991 #else 992 return ENODEV; 993 #endif 994 995 default: 996 return EPASSTHROUGH; 997 } 998 } 999 1000 paddr_t 1001 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1002 { 1003 struct vcons_data *vd; 1004 struct radeonfb_display *dp; 1005 struct radeonfb_softc *sc; 1006 #ifdef RADEONFB_MMAP_BARS 1007 struct lwp *me; 1008 #endif 1009 paddr_t pa; 1010 1011 vd = (struct vcons_data *)v; 1012 dp = (struct radeonfb_display *)vd->cookie; 1013 sc = dp->rd_softc; 1014 1015 /* XXX: note that we don't allow mapping of registers right now */ 1016 /* XXX: this means that the XFree86 radeon driver won't work */ 1017 1018 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1019 pa = bus_space_mmap(sc->sc_memt, 1020 sc->sc_memaddr + dp->rd_offset + offset, 0, 1021 prot, BUS_SPACE_MAP_LINEAR); 1022 return pa; 1023 } 1024 1025 #ifdef RADEONFB_MMAP_BARS 1026 /* 1027 * restrict all other mappings to processes with superuser privileges 1028 * or the kernel itself 1029 */ 1030 me = curlwp; 1031 if (me != NULL) { 1032 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1033 NULL) != 0) { 1034 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1035 return -1; 1036 } 1037 } 1038 1039 if ((offset >= sc->sc_regaddr) && 1040 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1041 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1042 BUS_SPACE_MAP_LINEAR); 1043 } 1044 1045 if ((offset >= sc->sc_memaddr) && 1046 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1047 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1048 BUS_SPACE_MAP_LINEAR); 1049 } 1050 1051 #ifdef macppc 1052 /* allow mapping of IO space */ 1053 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1054 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1055 BUS_SPACE_MAP_LINEAR); 1056 return pa; 1057 } 1058 #endif /* macppc */ 1059 1060 #endif /* RADEONFB_MMAP_BARS */ 1061 1062 return -1; 1063 } 1064 1065 static void 1066 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1067 { 1068 bus_space_tag_t romt; 1069 bus_space_handle_t romh, biosh; 1070 bus_size_t romsz; 1071 bus_addr_t ptr; 1072 1073 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1074 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1075 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1076 return; 1077 } 1078 1079 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1080 &sc->sc_biossz); 1081 if (sc->sc_biossz == 0) { 1082 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1083 return; 1084 } 1085 1086 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1087 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1088 1089 /* unmap the PCI expansion rom */ 1090 bus_space_unmap(romt, romh, romsz); 1091 1092 /* turn off rom decoder now */ 1093 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1094 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1095 ~PCI_MAPREG_ROM_ENABLE); 1096 1097 ptr = GETBIOS16(sc, 0x48); 1098 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1099 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1100 sc->sc_flags |= RFB_ATOM; 1101 } 1102 1103 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1104 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1105 } 1106 1107 1108 uint32_t 1109 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1110 { 1111 1112 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1113 } 1114 1115 void 1116 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1117 { 1118 1119 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1120 } 1121 1122 void 1123 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1124 uint32_t andmask, uint32_t ormask) 1125 { 1126 int s; 1127 uint32_t val; 1128 1129 s = splhigh(); 1130 val = radeonfb_get32(sc, reg); 1131 val = (val & andmask) | ormask; 1132 radeonfb_put32(sc, reg, val); 1133 splx(s); 1134 } 1135 1136 uint32_t 1137 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1138 { 1139 int s; 1140 uint32_t val; 1141 1142 s = splhigh(); 1143 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1144 val = radeonfb_get32(sc, RADEON_MM_DATA); 1145 splx(s); 1146 1147 return (val); 1148 } 1149 1150 void 1151 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1152 { 1153 int s; 1154 1155 s = splhigh(); 1156 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1157 radeonfb_put32(sc, RADEON_MM_DATA, val); 1158 splx(s); 1159 } 1160 1161 void 1162 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1163 uint32_t andmask, uint32_t ormask) 1164 { 1165 int s; 1166 uint32_t val; 1167 1168 s = splhigh(); 1169 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1170 val = radeonfb_get32(sc, RADEON_MM_DATA); 1171 val = (val & andmask) | ormask; 1172 radeonfb_put32(sc, RADEON_MM_DATA, val); 1173 splx(s); 1174 } 1175 1176 uint32_t 1177 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1178 { 1179 int s; 1180 uint32_t val; 1181 1182 s = splhigh(); 1183 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1184 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1185 if (HAS_R300CG(sc)) 1186 radeonfb_r300cg_workaround(sc); 1187 splx(s); 1188 1189 return (val); 1190 } 1191 1192 void 1193 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1194 { 1195 int s; 1196 1197 s = splhigh(); 1198 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1199 RADEON_PLL_WR_EN); 1200 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1201 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1202 splx(s); 1203 } 1204 1205 void 1206 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1207 uint32_t andmask, uint32_t ormask) 1208 { 1209 int s; 1210 uint32_t val; 1211 1212 s = splhigh(); 1213 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1214 RADEON_PLL_WR_EN); 1215 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1216 val = (val & andmask) | ormask; 1217 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1218 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1219 splx(s); 1220 } 1221 1222 int 1223 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1224 { 1225 uint32_t saved; 1226 1227 saved = GET32(sc, reg); 1228 PUT32(sc, reg, v); 1229 if (GET32(sc, reg) != v) { 1230 return -1; 1231 } 1232 PUT32(sc, reg, saved); 1233 return 0; 1234 } 1235 1236 uintmax_t 1237 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1238 uintmax_t defval) 1239 { 1240 prop_number_t pn; 1241 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1242 if (pn == NULL) { 1243 return defval; 1244 } 1245 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1246 return (prop_number_integer_value(pn)); 1247 } 1248 1249 int 1250 radeonfb_getclocks(struct radeonfb_softc *sc) 1251 { 1252 bus_addr_t ptr; 1253 int refclk = 0; 1254 int refdiv = 0; 1255 int minpll = 0; 1256 int maxpll = 0; 1257 1258 /* load initial property values if port/board provides them */ 1259 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1260 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1261 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1262 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1263 1264 if (refclk && refdiv && minpll && maxpll) 1265 goto dontprobe; 1266 1267 if (!sc->sc_biossz) { 1268 /* no BIOS */ 1269 aprint_verbose("%s: No video BIOS, using default clocks\n", 1270 XNAME(sc)); 1271 if (IS_IGP(sc)) 1272 refclk = refclk ? refclk : 1432; 1273 else 1274 refclk = refclk ? refclk : 2700; 1275 refdiv = refdiv ? refdiv : 12; 1276 minpll = minpll ? minpll : 12500; 1277 maxpll = maxpll ? maxpll : 35000; 1278 } else if (IS_ATOM(sc)) { 1279 /* ATOM BIOS */ 1280 ptr = GETBIOS16(sc, 0x48); 1281 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1282 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1283 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1284 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1285 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1286 /* 1287 * ATOM BIOS doesn't supply a reference divider, so we 1288 * have to probe for it. 1289 */ 1290 if (refdiv < 2) 1291 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1292 RADEON_PPLL_REF_DIV_MASK; 1293 /* 1294 * if probe is zero, just assume one that should work 1295 * for most parts 1296 */ 1297 if (refdiv < 2) 1298 refdiv = 12; 1299 1300 } else { 1301 /* Legacy BIOS */ 1302 ptr = GETBIOS16(sc, 0x48); 1303 ptr = GETBIOS16(sc, ptr + 0x30); 1304 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1305 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1306 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1307 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1308 } 1309 1310 1311 dontprobe: 1312 sc->sc_refclk = refclk * 10; 1313 sc->sc_refdiv = refdiv; 1314 sc->sc_minpll = minpll * 10; 1315 sc->sc_maxpll = maxpll * 10; 1316 return 0; 1317 } 1318 1319 int 1320 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1321 uint32_t *postdivbit, uint32_t *feedbackdiv) 1322 { 1323 int i; 1324 uint32_t outfreq; 1325 int div; 1326 1327 DPRINTF(("dot clock: %u\n", dotclock)); 1328 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1329 outfreq = div * dotclock; 1330 if ((outfreq >= sc->sc_minpll) && 1331 (outfreq <= sc->sc_maxpll)) { 1332 DPRINTF(("outfreq: %u\n", outfreq)); 1333 *postdivbit = 1334 ((uint32_t)radeonfb_dividers[i].mask << 16); 1335 DPRINTF(("post divider: %d (mask %x)\n", div, 1336 *postdivbit)); 1337 break; 1338 } 1339 } 1340 1341 if (div == 0) 1342 return 1; 1343 1344 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1345 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1346 return 0; 1347 } 1348 1349 #if 0 1350 #ifdef RADEON_DEBUG 1351 static void 1352 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1353 { 1354 char asc[17]; 1355 unsigned ptr = (unsigned)buffer; 1356 char *start = (char *)(ptr & ~0xf); 1357 char *end = (char *)(ptr + size); 1358 1359 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1360 1361 if (pfx == NULL) { 1362 pfx = ""; 1363 } 1364 1365 while (start < end) { 1366 unsigned offset = (unsigned)start & 0xf; 1367 if (offset == 0) { 1368 printf("%s%x: ", pfx, (unsigned)start); 1369 } 1370 if (((unsigned)start < ptr) || 1371 ((unsigned)start >= (ptr + size))) { 1372 printf(" "); 1373 asc[offset] = ' '; 1374 } else { 1375 printf("%02x", *(unsigned char *)start); 1376 if ((*start >= ' ') && (*start <= '~')) { 1377 asc[offset] = *start; 1378 } else { 1379 asc[offset] = '.'; 1380 } 1381 } 1382 asc[offset + 1] = 0; 1383 if (offset % 2) { 1384 printf(" "); 1385 } 1386 if (offset == 15) { 1387 printf(" %s\n", asc); 1388 } 1389 start++; 1390 } 1391 } 1392 #endif 1393 #endif 1394 1395 int 1396 radeonfb_getconnectors(struct radeonfb_softc *sc) 1397 { 1398 int i; 1399 int found = 0; 1400 1401 for (i = 0; i < 2; i++) { 1402 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1403 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1404 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1405 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1406 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1407 } 1408 1409 /* 1410 * This logic is borrowed from Xorg's radeon driver. 1411 */ 1412 if (!sc->sc_biossz) 1413 goto nobios; 1414 1415 if (IS_ATOM(sc)) { 1416 /* not done yet */ 1417 } else { 1418 uint16_t ptr; 1419 int port = 0; 1420 1421 ptr = GETBIOS16(sc, 0x48); 1422 ptr = GETBIOS16(sc, ptr + 0x50); 1423 for (i = 1; i < 4; i++) { 1424 uint16_t entry; 1425 uint8_t conn, ddc, dac, tmds; 1426 1427 /* 1428 * Parse the connector table. From reading the code, 1429 * it appears to made up of 16-bit entries for each 1430 * connector. The 16-bits are defined as: 1431 * 1432 * bits 12-15 - connector type (0 == end of table) 1433 * bits 8-11 - DDC type 1434 * bits 5-7 - ??? 1435 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1436 * bits 1-3 - ??? 1437 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1438 */ 1439 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1440 break; 1441 entry = GETBIOS16(sc, ptr + i * 2); 1442 1443 conn = (entry >> 12) & 0xf; 1444 ddc = (entry >> 8) & 0xf; 1445 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1446 RADEON_DAC_PRIMARY; 1447 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1448 RADEON_TMDS_INT; 1449 1450 if (conn == RADEON_CONN_NONE) 1451 continue; /* no connector */ 1452 1453 if ((found > 0) && 1454 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1455 /* duplicate entry for same connector */ 1456 continue; 1457 } 1458 1459 /* internal DDC_DVI port gets priority */ 1460 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1461 port = 0; 1462 else 1463 port = 1; 1464 1465 sc->sc_ports[port].rp_ddc_type = 1466 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1467 sc->sc_ports[port].rp_dac_type = dac; 1468 sc->sc_ports[port].rp_conn_type = 1469 min(conn, RADEON_CONN_UNSUPPORTED) ; 1470 1471 sc->sc_ports[port].rp_tmds_type = tmds; 1472 1473 if ((conn != RADEON_CONN_DVI_I) && 1474 (conn != RADEON_CONN_DVI_D) && 1475 (tmds == RADEON_TMDS_INT)) 1476 sc->sc_ports[port].rp_tmds_type = 1477 RADEON_TMDS_UNKNOWN; 1478 1479 found += (port + 1); 1480 } 1481 } 1482 1483 nobios: 1484 if (!found) { 1485 DPRINTF(("No connector info in BIOS!\n")); 1486 /* default, port 0 = internal TMDS, port 1 = CRT */ 1487 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1488 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1489 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1490 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1491 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1492 1493 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1494 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1495 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1496 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1497 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1498 } 1499 1500 /* 1501 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1502 * these chips should use TVDAC for the VGA port. 1503 */ 1504 if (HAS_SDAC(sc)) { 1505 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1506 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1507 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1508 } else { 1509 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1510 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1511 } 1512 } else if (!HAS_CRTC2(sc)) { 1513 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1514 } 1515 1516 for (i = 0; i < 2; i++) { 1517 char edid[128]; 1518 uint8_t ddc; 1519 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1520 1521 DPRINTF(("Port #%d:\n", i)); 1522 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1523 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1524 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1525 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1526 1527 sc->sc_ports[i].rp_edid_valid = 0; 1528 ddc = sc->sc_ports[i].rp_ddc_type; 1529 if (ddc != RADEON_DDC_NONE) { 1530 if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1531 (edid_parse(edid, eip) == 0)) { 1532 sc->sc_ports[i].rp_edid_valid = 1; 1533 edid_print(eip); 1534 } 1535 } 1536 } 1537 1538 return found; 1539 } 1540 1541 int 1542 radeonfb_gettmds(struct radeonfb_softc *sc) 1543 { 1544 int i; 1545 1546 if (!sc->sc_biossz) { 1547 goto nobios; 1548 } 1549 1550 if (IS_ATOM(sc)) { 1551 /* XXX: not done yet */ 1552 } else { 1553 uint16_t ptr; 1554 int n; 1555 1556 ptr = GETBIOS16(sc, 0x48); 1557 ptr = GETBIOS16(sc, ptr + 0x34); 1558 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1559 if (GETBIOS8(sc, ptr) == 3) { 1560 /* revision three table */ 1561 n = GETBIOS8(sc, ptr + 5) + 1; 1562 n = min(n, 4); 1563 1564 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1565 for (i = 0; i < n; i++) { 1566 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1567 ptr + i * 10 + 8); 1568 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1569 ptr + i * 10 + 0x10); 1570 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1571 sc->sc_tmds_pll[i].rtp_freq, 1572 sc->sc_tmds_pll[i].rtp_pll)); 1573 } 1574 return 0; 1575 } 1576 } 1577 1578 nobios: 1579 DPRINTF(("no suitable DFP table present\n")); 1580 for (i = 0; 1581 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1582 i++) { 1583 int j; 1584 1585 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1586 continue; 1587 1588 for (j = 0; j < 4; j++) { 1589 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1590 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1591 sc->sc_tmds_pll[j].rtp_freq, 1592 sc->sc_tmds_pll[j].rtp_pll)); 1593 } 1594 return 0; 1595 } 1596 1597 return -1; 1598 } 1599 1600 const struct videomode * 1601 radeonfb_modelookup(const char *name) 1602 { 1603 int i; 1604 1605 for (i = 0; i < videomode_count; i++) 1606 if (!strcmp(name, videomode_list[i].name)) 1607 return &videomode_list[i]; 1608 1609 return NULL; 1610 } 1611 1612 void 1613 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1614 { 1615 if (crtc) { 1616 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1617 RADEON_P2PLL_ATOMIC_UPDATE_R); 1618 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1619 } else { 1620 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1621 RADEON_PPLL_ATOMIC_UPDATE_R); 1622 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1623 } 1624 } 1625 1626 void 1627 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1628 { 1629 int i; 1630 1631 for (i = 10000; i; i--) { 1632 if (crtc) { 1633 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1634 RADEON_P2PLL_ATOMIC_UPDATE_R) 1635 break; 1636 } else { 1637 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1638 RADEON_PPLL_ATOMIC_UPDATE_R) 1639 break; 1640 } 1641 } 1642 } 1643 1644 void 1645 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1646 { 1647 uint32_t pbit = 0; 1648 uint32_t feed = 0; 1649 uint32_t data; 1650 #if 1 1651 int i; 1652 #endif 1653 1654 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1655 1656 if (crtc == 0) { 1657 1658 /* XXXX: mobility workaround missing */ 1659 /* XXXX: R300 stuff missing */ 1660 1661 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1662 RADEON_VCLK_SRC_SEL_CPUCLK, 1663 ~RADEON_VCLK_SRC_SEL_MASK); 1664 1665 /* put vclk into reset, use atomic updates */ 1666 SETPLL(sc, RADEON_PPLL_CNTL, 1667 RADEON_PPLL_REFCLK_SEL | 1668 RADEON_PPLL_FBCLK_SEL | 1669 RADEON_PPLL_RESET | 1670 RADEON_PPLL_ATOMIC_UPDATE_EN | 1671 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1672 1673 /* select clock 3 */ 1674 #if 0 1675 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1676 ~RADEON_PLL_DIV_SEL); 1677 #else 1678 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1679 ~RADEON_PLL_DIV_SEL); 1680 #endif 1681 1682 /* XXX: R300 family -- program divider differently? */ 1683 1684 /* program reference divider */ 1685 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1686 ~RADEON_PPLL_REF_DIV_MASK); 1687 PRINTPLL(RADEON_PPLL_REF_DIV); 1688 1689 #if 0 1690 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1691 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1692 RADEON_PPLL_POST3_DIV_MASK); 1693 data |= pbit; 1694 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1695 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1696 #else 1697 for (i = 0; i < 4; i++) { 1698 } 1699 #endif 1700 1701 /* use the atomic update */ 1702 radeonfb_pllwriteupdate(sc, crtc); 1703 1704 /* and wait for it to complete */ 1705 radeonfb_pllwaitatomicread(sc, crtc); 1706 1707 /* program HTOTAL (why?) */ 1708 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1709 1710 /* drop reset */ 1711 CLRPLL(sc, RADEON_PPLL_CNTL, 1712 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1713 RADEON_PPLL_ATOMIC_UPDATE_EN | 1714 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1715 1716 PRINTPLL(RADEON_PPLL_CNTL); 1717 1718 /* give clock time to lock */ 1719 delay(50000); 1720 1721 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1722 RADEON_VCLK_SRC_SEL_PPLLCLK, 1723 ~RADEON_VCLK_SRC_SEL_MASK); 1724 1725 } else { 1726 1727 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1728 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1729 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1730 1731 /* put vclk into reset, use atomic updates */ 1732 SETPLL(sc, RADEON_P2PLL_CNTL, 1733 RADEON_P2PLL_RESET | 1734 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1735 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1736 1737 /* XXX: R300 family -- program divider differently? */ 1738 1739 /* program reference divider */ 1740 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1741 ~RADEON_P2PLL_REF_DIV_MASK); 1742 1743 /* program feedback and post dividers */ 1744 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1745 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1746 RADEON_P2PLL_POST0_DIV_MASK); 1747 data |= pbit; 1748 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1749 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1750 1751 /* use the atomic update */ 1752 radeonfb_pllwriteupdate(sc, crtc); 1753 1754 /* and wait for it to complete */ 1755 radeonfb_pllwaitatomicread(sc, crtc); 1756 1757 /* program HTOTAL (why?) */ 1758 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1759 1760 /* drop reset */ 1761 CLRPLL(sc, RADEON_P2PLL_CNTL, 1762 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1763 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1764 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1765 1766 /* allow time for clock to lock */ 1767 delay(50000); 1768 1769 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1770 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1771 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1772 } 1773 PRINTREG(RADEON_CRTC_MORE_CNTL); 1774 } 1775 1776 void 1777 radeonfb_modeswitch(struct radeonfb_display *dp) 1778 { 1779 struct radeonfb_softc *sc = dp->rd_softc; 1780 int i; 1781 1782 /* blank the display while we switch modes */ 1783 //radeonfb_blank(dp, 1); 1784 1785 #if 0 1786 SET32(sc, RADEON_CRTC_EXT_CNTL, 1787 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1788 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1789 #endif 1790 1791 /* these registers might get in the way... */ 1792 PUT32(sc, RADEON_OVR_CLR, 0); 1793 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1794 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1795 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1796 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1797 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1798 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1799 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1800 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1801 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1802 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1803 1804 for (i = 0; i < dp->rd_ncrtcs; i++) 1805 radeonfb_setcrtc(dp, i); 1806 1807 /* activate the display */ 1808 //radeonfb_blank(dp, 0); 1809 } 1810 1811 void 1812 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1813 { 1814 int crtc; 1815 struct videomode *mode; 1816 struct radeonfb_softc *sc; 1817 struct radeonfb_crtc *cp; 1818 uint32_t v; 1819 uint32_t gencntl; 1820 uint32_t htotaldisp; 1821 uint32_t hsyncstrt; 1822 uint32_t vtotaldisp; 1823 uint32_t vsyncstrt; 1824 uint32_t fphsyncstrt; 1825 uint32_t fpvsyncstrt; 1826 uint32_t fphtotaldisp; 1827 uint32_t fpvtotaldisp; 1828 uint32_t pitch; 1829 1830 sc = dp->rd_softc; 1831 cp = &dp->rd_crtcs[index]; 1832 crtc = cp->rc_number; 1833 mode = &cp->rc_videomode; 1834 1835 #if 1 1836 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1837 (dp->rd_bpp * 8)); 1838 #else 1839 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1840 (sc->sc_maxbpp * 8)); 1841 #endif 1842 //pitch = pitch | (pitch << 16); 1843 1844 switch (crtc) { 1845 case 0: 1846 gencntl = RADEON_CRTC_GEN_CNTL; 1847 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1848 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1849 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1850 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1851 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1852 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1853 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1854 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1855 break; 1856 case 1: 1857 gencntl = RADEON_CRTC2_GEN_CNTL; 1858 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1859 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1860 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1861 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1862 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1863 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1864 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1865 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1866 break; 1867 default: 1868 panic("Bad CRTC!"); 1869 break; 1870 } 1871 1872 /* 1873 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1874 */ 1875 /* only bother with 32bpp and 8bpp */ 1876 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1877 1878 if (crtc == 1) { 1879 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1880 } else { 1881 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1882 } 1883 1884 if (mode->flags & VID_DBLSCAN) 1885 v |= RADEON_CRTC2_DBL_SCAN_EN; 1886 1887 if (mode->flags & VID_INTERLACE) 1888 v |= RADEON_CRTC2_INTERLACE_EN; 1889 1890 if (mode->flags & VID_CSYNC) { 1891 v |= RADEON_CRTC2_CSYNC_EN; 1892 if (crtc == 1) 1893 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1894 } 1895 1896 PUT32(sc, gencntl, v); 1897 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1898 1899 /* 1900 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1901 */ 1902 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1903 if (crtc == 0) { 1904 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1905 RADEON_CRTC_DISPLAY_DIS); 1906 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1907 if (mode->flags & VID_CSYNC) 1908 v |= RADEON_CRTC_VSYNC_TRISTAT; 1909 } 1910 /* unconditional turn on CRT, in case first CRTC is DFP */ 1911 v |= RADEON_CRTC_CRT_ON; 1912 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1913 PRINTREG(RADEON_CRTC_EXT_CNTL); 1914 1915 /* 1916 * H_TOTAL_DISP 1917 */ 1918 v = ((mode->hdisplay / 8) - 1) << 16; 1919 v |= (mode->htotal / 8) - 1; 1920 PUT32(sc, htotaldisp, v); 1921 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1922 PUT32(sc, fphtotaldisp, v); 1923 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1924 1925 /* 1926 * H_SYNC_STRT_WID 1927 */ 1928 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1929 v |= mode->hsync_start; 1930 if (mode->flags & VID_NHSYNC) 1931 v |= RADEON_CRTC_H_SYNC_POL; 1932 PUT32(sc, hsyncstrt, v); 1933 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1934 PUT32(sc, fphsyncstrt, v); 1935 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1936 1937 /* 1938 * V_TOTAL_DISP 1939 */ 1940 v = ((mode->vdisplay - 1) << 16); 1941 v |= (mode->vtotal - 1); 1942 PUT32(sc, vtotaldisp, v); 1943 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1944 PUT32(sc, fpvtotaldisp, v); 1945 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1946 1947 /* 1948 * V_SYNC_STRT_WID 1949 */ 1950 v = ((mode->vsync_end - mode->vsync_start) << 16); 1951 v |= (mode->vsync_start - 1); 1952 if (mode->flags & VID_NVSYNC) 1953 v |= RADEON_CRTC_V_SYNC_POL; 1954 PUT32(sc, vsyncstrt, v); 1955 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1956 PUT32(sc, fpvsyncstrt, v); 1957 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1958 1959 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1960 1961 switch (crtc) { 1962 case 0: 1963 PUT32(sc, RADEON_CRTC_OFFSET, 0); 1964 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1965 PUT32(sc, RADEON_CRTC_PITCH, pitch); 1966 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1967 1968 CLR32(sc, RADEON_CRTC_EXT_CNTL, 1969 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1970 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1971 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1972 PRINTREG(RADEON_CRTC_EXT_CNTL); 1973 PRINTREG(RADEON_CRTC_GEN_CNTL); 1974 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1975 break; 1976 1977 case 1: 1978 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 1979 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 1980 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 1981 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 1982 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 1983 RADEON_CRTC2_VSYNC_DIS | 1984 RADEON_CRTC2_HSYNC_DIS | 1985 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 1986 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1987 break; 1988 } 1989 } 1990 1991 int 1992 radeonfb_isblank(struct radeonfb_display *dp) 1993 { 1994 uint32_t reg, mask; 1995 1996 if (dp->rd_crtcs[0].rc_number) { 1997 reg = RADEON_CRTC2_GEN_CNTL; 1998 mask = RADEON_CRTC2_DISP_DIS; 1999 } else { 2000 reg = RADEON_CRTC_EXT_CNTL; 2001 mask = RADEON_CRTC_DISPLAY_DIS; 2002 } 2003 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2004 } 2005 2006 void 2007 radeonfb_blank(struct radeonfb_display *dp, int blank) 2008 { 2009 struct radeonfb_softc *sc = dp->rd_softc; 2010 uint32_t reg, mask; 2011 uint32_t fpreg, fpval; 2012 int i; 2013 2014 for (i = 0; i < dp->rd_ncrtcs; i++) { 2015 2016 if (dp->rd_crtcs[i].rc_number) { 2017 reg = RADEON_CRTC2_GEN_CNTL; 2018 mask = RADEON_CRTC2_DISP_DIS; 2019 fpreg = RADEON_FP2_GEN_CNTL; 2020 fpval = RADEON_FP2_ON; 2021 } else { 2022 reg = RADEON_CRTC_EXT_CNTL; 2023 mask = RADEON_CRTC_DISPLAY_DIS; 2024 fpreg = RADEON_FP_GEN_CNTL; 2025 fpval = RADEON_FP_FPON; 2026 } 2027 2028 if (blank) { 2029 SET32(sc, reg, mask); 2030 CLR32(sc, fpreg, fpval); 2031 } else { 2032 CLR32(sc, reg, mask); 2033 SET32(sc, fpreg, fpval); 2034 } 2035 } 2036 PRINTREG(RADEON_FP_GEN_CNTL); 2037 PRINTREG(RADEON_FP2_GEN_CNTL); 2038 } 2039 2040 void 2041 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2042 long *defattr) 2043 { 2044 struct radeonfb_display *dp = cookie; 2045 struct rasops_info *ri = &scr->scr_ri; 2046 2047 /* initialize font subsystem */ 2048 wsfont_init(); 2049 2050 DPRINTF(("init screen called, existing %d\n", existing)); 2051 2052 ri->ri_depth = dp->rd_bpp; 2053 ri->ri_width = dp->rd_virtx; 2054 ri->ri_height = dp->rd_virty; 2055 ri->ri_stride = dp->rd_stride; 2056 ri->ri_flg = RI_CENTER; 2057 ri->ri_bits = (void *)dp->rd_fbptr; 2058 2059 /* XXX: 32 bpp only */ 2060 /* this is rgb in "big-endian order..." */ 2061 ri->ri_rnum = 8; 2062 ri->ri_gnum = 8; 2063 ri->ri_bnum = 8; 2064 ri->ri_rpos = 16; 2065 ri->ri_gpos = 8; 2066 ri->ri_bpos = 0; 2067 2068 if (existing) { 2069 ri->ri_flg |= RI_CLEAR; 2070 2071 /* start a modeswitch now */ 2072 radeonfb_modeswitch(dp); 2073 } 2074 2075 /* 2076 * XXX: font selection should be based on properties, with some 2077 * normal/reasonable default. 2078 */ 2079 ri->ri_caps = WSSCREEN_WSCOLORS; 2080 2081 /* initialize and look for an initial font */ 2082 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2083 2084 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2085 dp->rd_virtx / ri->ri_font->fontwidth); 2086 2087 /* enable acceleration */ 2088 ri->ri_ops.copyrows = radeonfb_copyrows; 2089 ri->ri_ops.copycols = radeonfb_copycols; 2090 ri->ri_ops.eraserows = radeonfb_eraserows; 2091 ri->ri_ops.erasecols = radeonfb_erasecols; 2092 ri->ri_ops.allocattr = radeonfb_allocattr; 2093 if (!IS_R300(dp->rd_softc)) { 2094 ri->ri_ops.putchar = radeonfb_putchar; 2095 } 2096 ri->ri_ops.cursor = radeonfb_cursor; 2097 } 2098 2099 void 2100 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2101 { 2102 uint32_t gen, ext, gen2 = 0; 2103 uint32_t agploc, aperbase, apersize, mcfbloc; 2104 2105 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2106 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2107 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2108 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2109 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2110 2111 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2112 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2113 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2114 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2115 2116 if (HAS_CRTC2(sc)) { 2117 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2118 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2119 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2120 } 2121 2122 delay(100000); 2123 2124 mcfbloc = (aperbase >> 16) | 2125 ((aperbase + (apersize - 1)) & 0xffff0000); 2126 2127 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2128 sc->sc_memsz = apersize; 2129 2130 if (((agploc & 0xffff) << 16) != 2131 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2132 agploc = mcfbloc & 0xffff0000U; 2133 agploc |= ((agploc + 0x10000) >> 16); 2134 } 2135 2136 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2137 2138 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2139 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2140 2141 DPRINTF(("aperbase = %u\n", aperbase)); 2142 PRINTREG(RADEON_MC_FB_LOCATION); 2143 PRINTREG(RADEON_MC_AGP_LOCATION); 2144 2145 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2146 2147 if (HAS_CRTC2(sc)) 2148 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2149 2150 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2151 2152 #if 0 2153 /* XXX: what is this AGP garbage? :-) */ 2154 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2155 #endif 2156 2157 delay(100000); 2158 2159 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2160 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2161 2162 if (HAS_CRTC2(sc)) 2163 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2164 } 2165 2166 void 2167 radeonfb_init_misc(struct radeonfb_softc *sc) 2168 { 2169 PUT32(sc, RADEON_BUS_CNTL, 2170 RADEON_BUS_MASTER_DIS | 2171 RADEON_BUS_PREFETCH_MODE_ACT | 2172 RADEON_BUS_PCI_READ_RETRY_EN | 2173 RADEON_BUS_PCI_WRT_RETRY_EN | 2174 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2175 RADEON_BUS_MSTR_RD_MULT | 2176 RADEON_BUS_MSTR_RD_LINE | 2177 RADEON_BUS_RD_DISCARD_EN | 2178 RADEON_BUS_MSTR_DISCONNECT_EN | 2179 RADEON_BUS_READ_BURST); 2180 2181 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2182 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2183 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2184 PUT32(sc, RADEON_RBBM_CNTL, 2185 (3 << RADEON_RB_SETTLE_SHIFT) | 2186 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2187 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2188 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2189 2190 /* XXX: figure out what these mean! */ 2191 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2192 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2193 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2194 2195 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2196 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2197 } 2198 2199 /* 2200 * This loads a linear color map for true color. 2201 */ 2202 void 2203 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2204 { 2205 int i; 2206 uint32_t vclk; 2207 2208 #define DAC_WIDTH ((1 << 10) - 1) 2209 #define CLUT_WIDTH ((1 << 8) - 1) 2210 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2211 2212 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2213 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2214 2215 if (crtc) 2216 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2217 else 2218 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2219 2220 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2221 for (i = 0; i <= CLUT_WIDTH; ++i) { 2222 PUT32(sc, RADEON_PALETTE_30_DATA, 2223 (CLUT_COLOR(i) << 10) | 2224 (CLUT_COLOR(i) << 20) | 2225 (CLUT_COLOR(i))); 2226 } 2227 2228 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2229 PRINTREG(RADEON_DAC_CNTL2); 2230 2231 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2232 } 2233 2234 /* 2235 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2236 */ 2237 void 2238 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2239 { 2240 uint32_t tmp, save; 2241 2242 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2243 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2244 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2245 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2246 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2247 } 2248 2249 /* 2250 * Acceleration entry points. 2251 */ 2252 static void 2253 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2254 { 2255 struct rasops_info *ri = cookie; 2256 struct vcons_screen *scr = ri->ri_hw; 2257 struct radeonfb_display *dp = scr->scr_cookie; 2258 uint32_t x, y, w, h; 2259 uint32_t bg, fg; 2260 uint8_t *data; 2261 2262 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2263 return; 2264 2265 if (!CHAR_IN_FONT(c, ri->ri_font)) 2266 return; 2267 2268 w = ri->ri_font->fontwidth; 2269 h = ri->ri_font->fontheight; 2270 2271 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2272 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2273 2274 x = ri->ri_xorigin + col * w; 2275 y = ri->ri_yorigin + row * h; 2276 2277 if (c == 0x20) { 2278 radeonfb_rectfill(dp, x, y, w, h, bg); 2279 } else { 2280 data = (uint8_t *)ri->ri_font->data + 2281 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2282 2283 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2284 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2285 } 2286 } 2287 2288 static void 2289 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2290 { 2291 struct rasops_info *ri = cookie; 2292 struct vcons_screen *scr = ri->ri_hw; 2293 struct radeonfb_display *dp = scr->scr_cookie; 2294 uint32_t x, y, w, h, fg, bg, ul; 2295 2296 /* XXX: check for full emulation mode? */ 2297 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2298 x = ri->ri_xorigin; 2299 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2300 w = ri->ri_emuwidth; 2301 h = ri->ri_font->fontheight * nrows; 2302 2303 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2304 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2305 } 2306 } 2307 2308 static void 2309 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2310 { 2311 struct rasops_info *ri = cookie; 2312 struct vcons_screen *scr = ri->ri_hw; 2313 struct radeonfb_display *dp = scr->scr_cookie; 2314 uint32_t x, ys, yd, w, h; 2315 2316 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2317 x = ri->ri_xorigin; 2318 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2319 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2320 w = ri->ri_emuwidth; 2321 h = ri->ri_font->fontheight * nrows; 2322 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2323 RADEON_ROP3_S, 0xffffffff); 2324 } 2325 } 2326 2327 static void 2328 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2329 { 2330 struct rasops_info *ri = cookie; 2331 struct vcons_screen *scr = ri->ri_hw; 2332 struct radeonfb_display *dp = scr->scr_cookie; 2333 uint32_t xs, xd, y, w, h; 2334 2335 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2336 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2337 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2338 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2339 w = ri->ri_font->fontwidth * ncols; 2340 h = ri->ri_font->fontheight; 2341 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2342 RADEON_ROP3_S, 0xffffffff); 2343 } 2344 } 2345 2346 static void 2347 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2348 long fillattr) 2349 { 2350 struct rasops_info *ri = cookie; 2351 struct vcons_screen *scr = ri->ri_hw; 2352 struct radeonfb_display *dp = scr->scr_cookie; 2353 uint32_t x, y, w, h, fg, bg, ul; 2354 2355 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2356 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2357 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2358 w = ri->ri_font->fontwidth * ncols; 2359 h = ri->ri_font->fontheight; 2360 2361 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2362 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2363 } 2364 } 2365 2366 static void 2367 radeonfb_cursor(void *cookie, int on, int row, int col) 2368 { 2369 struct rasops_info *ri = cookie; 2370 struct vcons_screen *scr = ri->ri_hw; 2371 struct radeonfb_display *dp = scr->scr_cookie; 2372 int x, y, wi, he; 2373 2374 wi = ri->ri_font->fontwidth; 2375 he = ri->ri_font->fontheight; 2376 2377 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2378 x = ri->ri_ccol * wi + ri->ri_xorigin; 2379 y = ri->ri_crow * he + ri->ri_yorigin; 2380 /* first turn off the old cursor */ 2381 if (ri->ri_flg & RI_CURSOR) { 2382 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2383 RADEON_ROP3_Dn, 0xffffffff); 2384 ri->ri_flg &= ~RI_CURSOR; 2385 } 2386 ri->ri_crow = row; 2387 ri->ri_ccol = col; 2388 /* then (possibly) turn on the new one */ 2389 if (on) { 2390 x = ri->ri_ccol * wi + ri->ri_xorigin; 2391 y = ri->ri_crow * he + ri->ri_yorigin; 2392 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2393 RADEON_ROP3_Dn, 0xffffffff); 2394 ri->ri_flg |= RI_CURSOR; 2395 } 2396 } else { 2397 scr->scr_ri.ri_crow = row; 2398 scr->scr_ri.ri_ccol = col; 2399 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2400 } 2401 } 2402 2403 static int 2404 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2405 { 2406 if ((fg == 0) && (bg == 0)) { 2407 fg = WS_DEFAULT_FG; 2408 bg = WS_DEFAULT_BG; 2409 } 2410 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2411 return 0; 2412 } 2413 2414 /* 2415 * Underlying acceleration support. 2416 */ 2417 static void 2418 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2419 int height, uint32_t fg, uint32_t bg) 2420 { 2421 struct radeonfb_softc *sc = dp->rd_softc; 2422 uint32_t gmc; 2423 uint32_t padded_width = (width+7) & 0xfff8; 2424 uint32_t topleft, bottomright; 2425 2426 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2427 2428 if (width != padded_width) { 2429 2430 radeonfb_wait_fifo(sc, 2); 2431 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2432 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2433 ((xd + width) & 0x1fff); 2434 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2435 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2436 } 2437 2438 radeonfb_wait_fifo(sc, 5); 2439 2440 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2441 RADEON_GMC_BRUSH_NONE | 2442 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2443 //RADEON_GMC_BYTE_LSB_TO_MSB | 2444 RADEON_GMC_DST_CLIPPING | 2445 RADEON_ROP3_S | 2446 RADEON_DP_SRC_SOURCE_HOST_DATA | 2447 RADEON_GMC_CLR_CMP_CNTL_DIS | 2448 RADEON_GMC_WR_MSK_DIS | 2449 gmc); 2450 2451 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2452 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2453 2454 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2455 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2456 2457 } 2458 2459 static void 2460 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2461 { 2462 struct radeonfb_softc *sc = dp->rd_softc; 2463 int i; 2464 uint32_t latch = 0; 2465 int shift = 0; 2466 2467 for (i = 0; i < count; i++) { 2468 latch |= (data[i] << shift); 2469 if (shift == 24) { 2470 radeonfb_wait_fifo(sc, 1); 2471 PUT32(sc, RADEON_HOST_DATA0, latch); 2472 latch = 0; 2473 shift = 0; 2474 } else 2475 shift += 8; 2476 } 2477 if (shift != 0) { 2478 radeonfb_wait_fifo(sc, 1); 2479 PUT32(sc, RADEON_HOST_DATA0, latch); 2480 } 2481 radeonfb_unclip(sc); 2482 } 2483 2484 static void 2485 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2486 int width, int height, uint32_t color) 2487 { 2488 struct radeonfb_softc *sc = dp->rd_softc; 2489 uint32_t gmc; 2490 2491 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2492 2493 radeonfb_wait_fifo(sc, 6); 2494 2495 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2496 RADEON_GMC_BRUSH_SOLID_COLOR | 2497 RADEON_GMC_SRC_DATATYPE_COLOR | 2498 RADEON_GMC_CLR_CMP_CNTL_DIS | 2499 RADEON_ROP3_P | gmc); 2500 2501 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2502 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2503 PUT32(sc, RADEON_DP_CNTL, 2504 RADEON_DST_X_LEFT_TO_RIGHT | 2505 RADEON_DST_Y_TOP_TO_BOTTOM); 2506 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2507 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2508 2509 /* 2510 * XXX: we don't wait for the fifo to empty -- that would slow 2511 * things down! The linux radeonfb driver waits, but xfree doesn't 2512 */ 2513 /* XXX: for now we do, to make it safe for direct drawing */ 2514 radeonfb_engine_idle(sc); 2515 } 2516 2517 static void 2518 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2519 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2520 { 2521 struct radeonfb_softc *sc = dp->rd_softc; 2522 uint32_t gmc; 2523 uint32_t dir; 2524 2525 if (dsty < srcy) { 2526 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2527 } else { 2528 srcy += height - 1; 2529 dsty += height - 1; 2530 dir = 0; 2531 } 2532 if (dstx < srcx) { 2533 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2534 } else { 2535 srcx += width - 1; 2536 dstx += width - 1; 2537 } 2538 2539 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2540 2541 radeonfb_wait_fifo(sc, 6); 2542 2543 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2544 //RADEON_GMC_SRC_CLIPPING | 2545 RADEON_GMC_BRUSH_SOLID_COLOR | 2546 RADEON_GMC_SRC_DATATYPE_COLOR | 2547 RADEON_GMC_CLR_CMP_CNTL_DIS | 2548 RADEON_DP_SRC_SOURCE_MEMORY | 2549 rop | gmc); 2550 2551 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2552 PUT32(sc, RADEON_DP_CNTL, dir); 2553 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2554 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2555 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2556 2557 /* 2558 * XXX: we don't wait for the fifo to empty -- that would slow 2559 * things down! The linux radeonfb driver waits, but xfree doesn't 2560 */ 2561 /* XXX: for now we do, to make it safe for direct drawing */ 2562 radeonfb_engine_idle(sc); 2563 } 2564 2565 static void 2566 radeonfb_engine_idle(struct radeonfb_softc *sc) 2567 { 2568 int i; 2569 2570 radeonfb_wait_fifo(sc, 64); 2571 for (i = RADEON_TIMEOUT; i; i--) { 2572 if ((GET32(sc, RADEON_RBBM_STATUS) & 2573 RADEON_RBBM_ACTIVE) == 0) { 2574 radeonfb_engine_flush(sc); 2575 break; 2576 } 2577 } 2578 } 2579 2580 static void 2581 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2582 { 2583 int i; 2584 2585 for (i = RADEON_TIMEOUT; i; i--) { 2586 if ((GET32(sc, RADEON_RBBM_STATUS) & 2587 RADEON_RBBM_FIFOCNT_MASK) >= n) 2588 return; 2589 } 2590 #ifdef DIAGNOSTIC 2591 if (!i) 2592 printf("%s: timed out waiting for fifo (%x)\n", 2593 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2594 #endif 2595 } 2596 2597 static void 2598 radeonfb_engine_flush(struct radeonfb_softc *sc) 2599 { 2600 int i; 2601 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2602 for (i = RADEON_TIMEOUT; i; i--) { 2603 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2604 RADEON_RB2D_DC_BUSY) == 0) 2605 break; 2606 } 2607 #ifdef DIAGNOSTIC 2608 if (!i) 2609 printf("%s: engine flush timed out!\n", XNAME(sc)); 2610 #endif 2611 } 2612 2613 static inline void 2614 radeonfb_unclip(struct radeonfb_softc *sc) 2615 { 2616 2617 radeonfb_wait_fifo(sc, 2); 2618 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2619 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2620 } 2621 2622 static void 2623 radeonfb_engine_init(struct radeonfb_display *dp) 2624 { 2625 struct radeonfb_softc *sc = dp->rd_softc; 2626 uint32_t pitch; 2627 2628 /* no 3D */ 2629 PUT32(sc, RADEON_RB3D_CNTL, 0); 2630 2631 radeonfb_engine_reset(sc); 2632 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2633 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2634 2635 radeonfb_wait_fifo(sc, 1); 2636 if (!IS_R300(sc)) 2637 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2638 2639 radeonfb_wait_fifo(sc, 3); 2640 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2641 (pitch << 22) | (sc->sc_aperbase >> 10)); 2642 2643 2644 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2645 (pitch << 22) | (sc->sc_aperbase >> 10)); 2646 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2647 (pitch << 22) | (sc->sc_aperbase >> 10)); 2648 2649 radeonfb_wait_fifo(sc, 1); 2650 #if _BYTE_ORDER == _BIG_ENDIAN 2651 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2652 #else 2653 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2654 #endif 2655 2656 /* default scissors -- no clipping */ 2657 radeonfb_wait_fifo(sc, 1); 2658 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2659 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2660 2661 radeonfb_wait_fifo(sc, 1); 2662 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2663 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2664 RADEON_GMC_CLR_CMP_CNTL_DIS | 2665 RADEON_GMC_BRUSH_SOLID_COLOR | 2666 RADEON_GMC_SRC_DATATYPE_COLOR); 2667 2668 radeonfb_wait_fifo(sc, 7); 2669 PUT32(sc, RADEON_DST_LINE_START, 0); 2670 PUT32(sc, RADEON_DST_LINE_END, 0); 2671 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2672 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2673 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2674 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2675 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2676 2677 radeonfb_engine_idle(sc); 2678 } 2679 2680 static void 2681 radeonfb_engine_reset(struct radeonfb_softc *sc) 2682 { 2683 uint32_t hpc, rbbm, mclkcntl, clkindex; 2684 2685 radeonfb_engine_flush(sc); 2686 2687 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2688 if (HAS_R300CG(sc)) 2689 radeonfb_r300cg_workaround(sc); 2690 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2691 2692 /* 2693 * According to comments in XFree code, resetting the HDP via 2694 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2695 * So we use HOST_PATH_CNTL instead. 2696 */ 2697 2698 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2699 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2700 if (IS_R300(sc)) { 2701 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2702 RADEON_SOFT_RESET_CP | 2703 RADEON_SOFT_RESET_HI | 2704 RADEON_SOFT_RESET_E2); 2705 GET32(sc, RADEON_RBBM_SOFT_RESET); 2706 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2707 /* 2708 * XXX: this bit is not defined in any ATI docs I have, 2709 * nor in the XFree code, but XFree does it. Why? 2710 */ 2711 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2712 } else { 2713 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2714 RADEON_SOFT_RESET_CP | 2715 RADEON_SOFT_RESET_SE | 2716 RADEON_SOFT_RESET_RE | 2717 RADEON_SOFT_RESET_PP | 2718 RADEON_SOFT_RESET_E2 | 2719 RADEON_SOFT_RESET_RB); 2720 GET32(sc, RADEON_RBBM_SOFT_RESET); 2721 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2722 ~(RADEON_SOFT_RESET_CP | 2723 RADEON_SOFT_RESET_SE | 2724 RADEON_SOFT_RESET_RE | 2725 RADEON_SOFT_RESET_PP | 2726 RADEON_SOFT_RESET_E2 | 2727 RADEON_SOFT_RESET_RB)); 2728 GET32(sc, RADEON_RBBM_SOFT_RESET); 2729 } 2730 2731 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2732 GET32(sc, RADEON_HOST_PATH_CNTL); 2733 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2734 2735 if (IS_R300(sc)) 2736 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2737 2738 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2739 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2740 2741 if (HAS_R300CG(sc)) 2742 radeonfb_r300cg_workaround(sc); 2743 } 2744 2745 static int 2746 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2747 { 2748 int x, y; 2749 2750 x = pos->x; 2751 y = pos->y; 2752 2753 /* 2754 * This doesn't let a cursor move off the screen. I'm not 2755 * sure if this will have negative effects for e.g. Xinerama. 2756 * I'd guess Xinerama handles it by changing the cursor shape, 2757 * but that needs verification. 2758 */ 2759 if (x >= dp->rd_virtx) 2760 x = dp->rd_virtx - 1; 2761 if (x < 0) 2762 x = 0; 2763 if (y >= dp->rd_virty) 2764 y = dp->rd_virty - 1; 2765 if (y < 0) 2766 y = 0; 2767 2768 dp->rd_cursor.rc_pos.x = x; 2769 dp->rd_cursor.rc_pos.y = y; 2770 2771 radeonfb_cursor_position(dp); 2772 return 0; 2773 } 2774 2775 static int 2776 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2777 { 2778 unsigned flags; 2779 2780 uint8_t r[2], g[2], b[2]; 2781 unsigned index, count; 2782 int i, err; 2783 int pitch, size; 2784 struct radeonfb_cursor nc; 2785 2786 flags = wc->which; 2787 2788 /* copy old values */ 2789 nc = dp->rd_cursor; 2790 2791 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2792 index = wc->cmap.index; 2793 count = wc->cmap.count; 2794 2795 if (index >= 2 || (index + count) > 2) 2796 return EINVAL; 2797 2798 err = copyin(wc->cmap.red, &r[index], count); 2799 if (err) 2800 return err; 2801 err = copyin(wc->cmap.green, &g[index], count); 2802 if (err) 2803 return err; 2804 err = copyin(wc->cmap.blue, &b[index], count); 2805 if (err) 2806 return err; 2807 2808 for (i = index; i < index + count; i++) { 2809 nc.rc_cmap[i] = 2810 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2811 } 2812 } 2813 2814 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2815 if ((wc->size.x > RADEON_CURSORMAXX) || 2816 (wc->size.y > RADEON_CURSORMAXY)) 2817 return EINVAL; 2818 2819 /* figure bytes per line */ 2820 pitch = (wc->size.x + 7) / 8; 2821 size = pitch * wc->size.y; 2822 2823 /* clear the old cursor and mask */ 2824 memset(nc.rc_image, 0, 512); 2825 memset(nc.rc_mask, 0, 512); 2826 2827 nc.rc_size = wc->size; 2828 2829 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2830 return err; 2831 2832 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2833 return err; 2834 } 2835 2836 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2837 nc.rc_hot = wc->hot; 2838 if (nc.rc_hot.x >= nc.rc_size.x) 2839 nc.rc_hot.x = nc.rc_size.x - 1; 2840 if (nc.rc_hot.y >= nc.rc_size.y) 2841 nc.rc_hot.y = nc.rc_size.y - 1; 2842 } 2843 2844 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2845 nc.rc_pos = wc->pos; 2846 if (nc.rc_pos.x >= dp->rd_virtx) 2847 nc.rc_pos.x = dp->rd_virtx - 1; 2848 #if 0 2849 if (nc.rc_pos.x < 0) 2850 nc.rc_pos.x = 0; 2851 #endif 2852 if (nc.rc_pos.y >= dp->rd_virty) 2853 nc.rc_pos.y = dp->rd_virty - 1; 2854 #if 0 2855 if (nc.rc_pos.y < 0) 2856 nc.rc_pos.y = 0; 2857 #endif 2858 } 2859 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2860 nc.rc_visible = wc->enable; 2861 } 2862 2863 dp->rd_cursor = nc; 2864 radeonfb_cursor_update(dp, wc->which); 2865 2866 return 0; 2867 } 2868 2869 /* 2870 * Change the cursor shape. Call this with the cursor locked to avoid 2871 * flickering/tearing. 2872 */ 2873 static void 2874 radeonfb_cursor_shape(struct radeonfb_display *dp) 2875 { 2876 uint8_t and[512], xor[512]; 2877 int i, j, src, dst, pitch; 2878 const uint8_t *msk = dp->rd_cursor.rc_mask; 2879 const uint8_t *img = dp->rd_cursor.rc_image; 2880 2881 /* 2882 * Radeon cursor data interleaves one line of AND data followed 2883 * by a line of XOR data. (Each line corresponds to a whole hardware 2884 * pitch - i.e. 64 pixels or 8 bytes.) 2885 * 2886 * The cursor is displayed using the following table: 2887 * 2888 * AND XOR Result 2889 * ---------------------- 2890 * 0 0 Cursor color 0 2891 * 0 1 Cursor color 1 2892 * 1 0 Transparent 2893 * 1 1 Complement of background 2894 * 2895 * Our masks are therefore different from what we were passed. 2896 * Passed in, I'm assuming the data represents either color 0 or 1, 2897 * and a mask, so the passed in table looks like: 2898 * 2899 * IMG Mask Result 2900 * ----------------------- 2901 * 0 0 Transparent 2902 * 0 1 Cursor color 0 2903 * 1 0 Transparent 2904 * 1 1 Cursor color 1 2905 * 2906 * IF mask bit == 1, AND = 0, XOR = color. 2907 * IF mask bit == 0, AND = 1, XOR = 0. 2908 * 2909 * hence: AND = ~(mask); XOR = color & ~(mask); 2910 */ 2911 2912 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2913 2914 /* start by assuming all bits are transparent */ 2915 memset(and, 0xff, 512); 2916 memset(xor, 0x00, 512); 2917 2918 src = 0; 2919 dst = 0; 2920 for (i = 0; i < 64; i++) { 2921 for (j = 0; j < 64; j += 8) { 2922 if ((i < dp->rd_cursor.rc_size.y) && 2923 (j < dp->rd_cursor.rc_size.x)) { 2924 2925 /* take care to leave odd bits alone */ 2926 and[dst] &= ~(msk[src]); 2927 xor[dst] = img[src] & msk[src]; 2928 src++; 2929 } 2930 dst++; 2931 } 2932 } 2933 2934 /* copy the image into place */ 2935 for (i = 0; i < 64; i++) { 2936 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2937 &and[i * 8], 8); 2938 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2939 &xor[i * 8], 8); 2940 } 2941 } 2942 2943 static void 2944 radeonfb_cursor_position(struct radeonfb_display *dp) 2945 { 2946 struct radeonfb_softc *sc = dp->rd_softc; 2947 uint32_t offset, hvoff, hvpos; /* registers */ 2948 uint32_t coff; /* cursor offset */ 2949 int i, x, y, xoff, yoff, crtcoff; 2950 2951 /* 2952 * XXX: this also needs to handle pan/scan 2953 */ 2954 for (i = 0; i < dp->rd_ncrtcs; i++) { 2955 2956 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2957 2958 if (rcp->rc_number) { 2959 offset = RADEON_CUR2_OFFSET; 2960 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2961 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2962 crtcoff = RADEON_CRTC2_OFFSET; 2963 } else { 2964 offset = RADEON_CUR_OFFSET; 2965 hvoff = RADEON_CUR_HORZ_VERT_OFF; 2966 hvpos = RADEON_CUR_HORZ_VERT_POSN; 2967 crtcoff = RADEON_CRTC_OFFSET; 2968 } 2969 2970 x = dp->rd_cursor.rc_pos.x; 2971 y = dp->rd_cursor.rc_pos.y; 2972 2973 while (y < rcp->rc_yoffset) { 2974 rcp->rc_yoffset -= RADEON_PANINCREMENT; 2975 } 2976 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 2977 rcp->rc_yoffset += RADEON_PANINCREMENT; 2978 } 2979 while (x < rcp->rc_xoffset) { 2980 rcp->rc_xoffset -= RADEON_PANINCREMENT; 2981 } 2982 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 2983 rcp->rc_xoffset += RADEON_PANINCREMENT; 2984 } 2985 2986 /* adjust for the cursor's hotspot */ 2987 x -= dp->rd_cursor.rc_hot.x; 2988 y -= dp->rd_cursor.rc_hot.y; 2989 xoff = yoff = 0; 2990 2991 if (x >= dp->rd_virtx) 2992 x = dp->rd_virtx - 1; 2993 if (y >= dp->rd_virty) 2994 y = dp->rd_virty - 1; 2995 2996 /* now adjust cursor so it is relative to viewport */ 2997 x -= rcp->rc_xoffset; 2998 y -= rcp->rc_yoffset; 2999 3000 /* 3001 * no need to check for fall off, because we should 3002 * never move off the screen entirely! 3003 */ 3004 coff = 0; 3005 if (x < 0) { 3006 xoff = -x; 3007 x = 0; 3008 } 3009 if (y < 0) { 3010 yoff = -y; 3011 y = 0; 3012 coff = (yoff * 2) * 8; 3013 } 3014 3015 /* pan the display */ 3016 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3017 rcp->rc_xoffset); 3018 3019 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3020 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3021 /* NB: this unlocks the cursor */ 3022 PUT32(sc, hvpos, (x << 16) | y); 3023 } 3024 } 3025 3026 static void 3027 radeonfb_cursor_visible(struct radeonfb_display *dp) 3028 { 3029 int i; 3030 uint32_t gencntl, bit; 3031 3032 for (i = 0; i < dp->rd_ncrtcs; i++) { 3033 if (dp->rd_crtcs[i].rc_number) { 3034 gencntl = RADEON_CRTC2_GEN_CNTL; 3035 bit = RADEON_CRTC2_CUR_EN; 3036 } else { 3037 gencntl = RADEON_CRTC_GEN_CNTL; 3038 bit = RADEON_CRTC_CUR_EN; 3039 } 3040 3041 if (dp->rd_cursor.rc_visible) 3042 SET32(dp->rd_softc, gencntl, bit); 3043 else 3044 CLR32(dp->rd_softc, gencntl, bit); 3045 } 3046 } 3047 3048 static void 3049 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3050 { 3051 int i; 3052 uint32_t c0reg, c1reg; 3053 struct radeonfb_softc *sc = dp->rd_softc; 3054 3055 for (i = 0; i < dp->rd_ncrtcs; i++) { 3056 if (dp->rd_crtcs[i].rc_number) { 3057 c0reg = RADEON_CUR2_CLR0; 3058 c1reg = RADEON_CUR2_CLR1; 3059 } else { 3060 c0reg = RADEON_CUR_CLR0; 3061 c1reg = RADEON_CUR_CLR1; 3062 } 3063 3064 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3065 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3066 } 3067 } 3068 3069 static void 3070 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3071 { 3072 struct radeonfb_softc *sc; 3073 int i; 3074 3075 sc = dp->rd_softc; 3076 for (i = 0; i < dp->rd_ncrtcs; i++) { 3077 if (dp->rd_crtcs[i].rc_number) { 3078 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3079 } else { 3080 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3081 } 3082 } 3083 3084 if (which & WSDISPLAY_CURSOR_DOCMAP) 3085 radeonfb_cursor_cmap(dp); 3086 3087 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3088 radeonfb_cursor_shape(dp); 3089 3090 if (which & WSDISPLAY_CURSOR_DOCUR) 3091 radeonfb_cursor_visible(dp); 3092 3093 /* this one is unconditional, because it updates other stuff */ 3094 radeonfb_cursor_position(dp); 3095 } 3096 3097 static struct videomode * 3098 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3099 { 3100 int r1, r2; 3101 3102 /* otherwise pick the higher refresh rate */ 3103 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3104 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3105 3106 return (r1 < r2 ? m2 : m1); 3107 } 3108 3109 static const struct videomode * 3110 radeonfb_port_mode(struct radeonfb_port *rp, int x, int y) 3111 { 3112 struct edid_info *ep = &rp->rp_edid; 3113 struct videomode *vmp = NULL; 3114 int i; 3115 3116 if (!rp->rp_edid_valid) { 3117 /* fallback to safe mode */ 3118 return radeonfb_modelookup(RADEON_DEFAULT_MODE); 3119 } 3120 3121 /* always choose the preferred mode first! */ 3122 if (ep->edid_preferred_mode) { 3123 3124 /* XXX: add auto-stretching support for native mode */ 3125 3126 /* this may want panning to occur, btw */ 3127 if ((ep->edid_preferred_mode->hdisplay <= x) && 3128 (ep->edid_preferred_mode->vdisplay <= y)) 3129 return ep->edid_preferred_mode; 3130 } 3131 3132 for (i = 0; i < ep->edid_nmodes; i++) { 3133 /* 3134 * We elect to pick a resolution that is too large for 3135 * the monitor than one that is too small. This means 3136 * that we will prefer to pan rather than to try to 3137 * center a smaller display on a larger screen. In 3138 * practice, this shouldn't matter because if a 3139 * monitor can support a larger resolution, it can 3140 * probably also support the smaller. A specific 3141 * exception is fixed format panels, but hopefully 3142 * they are properly dealt with by the "autostretch" 3143 * logic above. 3144 */ 3145 if ((ep->edid_modes[i].hdisplay > x) || 3146 (ep->edid_modes[i].vdisplay > y)) { 3147 continue; 3148 } 3149 3150 /* 3151 * at this point, the display mode is no larger than 3152 * what we've requested. 3153 */ 3154 if (vmp == NULL) 3155 vmp = &ep->edid_modes[i]; 3156 3157 /* eliminate smaller modes */ 3158 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3159 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3160 continue; 3161 3162 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3163 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3164 vmp = &ep->edid_modes[i]; 3165 continue; 3166 } 3167 3168 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3169 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3170 3171 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3172 } 3173 3174 return (vmp ? vmp : radeonfb_modelookup(RADEON_DEFAULT_MODE)); 3175 } 3176 3177 static int 3178 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3179 { 3180 int i; 3181 3182 for (i = 0; i < nlist; i++) { 3183 if ((x == list[i].hdisplay) && 3184 (y == list[i].vdisplay)) { 3185 return 1; 3186 } 3187 } 3188 return 0; 3189 } 3190 3191 static void 3192 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3193 int pan) 3194 { 3195 struct radeonfb_port *rp; 3196 struct edid_info *ep; 3197 int i, j; 3198 3199 *x = 0; 3200 *y = 0; 3201 3202 if (pan) { 3203 for (i = 0; i < dp->rd_ncrtcs; i++) { 3204 rp = dp->rd_crtcs[i].rc_port; 3205 ep = &rp->rp_edid; 3206 if (!rp->rp_edid_valid) { 3207 /* monitor not present */ 3208 continue; 3209 } 3210 3211 /* 3212 * For now we are ignoring "conflict" that 3213 * could occur when mixing some modes like 3214 * 1280x1024 and 1400x800. It isn't clear 3215 * which is better, so the first one wins. 3216 */ 3217 for (j = 0; j < ep->edid_nmodes; j++) { 3218 /* 3219 * ignore resolutions that are too big for 3220 * the radeon 3221 */ 3222 if (ep->edid_modes[j].hdisplay > 3223 dp->rd_softc->sc_maxx) 3224 continue; 3225 if (ep->edid_modes[j].vdisplay > 3226 dp->rd_softc->sc_maxy) 3227 continue; 3228 3229 /* 3230 * pick largest resolution, the 3231 * smaller monitor will pan 3232 */ 3233 if ((ep->edid_modes[j].hdisplay >= *x) && 3234 (ep->edid_modes[j].vdisplay >= *y)) { 3235 *x = ep->edid_modes[j].hdisplay; 3236 *y = ep->edid_modes[j].vdisplay; 3237 } 3238 } 3239 } 3240 3241 } else { 3242 struct videomode modes[64]; 3243 int nmodes = 0; 3244 int valid = 0; 3245 3246 for (i = 0; i < dp->rd_ncrtcs; i++) { 3247 /* 3248 * pick the largest resolution in common. 3249 */ 3250 rp = dp->rd_crtcs[i].rc_port; 3251 ep = &rp->rp_edid; 3252 3253 if (!rp->rp_edid_valid) 3254 continue; 3255 3256 if (!valid) { 3257 /* initialize starting list */ 3258 for (j = 0; j < ep->edid_nmodes; j++) { 3259 /* 3260 * ignore resolutions that are 3261 * too big for the radeon 3262 */ 3263 if (ep->edid_modes[j].hdisplay > 3264 dp->rd_softc->sc_maxx) 3265 continue; 3266 if (ep->edid_modes[j].vdisplay > 3267 dp->rd_softc->sc_maxy) 3268 continue; 3269 3270 modes[nmodes] = ep->edid_modes[j]; 3271 nmodes++; 3272 } 3273 valid = 1; 3274 } else { 3275 /* merge into preexisting list */ 3276 for (j = 0; j < nmodes; j++) { 3277 if (!radeonfb_hasres(ep->edid_modes, 3278 ep->edid_nmodes, 3279 modes[j].hdisplay, 3280 modes[j].vdisplay)) { 3281 modes[j] = modes[nmodes]; 3282 j--; 3283 nmodes--; 3284 } 3285 } 3286 } 3287 } 3288 3289 /* now we have to pick from the merged list */ 3290 for (i = 0; i < nmodes; i++) { 3291 if ((modes[i].hdisplay >= *x) && 3292 (modes[i].vdisplay >= *y)) { 3293 *x = modes[i].hdisplay; 3294 *y = modes[i].vdisplay; 3295 } 3296 } 3297 } 3298 3299 if ((*x == 0) || (*y == 0)) { 3300 /* fallback to safe mode */ 3301 *x = 640; 3302 *y = 480; 3303 } 3304 } 3305
Indexes created Tue Sep 23 07:09:52 GMT 2025