radeonfb.c revision 1.80
1 /* $NetBSD: radeonfb.c,v 1.80 2014/01/14 01:35:13 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.80 2014/01/14 01:35:13 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 144 /* acceleration support */ 145 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 146 int width, int height, uint32_t color); 147 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 148 static void radeonfb_bitblt(void *, int srcx, int srcy, 149 int dstx, int dsty, int width, int height, int rop); 150 151 /* hw cursor support */ 152 static void radeonfb_cursor_cmap(struct radeonfb_display *); 153 static void radeonfb_cursor_shape(struct radeonfb_display *); 154 static void radeonfb_cursor_position(struct radeonfb_display *); 155 static void radeonfb_cursor_visible(struct radeonfb_display *); 156 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 157 158 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 159 static void radeonfb_engine_idle(struct radeonfb_softc *); 160 static void radeonfb_engine_flush(struct radeonfb_softc *); 161 static void radeonfb_engine_reset(struct radeonfb_softc *); 162 static void radeonfb_engine_init(struct radeonfb_display *); 163 static inline void radeonfb_unclip(struct radeonfb_softc *); 164 165 static void radeonfb_eraserows(void *, int, int, long); 166 static void radeonfb_erasecols(void *, int, int, int, long); 167 static void radeonfb_copyrows(void *, int, int, int); 168 static void radeonfb_copycols(void *, int, int, int, int); 169 static void radeonfb_cursor(void *, int, int, int); 170 static void radeonfb_putchar(void *, int, int, unsigned, long); 171 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 172 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 173 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 174 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 175 #endif 176 177 static int radeonfb_set_backlight(struct radeonfb_display *, int); 178 static int radeonfb_get_backlight(struct radeonfb_display *); 179 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 180 static void radeonfb_lvds_callout(void *); 181 182 static void radeonfb_brightness_up(device_t); 183 static void radeonfb_brightness_down(device_t); 184 185 static struct videomode *radeonfb_best_refresh(struct videomode *, 186 struct videomode *); 187 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 188 uint16_t *, int); 189 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 190 struct radeonfb_port *, int, int); 191 192 static int radeonfb_drm_print(void *, const char *); 193 194 #ifdef RADEONFB_DEBUG 195 int radeon_debug = 1; 196 #define DPRINTF(x) \ 197 if (radeon_debug) printf x 198 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 199 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 200 #else 201 #define DPRINTF(x) 202 #define PRINTREG(r) 203 #define PRINTPLL(r) 204 #endif 205 206 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 207 208 #ifndef RADEON_DEFAULT_MODE 209 /* any reasonably modern display should handle this */ 210 #define RADEON_DEFAULT_MODE "1024x768x60" 211 #endif 212 213 extern const u_char rasops_cmap[768]; 214 215 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 216 217 static struct { 218 int size; /* minimum memory size (MB) */ 219 int maxx; /* maximum x dimension */ 220 int maxy; /* maximum y dimension */ 221 int maxbpp; /* maximum bpp */ 222 int maxdisp; /* maximum logical display count */ 223 } radeonfb_limits[] = { 224 { 32, 2048, 1536, 32, 2 }, 225 { 16, 1600, 1200, 32, 2 }, 226 { 8, 1600, 1200, 32, 1 }, 227 { 0, 0, 0, 0, 0 }, 228 }; 229 230 static struct wsscreen_descr radeonfb_stdscreen = { 231 "fb", /* name */ 232 0, 0, /* ncols, nrows */ 233 NULL, /* textops */ 234 8, 16, /* fontwidth, fontheight */ 235 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 236 0, /* modecookie */ 237 }; 238 239 struct wsdisplay_accessops radeonfb_accessops = { 240 radeonfb_ioctl, 241 radeonfb_mmap, 242 NULL, /* vcons_alloc_screen */ 243 NULL, /* vcons_free_screen */ 244 NULL, /* vcons_show_screen */ 245 NULL, /* load_font */ 246 NULL, /* pollc */ 247 NULL, /* scroll */ 248 }; 249 250 static struct { 251 uint16_t devid; 252 uint16_t family; 253 uint16_t flags; 254 } radeonfb_devices[] = 255 { 256 /* R100 family */ 257 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 258 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 260 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 261 262 /* RV100 family */ 263 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 264 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 265 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 267 268 /* RS100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 270 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 271 272 /* RS200/RS250 family */ 273 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 274 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 275 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 276 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 277 278 /* R200 family */ 279 /* add more R200 products? , 5148 */ 280 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 282 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 283 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 285 286 /* RV200 family */ 287 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 288 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 289 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 291 292 /* RV250 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 298 299 /* RS300 family */ 300 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 304 305 /* RV280 family */ 306 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 313 314 /* R300 family */ 315 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 318 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 323 324 /* RV350/RV360 family */ 325 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 337 338 /* R350/R360 family */ 339 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 342 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 347 348 /* RV380/RV370 family */ 349 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 350 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 355 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 359 360 #if notyet 361 /* R420/R423 family */ 362 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 365 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 379 #endif 380 { 0, 0, 0 } 381 }; 382 383 static struct { 384 int divider; 385 int mask; 386 } radeonfb_dividers[] = { 387 { 16, 5 }, 388 { 12, 7 }, 389 { 8, 3 }, 390 { 6, 6 }, 391 { 4, 2 }, 392 { 3, 4 }, 393 { 2, 1 }, 394 { 1, 0 }, 395 { 0, 0 } 396 }; 397 398 /* 399 * This table taken from X11. 400 */ 401 static const struct { 402 int family; 403 struct radeon_tmds_pll plls[4]; 404 } radeonfb_tmds_pll[] = { 405 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 406 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 407 { RADEON_RS100, {{0, 0}}}, 408 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 411 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 412 { RADEON_RS300, {{0, 0}}}, 413 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 414 { RADEON_R300, {{-1, 0xb01cb}}}, 415 { RADEON_R350, {{-1, 0xb01cb}}}, 416 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 417 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 418 { RADEON_R420, {{-1, 0xb01cb}}}, 419 }; 420 421 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 422 423 424 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 425 radeonfb_match, radeonfb_attach, NULL, NULL); 426 427 static int 428 radeonfb_match(device_t parent, cfdata_t match, void *aux) 429 { 430 const struct pci_attach_args *pa = aux; 431 int i; 432 433 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 434 return 0; 435 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 438 return 100; /* high to defeat VGA/VESA */ 439 } 440 441 return 0; 442 } 443 444 static void 445 radeonfb_attach(device_t parent, device_t dev, void *aux) 446 { 447 struct radeonfb_softc *sc = device_private(dev); 448 const struct pci_attach_args *pa = aux; 449 const char *mptr; 450 bus_size_t bsz; 451 pcireg_t screg; 452 int i, j, fg, bg, ul, flags; 453 uint32_t v; 454 455 sc->sc_dev = dev; 456 sc->sc_id = pa->pa_id; 457 for (i = 0; radeonfb_devices[i].devid; i++) { 458 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 459 break; 460 } 461 462 pci_aprint_devinfo(pa, NULL); 463 464 DPRINTF((prop_dictionary_externalize(device_properties(dev)))); 465 466 KASSERT(radeonfb_devices[i].devid != 0); 467 sc->sc_pt = pa->pa_tag; 468 sc->sc_iot = pa->pa_iot; 469 sc->sc_pc = pa->pa_pc; 470 sc->sc_family = radeonfb_devices[i].family; 471 sc->sc_flags = radeonfb_devices[i].flags; 472 473 /* enable memory and IO access */ 474 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 475 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 476 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 477 478 /* 479 * Some flags are general to entire chip families, and rather 480 * than clutter up the table with them, we go ahead and set 481 * them here. 482 */ 483 switch (sc->sc_family) { 484 case RADEON_RS100: 485 case RADEON_RS200: 486 sc->sc_flags |= RFB_IGP | RFB_RV100; 487 break; 488 489 case RADEON_RV100: 490 case RADEON_RV200: 491 case RADEON_RV250: 492 case RADEON_RV280: 493 sc->sc_flags |= RFB_RV100; 494 break; 495 496 case RADEON_RS300: 497 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_R300: 501 case RADEON_RV350: 502 case RADEON_R350: 503 case RADEON_RV380: 504 case RADEON_R420: 505 /* newer chips */ 506 sc->sc_flags |= RFB_R300; 507 break; 508 509 case RADEON_R100: 510 sc->sc_flags |= RFB_NCRTC2; 511 break; 512 } 513 514 if ((sc->sc_family == RADEON_RV200) || 515 (sc->sc_family == RADEON_RV250) || 516 (sc->sc_family == RADEON_RV280) || 517 (sc->sc_family == RADEON_RV350)) { 518 bool inverted = 0; 519 /* backlight level is linear */ 520 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 521 prop_dictionary_get_bool(device_properties(sc->sc_dev), 522 "backlight_level_reverted", &inverted); 523 if (inverted) { 524 DPRINTF(("nope, it's inverted\n")); 525 sc->sc_flags |= RFB_INV_BLIGHT; 526 } 527 } else 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 530 /* 531 * XXX: to support true multihead, this must change. 532 */ 533 sc->sc_ndisplays = 1; 534 535 /* XXX: */ 536 if (!HAS_CRTC2(sc)) { 537 sc->sc_ndisplays = 1; 538 } 539 540 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 541 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 542 &sc->sc_regsz) != 0) { 543 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 544 goto error; 545 } 546 547 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 548 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 549 { 550 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 551 goto error; 552 } 553 sc->sc_romt = sc->sc_memt; 554 555 sc->sc_mapped = TRUE; 556 557 /* scratch register test... */ 558 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 559 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 560 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 561 goto error; 562 } 563 564 PRINTREG(RADEON_CRTC_EXT_CNTL); 565 PRINTREG(RADEON_CRTC_GEN_CNTL); 566 PRINTREG(RADEON_CRTC2_GEN_CNTL); 567 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 568 PRINTREG(RADEON_DAC_CNTL2); 569 PRINTREG(RADEON_FP_GEN_CNTL); 570 PRINTREG(RADEON_FP2_GEN_CNTL); 571 572 PRINTREG(RADEON_BIOS_4_SCRATCH); 573 PRINTREG(RADEON_FP_GEN_CNTL); 574 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 575 PRINTREG(RADEON_FP2_GEN_CNTL); 576 PRINTREG(RADEON_TMDS_CNTL); 577 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 578 PRINTREG(RADEON_TMDS_PLL_CNTL); 579 PRINTREG(RADEON_LVDS_GEN_CNTL); 580 PRINTREG(RADEON_FP_HORZ_STRETCH); 581 PRINTREG(RADEON_FP_VERT_STRETCH); 582 583 if (IS_RV100(sc)) 584 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 585 586 /* XXX 587 * according to xf86-video-radeon R3xx has this bit backwards 588 */ 589 if (IS_R300(sc)) { 590 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 591 0, 592 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 593 } else { 594 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 595 RADEON_TMDS_TRANSMITTER_PLLEN, 596 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 597 } 598 599 radeonfb_i2c_init(sc); 600 601 radeonfb_loadbios(sc, pa); 602 603 #ifdef RADEONFB_BIOS_INIT 604 if (radeonfb_bios_init(sc)) { 605 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 606 } 607 #endif 608 609 if (radeonfb_getclocks(sc)) { 610 aprint_error("%s: Unable to get reference clocks from BIOS\n", 611 XNAME(sc)); 612 goto error; 613 } 614 615 if (radeonfb_gettmds(sc)) { 616 aprint_error("%s: Unable to identify TMDS PLL settings\n", 617 XNAME(sc)); 618 goto error; 619 } 620 621 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 622 "minpll = %d, maxpll = %d\n", XNAME(sc), 623 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 624 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 625 626 radeonfb_getconnectors(sc); 627 628 radeonfb_set_fbloc(sc); 629 630 for (i = 0; radeonfb_limits[i].size; i++) { 631 if (sc->sc_memsz >= radeonfb_limits[i].size) { 632 sc->sc_maxx = radeonfb_limits[i].maxx; 633 sc->sc_maxy = radeonfb_limits[i].maxy; 634 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 635 /* framebuffer offset, start at a 4K page */ 636 sc->sc_fboffset = sc->sc_memsz / 637 radeonfb_limits[i].maxdisp; 638 /* 639 * we use the fbsize to figure out where we can store 640 * things like cursor data. 641 */ 642 sc->sc_fbsize = 643 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 644 RADEON_STRIDEALIGN) * sc->sc_maxy, 645 4096); 646 break; 647 } 648 } 649 650 651 radeonfb_init_misc(sc); 652 653 /* program the DAC wirings */ 654 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 655 switch (sc->sc_ports[i].rp_dac_type) { 656 case RADEON_DAC_PRIMARY: 657 PATCH32(sc, RADEON_DAC_CNTL2, 658 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 659 ~RADEON_DAC2_DAC_CLK_SEL); 660 break; 661 case RADEON_DAC_TVDAC: 662 /* we always use the TVDAC to drive a secondary analog 663 * CRT for now. if we ever support TV-out this will 664 * have to change. 665 */ 666 SET32(sc, RADEON_DAC_CNTL2, 667 RADEON_DAC2_DAC2_CLK_SEL); 668 PATCH32(sc, RADEON_DISP_HW_DEBUG, 669 i ? 0 : RADEON_CRT2_DISP1_SEL, 670 ~RADEON_CRT2_DISP1_SEL); 671 /* we're using CRTC2 for the 2nd port */ 672 if (sc->sc_ports[i].rp_number == 1) { 673 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 674 RADEON_DISP_DAC2_SOURCE_CRTC2, 675 ~RADEON_DISP_DAC2_SOURCE_MASK); 676 } 677 678 break; 679 } 680 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 681 sc->sc_ports[i].rp_tmds_type)); 682 switch (sc->sc_ports[i].rp_tmds_type) { 683 case RADEON_TMDS_INT: 684 /* point FP0 at the CRTC this port uses */ 685 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 686 __func__, sc->sc_ports[i].rp_number)); 687 if (IS_R300(sc)) { 688 PATCH32(sc, RADEON_FP_GEN_CNTL, 689 sc->sc_ports[i].rp_number ? 690 R200_FP_SOURCE_SEL_CRTC2 : 691 R200_FP_SOURCE_SEL_CRTC1, 692 ~R200_FP_SOURCE_SEL_MASK); 693 } else { 694 PATCH32(sc, RADEON_FP_GEN_CNTL, 695 sc->sc_ports[i].rp_number ? 696 RADEON_FP_SEL_CRTC2 : 697 RADEON_FP_SEL_CRTC1, 698 ~RADEON_FP_SEL_MASK); 699 } 700 } 701 } 702 PRINTREG(RADEON_DAC_CNTL2); 703 PRINTREG(RADEON_DISP_HW_DEBUG); 704 705 /* other DAC programming */ 706 v = GET32(sc, RADEON_DAC_CNTL); 707 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 708 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 709 PUT32(sc, RADEON_DAC_CNTL, v); 710 PRINTREG(RADEON_DAC_CNTL); 711 712 /* XXX: this may need more investigation */ 713 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 714 PRINTREG(RADEON_TV_DAC_CNTL); 715 716 /* enable TMDS */ 717 SET32(sc, RADEON_FP_GEN_CNTL, 718 RADEON_FP_TMDS_EN | 719 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 720 RADEON_FP_CRTC_DONT_SHADOW_HEND); 721 /* 722 * XXX 723 * no idea why this is necessary - if I do not clear this bit on my 724 * iBook G4 the screen remains black, even though it's already clear. 725 * It needs to be set on my Sun XVR-100 for the DVI port to work 726 * TODO: 727 * see if this is still necessary now that CRTCs, DACs and outputs are 728 * getting wired up in a halfway sane way 729 */ 730 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 731 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 732 } else { 733 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 734 } 735 736 /* 737 * we use bus_space_map instead of pci_mapreg, because we don't 738 * need the full aperature space. no point in wasting virtual 739 * address space we don't intend to use, right? 740 */ 741 if ((sc->sc_memsz < (4096 * 1024)) || 742 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 743 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 744 (bsz < sc->sc_memsz)) { 745 sc->sc_memsz = 0; 746 aprint_error("%s: Bad frame buffer configuration\n", 747 XNAME(sc)); 748 goto error; 749 } 750 751 /* 64 MB should be enough -- more just wastes map entries */ 752 if (sc->sc_memsz > (64 << 20)) 753 sc->sc_memsz = (64 << 20); 754 755 sc->sc_memt = pa->pa_memt; 756 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 757 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 758 sc->sc_memsz = 0; 759 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 760 goto error; 761 } 762 763 aprint_normal("%s: %d MB aperture at 0x%08x, " 764 "%d KB registers at 0x%08x\n", XNAME(sc), 765 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 766 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 767 768 /* setup default video mode from devprop (allows PROM override) */ 769 sc->sc_defaultmode = radeonfb_default_mode; 770 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 771 "videomode", &mptr)) { 772 773 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 774 sc->sc_defaultmode = sc->sc_modebuf; 775 } 776 777 /* initialize some basic display parameters */ 778 for (i = 0; i < sc->sc_ndisplays; i++) { 779 struct radeonfb_display *dp = &sc->sc_displays[i]; 780 struct rasops_info *ri; 781 long defattr; 782 struct wsemuldisplaydev_attach_args aa; 783 784 /* 785 * Figure out how many "displays" (desktops) we are going to 786 * support. If more than one, then each CRTC gets its own 787 * programming. 788 * 789 * XXX: this code needs to change to support mergedfb. 790 * XXX: would be nice to allow this to be overridden 791 */ 792 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 793 DPRINTF(("dual crtcs!\n")); 794 dp->rd_ncrtcs = 2; 795 dp->rd_crtcs[0].rc_port = 796 &sc->sc_ports[0]; 797 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 798 dp->rd_crtcs[1].rc_port = 799 &sc->sc_ports[1]; 800 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 801 } else { 802 dp->rd_ncrtcs = 1; 803 dp->rd_crtcs[0].rc_port = 804 &sc->sc_ports[i]; 805 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 806 } 807 808 dp->rd_softc = sc; 809 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 810 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 811 812 /* for text mode, we pick a resolution that won't 813 * require panning */ 814 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 815 816 aprint_normal("%s: display %d: " 817 "initial virtual resolution %dx%d at %d bpp\n", 818 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 819 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 820 sc->sc_fboffset >> 20); 821 /* now select the *video mode* that we will use */ 822 for (j = 0; j < dp->rd_ncrtcs; j++) { 823 const struct videomode *vmp; 824 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 825 dp->rd_virtx, dp->rd_virty); 826 827 /* 828 * virtual resolution should be at least as high as 829 * physical 830 */ 831 if (dp->rd_virtx < vmp->hdisplay || 832 dp->rd_virty < vmp->vdisplay) { 833 dp->rd_virtx = vmp->hdisplay; 834 dp->rd_virty = vmp->vdisplay; 835 } 836 837 dp->rd_crtcs[j].rc_videomode = *vmp; 838 printf("%s: port %d: physical %dx%d %dHz\n", 839 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 840 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 841 vmp->htotal), vmp->vtotal)); 842 } 843 844 /* N.B.: radeon wants 64-byte aligned stride */ 845 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 846 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 847 DPRINTF(("stride: %d\n", dp->rd_stride)); 848 849 dp->rd_offset = sc->sc_fboffset * i; 850 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 851 sc->sc_memh) + dp->rd_offset; 852 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 853 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 854 855 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 856 857 switch (dp->rd_bpp) { 858 case 8: 859 dp->rd_format = 2; 860 break; 861 case 32: 862 dp->rd_format = 6; 863 break; 864 default: 865 aprint_error("%s: bad depth %d\n", XNAME(sc), 866 dp->rd_bpp); 867 goto error; 868 } 869 870 DPRINTF(("init engine\n")); 871 /* XXX: this seems suspicious - per display engine 872 initialization? */ 873 radeonfb_engine_init(dp); 874 875 /* copy the template into place */ 876 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 877 dp->rd_wsscreens = dp->rd_wsscreens_storage; 878 879 /* and make up the list */ 880 dp->rd_wsscreenlist.nscreens = 1; 881 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 882 883 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 884 &radeonfb_accessops); 885 886 dp->rd_vd.init_screen = radeonfb_init_screen; 887 888 #ifdef RADEONFB_DEBUG 889 dp->rd_virty -= 200; 890 #endif 891 892 dp->rd_console = 0; 893 prop_dictionary_get_bool(device_properties(sc->sc_dev), 894 "is_console", &dp->rd_console); 895 896 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 897 898 899 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 900 dp->rd_console, &defattr); 901 902 ri = &dp->rd_vscreen.scr_ri; 903 904 /* clear the screen */ 905 rasops_unpack_attr(defattr, &fg, &bg, &ul); 906 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 907 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 908 dp->rd_bg); 909 910 dp->rd_wsscreens->textops = &ri->ri_ops; 911 dp->rd_wsscreens->capabilities = ri->ri_caps; 912 dp->rd_wsscreens->nrows = ri->ri_rows; 913 dp->rd_wsscreens->ncols = ri->ri_cols; 914 915 #ifdef SPLASHSCREEN 916 dp->rd_splash.si_depth = ri->ri_depth; 917 dp->rd_splash.si_bits = ri->ri_bits; 918 dp->rd_splash.si_hwbits = ri->ri_hwbits; 919 dp->rd_splash.si_width = ri->ri_width; 920 dp->rd_splash.si_height = ri->ri_height; 921 dp->rd_splash.si_stride = ri->ri_stride; 922 dp->rd_splash.si_fillrect = NULL; 923 #endif 924 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 925 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 926 dp->rd_gc.gc_rop = RADEON_ROP3_S; 927 dp->rd_gc.gc_blitcookie = dp; 928 /* 929 * use memory between framebuffer and cursor area as glyph 930 * cache, cap at 4096 lines 931 */ 932 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 933 min(4096, 934 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 935 dp->rd_virtx, 936 ri->ri_font->fontwidth, 937 ri->ri_font->fontheight, 938 defattr); 939 if (dp->rd_console) { 940 941 radeonfb_modeswitch(dp); 942 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 943 defattr); 944 #ifdef SPLASHSCREEN 945 if (splash_render(&dp->rd_splash, 946 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 947 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 948 else 949 #endif 950 vcons_replay_msgbuf(&dp->rd_vscreen); 951 } else { 952 953 /* 954 * since we're not the console we can postpone 955 * the rest until someone actually allocates a 956 * screen for us. but we do clear the screen 957 * at least. 958 */ 959 memset(ri->ri_bits, 0, 1024); 960 961 radeonfb_modeswitch(dp); 962 #ifdef SPLASHSCREEN 963 if (splash_render(&dp->rd_splash, 964 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 965 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 966 #endif 967 } 968 969 aa.console = dp->rd_console; 970 aa.scrdata = &dp->rd_wsscreenlist; 971 aa.accessops = &radeonfb_accessops; 972 aa.accesscookie = &dp->rd_vd; 973 974 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 975 976 radeonfb_blank(dp, 0); 977 978 /* Initialise delayed lvds operations for backlight. */ 979 callout_init(&dp->rd_bl_lvds_co, 0); 980 callout_setfunc(&dp->rd_bl_lvds_co, 981 radeonfb_lvds_callout, dp); 982 dp->rd_bl_on = 1; 983 dp->rd_bl_level = radeonfb_get_backlight(dp); 984 radeonfb_set_backlight(dp, dp->rd_bl_level); 985 } 986 987 for (i = 0; i < RADEON_NDISPLAYS; i++) 988 radeonfb_init_palette(&sc->sc_displays[i]); 989 990 if (HAS_CRTC2(sc)) { 991 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 992 } 993 994 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 995 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 996 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 997 radeonfb_brightness_up, TRUE); 998 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 999 radeonfb_brightness_down, TRUE); 1000 1001 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 1002 1003 PRINTREG(RADEON_CRTC_EXT_CNTL); 1004 PRINTREG(RADEON_CRTC_GEN_CNTL); 1005 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1006 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1007 PRINTREG(RADEON_DAC_CNTL2); 1008 PRINTREG(RADEON_FP_GEN_CNTL); 1009 PRINTREG(RADEON_FP2_GEN_CNTL); 1010 1011 return; 1012 1013 error: 1014 if (sc->sc_biossz) 1015 free(sc->sc_bios, M_DEVBUF); 1016 1017 if (sc->sc_regsz) 1018 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1019 1020 if (sc->sc_memsz) 1021 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1022 } 1023 1024 static void 1025 radeonfb_map(struct radeonfb_softc *sc) 1026 { 1027 if (!sc->sc_mapped) { 1028 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1029 &sc->sc_regh) != 0) { 1030 aprint_error_dev(sc->sc_dev, 1031 "unable to map registers!\n"); 1032 return; 1033 } 1034 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1035 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1036 sc->sc_memsz = 0; 1037 aprint_error_dev(sc->sc_dev, 1038 "Unable to map frame buffer\n"); 1039 return; 1040 } 1041 sc->sc_mapped = TRUE; 1042 } 1043 } 1044 1045 static void 1046 radeonfb_unmap(struct radeonfb_softc *sc) 1047 { 1048 if (sc->sc_mapped) { 1049 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1050 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1051 sc->sc_mapped = FALSE; 1052 } 1053 } 1054 1055 static int 1056 radeonfb_drm_print(void *aux, const char *pnp) 1057 { 1058 if (pnp) 1059 aprint_normal("drm at %s", pnp); 1060 return (UNCONF); 1061 } 1062 1063 int 1064 radeonfb_ioctl(void *v, void *vs, 1065 unsigned long cmd, void *d, int flag, struct lwp *l) 1066 { 1067 struct vcons_data *vd; 1068 struct radeonfb_display *dp; 1069 struct radeonfb_softc *sc; 1070 struct wsdisplay_param *param; 1071 struct vcons_screen *ms; 1072 1073 vd = (struct vcons_data *)v; 1074 ms = vd->active; 1075 dp = (struct radeonfb_display *)vd->cookie; 1076 sc = dp->rd_softc; 1077 1078 switch (cmd) { 1079 case WSDISPLAYIO_GTYPE: 1080 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1081 return 0; 1082 1083 case WSDISPLAYIO_GINFO: 1084 if (vd->active != NULL) { 1085 struct wsdisplay_fbinfo *fb; 1086 fb = (struct wsdisplay_fbinfo *)d; 1087 fb->width = dp->rd_virtx; 1088 fb->height = dp->rd_virty; 1089 fb->depth = dp->rd_bpp; 1090 fb->cmsize = 256; 1091 return 0; 1092 } else 1093 return ENODEV; 1094 case WSDISPLAYIO_GVIDEO: 1095 if (radeonfb_isblank(dp)) 1096 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1097 else 1098 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1099 return 0; 1100 1101 case WSDISPLAYIO_SVIDEO: 1102 radeonfb_blank(dp, 1103 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1104 return 0; 1105 1106 case WSDISPLAYIO_GETCMAP: 1107 #if 0 1108 if (dp->rd_bpp == 8) 1109 return radeonfb_getcmap(sc, 1110 (struct wsdisplay_cmap *)d); 1111 #endif 1112 return EINVAL; 1113 1114 case WSDISPLAYIO_PUTCMAP: 1115 #if 0 1116 if (dp->rd_bpp == 8) 1117 return radeonfb_putcmap(sc, 1118 (struct wsdisplay_cmap *)d); 1119 #endif 1120 return EINVAL; 1121 1122 case WSDISPLAYIO_LINEBYTES: 1123 *(unsigned *)d = dp->rd_stride; 1124 return 0; 1125 1126 case WSDISPLAYIO_SMODE: 1127 if (*(int *)d != dp->rd_wsmode) { 1128 dp->rd_wsmode = *(int *)d; 1129 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1130 (dp->rd_vd.active)) { 1131 radeonfb_map(sc); 1132 radeonfb_engine_init(dp); 1133 glyphcache_wipe(&dp->rd_gc); 1134 radeonfb_init_palette(dp); 1135 radeonfb_modeswitch(dp); 1136 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1137 dp->rd_virty, dp->rd_bg); 1138 vcons_redraw_screen(dp->rd_vd.active); 1139 } else { 1140 radeonfb_unmap(sc); 1141 } 1142 } 1143 return 0; 1144 1145 case WSDISPLAYIO_GCURMAX: 1146 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1147 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1148 return 0; 1149 1150 case WSDISPLAYIO_SCURSOR: 1151 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1152 1153 case WSDISPLAYIO_GCURSOR: 1154 return EPASSTHROUGH; 1155 1156 case WSDISPLAYIO_GCURPOS: 1157 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1158 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1159 return 0; 1160 1161 case WSDISPLAYIO_SCURPOS: 1162 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1163 1164 case WSDISPLAYIO_SSPLASH: 1165 #if defined(SPLASHSCREEN) 1166 if (*(int *)d == 1) { 1167 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1168 splash_render(&dp->rd_splash, 1169 SPLASH_F_CENTER|SPLASH_F_FILL); 1170 } else 1171 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1172 return 0; 1173 #else 1174 return ENODEV; 1175 #endif 1176 case WSDISPLAYIO_GETPARAM: 1177 param = (struct wsdisplay_param *)d; 1178 switch (param->param) { 1179 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1180 param->min = 0; 1181 param->max = 255; 1182 param->curval = dp->rd_bl_level; 1183 return 0; 1184 case WSDISPLAYIO_PARAM_BACKLIGHT: 1185 param->min = 0; 1186 param->max = RADEONFB_BACKLIGHT_MAX; 1187 param->curval = dp->rd_bl_on; 1188 return 0; 1189 } 1190 return EPASSTHROUGH; 1191 1192 case WSDISPLAYIO_SETPARAM: 1193 param = (struct wsdisplay_param *)d; 1194 switch (param->param) { 1195 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1196 radeonfb_set_backlight(dp, param->curval); 1197 return 0; 1198 case WSDISPLAYIO_PARAM_BACKLIGHT: 1199 radeonfb_switch_backlight(dp, param->curval); 1200 return 0; 1201 } 1202 return EPASSTHROUGH; 1203 1204 /* PCI config read/write passthrough. */ 1205 case PCI_IOC_CFGREAD: 1206 case PCI_IOC_CFGWRITE: 1207 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1208 1209 case WSDISPLAYIO_GET_BUSID: 1210 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1211 sc->sc_pt, d); 1212 1213 case WSDISPLAYIO_GET_EDID: { 1214 struct wsdisplayio_edid_info *ei = d; 1215 return wsdisplayio_get_edid(sc->sc_dev, ei); 1216 } 1217 1218 case WSDISPLAYIO_GET_FBINFO: { 1219 struct wsdisplayio_fbinfo *fbi = d; 1220 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1221 } 1222 1223 default: 1224 return EPASSTHROUGH; 1225 } 1226 } 1227 1228 paddr_t 1229 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1230 { 1231 struct vcons_data *vd; 1232 struct radeonfb_display *dp; 1233 struct radeonfb_softc *sc; 1234 paddr_t pa; 1235 1236 vd = (struct vcons_data *)v; 1237 dp = (struct radeonfb_display *)vd->cookie; 1238 sc = dp->rd_softc; 1239 1240 /* XXX: note that we don't allow mapping of registers right now */ 1241 /* XXX: this means that the XFree86 radeon driver won't work */ 1242 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1243 pa = bus_space_mmap(sc->sc_memt, 1244 sc->sc_memaddr + dp->rd_offset + offset, 0, 1245 prot, BUS_SPACE_MAP_LINEAR); 1246 return pa; 1247 } 1248 1249 #ifdef RADEONFB_MMAP_BARS 1250 /* 1251 * restrict all other mappings to processes with superuser privileges 1252 * or the kernel itself 1253 */ 1254 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1255 NULL, NULL, NULL, NULL) != 0) { 1256 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1257 return -1; 1258 } 1259 1260 if ((offset >= sc->sc_regaddr) && 1261 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1262 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1263 BUS_SPACE_MAP_LINEAR); 1264 } 1265 1266 if ((offset >= sc->sc_memaddr) && 1267 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1268 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1269 BUS_SPACE_MAP_LINEAR); 1270 } 1271 1272 if ((offset >= sc->sc_romaddr) && 1273 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1274 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1275 BUS_SPACE_MAP_LINEAR); 1276 } 1277 1278 #ifdef PCI_MAGIC_IO_RANGE 1279 /* allow mapping of IO space */ 1280 if ((offset >= PCI_MAGIC_IO_RANGE) && 1281 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1282 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1283 0, prot, 0); 1284 return pa; 1285 } 1286 #endif /* PCI_MAGIC_IO_RANGE */ 1287 1288 #endif /* RADEONFB_MMAP_BARS */ 1289 1290 return -1; 1291 } 1292 1293 static void 1294 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1295 { 1296 bus_space_tag_t romt; 1297 bus_space_handle_t romh, biosh; 1298 bus_size_t romsz; 1299 bus_addr_t ptr; 1300 1301 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1302 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1303 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1304 return; 1305 } 1306 1307 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1308 &sc->sc_biossz); 1309 if (sc->sc_biossz == 0) { 1310 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1311 return; 1312 } 1313 1314 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1315 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1316 1317 /* unmap the PCI expansion rom */ 1318 bus_space_unmap(romt, romh, romsz); 1319 1320 /* turn off rom decoder now */ 1321 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1322 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1323 ~PCI_MAPREG_ROM_ENABLE); 1324 1325 ptr = GETBIOS16(sc, 0x48); 1326 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1327 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1328 sc->sc_flags |= RFB_ATOM; 1329 } 1330 1331 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1332 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1333 } 1334 1335 1336 uint32_t 1337 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1338 { 1339 1340 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1341 } 1342 1343 void 1344 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1345 { 1346 1347 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1348 } 1349 1350 void 1351 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1352 { 1353 1354 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1355 } 1356 1357 void 1358 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1359 uint32_t andmask, uint32_t ormask) 1360 { 1361 int s; 1362 uint32_t val; 1363 1364 s = splhigh(); 1365 val = radeonfb_get32(sc, reg); 1366 val = (val & andmask) | ormask; 1367 radeonfb_put32(sc, reg, val); 1368 splx(s); 1369 } 1370 1371 uint32_t 1372 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1373 { 1374 int s; 1375 uint32_t val; 1376 1377 s = splhigh(); 1378 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1379 val = radeonfb_get32(sc, RADEON_MM_DATA); 1380 splx(s); 1381 1382 return (val); 1383 } 1384 1385 void 1386 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1387 { 1388 int s; 1389 1390 s = splhigh(); 1391 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1392 radeonfb_put32(sc, RADEON_MM_DATA, val); 1393 splx(s); 1394 } 1395 1396 void 1397 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1398 uint32_t andmask, uint32_t ormask) 1399 { 1400 int s; 1401 uint32_t val; 1402 1403 s = splhigh(); 1404 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1405 val = radeonfb_get32(sc, RADEON_MM_DATA); 1406 val = (val & andmask) | ormask; 1407 radeonfb_put32(sc, RADEON_MM_DATA, val); 1408 splx(s); 1409 } 1410 1411 uint32_t 1412 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1413 { 1414 int s; 1415 uint32_t val; 1416 1417 s = splhigh(); 1418 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1419 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1420 if (HAS_R300CG(sc)) 1421 radeonfb_r300cg_workaround(sc); 1422 splx(s); 1423 1424 return (val); 1425 } 1426 1427 void 1428 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1429 { 1430 int s; 1431 1432 s = splhigh(); 1433 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1434 RADEON_PLL_WR_EN); 1435 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1436 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1437 splx(s); 1438 } 1439 1440 void 1441 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1442 uint32_t andmask, uint32_t ormask) 1443 { 1444 int s; 1445 uint32_t val; 1446 1447 s = splhigh(); 1448 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1449 RADEON_PLL_WR_EN); 1450 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1451 val = (val & andmask) | ormask; 1452 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1453 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1454 splx(s); 1455 } 1456 1457 int 1458 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1459 { 1460 uint32_t saved; 1461 1462 saved = GET32(sc, reg); 1463 PUT32(sc, reg, v); 1464 if (GET32(sc, reg) != v) { 1465 return -1; 1466 } 1467 PUT32(sc, reg, saved); 1468 return 0; 1469 } 1470 1471 uintmax_t 1472 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1473 uintmax_t defval) 1474 { 1475 prop_number_t pn; 1476 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1477 if (pn == NULL) { 1478 return defval; 1479 } 1480 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1481 return (prop_number_integer_value(pn)); 1482 } 1483 1484 int 1485 radeonfb_getclocks(struct radeonfb_softc *sc) 1486 { 1487 bus_addr_t ptr; 1488 int refclk = 0; 1489 int refdiv = 0; 1490 int minpll = 0; 1491 int maxpll = 0; 1492 1493 /* load initial property values if port/board provides them */ 1494 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1495 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1496 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1497 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1498 1499 PRINTPLL(RADEON_PPLL_REF_DIV); 1500 PRINTPLL(RADEON_PPLL_DIV_0); 1501 PRINTPLL(RADEON_PPLL_DIV_1); 1502 PRINTPLL(RADEON_PPLL_DIV_2); 1503 PRINTPLL(RADEON_PPLL_DIV_3); 1504 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1505 PRINTPLL(RADEON_P2PLL_REF_DIV); 1506 PRINTPLL(RADEON_P2PLL_DIV_0); 1507 1508 if (refclk && refdiv && minpll && maxpll) 1509 goto dontprobe; 1510 1511 if (!sc->sc_biossz) { 1512 /* no BIOS */ 1513 aprint_verbose("%s: No video BIOS, using default clocks\n", 1514 XNAME(sc)); 1515 if (IS_IGP(sc)) 1516 refclk = refclk ? refclk : 1432; 1517 else 1518 refclk = refclk ? refclk : 2700; 1519 refdiv = refdiv ? refdiv : 12; 1520 minpll = minpll ? minpll : 12500; 1521 /* XXX 1522 * Need to check if the firmware or something programmed a 1523 * higher value than this, and if so, bump it. 1524 * The RV280 in my iBook is unhappy if the PLL input is less 1525 * than 360MHz 1526 */ 1527 maxpll = maxpll ? maxpll : 40000/*35000*/; 1528 } else if (IS_ATOM(sc)) { 1529 /* ATOM BIOS */ 1530 ptr = GETBIOS16(sc, 0x48); 1531 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1532 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1533 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1534 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1535 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1536 /* 1537 * ATOM BIOS doesn't supply a reference divider, so we 1538 * have to probe for it. 1539 */ 1540 if (refdiv < 2) 1541 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1542 RADEON_PPLL_REF_DIV_MASK; 1543 /* 1544 * if probe is zero, just assume one that should work 1545 * for most parts 1546 */ 1547 if (refdiv < 2) 1548 refdiv = 12; 1549 1550 } else { 1551 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1552 /* Legacy BIOS */ 1553 ptr = GETBIOS16(sc, 0x48); 1554 ptr = GETBIOS16(sc, ptr + 0x30); 1555 if (IS_R300(sc)) { 1556 refdiv = refdiv ? refdiv : 1557 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1558 R300_PPLL_REF_DIV_ACC_SHIFT; 1559 } else { 1560 refdiv = refdiv ? refdiv : 1561 tmp & RADEON_PPLL_REF_DIV_MASK; 1562 } 1563 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1564 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1565 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1566 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1567 } 1568 1569 1570 dontprobe: 1571 sc->sc_refclk = refclk * 10; 1572 sc->sc_refdiv = refdiv; 1573 sc->sc_minpll = minpll * 10; 1574 sc->sc_maxpll = maxpll * 10; 1575 return 0; 1576 } 1577 1578 int 1579 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1580 uint32_t *postdivbit, uint32_t *feedbackdiv) 1581 { 1582 int i; 1583 uint32_t outfreq; 1584 int div; 1585 1586 DPRINTF(("dot clock: %u\n", dotclock)); 1587 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1588 outfreq = div * dotclock; 1589 if ((outfreq >= sc->sc_minpll) && 1590 (outfreq <= sc->sc_maxpll)) { 1591 DPRINTF(("outfreq: %u\n", outfreq)); 1592 *postdivbit = 1593 ((uint32_t)radeonfb_dividers[i].mask << 16); 1594 DPRINTF(("post divider: %d (mask %x)\n", div, 1595 *postdivbit)); 1596 break; 1597 } 1598 } 1599 1600 if (div == 0) 1601 return 1; 1602 1603 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1604 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1605 return 0; 1606 } 1607 1608 #if 0 1609 #ifdef RADEONFB_DEBUG 1610 static void 1611 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1612 { 1613 char asc[17]; 1614 unsigned ptr = (unsigned)buffer; 1615 char *start = (char *)(ptr & ~0xf); 1616 char *end = (char *)(ptr + size); 1617 1618 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1619 1620 if (pfx == NULL) { 1621 pfx = ""; 1622 } 1623 1624 while (start < end) { 1625 unsigned offset = (unsigned)start & 0xf; 1626 if (offset == 0) { 1627 printf("%s%x: ", pfx, (unsigned)start); 1628 } 1629 if (((unsigned)start < ptr) || 1630 ((unsigned)start >= (ptr + size))) { 1631 printf(" "); 1632 asc[offset] = ' '; 1633 } else { 1634 printf("%02x", *(unsigned char *)start); 1635 if ((*start >= ' ') && (*start <= '~')) { 1636 asc[offset] = *start; 1637 } else { 1638 asc[offset] = '.'; 1639 } 1640 } 1641 asc[offset + 1] = 0; 1642 if (offset % 2) { 1643 printf(" "); 1644 } 1645 if (offset == 15) { 1646 printf(" %s\n", asc); 1647 } 1648 start++; 1649 } 1650 } 1651 #endif 1652 #endif 1653 1654 int 1655 radeonfb_getconnectors(struct radeonfb_softc *sc) 1656 { 1657 int i; 1658 int found = 0; 1659 1660 for (i = 0; i < 2; i++) { 1661 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1662 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1663 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1664 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1665 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1666 } 1667 1668 /* 1669 * This logic is borrowed from Xorg's radeon driver. 1670 */ 1671 if (!sc->sc_biossz) 1672 goto nobios; 1673 1674 if (IS_ATOM(sc)) { 1675 /* not done yet */ 1676 } else { 1677 uint16_t ptr; 1678 int port = 0; 1679 1680 ptr = GETBIOS16(sc, 0x48); 1681 ptr = GETBIOS16(sc, ptr + 0x50); 1682 for (i = 1; i < 4; i++) { 1683 uint16_t entry; 1684 uint8_t conn, ddc, dac, tmds; 1685 1686 /* 1687 * Parse the connector table. From reading the code, 1688 * it appears to made up of 16-bit entries for each 1689 * connector. The 16-bits are defined as: 1690 * 1691 * bits 12-15 - connector type (0 == end of table) 1692 * bits 8-11 - DDC type 1693 * bits 5-7 - ??? 1694 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1695 * bits 1-3 - ??? 1696 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1697 */ 1698 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1699 break; 1700 entry = GETBIOS16(sc, ptr + i * 2); 1701 1702 conn = (entry >> 12) & 0xf; 1703 ddc = (entry >> 8) & 0xf; 1704 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1705 RADEON_DAC_PRIMARY; 1706 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1707 RADEON_TMDS_INT; 1708 1709 if (conn == RADEON_CONN_NONE) 1710 continue; /* no connector */ 1711 1712 if ((found > 0) && 1713 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1714 /* duplicate entry for same connector */ 1715 continue; 1716 } 1717 1718 /* internal DDC_DVI port gets priority */ 1719 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1720 port = 0; 1721 else 1722 port = 1; 1723 1724 sc->sc_ports[port].rp_ddc_type = 1725 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1726 sc->sc_ports[port].rp_dac_type = dac; 1727 sc->sc_ports[port].rp_conn_type = 1728 min(conn, RADEON_CONN_UNSUPPORTED) ; 1729 1730 sc->sc_ports[port].rp_tmds_type = tmds; 1731 1732 if ((conn != RADEON_CONN_DVI_I) && 1733 (conn != RADEON_CONN_DVI_D) && 1734 (tmds == RADEON_TMDS_INT)) 1735 sc->sc_ports[port].rp_tmds_type = 1736 RADEON_TMDS_UNKNOWN; 1737 sc->sc_ports[port].rp_number = i - 1; 1738 1739 found += (port + 1); 1740 } 1741 } 1742 1743 nobios: 1744 if (!found) { 1745 DPRINTF(("No connector info in BIOS!\n")); 1746 if IS_MOBILITY(sc) { 1747 /* default, port 0 = internal TMDS, port 1 = CRT */ 1748 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1749 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1750 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1751 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1752 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1753 sc->sc_ports[0].rp_number = 0; 1754 1755 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1756 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1757 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1758 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1759 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1760 sc->sc_ports[1].rp_number = 1; 1761 } else { 1762 /* default, port 0 = DVI, port 1 = CRT */ 1763 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1764 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1765 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1766 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1767 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1768 sc->sc_ports[0].rp_number = 1; 1769 1770 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1771 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1772 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1773 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1774 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1775 sc->sc_ports[1].rp_number = 0; 1776 } 1777 } 1778 1779 /* 1780 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1781 * these chips should use TVDAC for the VGA port. 1782 */ 1783 if (HAS_SDAC(sc)) { 1784 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1785 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1786 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1787 } else { 1788 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1789 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1790 } 1791 } else if (!HAS_CRTC2(sc)) { 1792 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1793 } 1794 1795 for (i = 0; i < 2; i++) { 1796 char edid[128]; 1797 uint8_t ddc; 1798 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1799 prop_data_t edid_data; 1800 1801 DPRINTF(("Port #%d:\n", i)); 1802 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1803 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1804 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1805 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1806 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1807 1808 sc->sc_ports[i].rp_edid_valid = 0; 1809 /* first look for static EDID data */ 1810 if ((edid_data = prop_dictionary_get(device_properties( 1811 sc->sc_dev), "EDID")) != NULL) { 1812 1813 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1814 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1815 if (edid_parse(edid, eip) == 0) { 1816 1817 sc->sc_ports[i].rp_edid_valid = 1; 1818 } 1819 } 1820 /* if we didn't find any we'll try to talk to the monitor */ 1821 if (sc->sc_ports[i].rp_edid_valid != 1) { 1822 1823 ddc = sc->sc_ports[i].rp_ddc_type; 1824 if (ddc != RADEON_DDC_NONE) { 1825 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1826 == 0) && (edid_parse(edid, eip) == 0)) { 1827 1828 sc->sc_ports[i].rp_edid_valid = 1; 1829 #ifdef RADEONFB_DEBUG 1830 edid_print(eip); 1831 #endif 1832 } 1833 } 1834 } 1835 } 1836 1837 return found; 1838 } 1839 1840 int 1841 radeonfb_gettmds(struct radeonfb_softc *sc) 1842 { 1843 int i; 1844 1845 if (!sc->sc_biossz) { 1846 goto nobios; 1847 } 1848 1849 if (IS_ATOM(sc)) { 1850 /* XXX: not done yet */ 1851 } else { 1852 uint16_t ptr; 1853 int n; 1854 1855 ptr = GETBIOS16(sc, 0x48); 1856 ptr = GETBIOS16(sc, ptr + 0x34); 1857 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1858 if (GETBIOS8(sc, ptr) == 3) { 1859 /* revision three table */ 1860 n = GETBIOS8(sc, ptr + 5) + 1; 1861 n = min(n, 4); 1862 1863 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1864 for (i = 0; i < n; i++) { 1865 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1866 ptr + i * 10 + 8); 1867 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1868 ptr + i * 10 + 0x10); 1869 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1870 sc->sc_tmds_pll[i].rtp_freq, 1871 sc->sc_tmds_pll[i].rtp_pll)); 1872 } 1873 return 0; 1874 } 1875 } 1876 1877 nobios: 1878 DPRINTF(("no suitable DFP table present\n")); 1879 for (i = 0; 1880 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1881 i++) { 1882 int j; 1883 1884 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1885 continue; 1886 1887 for (j = 0; j < 4; j++) { 1888 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1889 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1890 sc->sc_tmds_pll[j].rtp_freq, 1891 sc->sc_tmds_pll[j].rtp_pll)); 1892 } 1893 return 0; 1894 } 1895 1896 return -1; 1897 } 1898 1899 const struct videomode * 1900 radeonfb_modelookup(const char *name) 1901 { 1902 int i; 1903 1904 for (i = 0; i < videomode_count; i++) 1905 if (!strcmp(name, videomode_list[i].name)) 1906 return &videomode_list[i]; 1907 1908 return NULL; 1909 } 1910 1911 void 1912 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1913 { 1914 if (crtc) { 1915 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1916 RADEON_P2PLL_ATOMIC_UPDATE_R); 1917 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1918 } else { 1919 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1920 RADEON_PPLL_ATOMIC_UPDATE_R); 1921 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1922 } 1923 } 1924 1925 void 1926 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1927 { 1928 int i; 1929 1930 for (i = 10000; i; i--) { 1931 if (crtc) { 1932 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1933 RADEON_P2PLL_ATOMIC_UPDATE_R) 1934 break; 1935 } else { 1936 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1937 RADEON_PPLL_ATOMIC_UPDATE_R) 1938 break; 1939 } 1940 } 1941 } 1942 1943 void 1944 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1945 { 1946 uint32_t pbit = 0; 1947 uint32_t feed = 0; 1948 uint32_t data, refdiv, div0; 1949 1950 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1951 1952 if (crtc == 0) { 1953 1954 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1955 if (IS_R300(sc)) { 1956 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1957 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1958 } else { 1959 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1960 sc->sc_refdiv; 1961 } 1962 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1963 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1964 RADEON_PPLL_POST3_DIV_MASK); 1965 div0 |= pbit; 1966 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1967 1968 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1969 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1970 /* 1971 * nothing to do here, the PLL is already where we 1972 * want it 1973 */ 1974 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1975 ~RADEON_PLL_DIV_SEL); 1976 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1977 return; 1978 } 1979 1980 /* alright, we do need to reprogram stuff */ 1981 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1982 RADEON_VCLK_SRC_SEL_CPUCLK, 1983 ~RADEON_VCLK_SRC_SEL_MASK); 1984 1985 /* put vclk into reset, use atomic updates */ 1986 SETPLL(sc, RADEON_PPLL_CNTL, 1987 RADEON_PPLL_REFCLK_SEL | 1988 RADEON_PPLL_FBCLK_SEL | 1989 RADEON_PPLL_RESET | 1990 RADEON_PPLL_ATOMIC_UPDATE_EN | 1991 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1992 1993 /* select clock 0 */ 1994 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1995 ~RADEON_PLL_DIV_SEL); 1996 1997 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 1998 1999 /* xf86-video-radeon does this, not sure why */ 2000 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2001 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2002 2003 /* use the atomic update */ 2004 radeonfb_pllwriteupdate(sc, crtc); 2005 2006 /* and wait for it to complete */ 2007 radeonfb_pllwaitatomicread(sc, crtc); 2008 2009 /* program HTOTAL (why?) */ 2010 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2011 2012 /* drop reset */ 2013 CLRPLL(sc, RADEON_PPLL_CNTL, 2014 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2015 RADEON_PPLL_ATOMIC_UPDATE_EN | 2016 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2017 2018 PRINTPLL(RADEON_PPLL_CNTL); 2019 PRINTPLL(RADEON_PPLL_REF_DIV); 2020 PRINTPLL(RADEON_PPLL_DIV_3); 2021 2022 /* give clock time to lock */ 2023 delay(50000); 2024 2025 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2026 RADEON_VCLK_SRC_SEL_PPLLCLK, 2027 ~RADEON_VCLK_SRC_SEL_MASK); 2028 2029 } else { 2030 2031 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2032 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2033 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2034 2035 /* put vclk into reset, use atomic updates */ 2036 SETPLL(sc, RADEON_P2PLL_CNTL, 2037 RADEON_P2PLL_RESET | 2038 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2039 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2040 2041 /* program reference divider */ 2042 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2043 ~RADEON_P2PLL_REF_DIV_MASK); 2044 2045 /* program feedback and post dividers */ 2046 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2047 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2048 RADEON_P2PLL_POST0_DIV_MASK); 2049 data |= pbit; 2050 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2051 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2052 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2053 2054 PRINTPLL(RADEON_P2PLL_REF_DIV); 2055 PRINTPLL(RADEON_P2PLL_DIV_0); 2056 2057 /* use the atomic update */ 2058 radeonfb_pllwriteupdate(sc, crtc); 2059 2060 /* and wait for it to complete */ 2061 radeonfb_pllwaitatomicread(sc, crtc); 2062 2063 /* program HTOTAL (why?) */ 2064 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2065 2066 /* drop reset */ 2067 CLRPLL(sc, RADEON_P2PLL_CNTL, 2068 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2069 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2070 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2071 2072 /* allow time for clock to lock */ 2073 delay(50000); 2074 2075 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2076 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2077 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2078 } 2079 PRINTREG(RADEON_CRTC_MORE_CNTL); 2080 } 2081 2082 void 2083 radeonfb_modeswitch(struct radeonfb_display *dp) 2084 { 2085 struct radeonfb_softc *sc = dp->rd_softc; 2086 int i; 2087 2088 /* blank the display while we switch modes */ 2089 radeonfb_blank(dp, 1); 2090 2091 #if 0 2092 SET32(sc, RADEON_CRTC_EXT_CNTL, 2093 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2094 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2095 #endif 2096 2097 /* these registers might get in the way... */ 2098 PUT32(sc, RADEON_OVR_CLR, 0); 2099 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2100 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2101 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2102 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2103 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2104 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2105 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2106 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2107 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2108 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2109 2110 for (i = 0; i < dp->rd_ncrtcs; i++) 2111 radeonfb_setcrtc(dp, i); 2112 2113 /* activate the display */ 2114 radeonfb_blank(dp, 0); 2115 } 2116 2117 void 2118 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2119 { 2120 int crtc; 2121 struct videomode *mode; 2122 struct radeonfb_softc *sc; 2123 struct radeonfb_crtc *cp; 2124 uint32_t v; 2125 uint32_t gencntl; 2126 uint32_t htotaldisp; 2127 uint32_t hsyncstrt; 2128 uint32_t vtotaldisp; 2129 uint32_t vsyncstrt; 2130 uint32_t fphsyncstrt; 2131 uint32_t fpvsyncstrt; 2132 uint32_t fphtotaldisp; 2133 uint32_t fpvtotaldisp; 2134 uint32_t pitch; 2135 2136 sc = dp->rd_softc; 2137 cp = &dp->rd_crtcs[index]; 2138 crtc = cp->rc_number; 2139 mode = &cp->rc_videomode; 2140 2141 #if 1 2142 pitch = dp->rd_stride / dp->rd_bpp; 2143 #else 2144 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2145 (sc->sc_maxbpp * 8)); 2146 #endif 2147 switch (crtc) { 2148 case 0: 2149 gencntl = RADEON_CRTC_GEN_CNTL; 2150 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2151 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2152 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2153 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2154 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2155 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2156 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2157 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2158 break; 2159 case 1: 2160 gencntl = RADEON_CRTC2_GEN_CNTL; 2161 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2162 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2163 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2164 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2165 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2166 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2167 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2168 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2169 break; 2170 default: 2171 panic("Bad CRTC!"); 2172 break; 2173 } 2174 2175 /* 2176 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2177 */ 2178 /* only bother with 32bpp and 8bpp */ 2179 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2180 2181 if (crtc == 1) { 2182 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2183 } else { 2184 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2185 } 2186 2187 if (mode->flags & VID_DBLSCAN) 2188 v |= RADEON_CRTC2_DBL_SCAN_EN; 2189 2190 if (mode->flags & VID_INTERLACE) 2191 v |= RADEON_CRTC2_INTERLACE_EN; 2192 2193 if (mode->flags & VID_CSYNC) { 2194 v |= RADEON_CRTC2_CSYNC_EN; 2195 if (crtc == 1) 2196 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2197 } 2198 2199 PUT32(sc, gencntl, v); 2200 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2201 2202 /* 2203 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2204 */ 2205 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2206 if (crtc == 0) { 2207 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2208 RADEON_CRTC_DISPLAY_DIS); 2209 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2210 if (mode->flags & VID_CSYNC) 2211 v |= RADEON_CRTC_VSYNC_TRISTAT; 2212 } 2213 /* unconditional turn on CRT, in case first CRTC is DFP */ 2214 v |= RADEON_CRTC_CRT_ON; 2215 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2216 PRINTREG(RADEON_CRTC_EXT_CNTL); 2217 2218 /* 2219 * H_TOTAL_DISP 2220 */ 2221 v = ((mode->hdisplay / 8) - 1) << 16; 2222 v |= (mode->htotal / 8) - 1; 2223 PUT32(sc, htotaldisp, v); 2224 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2225 PUT32(sc, fphtotaldisp, v); 2226 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2227 2228 /* 2229 * H_SYNC_STRT_WID 2230 */ 2231 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2232 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2233 if (mode->flags & VID_NHSYNC) 2234 v |= RADEON_CRTC_H_SYNC_POL; 2235 PUT32(sc, hsyncstrt, v); 2236 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2237 PUT32(sc, fphsyncstrt, v); 2238 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2239 2240 /* 2241 * V_TOTAL_DISP 2242 */ 2243 v = ((mode->vdisplay - 1) << 16); 2244 v |= (mode->vtotal - 1); 2245 PUT32(sc, vtotaldisp, v); 2246 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2247 PUT32(sc, fpvtotaldisp, v); 2248 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2249 2250 /* 2251 * V_SYNC_STRT_WID 2252 */ 2253 v = ((mode->vsync_end - mode->vsync_start) << 16); 2254 v |= (mode->vsync_start - 1); 2255 if (mode->flags & VID_NVSYNC) 2256 v |= RADEON_CRTC_V_SYNC_POL; 2257 PUT32(sc, vsyncstrt, v); 2258 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2259 PUT32(sc, fpvsyncstrt, v); 2260 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2261 2262 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2263 2264 switch (crtc) { 2265 case 0: 2266 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2267 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2268 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2269 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2270 2271 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2272 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2273 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2274 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2275 PRINTREG(RADEON_CRTC_EXT_CNTL); 2276 PRINTREG(RADEON_CRTC_GEN_CNTL); 2277 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2278 break; 2279 2280 case 1: 2281 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2282 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2283 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2284 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2285 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2286 RADEON_CRTC2_VSYNC_DIS | 2287 RADEON_CRTC2_HSYNC_DIS | 2288 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2289 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2290 break; 2291 } 2292 } 2293 2294 int 2295 radeonfb_isblank(struct radeonfb_display *dp) 2296 { 2297 uint32_t reg, mask; 2298 2299 if(!dp->rd_softc->sc_mapped) 2300 return 1; 2301 2302 if (dp->rd_crtcs[0].rc_number) { 2303 reg = RADEON_CRTC2_GEN_CNTL; 2304 mask = RADEON_CRTC2_DISP_DIS; 2305 } else { 2306 reg = RADEON_CRTC_EXT_CNTL; 2307 mask = RADEON_CRTC_DISPLAY_DIS; 2308 } 2309 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2310 } 2311 2312 void 2313 radeonfb_blank(struct radeonfb_display *dp, int blank) 2314 { 2315 struct radeonfb_softc *sc = dp->rd_softc; 2316 uint32_t reg, mask; 2317 uint32_t fpreg, fpval; 2318 int i; 2319 2320 if (!sc->sc_mapped) 2321 return; 2322 2323 for (i = 0; i < dp->rd_ncrtcs; i++) { 2324 2325 if (dp->rd_crtcs[i].rc_number) { 2326 reg = RADEON_CRTC2_GEN_CNTL; 2327 mask = RADEON_CRTC2_DISP_DIS; 2328 fpreg = RADEON_FP2_GEN_CNTL; 2329 fpval = RADEON_FP2_ON; 2330 } else { 2331 reg = RADEON_CRTC_EXT_CNTL; 2332 mask = RADEON_CRTC_DISPLAY_DIS; 2333 fpreg = RADEON_FP_GEN_CNTL; 2334 fpval = RADEON_FP_FPON; 2335 } 2336 2337 if (blank) { 2338 SET32(sc, reg, mask); 2339 CLR32(sc, fpreg, fpval); 2340 } else { 2341 CLR32(sc, reg, mask); 2342 SET32(sc, fpreg, fpval); 2343 } 2344 } 2345 PRINTREG(RADEON_FP_GEN_CNTL); 2346 PRINTREG(RADEON_FP2_GEN_CNTL); 2347 } 2348 2349 void 2350 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2351 long *defattr) 2352 { 2353 struct radeonfb_display *dp = cookie; 2354 struct rasops_info *ri = &scr->scr_ri; 2355 2356 /* initialize font subsystem */ 2357 wsfont_init(); 2358 2359 DPRINTF(("init screen called, existing %d\n", existing)); 2360 2361 ri->ri_depth = dp->rd_bpp; 2362 ri->ri_width = dp->rd_virtx; 2363 ri->ri_height = dp->rd_virty; 2364 ri->ri_stride = dp->rd_stride; 2365 ri->ri_flg = RI_CENTER; 2366 switch (ri->ri_depth) { 2367 case 8: 2368 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2369 break; 2370 case 32: 2371 ri->ri_flg |= RI_ENABLE_ALPHA; 2372 /* we run radeons in RGB even on SPARC hardware */ 2373 ri->ri_rnum = 8; 2374 ri->ri_gnum = 8; 2375 ri->ri_bnum = 8; 2376 ri->ri_rpos = 16; 2377 ri->ri_gpos = 8; 2378 ri->ri_bpos = 0; 2379 break; 2380 } 2381 2382 ri->ri_bits = (void *)dp->rd_fbptr; 2383 2384 #ifdef VCONS_DRAW_INTR 2385 scr->scr_flags |= VCONS_DONT_READ; 2386 #endif 2387 2388 if (existing) { 2389 ri->ri_flg |= RI_CLEAR; 2390 2391 /* start a modeswitch now */ 2392 radeonfb_modeswitch(dp); 2393 } 2394 2395 /* 2396 * XXX: font selection should be based on properties, with some 2397 * normal/reasonable default. 2398 */ 2399 2400 /* initialize and look for an initial font */ 2401 rasops_init(ri, 0, 0); 2402 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2403 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2404 2405 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2406 dp->rd_virtx / ri->ri_font->fontwidth); 2407 2408 /* enable acceleration */ 2409 dp->rd_putchar = ri->ri_ops.putchar; 2410 ri->ri_ops.copyrows = radeonfb_copyrows; 2411 ri->ri_ops.copycols = radeonfb_copycols; 2412 ri->ri_ops.eraserows = radeonfb_eraserows; 2413 ri->ri_ops.erasecols = radeonfb_erasecols; 2414 /* pick a putchar method based on font and Radeon model */ 2415 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2416 /* got a bitmap font */ 2417 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2418 if (IS_R300(dp->rd_softc)) { 2419 /* 2420 * radeonfb_putchar() doesn't work right on some R3xx 2421 * so we use software drawing here, the wrapper just 2422 * makes sure the engine is idle before scribbling 2423 * into vram 2424 */ 2425 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2426 } else 2427 #endif 2428 ri->ri_ops.putchar = radeonfb_putchar; 2429 } else { 2430 /* got an alpha font */ 2431 switch(ri->ri_depth) { 2432 case 32: 2433 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2434 break; 2435 case 8: 2436 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2437 break; 2438 default: 2439 /* XXX this should never happen */ 2440 panic("%s: depth is not 8 or 32 but we got an" \ 2441 " alpha font?!", __func__); 2442 } 2443 } 2444 ri->ri_ops.cursor = radeonfb_cursor; 2445 } 2446 2447 void 2448 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2449 { 2450 uint32_t gen, ext, gen2 = 0; 2451 uint32_t agploc, aperbase, apersize, mcfbloc; 2452 2453 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2454 /* XXX */ 2455 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2456 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2457 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2458 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2459 2460 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2461 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2462 #if 0 2463 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2464 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2465 #endif 2466 2467 if (HAS_CRTC2(sc)) { 2468 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2469 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2470 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2471 } 2472 2473 delay(100000); 2474 2475 mcfbloc = (aperbase >> 16) | 2476 ((aperbase + (apersize - 1)) & 0xffff0000); 2477 2478 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2479 sc->sc_memsz = apersize; 2480 2481 if (((agploc & 0xffff) << 16) != 2482 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2483 agploc = mcfbloc & 0xffff0000U; 2484 agploc |= ((agploc + 0x10000) >> 16); 2485 } 2486 2487 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2488 2489 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2490 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2491 2492 DPRINTF(("aperbase = %u\n", aperbase)); 2493 PRINTREG(RADEON_MC_FB_LOCATION); 2494 PRINTREG(RADEON_MC_AGP_LOCATION); 2495 2496 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2497 2498 if (HAS_CRTC2(sc)) 2499 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2500 2501 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2502 2503 #if 0 2504 /* XXX: what is this AGP garbage? :-) */ 2505 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2506 #endif 2507 2508 delay(100000); 2509 2510 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2511 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2512 2513 if (HAS_CRTC2(sc)) 2514 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2515 } 2516 2517 void 2518 radeonfb_init_misc(struct radeonfb_softc *sc) 2519 { 2520 PUT32(sc, RADEON_BUS_CNTL, 2521 RADEON_BUS_MASTER_DIS | 2522 RADEON_BUS_PREFETCH_MODE_ACT | 2523 RADEON_BUS_PCI_READ_RETRY_EN | 2524 RADEON_BUS_PCI_WRT_RETRY_EN | 2525 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2526 RADEON_BUS_MSTR_RD_MULT | 2527 RADEON_BUS_MSTR_RD_LINE | 2528 RADEON_BUS_RD_DISCARD_EN | 2529 RADEON_BUS_MSTR_DISCONNECT_EN | 2530 RADEON_BUS_READ_BURST); 2531 2532 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2533 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2534 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2535 PUT32(sc, RADEON_RBBM_CNTL, 2536 (3 << RADEON_RB_SETTLE_SHIFT) | 2537 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2538 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2539 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2540 2541 /* XXX: figure out what these mean! */ 2542 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2543 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2544 #if 0 2545 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2546 #endif 2547 2548 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2549 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2550 } 2551 2552 /* 2553 * This loads a linear color map for true color. 2554 */ 2555 void 2556 radeonfb_init_palette(struct radeonfb_display *dp) 2557 { 2558 struct radeonfb_softc *sc = dp->rd_softc; 2559 int i, cc; 2560 uint32_t vclk; 2561 int crtc; 2562 2563 #define DAC_WIDTH ((1 << 10) - 1) 2564 #define CLUT_WIDTH ((1 << 8) - 1) 2565 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2566 2567 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2568 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2569 2570 /* initialize the palette for every CRTC used by this display */ 2571 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2572 crtc = dp->rd_crtcs[cc].rc_number; 2573 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2574 2575 if (crtc) 2576 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2577 else 2578 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2579 2580 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2581 2582 if (dp->rd_bpp == 8) { 2583 2584 /* R3G3B2 palette */ 2585 int j = 0; 2586 uint32_t tmp, r, g, b; 2587 2588 for (i = 0; i <= CLUT_WIDTH; ++i) { 2589 tmp = i & 0xe0; 2590 /* 2591 * replicate bits so 0xe0 maps to a red value of 0xff 2592 * in order to make white look actually white 2593 */ 2594 tmp |= (tmp >> 3) | (tmp >> 6); 2595 r = tmp; 2596 2597 tmp = (i & 0x1c) << 3; 2598 tmp |= (tmp >> 3) | (tmp >> 6); 2599 g = tmp; 2600 2601 tmp = (i & 0x03) << 6; 2602 tmp |= tmp >> 2; 2603 tmp |= tmp >> 4; 2604 b = tmp; 2605 2606 PUT32(sc, RADEON_PALETTE_30_DATA, 2607 (r << 22) | 2608 (g << 12) | 2609 (b << 2)); 2610 j += 3; 2611 } 2612 } else { 2613 /* linear ramp */ 2614 for (i = 0; i <= CLUT_WIDTH; ++i) { 2615 PUT32(sc, RADEON_PALETTE_30_DATA, 2616 (CLUT_COLOR(i) << 10) | 2617 (CLUT_COLOR(i) << 20) | 2618 (CLUT_COLOR(i))); 2619 } 2620 } 2621 } 2622 2623 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2624 PRINTREG(RADEON_DAC_CNTL2); 2625 2626 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2627 } 2628 2629 /* 2630 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2631 */ 2632 void 2633 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2634 { 2635 uint32_t tmp, save; 2636 2637 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2638 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2639 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2640 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2641 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2642 } 2643 2644 /* 2645 * Acceleration entry points. 2646 */ 2647 2648 /* this one draws characters using bitmap fonts */ 2649 static void 2650 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2651 { 2652 struct rasops_info *ri = cookie; 2653 struct vcons_screen *scr = ri->ri_hw; 2654 struct radeonfb_display *dp = scr->scr_cookie; 2655 struct radeonfb_softc *sc = dp->rd_softc; 2656 struct wsdisplay_font *font = PICK_FONT(ri, c); 2657 uint32_t w, h; 2658 int xd, yd, offset, i; 2659 uint32_t bg, fg, gmc; 2660 uint32_t reg; 2661 uint8_t *data8; 2662 uint16_t *data16; 2663 void *data; 2664 2665 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2666 return; 2667 2668 if (!CHAR_IN_FONT(c, font)) 2669 return; 2670 2671 w = font->fontwidth; 2672 h = font->fontheight; 2673 2674 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2675 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2676 2677 xd = ri->ri_xorigin + col * w; 2678 yd = ri->ri_yorigin + row * h; 2679 2680 if (c == 0x20) { 2681 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2682 return; 2683 } 2684 data = WSFONT_GLYPH(c, font); 2685 2686 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2687 2688 radeonfb_wait_fifo(sc, 9); 2689 2690 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2691 RADEON_GMC_BRUSH_NONE | 2692 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2693 RADEON_GMC_DST_CLIPPING | 2694 RADEON_ROP3_S | 2695 RADEON_DP_SRC_SOURCE_HOST_DATA | 2696 RADEON_GMC_CLR_CMP_CNTL_DIS | 2697 RADEON_GMC_WR_MSK_DIS | 2698 gmc); 2699 2700 PUT32(sc, RADEON_SC_LEFT, xd); 2701 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2702 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2703 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2704 PUT32(sc, RADEON_DP_CNTL, 2705 RADEON_DST_X_LEFT_TO_RIGHT | 2706 RADEON_DST_Y_TOP_TO_BOTTOM); 2707 2708 PUT32(sc, RADEON_SRC_X_Y, 0); 2709 offset = 32 - (font->stride << 3); 2710 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2711 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2712 2713 radeonfb_wait_fifo(sc, h); 2714 switch (font->stride) { 2715 case 1: { 2716 data8 = data; 2717 for (i = 0; i < h; i++) { 2718 reg = *data8; 2719 #if BYTE_ORDER == LITTLE_ENDIAN 2720 reg = reg << 24; 2721 #endif 2722 bus_space_write_stream_4(sc->sc_regt, 2723 sc->sc_regh, RADEON_HOST_DATA0, reg); 2724 data8++; 2725 } 2726 break; 2727 } 2728 case 2: { 2729 data16 = data; 2730 for (i = 0; i < h; i++) { 2731 reg = *data16; 2732 #if BYTE_ORDER == LITTLE_ENDIAN 2733 reg = reg << 16; 2734 #endif 2735 bus_space_write_stream_4(sc->sc_regt, 2736 sc->sc_regh, RADEON_HOST_DATA0, reg); 2737 data16++; 2738 } 2739 break; 2740 } 2741 } 2742 if (attr & 1) 2743 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2744 } 2745 2746 /* ... while this one is for anti-aliased ones */ 2747 static void 2748 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2749 { 2750 struct rasops_info *ri = cookie; 2751 struct vcons_screen *scr = ri->ri_hw; 2752 struct radeonfb_display *dp = scr->scr_cookie; 2753 struct radeonfb_softc *sc = dp->rd_softc; 2754 struct wsdisplay_font *font = PICK_FONT(ri, c); 2755 uint32_t bg, fg, gmc; 2756 uint8_t *data; 2757 int w, h, xd, yd; 2758 int i, r, g, b, aval; 2759 int rf, gf, bf, rb, gb, bb; 2760 uint32_t pixel; 2761 int rv; 2762 2763 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2764 return; 2765 2766 if (!CHAR_IN_FONT(c, font)) 2767 return; 2768 2769 w = font->fontwidth; 2770 h = font->fontheight; 2771 2772 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2773 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2774 2775 xd = ri->ri_xorigin + col * w; 2776 yd = ri->ri_yorigin + row * h; 2777 2778 if (c == 0x20) { 2779 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2780 if (attr & 1) 2781 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2782 return; 2783 } 2784 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2785 if (rv == GC_OK) 2786 return; 2787 2788 data = WSFONT_GLYPH(c, font); 2789 2790 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2791 2792 radeonfb_wait_fifo(sc, 5); 2793 2794 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2795 RADEON_GMC_BRUSH_NONE | 2796 RADEON_GMC_SRC_DATATYPE_COLOR | 2797 RADEON_ROP3_S | 2798 RADEON_DP_SRC_SOURCE_HOST_DATA | 2799 RADEON_GMC_CLR_CMP_CNTL_DIS | 2800 RADEON_GMC_WR_MSK_DIS | 2801 gmc); 2802 2803 PUT32(sc, RADEON_DP_CNTL, 2804 RADEON_DST_X_LEFT_TO_RIGHT | 2805 RADEON_DST_Y_TOP_TO_BOTTOM); 2806 2807 PUT32(sc, RADEON_SRC_X_Y, 0); 2808 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2809 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2810 2811 rf = (fg >> 16) & 0xff; 2812 rb = (bg >> 16) & 0xff; 2813 gf = (fg >> 8) & 0xff; 2814 gb = (bg >> 8) & 0xff; 2815 bf = fg & 0xff; 2816 bb = bg & 0xff; 2817 2818 /* 2819 * I doubt we can upload data faster than even the slowest Radeon 2820 * could process them, especially when doing the alpha blending stuff 2821 * along the way, so just make sure there's some room in the FIFO and 2822 * then hammer away 2823 * As it turns out we can, so make periodic stops to let the FIFO 2824 * drain. 2825 */ 2826 radeonfb_wait_fifo(sc, 20); 2827 for (i = 0; i < ri->ri_fontscale; i++) { 2828 aval = *data; 2829 data++; 2830 if (aval == 0) { 2831 pixel = bg; 2832 } else if (aval == 255) { 2833 pixel = fg; 2834 } else { 2835 r = aval * rf + (255 - aval) * rb; 2836 g = aval * gf + (255 - aval) * gb; 2837 b = aval * bf + (255 - aval) * bb; 2838 pixel = (r & 0xff00) << 8 | 2839 (g & 0xff00) | 2840 (b & 0xff00) >> 8; 2841 } 2842 if (i & 16) 2843 radeonfb_wait_fifo(sc, 20); 2844 PUT32(sc, RADEON_HOST_DATA0, pixel); 2845 } 2846 if (rv == GC_ADD) { 2847 glyphcache_add(&dp->rd_gc, c, xd, yd); 2848 } else 2849 if (attr & 1) 2850 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2851 2852 } 2853 2854 static void 2855 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2856 { 2857 struct rasops_info *ri = cookie; 2858 struct vcons_screen *scr = ri->ri_hw; 2859 struct radeonfb_display *dp = scr->scr_cookie; 2860 struct radeonfb_softc *sc = dp->rd_softc; 2861 struct wsdisplay_font *font = PICK_FONT(ri, c); 2862 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2863 int i, x, y, wi, he, r, g, b, aval; 2864 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2865 uint8_t *data8; 2866 int rv, cnt; 2867 2868 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2869 return; 2870 2871 if (!CHAR_IN_FONT(c, font)) 2872 return; 2873 2874 wi = font->fontwidth; 2875 he = font->fontheight; 2876 2877 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2878 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2879 2880 x = ri->ri_xorigin + col * wi; 2881 y = ri->ri_yorigin + row * he; 2882 2883 if (c == 0x20) { 2884 radeonfb_rectfill(dp, x, y, wi, he, bg); 2885 if (attr & 1) 2886 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2887 return; 2888 } 2889 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2890 if (rv == GC_OK) 2891 return; 2892 2893 data8 = WSFONT_GLYPH(c, font); 2894 2895 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2896 2897 radeonfb_wait_fifo(sc, 5); 2898 2899 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2900 RADEON_GMC_BRUSH_NONE | 2901 RADEON_GMC_SRC_DATATYPE_COLOR | 2902 RADEON_ROP3_S | 2903 RADEON_DP_SRC_SOURCE_HOST_DATA | 2904 RADEON_GMC_CLR_CMP_CNTL_DIS | 2905 RADEON_GMC_WR_MSK_DIS | 2906 gmc); 2907 2908 PUT32(sc, RADEON_DP_CNTL, 2909 RADEON_DST_X_LEFT_TO_RIGHT | 2910 RADEON_DST_Y_TOP_TO_BOTTOM); 2911 2912 PUT32(sc, RADEON_SRC_X_Y, 0); 2913 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2914 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2915 2916 /* 2917 * we need the RGB colours here, so get offsets into rasops_cmap 2918 */ 2919 fgo = ((attr >> 24) & 0xf) * 3; 2920 bgo = ((attr >> 16) & 0xf) * 3; 2921 2922 r0 = rasops_cmap[bgo]; 2923 r1 = rasops_cmap[fgo]; 2924 g0 = rasops_cmap[bgo + 1]; 2925 g1 = rasops_cmap[fgo + 1]; 2926 b0 = rasops_cmap[bgo + 2]; 2927 b1 = rasops_cmap[fgo + 2]; 2928 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 2929 bg8 = R3G3B2(r0, g0, b0); 2930 fg8 = R3G3B2(r1, g1, b1); 2931 2932 radeonfb_wait_fifo(sc, 20); 2933 cnt = 0; 2934 for (i = 0; i < ri->ri_fontscale; i++) { 2935 aval = *data8; 2936 if (aval == 0) { 2937 pixel = bg8; 2938 } else if (aval == 255) { 2939 pixel = fg8; 2940 } else { 2941 r = aval * r1 + (255 - aval) * r0; 2942 g = aval * g1 + (255 - aval) * g0; 2943 b = aval * b1 + (255 - aval) * b0; 2944 pixel = ((r & 0xe000) >> 8) | 2945 ((g & 0xe000) >> 11) | 2946 ((b & 0xc000) >> 14); 2947 } 2948 latch |= pixel << (8 * (i & 3)); 2949 /* write in 32bit chunks */ 2950 if ((i & 3) == 3) { 2951 PUT32(sc, RADEON_HOST_DATA0, latch); 2952 /* 2953 * not strictly necessary, old data should be shifted 2954 * out 2955 */ 2956 latch = 0; 2957 cnt++; 2958 if (cnt > 16) { 2959 cnt = 0; 2960 radeonfb_wait_fifo(sc, 20); 2961 } 2962 } 2963 data8++; 2964 } 2965 /* if we have pixels left in latch write them out */ 2966 if ((i & 3) != 0) { 2967 /* 2968 * radeon is weird - apparently leftover pixels are written 2969 * from the middle, not from the left as everything else 2970 */ 2971 PUT32(sc, RADEON_HOST_DATA0, latch); 2972 } 2973 2974 if (rv == GC_ADD) { 2975 glyphcache_add(&dp->rd_gc, c, x, y); 2976 } else 2977 if (attr & 1) 2978 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2979 2980 } 2981 2982 /* 2983 * wrapper for software character drawing 2984 * just sync the engine and call rasops*_putchar() 2985 */ 2986 2987 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2988 static void 2989 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 2990 { 2991 struct rasops_info *ri = cookie; 2992 struct vcons_screen *scr = ri->ri_hw; 2993 struct radeonfb_display *dp = scr->scr_cookie; 2994 2995 radeonfb_engine_idle(dp->rd_softc); 2996 dp->rd_putchar(ri, row, col, c, attr); 2997 } 2998 #endif 2999 3000 static void 3001 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3002 { 3003 struct rasops_info *ri = cookie; 3004 struct vcons_screen *scr = ri->ri_hw; 3005 struct radeonfb_display *dp = scr->scr_cookie; 3006 uint32_t x, y, w, h, fg, bg, ul; 3007 3008 /* XXX: check for full emulation mode? */ 3009 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3010 x = ri->ri_xorigin; 3011 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3012 w = ri->ri_emuwidth; 3013 h = ri->ri_font->fontheight * nrows; 3014 3015 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3016 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3017 } 3018 } 3019 3020 static void 3021 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3022 { 3023 struct rasops_info *ri = cookie; 3024 struct vcons_screen *scr = ri->ri_hw; 3025 struct radeonfb_display *dp = scr->scr_cookie; 3026 uint32_t x, ys, yd, w, h; 3027 3028 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3029 x = ri->ri_xorigin; 3030 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3031 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3032 w = ri->ri_emuwidth; 3033 h = ri->ri_font->fontheight * nrows; 3034 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3035 RADEON_ROP3_S); 3036 } 3037 } 3038 3039 static void 3040 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3041 { 3042 struct rasops_info *ri = cookie; 3043 struct vcons_screen *scr = ri->ri_hw; 3044 struct radeonfb_display *dp = scr->scr_cookie; 3045 uint32_t xs, xd, y, w, h; 3046 3047 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3048 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3049 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3050 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3051 w = ri->ri_font->fontwidth * ncols; 3052 h = ri->ri_font->fontheight; 3053 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3054 RADEON_ROP3_S); 3055 } 3056 } 3057 3058 static void 3059 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3060 long fillattr) 3061 { 3062 struct rasops_info *ri = cookie; 3063 struct vcons_screen *scr = ri->ri_hw; 3064 struct radeonfb_display *dp = scr->scr_cookie; 3065 uint32_t x, y, w, h, fg, bg, ul; 3066 3067 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3068 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3069 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3070 w = ri->ri_font->fontwidth * ncols; 3071 h = ri->ri_font->fontheight; 3072 3073 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3074 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3075 } 3076 } 3077 3078 static void 3079 radeonfb_cursor(void *cookie, int on, int row, int col) 3080 { 3081 struct rasops_info *ri = cookie; 3082 struct vcons_screen *scr = ri->ri_hw; 3083 struct radeonfb_display *dp = scr->scr_cookie; 3084 int x, y, wi, he; 3085 3086 wi = ri->ri_font->fontwidth; 3087 he = ri->ri_font->fontheight; 3088 3089 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3090 x = ri->ri_ccol * wi + ri->ri_xorigin; 3091 y = ri->ri_crow * he + ri->ri_yorigin; 3092 /* first turn off the old cursor */ 3093 if (ri->ri_flg & RI_CURSOR) { 3094 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3095 RADEON_ROP3_Dn); 3096 ri->ri_flg &= ~RI_CURSOR; 3097 } 3098 ri->ri_crow = row; 3099 ri->ri_ccol = col; 3100 /* then (possibly) turn on the new one */ 3101 if (on) { 3102 x = ri->ri_ccol * wi + ri->ri_xorigin; 3103 y = ri->ri_crow * he + ri->ri_yorigin; 3104 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3105 RADEON_ROP3_Dn); 3106 ri->ri_flg |= RI_CURSOR; 3107 } 3108 } else { 3109 scr->scr_ri.ri_crow = row; 3110 scr->scr_ri.ri_ccol = col; 3111 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3112 } 3113 } 3114 3115 /* 3116 * Underlying acceleration support. 3117 */ 3118 3119 static void 3120 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3121 int width, int height, uint32_t color) 3122 { 3123 struct radeonfb_softc *sc = dp->rd_softc; 3124 uint32_t gmc; 3125 3126 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3127 3128 radeonfb_wait_fifo(sc, 6); 3129 3130 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3131 RADEON_GMC_BRUSH_SOLID_COLOR | 3132 RADEON_GMC_SRC_DATATYPE_COLOR | 3133 RADEON_GMC_CLR_CMP_CNTL_DIS | 3134 RADEON_ROP3_P | gmc); 3135 3136 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3137 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3138 PUT32(sc, RADEON_DP_CNTL, 3139 RADEON_DST_X_LEFT_TO_RIGHT | 3140 RADEON_DST_Y_TOP_TO_BOTTOM); 3141 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3142 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3143 3144 } 3145 3146 static void 3147 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3148 int width, int height, long attr) 3149 { 3150 struct radeonfb_display *dp = cookie; 3151 3152 radeonfb_rectfill(dp, dstx, dsty, width, height, 3153 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3154 } 3155 3156 static void 3157 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3158 int dstx, int dsty, int width, int height, int rop) 3159 { 3160 struct radeonfb_display *dp = cookie; 3161 struct radeonfb_softc *sc = dp->rd_softc; 3162 uint32_t gmc; 3163 uint32_t dir; 3164 3165 if (dsty < srcy) { 3166 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3167 } else { 3168 srcy += height - 1; 3169 dsty += height - 1; 3170 dir = 0; 3171 } 3172 if (dstx < srcx) { 3173 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3174 } else { 3175 srcx += width - 1; 3176 dstx += width - 1; 3177 } 3178 3179 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3180 3181 radeonfb_wait_fifo(sc, 6); 3182 3183 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3184 RADEON_GMC_BRUSH_SOLID_COLOR | 3185 RADEON_GMC_SRC_DATATYPE_COLOR | 3186 RADEON_GMC_CLR_CMP_CNTL_DIS | 3187 RADEON_DP_SRC_SOURCE_MEMORY | 3188 rop | gmc); 3189 3190 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3191 PUT32(sc, RADEON_DP_CNTL, dir); 3192 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3193 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3194 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3195 } 3196 3197 static void 3198 radeonfb_engine_idle(struct radeonfb_softc *sc) 3199 { 3200 3201 radeonfb_wait_fifo(sc, 64); 3202 while ((GET32(sc, RADEON_RBBM_STATUS) & 3203 RADEON_RBBM_ACTIVE) != 0); 3204 radeonfb_engine_flush(sc); 3205 } 3206 3207 static inline void 3208 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3209 { 3210 int i; 3211 3212 for (i = RADEON_TIMEOUT; i; i--) { 3213 if ((GET32(sc, RADEON_RBBM_STATUS) & 3214 RADEON_RBBM_FIFOCNT_MASK) >= n) 3215 return; 3216 } 3217 #ifdef DIAGNOSTIC 3218 if (!i) 3219 printf("%s: timed out waiting for fifo (%x)\n", 3220 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3221 #endif 3222 } 3223 3224 static void 3225 radeonfb_engine_flush(struct radeonfb_softc *sc) 3226 { 3227 int i = 0; 3228 3229 if (IS_R300(sc)) { 3230 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3231 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3232 i++; 3233 } 3234 } else { 3235 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3236 RADEON_RB2D_DC_FLUSH_ALL); 3237 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3238 RADEON_RB2D_DC_BUSY) { 3239 i++; 3240 } 3241 } 3242 #ifdef DIAGNOSTIC 3243 if (i > RADEON_TIMEOUT) 3244 printf("%s: engine flush timed out!\n", XNAME(sc)); 3245 #endif 3246 } 3247 3248 static inline void 3249 radeonfb_unclip(struct radeonfb_softc *sc) 3250 { 3251 3252 radeonfb_wait_fifo(sc, 2); 3253 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3254 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3255 } 3256 3257 static void 3258 radeonfb_engine_init(struct radeonfb_display *dp) 3259 { 3260 struct radeonfb_softc *sc = dp->rd_softc; 3261 uint32_t pitch; 3262 3263 /* no 3D */ 3264 PUT32(sc, RADEON_RB3D_CNTL, 0); 3265 3266 radeonfb_engine_reset(sc); 3267 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3268 3269 radeonfb_wait_fifo(sc, 1); 3270 if (!IS_R300(sc)) 3271 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3272 3273 radeonfb_wait_fifo(sc, 3); 3274 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3275 (pitch << 22) | (sc->sc_aperbase >> 10)); 3276 3277 3278 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3279 (pitch << 22) | (sc->sc_aperbase >> 10)); 3280 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3281 (pitch << 22) | (sc->sc_aperbase >> 10)); 3282 3283 (void)GET32(sc, RADEON_DP_DATATYPE); 3284 3285 /* default scissors -- no clipping */ 3286 radeonfb_wait_fifo(sc, 1); 3287 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3288 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3289 3290 radeonfb_wait_fifo(sc, 1); 3291 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3292 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3293 RADEON_GMC_CLR_CMP_CNTL_DIS | 3294 RADEON_GMC_BRUSH_SOLID_COLOR | 3295 RADEON_GMC_SRC_DATATYPE_COLOR); 3296 3297 radeonfb_wait_fifo(sc, 10); 3298 PUT32(sc, RADEON_DST_LINE_START, 0); 3299 PUT32(sc, RADEON_DST_LINE_END, 0); 3300 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3301 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3302 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3303 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3304 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3305 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3306 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3307 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3308 radeonfb_engine_idle(sc); 3309 } 3310 3311 static void 3312 radeonfb_engine_reset(struct radeonfb_softc *sc) 3313 { 3314 uint32_t hpc, rbbm, mclkcntl, clkindex; 3315 3316 radeonfb_engine_flush(sc); 3317 3318 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3319 if (HAS_R300CG(sc)) 3320 radeonfb_r300cg_workaround(sc); 3321 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3322 3323 /* 3324 * According to comments in XFree code, resetting the HDP via 3325 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3326 * So we use HOST_PATH_CNTL instead. 3327 */ 3328 3329 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3330 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3331 if (IS_R300(sc)) { 3332 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3333 RADEON_SOFT_RESET_CP | 3334 RADEON_SOFT_RESET_HI | 3335 RADEON_SOFT_RESET_E2); 3336 GET32(sc, RADEON_RBBM_SOFT_RESET); 3337 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3338 /* 3339 * XXX: this bit is not defined in any ATI docs I have, 3340 * nor in the XFree code, but XFree does it. Why? 3341 */ 3342 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3343 } else { 3344 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3345 RADEON_SOFT_RESET_CP | 3346 RADEON_SOFT_RESET_SE | 3347 RADEON_SOFT_RESET_RE | 3348 RADEON_SOFT_RESET_PP | 3349 RADEON_SOFT_RESET_E2 | 3350 RADEON_SOFT_RESET_RB); 3351 GET32(sc, RADEON_RBBM_SOFT_RESET); 3352 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3353 ~(RADEON_SOFT_RESET_CP | 3354 RADEON_SOFT_RESET_SE | 3355 RADEON_SOFT_RESET_RE | 3356 RADEON_SOFT_RESET_PP | 3357 RADEON_SOFT_RESET_E2 | 3358 RADEON_SOFT_RESET_RB)); 3359 GET32(sc, RADEON_RBBM_SOFT_RESET); 3360 } 3361 3362 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3363 GET32(sc, RADEON_HOST_PATH_CNTL); 3364 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3365 3366 if (IS_R300(sc)) 3367 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3368 3369 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3370 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3371 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3372 3373 if (HAS_R300CG(sc)) 3374 radeonfb_r300cg_workaround(sc); 3375 } 3376 3377 static int 3378 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3379 { 3380 int x, y; 3381 3382 x = pos->x; 3383 y = pos->y; 3384 3385 /* 3386 * This doesn't let a cursor move off the screen. I'm not 3387 * sure if this will have negative effects for e.g. Xinerama. 3388 * I'd guess Xinerama handles it by changing the cursor shape, 3389 * but that needs verification. 3390 */ 3391 if (x >= dp->rd_virtx) 3392 x = dp->rd_virtx - 1; 3393 if (x < 0) 3394 x = 0; 3395 if (y >= dp->rd_virty) 3396 y = dp->rd_virty - 1; 3397 if (y < 0) 3398 y = 0; 3399 3400 dp->rd_cursor.rc_pos.x = x; 3401 dp->rd_cursor.rc_pos.y = y; 3402 3403 radeonfb_cursor_position(dp); 3404 return 0; 3405 } 3406 3407 static int 3408 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3409 { 3410 unsigned flags; 3411 3412 uint8_t r[2], g[2], b[2]; 3413 unsigned index, count; 3414 int i, err; 3415 int pitch, size; 3416 struct radeonfb_cursor nc; 3417 3418 flags = wc->which; 3419 3420 /* copy old values */ 3421 nc = dp->rd_cursor; 3422 3423 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3424 index = wc->cmap.index; 3425 count = wc->cmap.count; 3426 3427 if (index >= 2 || (index + count) > 2) 3428 return EINVAL; 3429 3430 err = copyin(wc->cmap.red, &r[index], count); 3431 if (err) 3432 return err; 3433 err = copyin(wc->cmap.green, &g[index], count); 3434 if (err) 3435 return err; 3436 err = copyin(wc->cmap.blue, &b[index], count); 3437 if (err) 3438 return err; 3439 3440 for (i = index; i < index + count; i++) { 3441 nc.rc_cmap[i] = 3442 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3443 } 3444 } 3445 3446 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3447 if ((wc->size.x > RADEON_CURSORMAXX) || 3448 (wc->size.y > RADEON_CURSORMAXY)) 3449 return EINVAL; 3450 3451 /* figure bytes per line */ 3452 pitch = (wc->size.x + 7) / 8; 3453 size = pitch * wc->size.y; 3454 3455 /* clear the old cursor and mask */ 3456 memset(nc.rc_image, 0, 512); 3457 memset(nc.rc_mask, 0, 512); 3458 3459 nc.rc_size = wc->size; 3460 3461 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3462 return err; 3463 3464 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3465 return err; 3466 } 3467 3468 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3469 nc.rc_hot = wc->hot; 3470 if (nc.rc_hot.x >= nc.rc_size.x) 3471 nc.rc_hot.x = nc.rc_size.x - 1; 3472 if (nc.rc_hot.y >= nc.rc_size.y) 3473 nc.rc_hot.y = nc.rc_size.y - 1; 3474 } 3475 3476 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3477 nc.rc_pos = wc->pos; 3478 if (nc.rc_pos.x >= dp->rd_virtx) 3479 nc.rc_pos.x = dp->rd_virtx - 1; 3480 #if 0 3481 if (nc.rc_pos.x < 0) 3482 nc.rc_pos.x = 0; 3483 #endif 3484 if (nc.rc_pos.y >= dp->rd_virty) 3485 nc.rc_pos.y = dp->rd_virty - 1; 3486 #if 0 3487 if (nc.rc_pos.y < 0) 3488 nc.rc_pos.y = 0; 3489 #endif 3490 } 3491 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3492 nc.rc_visible = wc->enable; 3493 } 3494 3495 dp->rd_cursor = nc; 3496 radeonfb_cursor_update(dp, wc->which); 3497 3498 return 0; 3499 } 3500 3501 /* 3502 * Change the cursor shape. Call this with the cursor locked to avoid 3503 * flickering/tearing. 3504 */ 3505 static void 3506 radeonfb_cursor_shape(struct radeonfb_display *dp) 3507 { 3508 uint8_t and[512], xor[512]; 3509 int i, j, src, dst /* , pitch */; 3510 const uint8_t *msk = dp->rd_cursor.rc_mask; 3511 const uint8_t *img = dp->rd_cursor.rc_image; 3512 3513 /* 3514 * Radeon cursor data interleaves one line of AND data followed 3515 * by a line of XOR data. (Each line corresponds to a whole hardware 3516 * pitch - i.e. 64 pixels or 8 bytes.) 3517 * 3518 * The cursor is displayed using the following table: 3519 * 3520 * AND XOR Result 3521 * ---------------------- 3522 * 0 0 Cursor color 0 3523 * 0 1 Cursor color 1 3524 * 1 0 Transparent 3525 * 1 1 Complement of background 3526 * 3527 * Our masks are therefore different from what we were passed. 3528 * Passed in, I'm assuming the data represents either color 0 or 1, 3529 * and a mask, so the passed in table looks like: 3530 * 3531 * IMG Mask Result 3532 * ----------------------- 3533 * 0 0 Transparent 3534 * 0 1 Cursor color 0 3535 * 1 0 Transparent 3536 * 1 1 Cursor color 1 3537 * 3538 * IF mask bit == 1, AND = 0, XOR = color. 3539 * IF mask bit == 0, AND = 1, XOR = 0. 3540 * 3541 * hence: AND = ~(mask); XOR = color & ~(mask); 3542 */ 3543 3544 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3545 3546 /* start by assuming all bits are transparent */ 3547 memset(and, 0xff, 512); 3548 memset(xor, 0x00, 512); 3549 3550 src = 0; 3551 dst = 0; 3552 for (i = 0; i < 64; i++) { 3553 for (j = 0; j < 64; j += 8) { 3554 if ((i < dp->rd_cursor.rc_size.y) && 3555 (j < dp->rd_cursor.rc_size.x)) { 3556 3557 /* take care to leave odd bits alone */ 3558 and[dst] &= ~(msk[src]); 3559 xor[dst] = img[src] & msk[src]; 3560 src++; 3561 } 3562 dst++; 3563 } 3564 } 3565 3566 /* copy the image into place */ 3567 for (i = 0; i < 64; i++) { 3568 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3569 &and[i * 8], 8); 3570 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3571 &xor[i * 8], 8); 3572 } 3573 } 3574 3575 static void 3576 radeonfb_cursor_position(struct radeonfb_display *dp) 3577 { 3578 struct radeonfb_softc *sc = dp->rd_softc; 3579 uint32_t offset, hvoff, hvpos; /* registers */ 3580 uint32_t coff; /* cursor offset */ 3581 int i, x, y, xoff, yoff, crtcoff; 3582 3583 /* 3584 * XXX: this also needs to handle pan/scan 3585 */ 3586 for (i = 0; i < dp->rd_ncrtcs; i++) { 3587 3588 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3589 3590 if (rcp->rc_number) { 3591 offset = RADEON_CUR2_OFFSET; 3592 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3593 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3594 crtcoff = RADEON_CRTC2_OFFSET; 3595 } else { 3596 offset = RADEON_CUR_OFFSET; 3597 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3598 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3599 crtcoff = RADEON_CRTC_OFFSET; 3600 } 3601 3602 x = dp->rd_cursor.rc_pos.x; 3603 y = dp->rd_cursor.rc_pos.y; 3604 3605 while (y < rcp->rc_yoffset) { 3606 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3607 } 3608 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3609 rcp->rc_yoffset += RADEON_PANINCREMENT; 3610 } 3611 while (x < rcp->rc_xoffset) { 3612 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3613 } 3614 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3615 rcp->rc_xoffset += RADEON_PANINCREMENT; 3616 } 3617 3618 /* adjust for the cursor's hotspot */ 3619 x -= dp->rd_cursor.rc_hot.x; 3620 y -= dp->rd_cursor.rc_hot.y; 3621 xoff = yoff = 0; 3622 3623 if (x >= dp->rd_virtx) 3624 x = dp->rd_virtx - 1; 3625 if (y >= dp->rd_virty) 3626 y = dp->rd_virty - 1; 3627 3628 /* now adjust cursor so it is relative to viewport */ 3629 x -= rcp->rc_xoffset; 3630 y -= rcp->rc_yoffset; 3631 3632 /* 3633 * no need to check for fall off, because we should 3634 * never move off the screen entirely! 3635 */ 3636 coff = 0; 3637 if (x < 0) { 3638 xoff = -x; 3639 x = 0; 3640 } 3641 if (y < 0) { 3642 yoff = -y; 3643 y = 0; 3644 coff = (yoff * 2) * 8; 3645 } 3646 3647 /* pan the display */ 3648 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3649 rcp->rc_xoffset); 3650 3651 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3652 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3653 /* NB: this unlocks the cursor */ 3654 PUT32(sc, hvpos, (x << 16) | y); 3655 } 3656 } 3657 3658 static void 3659 radeonfb_cursor_visible(struct radeonfb_display *dp) 3660 { 3661 int i; 3662 uint32_t gencntl, bit; 3663 3664 for (i = 0; i < dp->rd_ncrtcs; i++) { 3665 if (dp->rd_crtcs[i].rc_number) { 3666 gencntl = RADEON_CRTC2_GEN_CNTL; 3667 bit = RADEON_CRTC2_CUR_EN; 3668 } else { 3669 gencntl = RADEON_CRTC_GEN_CNTL; 3670 bit = RADEON_CRTC_CUR_EN; 3671 } 3672 3673 if (dp->rd_cursor.rc_visible) 3674 SET32(dp->rd_softc, gencntl, bit); 3675 else 3676 CLR32(dp->rd_softc, gencntl, bit); 3677 } 3678 } 3679 3680 static void 3681 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3682 { 3683 int i; 3684 uint32_t c0reg, c1reg; 3685 struct radeonfb_softc *sc = dp->rd_softc; 3686 3687 for (i = 0; i < dp->rd_ncrtcs; i++) { 3688 if (dp->rd_crtcs[i].rc_number) { 3689 c0reg = RADEON_CUR2_CLR0; 3690 c1reg = RADEON_CUR2_CLR1; 3691 } else { 3692 c0reg = RADEON_CUR_CLR0; 3693 c1reg = RADEON_CUR_CLR1; 3694 } 3695 3696 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3697 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3698 } 3699 } 3700 3701 static void 3702 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3703 { 3704 struct radeonfb_softc *sc; 3705 int i; 3706 3707 sc = dp->rd_softc; 3708 for (i = 0; i < dp->rd_ncrtcs; i++) { 3709 if (dp->rd_crtcs[i].rc_number) { 3710 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3711 } else { 3712 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3713 } 3714 } 3715 3716 if (which & WSDISPLAY_CURSOR_DOCMAP) 3717 radeonfb_cursor_cmap(dp); 3718 3719 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3720 radeonfb_cursor_shape(dp); 3721 3722 if (which & WSDISPLAY_CURSOR_DOCUR) 3723 radeonfb_cursor_visible(dp); 3724 3725 /* this one is unconditional, because it updates other stuff */ 3726 radeonfb_cursor_position(dp); 3727 } 3728 3729 static struct videomode * 3730 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3731 { 3732 int r1, r2; 3733 3734 /* otherwise pick the higher refresh rate */ 3735 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3736 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3737 3738 return (r1 < r2 ? m2 : m1); 3739 } 3740 3741 static const struct videomode * 3742 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3743 int x, int y) 3744 { 3745 struct edid_info *ep = &rp->rp_edid; 3746 struct videomode *vmp = NULL; 3747 int i; 3748 3749 if (!rp->rp_edid_valid) { 3750 /* fallback to safe mode */ 3751 return radeonfb_modelookup(sc->sc_defaultmode); 3752 } 3753 3754 /* always choose the preferred mode first! */ 3755 if (ep->edid_preferred_mode) { 3756 3757 /* XXX: add auto-stretching support for native mode */ 3758 3759 /* this may want panning to occur, btw */ 3760 if ((ep->edid_preferred_mode->hdisplay <= x) && 3761 (ep->edid_preferred_mode->vdisplay <= y)) 3762 return ep->edid_preferred_mode; 3763 } 3764 3765 for (i = 0; i < ep->edid_nmodes; i++) { 3766 /* 3767 * We elect to pick a resolution that is too large for 3768 * the monitor than one that is too small. This means 3769 * that we will prefer to pan rather than to try to 3770 * center a smaller display on a larger screen. In 3771 * practice, this shouldn't matter because if a 3772 * monitor can support a larger resolution, it can 3773 * probably also support the smaller. A specific 3774 * exception is fixed format panels, but hopefully 3775 * they are properly dealt with by the "autostretch" 3776 * logic above. 3777 */ 3778 if ((ep->edid_modes[i].hdisplay > x) || 3779 (ep->edid_modes[i].vdisplay > y)) { 3780 continue; 3781 } 3782 3783 /* 3784 * at this point, the display mode is no larger than 3785 * what we've requested. 3786 */ 3787 if (vmp == NULL) 3788 vmp = &ep->edid_modes[i]; 3789 3790 /* eliminate smaller modes */ 3791 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3792 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3793 continue; 3794 3795 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3796 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3797 vmp = &ep->edid_modes[i]; 3798 continue; 3799 } 3800 3801 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3802 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3803 3804 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3805 } 3806 3807 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3808 } 3809 3810 static int 3811 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3812 { 3813 int i; 3814 3815 for (i = 0; i < nlist; i++) { 3816 if ((x == list[i].hdisplay) && 3817 (y == list[i].vdisplay)) { 3818 return 1; 3819 } 3820 } 3821 return 0; 3822 } 3823 3824 static void 3825 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3826 int pan) 3827 { 3828 struct radeonfb_port *rp; 3829 struct edid_info *ep; 3830 int i, j; 3831 3832 *x = 0; 3833 *y = 0; 3834 3835 if (pan) { 3836 for (i = 0; i < dp->rd_ncrtcs; i++) { 3837 rp = dp->rd_crtcs[i].rc_port; 3838 ep = &rp->rp_edid; 3839 if (!rp->rp_edid_valid) { 3840 /* monitor not present */ 3841 continue; 3842 } 3843 3844 /* 3845 * For now we are ignoring "conflict" that 3846 * could occur when mixing some modes like 3847 * 1280x1024 and 1400x800. It isn't clear 3848 * which is better, so the first one wins. 3849 */ 3850 for (j = 0; j < ep->edid_nmodes; j++) { 3851 /* 3852 * ignore resolutions that are too big for 3853 * the radeon 3854 */ 3855 if (ep->edid_modes[j].hdisplay > 3856 dp->rd_softc->sc_maxx) 3857 continue; 3858 if (ep->edid_modes[j].vdisplay > 3859 dp->rd_softc->sc_maxy) 3860 continue; 3861 3862 /* 3863 * pick largest resolution, the 3864 * smaller monitor will pan 3865 */ 3866 if ((ep->edid_modes[j].hdisplay >= *x) && 3867 (ep->edid_modes[j].vdisplay >= *y)) { 3868 *x = ep->edid_modes[j].hdisplay; 3869 *y = ep->edid_modes[j].vdisplay; 3870 } 3871 } 3872 } 3873 3874 } else { 3875 struct videomode modes[64]; 3876 int nmodes = 0; 3877 int valid = 0; 3878 3879 for (i = 0; i < dp->rd_ncrtcs; i++) { 3880 /* 3881 * pick the largest resolution in common. 3882 */ 3883 rp = dp->rd_crtcs[i].rc_port; 3884 ep = &rp->rp_edid; 3885 3886 if (!rp->rp_edid_valid) 3887 continue; 3888 3889 if (!valid) { 3890 /* 3891 * Pick the preferred mode for this port 3892 * if available. 3893 */ 3894 if (ep->edid_preferred_mode) { 3895 struct videomode *vmp = 3896 ep->edid_preferred_mode; 3897 3898 if ((vmp->hdisplay <= 3899 dp->rd_softc->sc_maxx) && 3900 (vmp->vdisplay <= 3901 dp->rd_softc->sc_maxy)) 3902 modes[nmodes++] = *vmp; 3903 } else { 3904 3905 /* initialize starting list */ 3906 for (j = 0; j < ep->edid_nmodes; j++) { 3907 /* 3908 * ignore resolutions that are 3909 * too big for the radeon 3910 */ 3911 if (ep->edid_modes[j].hdisplay > 3912 dp->rd_softc->sc_maxx) 3913 continue; 3914 if (ep->edid_modes[j].vdisplay > 3915 dp->rd_softc->sc_maxy) 3916 continue; 3917 3918 modes[nmodes] = 3919 ep->edid_modes[j]; 3920 nmodes++; 3921 } 3922 } 3923 valid = 1; 3924 } else { 3925 /* merge into preexisting list */ 3926 for (j = 0; j < nmodes; j++) { 3927 if (!radeonfb_hasres(ep->edid_modes, 3928 ep->edid_nmodes, 3929 modes[j].hdisplay, 3930 modes[j].vdisplay)) { 3931 modes[j] = modes[nmodes]; 3932 j--; 3933 nmodes--; 3934 } 3935 } 3936 } 3937 } 3938 3939 /* now we have to pick from the merged list */ 3940 for (i = 0; i < nmodes; i++) { 3941 if ((modes[i].hdisplay >= *x) && 3942 (modes[i].vdisplay >= *y)) { 3943 *x = modes[i].hdisplay; 3944 *y = modes[i].vdisplay; 3945 } 3946 } 3947 } 3948 3949 if ((*x == 0) || (*y == 0)) { 3950 /* fallback to safe mode */ 3951 *x = 640; 3952 *y = 480; 3953 } 3954 } 3955 3956 /* 3957 * backlight levels are linear on: 3958 * - RV200, RV250, RV280, RV350 3959 * - but NOT on PowerBook4,3 6,3 6,5 3960 * according to Linux' radeonfb 3961 */ 3962 3963 /* Get the current backlight level for the display. */ 3964 3965 static int 3966 radeonfb_get_backlight(struct radeonfb_display *dp) 3967 { 3968 int s; 3969 uint32_t level; 3970 3971 s = spltty(); 3972 3973 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3974 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3975 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3976 3977 /* 3978 * On some chips, we should negate the backlight level. 3979 * XXX Find out on which chips. 3980 */ 3981 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 3982 level = RADEONFB_BACKLIGHT_MAX - level; 3983 3984 splx(s); 3985 3986 return level; 3987 } 3988 3989 /* Set the backlight to the given level for the display. */ 3990 static void 3991 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 3992 { 3993 if (dp->rd_bl_on == on) 3994 return; 3995 dp->rd_bl_on = on; 3996 radeonfb_set_backlight(dp, dp->rd_bl_level); 3997 } 3998 3999 static int 4000 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4001 { 4002 struct radeonfb_softc *sc; 4003 int rlevel, s; 4004 uint32_t lvds; 4005 4006 s = spltty(); 4007 4008 dp->rd_bl_level = level; 4009 if (dp->rd_bl_on == 0) 4010 level = 0; 4011 4012 if (level < 0) 4013 level = 0; 4014 else if (level >= RADEONFB_BACKLIGHT_MAX) 4015 level = RADEONFB_BACKLIGHT_MAX; 4016 4017 sc = dp->rd_softc; 4018 4019 /* On some chips, we should negate the backlight level. */ 4020 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4021 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4022 } else 4023 rlevel = level; 4024 4025 callout_stop(&dp->rd_bl_lvds_co); 4026 radeonfb_engine_idle(sc); 4027 4028 /* 4029 * Turn off the display if the backlight is set to 0, since the 4030 * display is useless without backlight anyway. 4031 */ 4032 if (level == 0) 4033 radeonfb_blank(dp, 1); 4034 else if (radeonfb_get_backlight(dp) == 0) 4035 radeonfb_blank(dp, 0); 4036 4037 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4038 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4039 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4040 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4041 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4042 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4043 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4044 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4045 lvds |= RADEON_LVDS_ON; 4046 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4047 } else { 4048 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4049 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4050 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4051 } 4052 4053 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4054 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4055 /* XXX What is the correct delay? */ 4056 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4057 4058 splx(s); 4059 4060 return 0; 4061 } 4062 4063 /* 4064 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4065 * Set the delayed bits in the register, and clear the stored delayed 4066 * value. 4067 */ 4068 4069 static void radeonfb_lvds_callout(void *arg) 4070 { 4071 struct radeonfb_display *dp = arg; 4072 int s; 4073 4074 s = splhigh(); 4075 4076 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4077 dp->rd_bl_lvds_val); 4078 dp->rd_bl_lvds_val = 0; 4079 4080 splx(s); 4081 } 4082 4083 static void 4084 radeonfb_brightness_up(device_t dev) 4085 { 4086 struct radeonfb_softc *sc = device_private(dev); 4087 struct radeonfb_display *dp = &sc->sc_displays[0]; 4088 int level; 4089 4090 /* we assume the main display is the first one - need a better way */ 4091 if (sc->sc_ndisplays < 1) return; 4092 /* make sure pushing the hotkeys always has an effect */ 4093 dp->rd_bl_on = 1; 4094 level = dp->rd_bl_level; 4095 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4096 radeonfb_set_backlight(dp, level); 4097 } 4098 4099 static void 4100 radeonfb_brightness_down(device_t dev) 4101 { 4102 struct radeonfb_softc *sc = device_private(dev); 4103 struct radeonfb_display *dp = &sc->sc_displays[0]; 4104 int level; 4105 4106 /* we assume the main display is the first one - need a better way */ 4107 if (sc->sc_ndisplays < 1) return; 4108 /* make sure pushing the hotkeys always has an effect */ 4109 dp->rd_bl_on = 1; 4110 level = dp->rd_bl_level; 4111 level = max(0, level - 5); 4112 radeonfb_set_backlight(dp, level); 4113 } 4114
Indexes created Thu Sep 25 16:09:42 GMT 2025