radeonfb.c revision 1.84
1 /* $NetBSD: radeonfb.c,v 1.84 2014/07/22 15:42:59 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.84 2014/07/22 15:42:59 riastradh Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 144 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 145 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 146 147 /* acceleration support */ 148 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 149 int width, int height, uint32_t color); 150 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 151 static void radeonfb_bitblt(void *, int srcx, int srcy, 152 int dstx, int dsty, int width, int height, int rop); 153 154 /* hw cursor support */ 155 static void radeonfb_cursor_cmap(struct radeonfb_display *); 156 static void radeonfb_cursor_shape(struct radeonfb_display *); 157 static void radeonfb_cursor_position(struct radeonfb_display *); 158 static void radeonfb_cursor_visible(struct radeonfb_display *); 159 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 160 161 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 162 static void radeonfb_engine_idle(struct radeonfb_softc *); 163 static void radeonfb_engine_flush(struct radeonfb_softc *); 164 static void radeonfb_engine_reset(struct radeonfb_softc *); 165 static void radeonfb_engine_init(struct radeonfb_display *); 166 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 167 168 static void radeonfb_eraserows(void *, int, int, long); 169 static void radeonfb_erasecols(void *, int, int, int, long); 170 static void radeonfb_copyrows(void *, int, int, int); 171 static void radeonfb_copycols(void *, int, int, int, int); 172 static void radeonfb_cursor(void *, int, int, int); 173 static void radeonfb_putchar(void *, int, int, unsigned, long); 174 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 175 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 176 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 177 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 178 #endif 179 180 static int radeonfb_set_backlight(struct radeonfb_display *, int); 181 static int radeonfb_get_backlight(struct radeonfb_display *); 182 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 183 static void radeonfb_lvds_callout(void *); 184 185 static void radeonfb_brightness_up(device_t); 186 static void radeonfb_brightness_down(device_t); 187 188 static struct videomode *radeonfb_best_refresh(struct videomode *, 189 struct videomode *); 190 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 191 uint16_t *, int); 192 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 193 struct radeonfb_port *, int, int); 194 195 static int radeonfb_drm_print(void *, const char *); 196 197 #ifdef RADEONFB_DEBUG 198 int radeon_debug = 1; 199 #define DPRINTF(x) \ 200 if (radeon_debug) printf x 201 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 202 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 203 #else 204 #define DPRINTF(x) 205 #define PRINTREG(r) 206 #define PRINTPLL(r) 207 #endif 208 209 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 210 211 #ifndef RADEON_DEFAULT_MODE 212 /* any reasonably modern display should handle this */ 213 #define RADEON_DEFAULT_MODE "1024x768x60" 214 #endif 215 216 extern const u_char rasops_cmap[768]; 217 218 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 219 220 static struct { 221 int size; /* minimum memory size (MB) */ 222 int maxx; /* maximum x dimension */ 223 int maxy; /* maximum y dimension */ 224 int maxbpp; /* maximum bpp */ 225 int maxdisp; /* maximum logical display count */ 226 } radeonfb_limits[] = { 227 { 32, 2048, 1536, 32, 2 }, 228 { 16, 1600, 1200, 32, 2 }, 229 { 8, 1600, 1200, 32, 1 }, 230 { 0, 0, 0, 0, 0 }, 231 }; 232 233 static struct wsscreen_descr radeonfb_stdscreen = { 234 "fb", /* name */ 235 0, 0, /* ncols, nrows */ 236 NULL, /* textops */ 237 8, 16, /* fontwidth, fontheight */ 238 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 239 0, /* modecookie */ 240 }; 241 242 struct wsdisplay_accessops radeonfb_accessops = { 243 radeonfb_ioctl, 244 radeonfb_mmap, 245 NULL, /* vcons_alloc_screen */ 246 NULL, /* vcons_free_screen */ 247 NULL, /* vcons_show_screen */ 248 NULL, /* load_font */ 249 NULL, /* pollc */ 250 NULL, /* scroll */ 251 }; 252 253 static struct { 254 uint16_t devid; 255 uint16_t family; 256 uint16_t flags; 257 } radeonfb_devices[] = 258 { 259 /* R100 family */ 260 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 264 265 /* RV100 family */ 266 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 267 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 270 271 /* RS100 family */ 272 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 274 275 /* RS200/RS250 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 280 281 /* R200 family */ 282 /* add more R200 products? , 5148 */ 283 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 288 289 /* RV200 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 294 295 /* RV250 family */ 296 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 299 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 301 302 /* RS300 family */ 303 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 307 308 /* RV280 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 316 317 /* R300 family */ 318 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 326 327 /* RV350/RV360 family */ 328 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 340 341 /* R350/R360 family */ 342 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 350 351 /* RV380/RV370 family */ 352 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 362 363 #if notyet 364 /* R420/R423 family */ 365 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 382 #endif 383 { 0, 0, 0 } 384 }; 385 386 static struct { 387 int divider; 388 int mask; 389 } radeonfb_dividers[] = { 390 { 16, 5 }, 391 { 12, 7 }, 392 { 8, 3 }, 393 { 6, 6 }, 394 { 4, 2 }, 395 { 3, 4 }, 396 { 2, 1 }, 397 { 1, 0 }, 398 { 0, 0 } 399 }; 400 401 /* 402 * This table taken from X11. 403 */ 404 static const struct { 405 int family; 406 struct radeon_tmds_pll plls[4]; 407 } radeonfb_tmds_pll[] = { 408 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_RS100, {{0, 0}}}, 411 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 412 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 413 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 414 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 415 { RADEON_RS300, {{0, 0}}}, 416 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 417 { RADEON_R300, {{-1, 0xb01cb}}}, 418 { RADEON_R350, {{-1, 0xb01cb}}}, 419 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 420 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 421 { RADEON_R420, {{-1, 0xb01cb}}}, 422 }; 423 424 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 425 426 427 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 428 radeonfb_match, radeonfb_attach, NULL, NULL); 429 430 static int 431 radeonfb_match(device_t parent, cfdata_t match, void *aux) 432 { 433 const struct pci_attach_args *pa = aux; 434 int i; 435 436 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 437 return 0; 438 439 for (i = 0; radeonfb_devices[i].devid; i++) { 440 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 441 return 100; /* high to defeat VGA/VESA */ 442 } 443 444 return 0; 445 } 446 447 static void 448 radeonfb_attach(device_t parent, device_t dev, void *aux) 449 { 450 struct radeonfb_softc *sc = device_private(dev); 451 const struct pci_attach_args *pa = aux; 452 const char *mptr; 453 bus_size_t bsz; 454 pcireg_t screg; 455 int i, j, fg, bg, ul, flags; 456 uint32_t v; 457 458 sc->sc_dev = dev; 459 sc->sc_id = pa->pa_id; 460 for (i = 0; radeonfb_devices[i].devid; i++) { 461 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 462 break; 463 } 464 465 pci_aprint_devinfo(pa, NULL); 466 467 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 468 469 KASSERT(radeonfb_devices[i].devid != 0); 470 sc->sc_pt = pa->pa_tag; 471 sc->sc_iot = pa->pa_iot; 472 sc->sc_pc = pa->pa_pc; 473 sc->sc_family = radeonfb_devices[i].family; 474 sc->sc_flags = radeonfb_devices[i].flags; 475 476 /* enable memory and IO access */ 477 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 478 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 479 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 480 481 /* 482 * Some flags are general to entire chip families, and rather 483 * than clutter up the table with them, we go ahead and set 484 * them here. 485 */ 486 switch (sc->sc_family) { 487 case RADEON_RS100: 488 case RADEON_RS200: 489 sc->sc_flags |= RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_RV100: 493 case RADEON_RV200: 494 case RADEON_RV250: 495 case RADEON_RV280: 496 sc->sc_flags |= RFB_RV100; 497 break; 498 499 case RADEON_RS300: 500 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 501 break; 502 503 case RADEON_R300: 504 case RADEON_RV350: 505 case RADEON_R350: 506 case RADEON_RV380: 507 case RADEON_R420: 508 /* newer chips */ 509 sc->sc_flags |= RFB_R300; 510 break; 511 512 case RADEON_R100: 513 sc->sc_flags |= RFB_NCRTC2; 514 break; 515 } 516 517 if ((sc->sc_family == RADEON_RV200) || 518 (sc->sc_family == RADEON_RV250) || 519 (sc->sc_family == RADEON_RV280) || 520 (sc->sc_family == RADEON_RV350)) { 521 bool inverted = 0; 522 /* backlight level is linear */ 523 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 524 prop_dictionary_get_bool(device_properties(sc->sc_dev), 525 "backlight_level_reverted", &inverted); 526 if (inverted) { 527 DPRINTF(("nope, it's inverted\n")); 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 } 530 } else 531 sc->sc_flags |= RFB_INV_BLIGHT; 532 533 /* 534 * XXX: to support true multihead, this must change. 535 */ 536 sc->sc_ndisplays = 1; 537 538 /* XXX: */ 539 if (!HAS_CRTC2(sc)) { 540 sc->sc_ndisplays = 1; 541 } 542 543 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 544 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 545 &sc->sc_regsz) != 0) { 546 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 547 goto error; 548 } 549 550 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 551 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 552 { 553 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 554 goto error; 555 } 556 sc->sc_romt = sc->sc_memt; 557 558 sc->sc_mapped = TRUE; 559 560 /* scratch register test... */ 561 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 562 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 563 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 564 goto error; 565 } 566 567 PRINTREG(RADEON_CRTC_EXT_CNTL); 568 PRINTREG(RADEON_CRTC_GEN_CNTL); 569 PRINTREG(RADEON_CRTC2_GEN_CNTL); 570 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 571 PRINTREG(RADEON_DAC_CNTL2); 572 PRINTREG(RADEON_FP_GEN_CNTL); 573 PRINTREG(RADEON_FP2_GEN_CNTL); 574 575 PRINTREG(RADEON_BIOS_4_SCRATCH); 576 PRINTREG(RADEON_FP_GEN_CNTL); 577 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 578 PRINTREG(RADEON_FP2_GEN_CNTL); 579 PRINTREG(RADEON_TMDS_CNTL); 580 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 581 PRINTREG(RADEON_TMDS_PLL_CNTL); 582 PRINTREG(RADEON_LVDS_GEN_CNTL); 583 PRINTREG(RADEON_FP_HORZ_STRETCH); 584 PRINTREG(RADEON_FP_VERT_STRETCH); 585 586 if (IS_RV100(sc)) 587 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 588 589 /* XXX 590 * according to xf86-video-radeon R3xx has this bit backwards 591 */ 592 if (IS_R300(sc)) { 593 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 594 0, 595 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 596 } else { 597 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 598 RADEON_TMDS_TRANSMITTER_PLLEN, 599 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 600 } 601 602 radeonfb_i2c_init(sc); 603 604 radeonfb_loadbios(sc, pa); 605 606 #ifdef RADEONFB_BIOS_INIT 607 if (radeonfb_bios_init(sc)) { 608 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 609 } 610 #endif 611 612 if (radeonfb_getclocks(sc)) { 613 aprint_error("%s: Unable to get reference clocks from BIOS\n", 614 XNAME(sc)); 615 goto error; 616 } 617 618 if (radeonfb_gettmds(sc)) { 619 aprint_error("%s: Unable to identify TMDS PLL settings\n", 620 XNAME(sc)); 621 goto error; 622 } 623 624 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 625 "minpll = %d, maxpll = %d\n", XNAME(sc), 626 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 627 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 628 629 radeonfb_getconnectors(sc); 630 631 radeonfb_set_fbloc(sc); 632 633 /* 64 MB should be enough -- more just wastes map entries */ 634 if (sc->sc_memsz > (64 << 20)) 635 sc->sc_memsz = (64 << 20); 636 637 for (i = 0; radeonfb_limits[i].size; i++) { 638 if (sc->sc_memsz >= radeonfb_limits[i].size) { 639 sc->sc_maxx = radeonfb_limits[i].maxx; 640 sc->sc_maxy = radeonfb_limits[i].maxy; 641 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 642 /* framebuffer offset, start at a 4K page */ 643 sc->sc_fboffset = sc->sc_memsz / 644 radeonfb_limits[i].maxdisp; 645 /* 646 * we use the fbsize to figure out where we can store 647 * things like cursor data. 648 */ 649 sc->sc_fbsize = 650 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 651 RADEON_STRIDEALIGN) * sc->sc_maxy, 652 4096); 653 break; 654 } 655 } 656 657 658 radeonfb_init_misc(sc); 659 660 /* program the DAC wirings */ 661 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 662 switch (sc->sc_ports[i].rp_dac_type) { 663 case RADEON_DAC_PRIMARY: 664 PATCH32(sc, RADEON_DAC_CNTL2, 665 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 666 ~RADEON_DAC2_DAC_CLK_SEL); 667 break; 668 case RADEON_DAC_TVDAC: 669 /* we always use the TVDAC to drive a secondary analog 670 * CRT for now. if we ever support TV-out this will 671 * have to change. 672 */ 673 SET32(sc, RADEON_DAC_CNTL2, 674 RADEON_DAC2_DAC2_CLK_SEL); 675 PATCH32(sc, RADEON_DISP_HW_DEBUG, 676 i ? 0 : RADEON_CRT2_DISP1_SEL, 677 ~RADEON_CRT2_DISP1_SEL); 678 /* we're using CRTC2 for the 2nd port */ 679 if (sc->sc_ports[i].rp_number == 1) { 680 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 681 RADEON_DISP_DAC2_SOURCE_CRTC2, 682 ~RADEON_DISP_DAC2_SOURCE_MASK); 683 } 684 685 break; 686 } 687 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 688 sc->sc_ports[i].rp_tmds_type)); 689 switch (sc->sc_ports[i].rp_tmds_type) { 690 case RADEON_TMDS_INT: 691 /* point FP0 at the CRTC this port uses */ 692 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 693 __func__, sc->sc_ports[i].rp_number)); 694 if (IS_R300(sc)) { 695 PATCH32(sc, RADEON_FP_GEN_CNTL, 696 sc->sc_ports[i].rp_number ? 697 R200_FP_SOURCE_SEL_CRTC2 : 698 R200_FP_SOURCE_SEL_CRTC1, 699 ~R200_FP_SOURCE_SEL_MASK); 700 } else { 701 PATCH32(sc, RADEON_FP_GEN_CNTL, 702 sc->sc_ports[i].rp_number ? 703 RADEON_FP_SEL_CRTC2 : 704 RADEON_FP_SEL_CRTC1, 705 ~RADEON_FP_SEL_MASK); 706 } 707 } 708 } 709 PRINTREG(RADEON_DAC_CNTL2); 710 PRINTREG(RADEON_DISP_HW_DEBUG); 711 712 /* other DAC programming */ 713 v = GET32(sc, RADEON_DAC_CNTL); 714 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 715 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 716 PUT32(sc, RADEON_DAC_CNTL, v); 717 PRINTREG(RADEON_DAC_CNTL); 718 719 /* XXX: this may need more investigation */ 720 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 721 PRINTREG(RADEON_TV_DAC_CNTL); 722 723 /* enable TMDS */ 724 SET32(sc, RADEON_FP_GEN_CNTL, 725 RADEON_FP_TMDS_EN | 726 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 727 RADEON_FP_CRTC_DONT_SHADOW_HEND); 728 /* 729 * XXX 730 * no idea why this is necessary - if I do not clear this bit on my 731 * iBook G4 the screen remains black, even though it's already clear. 732 * It needs to be set on my Sun XVR-100 for the DVI port to work 733 * TODO: 734 * see if this is still necessary now that CRTCs, DACs and outputs are 735 * getting wired up in a halfway sane way 736 */ 737 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 738 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 739 } else { 740 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 741 } 742 743 /* 744 * we use bus_space_map instead of pci_mapreg, because we don't 745 * need the full aperature space. no point in wasting virtual 746 * address space we don't intend to use, right? 747 */ 748 if ((sc->sc_memsz < (4096 * 1024)) || 749 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 750 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 751 (bsz < sc->sc_memsz)) { 752 sc->sc_memsz = 0; 753 aprint_error("%s: Bad frame buffer configuration\n", 754 XNAME(sc)); 755 goto error; 756 } 757 758 sc->sc_memt = pa->pa_memt; 759 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 760 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 761 sc->sc_memsz = 0; 762 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 763 goto error; 764 } 765 766 aprint_normal("%s: %d MB aperture at 0x%08x, " 767 "%d KB registers at 0x%08x\n", XNAME(sc), 768 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 769 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 770 771 /* setup default video mode from devprop (allows PROM override) */ 772 sc->sc_defaultmode = radeonfb_default_mode; 773 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 774 "videomode", &mptr)) { 775 776 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 777 sc->sc_defaultmode = sc->sc_modebuf; 778 } 779 780 /* initialize some basic display parameters */ 781 for (i = 0; i < sc->sc_ndisplays; i++) { 782 struct radeonfb_display *dp = &sc->sc_displays[i]; 783 struct rasops_info *ri; 784 long defattr; 785 struct wsemuldisplaydev_attach_args aa; 786 787 /* 788 * Figure out how many "displays" (desktops) we are going to 789 * support. If more than one, then each CRTC gets its own 790 * programming. 791 * 792 * XXX: this code needs to change to support mergedfb. 793 * XXX: would be nice to allow this to be overridden 794 */ 795 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 796 DPRINTF(("dual crtcs!\n")); 797 dp->rd_ncrtcs = 2; 798 dp->rd_crtcs[0].rc_port = 799 &sc->sc_ports[0]; 800 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 801 dp->rd_crtcs[1].rc_port = 802 &sc->sc_ports[1]; 803 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 804 } else { 805 dp->rd_ncrtcs = 1; 806 dp->rd_crtcs[0].rc_port = 807 &sc->sc_ports[i]; 808 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 809 } 810 811 dp->rd_softc = sc; 812 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 813 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 814 815 /* for text mode, we pick a resolution that won't 816 * require panning */ 817 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 818 819 aprint_normal("%s: display %d: " 820 "initial virtual resolution %dx%d at %d bpp\n", 821 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 822 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 823 sc->sc_fboffset >> 20); 824 /* now select the *video mode* that we will use */ 825 for (j = 0; j < dp->rd_ncrtcs; j++) { 826 const struct videomode *vmp; 827 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 828 dp->rd_virtx, dp->rd_virty); 829 830 /* 831 * virtual resolution should be at least as high as 832 * physical 833 */ 834 if (dp->rd_virtx < vmp->hdisplay || 835 dp->rd_virty < vmp->vdisplay) { 836 dp->rd_virtx = vmp->hdisplay; 837 dp->rd_virty = vmp->vdisplay; 838 } 839 840 dp->rd_crtcs[j].rc_videomode = *vmp; 841 printf("%s: port %d: physical %dx%d %dHz\n", 842 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 843 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 844 vmp->htotal), vmp->vtotal)); 845 } 846 847 /* N.B.: radeon wants 64-byte aligned stride */ 848 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 849 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 850 DPRINTF(("stride: %d\n", dp->rd_stride)); 851 852 dp->rd_offset = sc->sc_fboffset * i; 853 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 854 sc->sc_memh) + dp->rd_offset; 855 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 856 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 857 858 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 859 860 switch (dp->rd_bpp) { 861 case 8: 862 dp->rd_format = 2; 863 break; 864 case 32: 865 dp->rd_format = 6; 866 break; 867 default: 868 aprint_error("%s: bad depth %d\n", XNAME(sc), 869 dp->rd_bpp); 870 goto error; 871 } 872 873 DPRINTF(("init engine\n")); 874 /* XXX: this seems suspicious - per display engine 875 initialization? */ 876 radeonfb_engine_init(dp); 877 878 /* copy the template into place */ 879 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 880 dp->rd_wsscreens = dp->rd_wsscreens_storage; 881 882 /* and make up the list */ 883 dp->rd_wsscreenlist.nscreens = 1; 884 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 885 886 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 887 &radeonfb_accessops); 888 889 dp->rd_vd.init_screen = radeonfb_init_screen; 890 891 #ifdef RADEONFB_DEBUG 892 dp->rd_virty -= 200; 893 #endif 894 895 dp->rd_console = 0; 896 prop_dictionary_get_bool(device_properties(sc->sc_dev), 897 "is_console", &dp->rd_console); 898 899 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 900 901 902 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 903 dp->rd_console, &defattr); 904 905 ri = &dp->rd_vscreen.scr_ri; 906 907 /* clear the screen */ 908 rasops_unpack_attr(defattr, &fg, &bg, &ul); 909 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 910 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 911 dp->rd_bg); 912 913 dp->rd_wsscreens->textops = &ri->ri_ops; 914 dp->rd_wsscreens->capabilities = ri->ri_caps; 915 dp->rd_wsscreens->nrows = ri->ri_rows; 916 dp->rd_wsscreens->ncols = ri->ri_cols; 917 918 #ifdef SPLASHSCREEN 919 dp->rd_splash.si_depth = ri->ri_depth; 920 dp->rd_splash.si_bits = ri->ri_bits; 921 dp->rd_splash.si_hwbits = ri->ri_hwbits; 922 dp->rd_splash.si_width = ri->ri_width; 923 dp->rd_splash.si_height = ri->ri_height; 924 dp->rd_splash.si_stride = ri->ri_stride; 925 dp->rd_splash.si_fillrect = NULL; 926 #endif 927 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 928 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 929 dp->rd_gc.gc_rop = RADEON_ROP3_S; 930 dp->rd_gc.gc_blitcookie = dp; 931 /* 932 * use memory between framebuffer and cursor area as glyph 933 * cache, cap at 4096 lines 934 */ 935 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 936 min(4096, 937 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 938 dp->rd_virtx, 939 ri->ri_font->fontwidth, 940 ri->ri_font->fontheight, 941 defattr); 942 if (dp->rd_console) { 943 944 radeonfb_modeswitch(dp); 945 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 946 defattr); 947 #ifdef SPLASHSCREEN 948 if (splash_render(&dp->rd_splash, 949 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 950 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 951 else 952 #endif 953 vcons_replay_msgbuf(&dp->rd_vscreen); 954 } else { 955 956 /* 957 * since we're not the console we can postpone 958 * the rest until someone actually allocates a 959 * screen for us. but we do clear the screen 960 * at least. 961 */ 962 memset(ri->ri_bits, 0, 1024); 963 964 radeonfb_modeswitch(dp); 965 #ifdef SPLASHSCREEN 966 if (splash_render(&dp->rd_splash, 967 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 968 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 969 #endif 970 } 971 972 aa.console = dp->rd_console; 973 aa.scrdata = &dp->rd_wsscreenlist; 974 aa.accessops = &radeonfb_accessops; 975 aa.accesscookie = &dp->rd_vd; 976 977 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 978 979 radeonfb_blank(dp, 0); 980 981 /* Initialise delayed lvds operations for backlight. */ 982 callout_init(&dp->rd_bl_lvds_co, 0); 983 callout_setfunc(&dp->rd_bl_lvds_co, 984 radeonfb_lvds_callout, dp); 985 dp->rd_bl_on = 1; 986 dp->rd_bl_level = radeonfb_get_backlight(dp); 987 radeonfb_set_backlight(dp, dp->rd_bl_level); 988 } 989 990 for (i = 0; i < RADEON_NDISPLAYS; i++) 991 radeonfb_init_palette(&sc->sc_displays[i]); 992 993 if (HAS_CRTC2(sc)) { 994 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 995 } 996 997 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 998 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 999 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1000 radeonfb_brightness_up, TRUE); 1001 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1002 radeonfb_brightness_down, TRUE); 1003 1004 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 1005 1006 PRINTREG(RADEON_CRTC_EXT_CNTL); 1007 PRINTREG(RADEON_CRTC_GEN_CNTL); 1008 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1009 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1010 PRINTREG(RADEON_DAC_CNTL2); 1011 PRINTREG(RADEON_FP_GEN_CNTL); 1012 PRINTREG(RADEON_FP2_GEN_CNTL); 1013 1014 return; 1015 1016 error: 1017 if (sc->sc_biossz) 1018 free(sc->sc_bios, M_DEVBUF); 1019 1020 if (sc->sc_regsz) 1021 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1022 1023 if (sc->sc_memsz) 1024 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1025 } 1026 1027 static void 1028 radeonfb_map(struct radeonfb_softc *sc) 1029 { 1030 if (!sc->sc_mapped) { 1031 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1032 &sc->sc_regh) != 0) { 1033 aprint_error_dev(sc->sc_dev, 1034 "unable to map registers!\n"); 1035 return; 1036 } 1037 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1038 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1039 sc->sc_memsz = 0; 1040 aprint_error_dev(sc->sc_dev, 1041 "Unable to map frame buffer\n"); 1042 return; 1043 } 1044 sc->sc_mapped = TRUE; 1045 } 1046 } 1047 1048 static void 1049 radeonfb_unmap(struct radeonfb_softc *sc) 1050 { 1051 if (sc->sc_mapped) { 1052 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1053 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1054 sc->sc_mapped = FALSE; 1055 } 1056 } 1057 1058 static int 1059 radeonfb_drm_print(void *aux, const char *pnp) 1060 { 1061 if (pnp) 1062 aprint_normal("drm at %s", pnp); 1063 return (UNCONF); 1064 } 1065 1066 int 1067 radeonfb_ioctl(void *v, void *vs, 1068 unsigned long cmd, void *d, int flag, struct lwp *l) 1069 { 1070 struct vcons_data *vd; 1071 struct radeonfb_display *dp; 1072 struct radeonfb_softc *sc; 1073 struct wsdisplay_param *param; 1074 struct vcons_screen *ms; 1075 1076 vd = (struct vcons_data *)v; 1077 ms = vd->active; 1078 dp = (struct radeonfb_display *)vd->cookie; 1079 sc = dp->rd_softc; 1080 1081 /* can't do these without registers being mapped */ 1082 if (!sc->sc_mapped) { 1083 switch (cmd) { 1084 case WSDISPLAYIO_GVIDEO: 1085 case WSDISPLAYIO_SVIDEO: 1086 case WSDISPLAYIO_GETCMAP: 1087 case WSDISPLAYIO_PUTCMAP: 1088 case WSDISPLAYIO_SCURSOR: 1089 case WSDISPLAYIO_GCURPOS: 1090 case WSDISPLAYIO_SCURPOS: 1091 case WSDISPLAYIO_SETPARAM: 1092 return EINVAL; 1093 } 1094 } 1095 1096 switch (cmd) { 1097 case WSDISPLAYIO_GTYPE: 1098 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1099 return 0; 1100 1101 case WSDISPLAYIO_GINFO: 1102 if (vd->active != NULL) { 1103 struct wsdisplay_fbinfo *fb; 1104 fb = (struct wsdisplay_fbinfo *)d; 1105 fb->width = dp->rd_virtx; 1106 fb->height = dp->rd_virty; 1107 fb->depth = dp->rd_bpp; 1108 fb->cmsize = 256; 1109 return 0; 1110 } else 1111 return ENODEV; 1112 case WSDISPLAYIO_GVIDEO: 1113 if (radeonfb_isblank(dp)) 1114 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1115 else 1116 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1117 return 0; 1118 1119 case WSDISPLAYIO_SVIDEO: 1120 radeonfb_blank(dp, 1121 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1122 return 0; 1123 1124 case WSDISPLAYIO_GETCMAP: 1125 if (dp->rd_bpp == 8) 1126 return radeonfb_getcmap(dp, 1127 (struct wsdisplay_cmap *)d); 1128 return EINVAL; 1129 1130 case WSDISPLAYIO_PUTCMAP: 1131 if (dp->rd_bpp == 8) 1132 return radeonfb_putcmap(dp, 1133 (struct wsdisplay_cmap *)d); 1134 return EINVAL; 1135 1136 case WSDISPLAYIO_LINEBYTES: 1137 *(unsigned *)d = dp->rd_stride; 1138 return 0; 1139 1140 case WSDISPLAYIO_SMODE: 1141 if (*(int *)d != dp->rd_wsmode) { 1142 dp->rd_wsmode = *(int *)d; 1143 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1144 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1145 radeonfb_map(sc); 1146 1147 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1148 (dp->rd_vd.active)) { 1149 radeonfb_engine_init(dp); 1150 glyphcache_wipe(&dp->rd_gc); 1151 radeonfb_init_palette(dp); 1152 radeonfb_modeswitch(dp); 1153 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1154 dp->rd_virty, dp->rd_bg); 1155 vcons_redraw_screen(dp->rd_vd.active); 1156 } 1157 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1158 radeonfb_unmap(sc); 1159 } 1160 return 0; 1161 1162 case WSDISPLAYIO_GCURMAX: 1163 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1164 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1165 return 0; 1166 1167 case WSDISPLAYIO_SCURSOR: 1168 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1169 1170 case WSDISPLAYIO_GCURSOR: 1171 return EPASSTHROUGH; 1172 1173 case WSDISPLAYIO_GCURPOS: 1174 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1175 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1176 return 0; 1177 1178 case WSDISPLAYIO_SCURPOS: 1179 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1180 1181 case WSDISPLAYIO_SSPLASH: 1182 #if defined(SPLASHSCREEN) 1183 if (*(int *)d == 1) { 1184 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1185 splash_render(&dp->rd_splash, 1186 SPLASH_F_CENTER|SPLASH_F_FILL); 1187 } else 1188 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1189 return 0; 1190 #else 1191 return ENODEV; 1192 #endif 1193 case WSDISPLAYIO_GETPARAM: 1194 param = (struct wsdisplay_param *)d; 1195 switch (param->param) { 1196 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1197 param->min = 0; 1198 param->max = 255; 1199 param->curval = dp->rd_bl_level; 1200 return 0; 1201 case WSDISPLAYIO_PARAM_BACKLIGHT: 1202 param->min = 0; 1203 param->max = RADEONFB_BACKLIGHT_MAX; 1204 param->curval = dp->rd_bl_on; 1205 return 0; 1206 } 1207 return EPASSTHROUGH; 1208 1209 case WSDISPLAYIO_SETPARAM: 1210 param = (struct wsdisplay_param *)d; 1211 switch (param->param) { 1212 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1213 radeonfb_set_backlight(dp, param->curval); 1214 return 0; 1215 case WSDISPLAYIO_PARAM_BACKLIGHT: 1216 radeonfb_switch_backlight(dp, param->curval); 1217 return 0; 1218 } 1219 return EPASSTHROUGH; 1220 1221 /* PCI config read/write passthrough. */ 1222 case PCI_IOC_CFGREAD: 1223 case PCI_IOC_CFGWRITE: 1224 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1225 1226 case WSDISPLAYIO_GET_BUSID: 1227 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1228 sc->sc_pt, d); 1229 1230 case WSDISPLAYIO_GET_EDID: { 1231 struct wsdisplayio_edid_info *ei = d; 1232 return wsdisplayio_get_edid(sc->sc_dev, ei); 1233 } 1234 1235 case WSDISPLAYIO_GET_FBINFO: { 1236 struct wsdisplayio_fbinfo *fbi = d; 1237 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1238 } 1239 1240 default: 1241 return EPASSTHROUGH; 1242 } 1243 } 1244 1245 paddr_t 1246 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1247 { 1248 struct vcons_data *vd; 1249 struct radeonfb_display *dp; 1250 struct radeonfb_softc *sc; 1251 paddr_t pa; 1252 1253 vd = (struct vcons_data *)v; 1254 dp = (struct radeonfb_display *)vd->cookie; 1255 sc = dp->rd_softc; 1256 1257 /* XXX: note that we don't allow mapping of registers right now */ 1258 /* XXX: this means that the XFree86 radeon driver won't work */ 1259 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1260 pa = bus_space_mmap(sc->sc_memt, 1261 sc->sc_memaddr + dp->rd_offset + offset, 0, 1262 prot, BUS_SPACE_MAP_LINEAR); 1263 return pa; 1264 } 1265 1266 #ifdef RADEONFB_MMAP_BARS 1267 /* 1268 * restrict all other mappings to processes with superuser privileges 1269 * or the kernel itself 1270 */ 1271 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1272 NULL, NULL, NULL, NULL) != 0) { 1273 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1274 return -1; 1275 } 1276 1277 if ((offset >= sc->sc_regaddr) && 1278 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1279 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1280 BUS_SPACE_MAP_LINEAR); 1281 } 1282 1283 if ((offset >= sc->sc_memaddr) && 1284 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1285 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1286 BUS_SPACE_MAP_LINEAR); 1287 } 1288 1289 if ((offset >= sc->sc_romaddr) && 1290 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1291 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1292 BUS_SPACE_MAP_LINEAR); 1293 } 1294 1295 #ifdef PCI_MAGIC_IO_RANGE 1296 /* allow mapping of IO space */ 1297 if ((offset >= PCI_MAGIC_IO_RANGE) && 1298 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1299 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1300 0, prot, 0); 1301 return pa; 1302 } 1303 #endif /* PCI_MAGIC_IO_RANGE */ 1304 1305 #endif /* RADEONFB_MMAP_BARS */ 1306 1307 return -1; 1308 } 1309 1310 static void 1311 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1312 { 1313 bus_space_tag_t romt; 1314 bus_space_handle_t romh, biosh; 1315 bus_size_t romsz; 1316 bus_addr_t ptr; 1317 1318 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1319 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1320 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1321 return; 1322 } 1323 1324 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1325 &sc->sc_biossz); 1326 if (sc->sc_biossz == 0) { 1327 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1328 return; 1329 } 1330 1331 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1332 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1333 1334 /* unmap the PCI expansion rom */ 1335 bus_space_unmap(romt, romh, romsz); 1336 1337 /* turn off rom decoder now */ 1338 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1339 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1340 ~PCI_MAPREG_ROM_ENABLE); 1341 1342 ptr = GETBIOS16(sc, 0x48); 1343 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1344 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1345 sc->sc_flags |= RFB_ATOM; 1346 } 1347 1348 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1349 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1350 } 1351 1352 1353 uint32_t 1354 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1355 { 1356 1357 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1358 } 1359 1360 void 1361 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1362 { 1363 1364 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1365 } 1366 1367 void 1368 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1369 { 1370 1371 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1372 } 1373 1374 void 1375 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1376 uint32_t andmask, uint32_t ormask) 1377 { 1378 int s; 1379 uint32_t val; 1380 1381 s = splhigh(); 1382 val = radeonfb_get32(sc, reg); 1383 val = (val & andmask) | ormask; 1384 radeonfb_put32(sc, reg, val); 1385 splx(s); 1386 } 1387 1388 uint32_t 1389 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1390 { 1391 int s; 1392 uint32_t val; 1393 1394 s = splhigh(); 1395 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1396 val = radeonfb_get32(sc, RADEON_MM_DATA); 1397 splx(s); 1398 1399 return (val); 1400 } 1401 1402 void 1403 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1404 { 1405 int s; 1406 1407 s = splhigh(); 1408 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1409 radeonfb_put32(sc, RADEON_MM_DATA, val); 1410 splx(s); 1411 } 1412 1413 void 1414 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1415 uint32_t andmask, uint32_t ormask) 1416 { 1417 int s; 1418 uint32_t val; 1419 1420 s = splhigh(); 1421 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1422 val = radeonfb_get32(sc, RADEON_MM_DATA); 1423 val = (val & andmask) | ormask; 1424 radeonfb_put32(sc, RADEON_MM_DATA, val); 1425 splx(s); 1426 } 1427 1428 uint32_t 1429 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1430 { 1431 int s; 1432 uint32_t val; 1433 1434 s = splhigh(); 1435 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1436 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1437 if (HAS_R300CG(sc)) 1438 radeonfb_r300cg_workaround(sc); 1439 splx(s); 1440 1441 return (val); 1442 } 1443 1444 void 1445 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1446 { 1447 int s; 1448 1449 s = splhigh(); 1450 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1451 RADEON_PLL_WR_EN); 1452 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1453 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1454 splx(s); 1455 } 1456 1457 void 1458 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1459 uint32_t andmask, uint32_t ormask) 1460 { 1461 int s; 1462 uint32_t val; 1463 1464 s = splhigh(); 1465 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1466 RADEON_PLL_WR_EN); 1467 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1468 val = (val & andmask) | ormask; 1469 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1470 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1471 splx(s); 1472 } 1473 1474 int 1475 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1476 { 1477 uint32_t saved; 1478 1479 saved = GET32(sc, reg); 1480 PUT32(sc, reg, v); 1481 if (GET32(sc, reg) != v) { 1482 return -1; 1483 } 1484 PUT32(sc, reg, saved); 1485 return 0; 1486 } 1487 1488 uintmax_t 1489 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1490 uintmax_t defval) 1491 { 1492 prop_number_t pn; 1493 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1494 if (pn == NULL) { 1495 return defval; 1496 } 1497 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1498 return (prop_number_integer_value(pn)); 1499 } 1500 1501 int 1502 radeonfb_getclocks(struct radeonfb_softc *sc) 1503 { 1504 bus_addr_t ptr; 1505 int refclk = 0; 1506 int refdiv = 0; 1507 int minpll = 0; 1508 int maxpll = 0; 1509 1510 /* load initial property values if port/board provides them */ 1511 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1512 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1513 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1514 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1515 1516 PRINTPLL(RADEON_PPLL_REF_DIV); 1517 PRINTPLL(RADEON_PPLL_DIV_0); 1518 PRINTPLL(RADEON_PPLL_DIV_1); 1519 PRINTPLL(RADEON_PPLL_DIV_2); 1520 PRINTPLL(RADEON_PPLL_DIV_3); 1521 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1522 PRINTPLL(RADEON_P2PLL_REF_DIV); 1523 PRINTPLL(RADEON_P2PLL_DIV_0); 1524 1525 if (refclk && refdiv && minpll && maxpll) 1526 goto dontprobe; 1527 1528 if (!sc->sc_biossz) { 1529 /* no BIOS */ 1530 aprint_verbose("%s: No video BIOS, using default clocks\n", 1531 XNAME(sc)); 1532 if (IS_IGP(sc)) 1533 refclk = refclk ? refclk : 1432; 1534 else 1535 refclk = refclk ? refclk : 2700; 1536 refdiv = refdiv ? refdiv : 12; 1537 minpll = minpll ? minpll : 12500; 1538 /* XXX 1539 * Need to check if the firmware or something programmed a 1540 * higher value than this, and if so, bump it. 1541 * The RV280 in my iBook is unhappy if the PLL input is less 1542 * than 360MHz 1543 */ 1544 maxpll = maxpll ? maxpll : 40000/*35000*/; 1545 } else if (IS_ATOM(sc)) { 1546 /* ATOM BIOS */ 1547 ptr = GETBIOS16(sc, 0x48); 1548 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1549 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1550 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1551 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1552 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1553 /* 1554 * ATOM BIOS doesn't supply a reference divider, so we 1555 * have to probe for it. 1556 */ 1557 if (refdiv < 2) 1558 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1559 RADEON_PPLL_REF_DIV_MASK; 1560 /* 1561 * if probe is zero, just assume one that should work 1562 * for most parts 1563 */ 1564 if (refdiv < 2) 1565 refdiv = 12; 1566 1567 } else { 1568 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1569 /* Legacy BIOS */ 1570 ptr = GETBIOS16(sc, 0x48); 1571 ptr = GETBIOS16(sc, ptr + 0x30); 1572 if (IS_R300(sc)) { 1573 refdiv = refdiv ? refdiv : 1574 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1575 R300_PPLL_REF_DIV_ACC_SHIFT; 1576 } else { 1577 refdiv = refdiv ? refdiv : 1578 tmp & RADEON_PPLL_REF_DIV_MASK; 1579 } 1580 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1581 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1582 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1583 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1584 } 1585 1586 1587 dontprobe: 1588 sc->sc_refclk = refclk * 10; 1589 sc->sc_refdiv = refdiv; 1590 sc->sc_minpll = minpll * 10; 1591 sc->sc_maxpll = maxpll * 10; 1592 return 0; 1593 } 1594 1595 int 1596 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1597 uint32_t *postdivbit, uint32_t *feedbackdiv) 1598 { 1599 int i; 1600 uint32_t outfreq; 1601 int div; 1602 1603 DPRINTF(("dot clock: %u\n", dotclock)); 1604 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1605 outfreq = div * dotclock; 1606 if ((outfreq >= sc->sc_minpll) && 1607 (outfreq <= sc->sc_maxpll)) { 1608 DPRINTF(("outfreq: %u\n", outfreq)); 1609 *postdivbit = 1610 ((uint32_t)radeonfb_dividers[i].mask << 16); 1611 DPRINTF(("post divider: %d (mask %x)\n", div, 1612 *postdivbit)); 1613 break; 1614 } 1615 } 1616 1617 if (div == 0) 1618 return 1; 1619 1620 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1621 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1622 return 0; 1623 } 1624 1625 #if 0 1626 #ifdef RADEONFB_DEBUG 1627 static void 1628 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1629 { 1630 char asc[17]; 1631 unsigned ptr = (unsigned)buffer; 1632 char *start = (char *)(ptr & ~0xf); 1633 char *end = (char *)(ptr + size); 1634 1635 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1636 1637 if (pfx == NULL) { 1638 pfx = ""; 1639 } 1640 1641 while (start < end) { 1642 unsigned offset = (unsigned)start & 0xf; 1643 if (offset == 0) { 1644 printf("%s%x: ", pfx, (unsigned)start); 1645 } 1646 if (((unsigned)start < ptr) || 1647 ((unsigned)start >= (ptr + size))) { 1648 printf(" "); 1649 asc[offset] = ' '; 1650 } else { 1651 printf("%02x", *(unsigned char *)start); 1652 if ((*start >= ' ') && (*start <= '~')) { 1653 asc[offset] = *start; 1654 } else { 1655 asc[offset] = '.'; 1656 } 1657 } 1658 asc[offset + 1] = 0; 1659 if (offset % 2) { 1660 printf(" "); 1661 } 1662 if (offset == 15) { 1663 printf(" %s\n", asc); 1664 } 1665 start++; 1666 } 1667 } 1668 #endif 1669 #endif 1670 1671 int 1672 radeonfb_getconnectors(struct radeonfb_softc *sc) 1673 { 1674 int i; 1675 int found = 0; 1676 1677 for (i = 0; i < 2; i++) { 1678 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1679 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1680 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1681 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1682 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1683 } 1684 1685 /* 1686 * This logic is borrowed from Xorg's radeon driver. 1687 */ 1688 if (!sc->sc_biossz) 1689 goto nobios; 1690 1691 if (IS_ATOM(sc)) { 1692 /* not done yet */ 1693 } else { 1694 uint16_t ptr; 1695 int port = 0; 1696 1697 ptr = GETBIOS16(sc, 0x48); 1698 ptr = GETBIOS16(sc, ptr + 0x50); 1699 for (i = 1; i < 4; i++) { 1700 uint16_t entry; 1701 uint8_t conn, ddc, dac, tmds; 1702 1703 /* 1704 * Parse the connector table. From reading the code, 1705 * it appears to made up of 16-bit entries for each 1706 * connector. The 16-bits are defined as: 1707 * 1708 * bits 12-15 - connector type (0 == end of table) 1709 * bits 8-11 - DDC type 1710 * bits 5-7 - ??? 1711 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1712 * bits 1-3 - ??? 1713 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1714 */ 1715 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1716 break; 1717 entry = GETBIOS16(sc, ptr + i * 2); 1718 1719 conn = (entry >> 12) & 0xf; 1720 ddc = (entry >> 8) & 0xf; 1721 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1722 RADEON_DAC_PRIMARY; 1723 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1724 RADEON_TMDS_INT; 1725 1726 if (conn == RADEON_CONN_NONE) 1727 continue; /* no connector */ 1728 1729 if ((found > 0) && 1730 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1731 /* duplicate entry for same connector */ 1732 continue; 1733 } 1734 1735 /* internal DDC_DVI port gets priority */ 1736 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1737 port = 0; 1738 else 1739 port = 1; 1740 1741 sc->sc_ports[port].rp_ddc_type = 1742 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1743 sc->sc_ports[port].rp_dac_type = dac; 1744 sc->sc_ports[port].rp_conn_type = 1745 min(conn, RADEON_CONN_UNSUPPORTED) ; 1746 1747 sc->sc_ports[port].rp_tmds_type = tmds; 1748 1749 if ((conn != RADEON_CONN_DVI_I) && 1750 (conn != RADEON_CONN_DVI_D) && 1751 (tmds == RADEON_TMDS_INT)) 1752 sc->sc_ports[port].rp_tmds_type = 1753 RADEON_TMDS_UNKNOWN; 1754 sc->sc_ports[port].rp_number = i - 1; 1755 1756 found += (port + 1); 1757 } 1758 } 1759 1760 nobios: 1761 if (!found) { 1762 DPRINTF(("No connector info in BIOS!\n")); 1763 if IS_MOBILITY(sc) { 1764 /* default, port 0 = internal TMDS, port 1 = CRT */ 1765 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1766 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1767 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1768 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1769 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1770 sc->sc_ports[0].rp_number = 0; 1771 1772 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1773 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1774 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1775 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1776 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1777 sc->sc_ports[1].rp_number = 1; 1778 } else { 1779 /* default, port 0 = DVI, port 1 = CRT */ 1780 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1781 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1782 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1783 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1784 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1785 sc->sc_ports[0].rp_number = 1; 1786 1787 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1788 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1789 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1790 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1791 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1792 sc->sc_ports[1].rp_number = 0; 1793 } 1794 } 1795 1796 /* 1797 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1798 * these chips should use TVDAC for the VGA port. 1799 */ 1800 if (HAS_SDAC(sc)) { 1801 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1802 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1803 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1804 } else { 1805 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1806 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1807 } 1808 } else if (!HAS_CRTC2(sc)) { 1809 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1810 } 1811 1812 for (i = 0; i < 2; i++) { 1813 char edid[128]; 1814 uint8_t ddc; 1815 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1816 prop_data_t edid_data; 1817 1818 DPRINTF(("Port #%d:\n", i)); 1819 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1820 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1821 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1822 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1823 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1824 1825 sc->sc_ports[i].rp_edid_valid = 0; 1826 /* first look for static EDID data */ 1827 if ((edid_data = prop_dictionary_get(device_properties( 1828 sc->sc_dev), "EDID")) != NULL) { 1829 1830 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1831 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1832 if (edid_parse(edid, eip) == 0) { 1833 1834 sc->sc_ports[i].rp_edid_valid = 1; 1835 } 1836 } 1837 /* if we didn't find any we'll try to talk to the monitor */ 1838 if (sc->sc_ports[i].rp_edid_valid != 1) { 1839 1840 ddc = sc->sc_ports[i].rp_ddc_type; 1841 if (ddc != RADEON_DDC_NONE) { 1842 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1843 == 0) && (edid_parse(edid, eip) == 0)) { 1844 1845 sc->sc_ports[i].rp_edid_valid = 1; 1846 #ifdef RADEONFB_DEBUG 1847 edid_print(eip); 1848 #endif 1849 } 1850 } 1851 } 1852 } 1853 1854 return found; 1855 } 1856 1857 int 1858 radeonfb_gettmds(struct radeonfb_softc *sc) 1859 { 1860 int i; 1861 1862 if (!sc->sc_biossz) { 1863 goto nobios; 1864 } 1865 1866 if (IS_ATOM(sc)) { 1867 /* XXX: not done yet */ 1868 } else { 1869 uint16_t ptr; 1870 int n; 1871 1872 ptr = GETBIOS16(sc, 0x48); 1873 ptr = GETBIOS16(sc, ptr + 0x34); 1874 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1875 if (GETBIOS8(sc, ptr) == 3) { 1876 /* revision three table */ 1877 n = GETBIOS8(sc, ptr + 5) + 1; 1878 n = min(n, 4); 1879 1880 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1881 for (i = 0; i < n; i++) { 1882 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1883 ptr + i * 10 + 8); 1884 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1885 ptr + i * 10 + 0x10); 1886 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1887 sc->sc_tmds_pll[i].rtp_freq, 1888 sc->sc_tmds_pll[i].rtp_pll)); 1889 } 1890 return 0; 1891 } 1892 } 1893 1894 nobios: 1895 DPRINTF(("no suitable DFP table present\n")); 1896 for (i = 0; 1897 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1898 i++) { 1899 int j; 1900 1901 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1902 continue; 1903 1904 for (j = 0; j < 4; j++) { 1905 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1906 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1907 sc->sc_tmds_pll[j].rtp_freq, 1908 sc->sc_tmds_pll[j].rtp_pll)); 1909 } 1910 return 0; 1911 } 1912 1913 return -1; 1914 } 1915 1916 const struct videomode * 1917 radeonfb_modelookup(const char *name) 1918 { 1919 int i; 1920 1921 for (i = 0; i < videomode_count; i++) 1922 if (!strcmp(name, videomode_list[i].name)) 1923 return &videomode_list[i]; 1924 1925 return NULL; 1926 } 1927 1928 void 1929 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1930 { 1931 if (crtc) { 1932 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1933 RADEON_P2PLL_ATOMIC_UPDATE_R); 1934 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1935 } else { 1936 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1937 RADEON_PPLL_ATOMIC_UPDATE_R); 1938 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1939 } 1940 } 1941 1942 void 1943 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1944 { 1945 int i; 1946 1947 for (i = 10000; i; i--) { 1948 if (crtc) { 1949 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1950 RADEON_P2PLL_ATOMIC_UPDATE_R) 1951 break; 1952 } else { 1953 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1954 RADEON_PPLL_ATOMIC_UPDATE_R) 1955 break; 1956 } 1957 } 1958 } 1959 1960 void 1961 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1962 { 1963 uint32_t pbit = 0; 1964 uint32_t feed = 0; 1965 uint32_t data, refdiv, div0; 1966 1967 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1968 1969 if (crtc == 0) { 1970 1971 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1972 if (IS_R300(sc)) { 1973 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1974 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1975 } else { 1976 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1977 sc->sc_refdiv; 1978 } 1979 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1980 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1981 RADEON_PPLL_POST3_DIV_MASK); 1982 div0 |= pbit; 1983 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1984 1985 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1986 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1987 /* 1988 * nothing to do here, the PLL is already where we 1989 * want it 1990 */ 1991 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1992 ~RADEON_PLL_DIV_SEL); 1993 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1994 return; 1995 } 1996 1997 /* alright, we do need to reprogram stuff */ 1998 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1999 RADEON_VCLK_SRC_SEL_CPUCLK, 2000 ~RADEON_VCLK_SRC_SEL_MASK); 2001 2002 /* put vclk into reset, use atomic updates */ 2003 SETPLL(sc, RADEON_PPLL_CNTL, 2004 RADEON_PPLL_REFCLK_SEL | 2005 RADEON_PPLL_FBCLK_SEL | 2006 RADEON_PPLL_RESET | 2007 RADEON_PPLL_ATOMIC_UPDATE_EN | 2008 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2009 2010 /* select clock 0 */ 2011 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2012 ~RADEON_PLL_DIV_SEL); 2013 2014 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2015 2016 /* xf86-video-radeon does this, not sure why */ 2017 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2018 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2019 2020 /* use the atomic update */ 2021 radeonfb_pllwriteupdate(sc, crtc); 2022 2023 /* and wait for it to complete */ 2024 radeonfb_pllwaitatomicread(sc, crtc); 2025 2026 /* program HTOTAL (why?) */ 2027 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2028 2029 /* drop reset */ 2030 CLRPLL(sc, RADEON_PPLL_CNTL, 2031 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2032 RADEON_PPLL_ATOMIC_UPDATE_EN | 2033 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2034 2035 PRINTPLL(RADEON_PPLL_CNTL); 2036 PRINTPLL(RADEON_PPLL_REF_DIV); 2037 PRINTPLL(RADEON_PPLL_DIV_3); 2038 2039 /* give clock time to lock */ 2040 delay(50000); 2041 2042 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2043 RADEON_VCLK_SRC_SEL_PPLLCLK, 2044 ~RADEON_VCLK_SRC_SEL_MASK); 2045 2046 } else { 2047 2048 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2049 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2050 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2051 2052 /* put vclk into reset, use atomic updates */ 2053 SETPLL(sc, RADEON_P2PLL_CNTL, 2054 RADEON_P2PLL_RESET | 2055 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2056 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2057 2058 /* program reference divider */ 2059 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2060 ~RADEON_P2PLL_REF_DIV_MASK); 2061 2062 /* program feedback and post dividers */ 2063 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2064 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2065 RADEON_P2PLL_POST0_DIV_MASK); 2066 data |= pbit; 2067 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2068 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2069 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2070 2071 PRINTPLL(RADEON_P2PLL_REF_DIV); 2072 PRINTPLL(RADEON_P2PLL_DIV_0); 2073 2074 /* use the atomic update */ 2075 radeonfb_pllwriteupdate(sc, crtc); 2076 2077 /* and wait for it to complete */ 2078 radeonfb_pllwaitatomicread(sc, crtc); 2079 2080 /* program HTOTAL (why?) */ 2081 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2082 2083 /* drop reset */ 2084 CLRPLL(sc, RADEON_P2PLL_CNTL, 2085 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2086 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2087 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2088 2089 /* allow time for clock to lock */ 2090 delay(50000); 2091 2092 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2093 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2094 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2095 } 2096 PRINTREG(RADEON_CRTC_MORE_CNTL); 2097 } 2098 2099 void 2100 radeonfb_modeswitch(struct radeonfb_display *dp) 2101 { 2102 struct radeonfb_softc *sc = dp->rd_softc; 2103 int i; 2104 2105 /* blank the display while we switch modes */ 2106 radeonfb_blank(dp, 1); 2107 2108 #if 0 2109 SET32(sc, RADEON_CRTC_EXT_CNTL, 2110 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2111 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2112 #endif 2113 2114 /* these registers might get in the way... */ 2115 PUT32(sc, RADEON_OVR_CLR, 0); 2116 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2117 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2118 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2119 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2120 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2121 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2122 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2123 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2124 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2125 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2126 2127 for (i = 0; i < dp->rd_ncrtcs; i++) 2128 radeonfb_setcrtc(dp, i); 2129 2130 /* activate the display */ 2131 radeonfb_blank(dp, 0); 2132 } 2133 2134 void 2135 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2136 { 2137 int crtc; 2138 struct videomode *mode; 2139 struct radeonfb_softc *sc; 2140 struct radeonfb_crtc *cp; 2141 uint32_t v; 2142 uint32_t gencntl; 2143 uint32_t htotaldisp; 2144 uint32_t hsyncstrt; 2145 uint32_t vtotaldisp; 2146 uint32_t vsyncstrt; 2147 uint32_t fphsyncstrt; 2148 uint32_t fpvsyncstrt; 2149 uint32_t fphtotaldisp; 2150 uint32_t fpvtotaldisp; 2151 uint32_t pitch; 2152 2153 sc = dp->rd_softc; 2154 cp = &dp->rd_crtcs[index]; 2155 crtc = cp->rc_number; 2156 mode = &cp->rc_videomode; 2157 2158 #if 1 2159 pitch = dp->rd_stride / dp->rd_bpp; 2160 #else 2161 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2162 (sc->sc_maxbpp * 8)); 2163 #endif 2164 switch (crtc) { 2165 case 0: 2166 gencntl = RADEON_CRTC_GEN_CNTL; 2167 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2168 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2169 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2170 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2171 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2172 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2173 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2174 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2175 break; 2176 case 1: 2177 gencntl = RADEON_CRTC2_GEN_CNTL; 2178 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2179 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2180 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2181 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2182 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2183 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2184 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2185 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2186 break; 2187 default: 2188 panic("Bad CRTC!"); 2189 break; 2190 } 2191 2192 /* 2193 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2194 */ 2195 /* only bother with 32bpp and 8bpp */ 2196 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2197 2198 if (crtc == 1) { 2199 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2200 } else { 2201 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2202 } 2203 2204 if (mode->flags & VID_DBLSCAN) 2205 v |= RADEON_CRTC2_DBL_SCAN_EN; 2206 2207 if (mode->flags & VID_INTERLACE) 2208 v |= RADEON_CRTC2_INTERLACE_EN; 2209 2210 if (mode->flags & VID_CSYNC) { 2211 v |= RADEON_CRTC2_CSYNC_EN; 2212 if (crtc == 1) 2213 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2214 } 2215 2216 PUT32(sc, gencntl, v); 2217 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2218 2219 /* 2220 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2221 */ 2222 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2223 if (crtc == 0) { 2224 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2225 RADEON_CRTC_DISPLAY_DIS); 2226 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2227 if (mode->flags & VID_CSYNC) 2228 v |= RADEON_CRTC_VSYNC_TRISTAT; 2229 } 2230 /* unconditional turn on CRT, in case first CRTC is DFP */ 2231 v |= RADEON_CRTC_CRT_ON; 2232 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2233 PRINTREG(RADEON_CRTC_EXT_CNTL); 2234 2235 /* 2236 * H_TOTAL_DISP 2237 */ 2238 v = ((mode->hdisplay / 8) - 1) << 16; 2239 v |= (mode->htotal / 8) - 1; 2240 PUT32(sc, htotaldisp, v); 2241 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2242 PUT32(sc, fphtotaldisp, v); 2243 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2244 2245 /* 2246 * H_SYNC_STRT_WID 2247 */ 2248 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2249 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2250 if (mode->flags & VID_NHSYNC) 2251 v |= RADEON_CRTC_H_SYNC_POL; 2252 PUT32(sc, hsyncstrt, v); 2253 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2254 PUT32(sc, fphsyncstrt, v); 2255 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2256 2257 /* 2258 * V_TOTAL_DISP 2259 */ 2260 v = ((mode->vdisplay - 1) << 16); 2261 v |= (mode->vtotal - 1); 2262 PUT32(sc, vtotaldisp, v); 2263 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2264 PUT32(sc, fpvtotaldisp, v); 2265 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2266 2267 /* 2268 * V_SYNC_STRT_WID 2269 */ 2270 v = ((mode->vsync_end - mode->vsync_start) << 16); 2271 v |= (mode->vsync_start - 1); 2272 if (mode->flags & VID_NVSYNC) 2273 v |= RADEON_CRTC_V_SYNC_POL; 2274 PUT32(sc, vsyncstrt, v); 2275 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2276 PUT32(sc, fpvsyncstrt, v); 2277 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2278 2279 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2280 2281 switch (crtc) { 2282 case 0: 2283 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2284 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2285 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2286 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2287 2288 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2289 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2290 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2291 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2292 PRINTREG(RADEON_CRTC_EXT_CNTL); 2293 PRINTREG(RADEON_CRTC_GEN_CNTL); 2294 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2295 break; 2296 2297 case 1: 2298 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2299 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2300 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2301 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2302 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2303 RADEON_CRTC2_VSYNC_DIS | 2304 RADEON_CRTC2_HSYNC_DIS | 2305 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2306 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2307 break; 2308 } 2309 } 2310 2311 int 2312 radeonfb_isblank(struct radeonfb_display *dp) 2313 { 2314 uint32_t reg, mask; 2315 2316 if(!dp->rd_softc->sc_mapped) 2317 return 1; 2318 2319 if (dp->rd_crtcs[0].rc_number) { 2320 reg = RADEON_CRTC2_GEN_CNTL; 2321 mask = RADEON_CRTC2_DISP_DIS; 2322 } else { 2323 reg = RADEON_CRTC_EXT_CNTL; 2324 mask = RADEON_CRTC_DISPLAY_DIS; 2325 } 2326 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2327 } 2328 2329 void 2330 radeonfb_blank(struct radeonfb_display *dp, int blank) 2331 { 2332 struct radeonfb_softc *sc = dp->rd_softc; 2333 uint32_t reg, mask; 2334 uint32_t fpreg, fpval; 2335 int i; 2336 2337 if (!sc->sc_mapped) 2338 return; 2339 2340 for (i = 0; i < dp->rd_ncrtcs; i++) { 2341 2342 if (dp->rd_crtcs[i].rc_number) { 2343 reg = RADEON_CRTC2_GEN_CNTL; 2344 mask = RADEON_CRTC2_DISP_DIS; 2345 fpreg = RADEON_FP2_GEN_CNTL; 2346 fpval = RADEON_FP2_ON; 2347 } else { 2348 reg = RADEON_CRTC_EXT_CNTL; 2349 mask = RADEON_CRTC_DISPLAY_DIS; 2350 fpreg = RADEON_FP_GEN_CNTL; 2351 fpval = RADEON_FP_FPON; 2352 } 2353 2354 if (blank) { 2355 SET32(sc, reg, mask); 2356 CLR32(sc, fpreg, fpval); 2357 } else { 2358 CLR32(sc, reg, mask); 2359 SET32(sc, fpreg, fpval); 2360 } 2361 } 2362 PRINTREG(RADEON_FP_GEN_CNTL); 2363 PRINTREG(RADEON_FP2_GEN_CNTL); 2364 } 2365 2366 void 2367 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2368 long *defattr) 2369 { 2370 struct radeonfb_display *dp = cookie; 2371 struct rasops_info *ri = &scr->scr_ri; 2372 2373 /* initialize font subsystem */ 2374 wsfont_init(); 2375 2376 DPRINTF(("init screen called, existing %d\n", existing)); 2377 2378 ri->ri_depth = dp->rd_bpp; 2379 ri->ri_width = dp->rd_virtx; 2380 ri->ri_height = dp->rd_virty; 2381 ri->ri_stride = dp->rd_stride; 2382 ri->ri_flg = RI_CENTER; 2383 switch (ri->ri_depth) { 2384 case 8: 2385 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2386 break; 2387 case 32: 2388 ri->ri_flg |= RI_ENABLE_ALPHA; 2389 /* we run radeons in RGB even on SPARC hardware */ 2390 ri->ri_rnum = 8; 2391 ri->ri_gnum = 8; 2392 ri->ri_bnum = 8; 2393 ri->ri_rpos = 16; 2394 ri->ri_gpos = 8; 2395 ri->ri_bpos = 0; 2396 break; 2397 } 2398 2399 ri->ri_bits = (void *)dp->rd_fbptr; 2400 2401 #ifdef VCONS_DRAW_INTR 2402 scr->scr_flags |= VCONS_DONT_READ; 2403 #endif 2404 2405 if (existing) { 2406 ri->ri_flg |= RI_CLEAR; 2407 2408 /* start a modeswitch now */ 2409 radeonfb_modeswitch(dp); 2410 } 2411 2412 /* 2413 * XXX: font selection should be based on properties, with some 2414 * normal/reasonable default. 2415 */ 2416 2417 /* initialize and look for an initial font */ 2418 rasops_init(ri, 0, 0); 2419 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2420 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2421 2422 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2423 dp->rd_virtx / ri->ri_font->fontwidth); 2424 2425 /* enable acceleration */ 2426 dp->rd_putchar = ri->ri_ops.putchar; 2427 ri->ri_ops.copyrows = radeonfb_copyrows; 2428 ri->ri_ops.copycols = radeonfb_copycols; 2429 ri->ri_ops.eraserows = radeonfb_eraserows; 2430 ri->ri_ops.erasecols = radeonfb_erasecols; 2431 /* pick a putchar method based on font and Radeon model */ 2432 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2433 /* got a bitmap font */ 2434 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2435 if (IS_R300(dp->rd_softc)) { 2436 /* 2437 * radeonfb_putchar() doesn't work right on some R3xx 2438 * so we use software drawing here, the wrapper just 2439 * makes sure the engine is idle before scribbling 2440 * into vram 2441 */ 2442 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2443 } else 2444 #endif 2445 ri->ri_ops.putchar = radeonfb_putchar; 2446 } else { 2447 /* got an alpha font */ 2448 switch(ri->ri_depth) { 2449 case 32: 2450 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2451 break; 2452 case 8: 2453 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2454 break; 2455 default: 2456 /* XXX this should never happen */ 2457 panic("%s: depth is not 8 or 32 but we got an" \ 2458 " alpha font?!", __func__); 2459 } 2460 } 2461 ri->ri_ops.cursor = radeonfb_cursor; 2462 } 2463 2464 void 2465 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2466 { 2467 uint32_t gen, ext, gen2 = 0; 2468 uint32_t agploc, aperbase, apersize, mcfbloc; 2469 2470 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2471 /* XXX */ 2472 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2473 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2474 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2475 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2476 2477 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2478 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2479 #if 0 2480 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2481 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2482 #endif 2483 2484 if (HAS_CRTC2(sc)) { 2485 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2486 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2487 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2488 } 2489 2490 delay(100000); 2491 2492 mcfbloc = (aperbase >> 16) | 2493 ((aperbase + (apersize - 1)) & 0xffff0000); 2494 2495 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2496 sc->sc_memsz = apersize; 2497 2498 if (((agploc & 0xffff) << 16) != 2499 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2500 agploc = mcfbloc & 0xffff0000U; 2501 agploc |= ((agploc + 0x10000) >> 16); 2502 } 2503 2504 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2505 2506 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2507 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2508 2509 DPRINTF(("aperbase = %u\n", aperbase)); 2510 PRINTREG(RADEON_MC_FB_LOCATION); 2511 PRINTREG(RADEON_MC_AGP_LOCATION); 2512 2513 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2514 2515 if (HAS_CRTC2(sc)) 2516 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2517 2518 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2519 2520 #if 0 2521 /* XXX: what is this AGP garbage? :-) */ 2522 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2523 #endif 2524 2525 delay(100000); 2526 2527 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2528 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2529 2530 if (HAS_CRTC2(sc)) 2531 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2532 } 2533 2534 void 2535 radeonfb_init_misc(struct radeonfb_softc *sc) 2536 { 2537 PUT32(sc, RADEON_BUS_CNTL, 2538 RADEON_BUS_MASTER_DIS | 2539 RADEON_BUS_PREFETCH_MODE_ACT | 2540 RADEON_BUS_PCI_READ_RETRY_EN | 2541 RADEON_BUS_PCI_WRT_RETRY_EN | 2542 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2543 RADEON_BUS_MSTR_RD_MULT | 2544 RADEON_BUS_MSTR_RD_LINE | 2545 RADEON_BUS_RD_DISCARD_EN | 2546 RADEON_BUS_MSTR_DISCONNECT_EN | 2547 RADEON_BUS_READ_BURST); 2548 2549 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2550 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2551 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2552 PUT32(sc, RADEON_RBBM_CNTL, 2553 (3 << RADEON_RB_SETTLE_SHIFT) | 2554 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2555 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2556 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2557 2558 /* XXX: figure out what these mean! */ 2559 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2560 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2561 #if 0 2562 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2563 #endif 2564 2565 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2566 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2567 } 2568 2569 static void 2570 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2571 { 2572 struct radeonfb_softc *sc = dp->rd_softc; 2573 int crtc, cc; 2574 uint32_t vclk; 2575 2576 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2577 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2578 2579 /* initialize the palette for every CRTC used by this display */ 2580 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2581 crtc = dp->rd_crtcs[cc].rc_number; 2582 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2583 2584 if (crtc) 2585 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2586 else 2587 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2588 2589 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2590 PUT32(sc, RADEON_PALETTE_30_DATA, 2591 (r << 22) | (g << 12) | (b << 2)); 2592 } 2593 2594 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2595 } 2596 2597 /* 2598 * This loads a linear color map for true color. 2599 */ 2600 void 2601 radeonfb_init_palette(struct radeonfb_display *dp) 2602 { 2603 int i; 2604 2605 #define DAC_WIDTH ((1 << 10) - 1) 2606 #define CLUT_WIDTH ((1 << 8) - 1) 2607 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2608 2609 if (dp->rd_bpp == 8) { 2610 2611 /* R3G3B2 palette */ 2612 uint32_t tmp, r, g, b; 2613 2614 for (i = 0; i <= CLUT_WIDTH; ++i) { 2615 tmp = i & 0xe0; 2616 2617 /* 2618 * replicate bits so 0xe0 maps to a red value of 0xff 2619 * in order to make white look actually white 2620 */ 2621 tmp |= (tmp >> 3) | (tmp >> 6); 2622 r = tmp; 2623 2624 tmp = (i & 0x1c) << 3; 2625 tmp |= (tmp >> 3) | (tmp >> 6); 2626 g = tmp; 2627 2628 tmp = (i & 0x03) << 6; 2629 tmp |= tmp >> 2; 2630 tmp |= tmp >> 4; 2631 b = tmp; 2632 2633 radeonfb_putpal(dp, i, r, g, b); 2634 } 2635 } else { 2636 /* linear ramp */ 2637 for (i = 0; i <= CLUT_WIDTH; ++i) { 2638 radeonfb_putpal(dp, i, i, i, i); 2639 } 2640 } 2641 } 2642 2643 static int 2644 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2645 { 2646 u_char *r, *g, *b; 2647 u_int index = cm->index; 2648 u_int count = cm->count; 2649 int i, error; 2650 u_char rbuf[256], gbuf[256], bbuf[256]; 2651 2652 #ifdef GENFB_DEBUG 2653 aprint_debug("putcmap: %d %d\n",index, count); 2654 #endif 2655 if (cm->index >= 256 || cm->count > 256 || 2656 (cm->index + cm->count) > 256) 2657 return EINVAL; 2658 error = copyin(cm->red, &rbuf[index], count); 2659 if (error) 2660 return error; 2661 error = copyin(cm->green, &gbuf[index], count); 2662 if (error) 2663 return error; 2664 error = copyin(cm->blue, &bbuf[index], count); 2665 if (error) 2666 return error; 2667 2668 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2669 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2670 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2671 2672 r = &dp->rd_cmap_red[index]; 2673 g = &dp->rd_cmap_green[index]; 2674 b = &dp->rd_cmap_blue[index]; 2675 2676 for (i = 0; i < count; i++) { 2677 radeonfb_putpal(dp, index, *r, *g, *b); 2678 index++; 2679 r++, g++, b++; 2680 } 2681 return 0; 2682 } 2683 2684 static int 2685 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2686 { 2687 u_int index = cm->index; 2688 u_int count = cm->count; 2689 int error; 2690 2691 if (index >= 255 || count > 256 || index + count > 256) 2692 return EINVAL; 2693 2694 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2695 if (error) 2696 return error; 2697 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2698 if (error) 2699 return error; 2700 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2701 if (error) 2702 return error; 2703 2704 return 0; 2705 } 2706 2707 /* 2708 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2709 */ 2710 void 2711 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2712 { 2713 uint32_t tmp, save; 2714 2715 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2716 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2717 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2718 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2719 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2720 } 2721 2722 /* 2723 * Acceleration entry points. 2724 */ 2725 2726 /* this one draws characters using bitmap fonts */ 2727 static void 2728 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2729 { 2730 struct rasops_info *ri = cookie; 2731 struct vcons_screen *scr = ri->ri_hw; 2732 struct radeonfb_display *dp = scr->scr_cookie; 2733 struct radeonfb_softc *sc = dp->rd_softc; 2734 struct wsdisplay_font *font = PICK_FONT(ri, c); 2735 uint32_t w, h; 2736 int xd, yd, offset, i; 2737 uint32_t bg, fg, gmc; 2738 uint32_t reg; 2739 uint8_t *data8; 2740 uint16_t *data16; 2741 void *data; 2742 2743 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2744 return; 2745 2746 if (!CHAR_IN_FONT(c, font)) 2747 return; 2748 2749 w = font->fontwidth; 2750 h = font->fontheight; 2751 2752 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2753 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2754 2755 xd = ri->ri_xorigin + col * w; 2756 yd = ri->ri_yorigin + row * h; 2757 2758 if (c == 0x20) { 2759 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2760 return; 2761 } 2762 data = WSFONT_GLYPH(c, font); 2763 2764 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2765 2766 radeonfb_wait_fifo(sc, 9); 2767 2768 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2769 RADEON_GMC_BRUSH_NONE | 2770 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2771 RADEON_GMC_DST_CLIPPING | 2772 RADEON_ROP3_S | 2773 RADEON_DP_SRC_SOURCE_HOST_DATA | 2774 RADEON_GMC_CLR_CMP_CNTL_DIS | 2775 RADEON_GMC_WR_MSK_DIS | 2776 gmc); 2777 2778 PUT32(sc, RADEON_SC_LEFT, xd); 2779 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2780 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2781 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2782 PUT32(sc, RADEON_DP_CNTL, 2783 RADEON_DST_X_LEFT_TO_RIGHT | 2784 RADEON_DST_Y_TOP_TO_BOTTOM); 2785 2786 PUT32(sc, RADEON_SRC_X_Y, 0); 2787 offset = 32 - (font->stride << 3); 2788 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2789 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2790 2791 radeonfb_wait_fifo(sc, h); 2792 switch (font->stride) { 2793 case 1: { 2794 data8 = data; 2795 for (i = 0; i < h; i++) { 2796 reg = *data8; 2797 #if BYTE_ORDER == LITTLE_ENDIAN 2798 reg = reg << 24; 2799 #endif 2800 bus_space_write_stream_4(sc->sc_regt, 2801 sc->sc_regh, RADEON_HOST_DATA0, reg); 2802 data8++; 2803 } 2804 break; 2805 } 2806 case 2: { 2807 data16 = data; 2808 for (i = 0; i < h; i++) { 2809 reg = *data16; 2810 #if BYTE_ORDER == LITTLE_ENDIAN 2811 reg = reg << 16; 2812 #endif 2813 bus_space_write_stream_4(sc->sc_regt, 2814 sc->sc_regh, RADEON_HOST_DATA0, reg); 2815 data16++; 2816 } 2817 break; 2818 } 2819 } 2820 if (attr & 1) 2821 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2822 } 2823 2824 /* ... while this one is for anti-aliased ones */ 2825 static void 2826 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2827 { 2828 struct rasops_info *ri = cookie; 2829 struct vcons_screen *scr = ri->ri_hw; 2830 struct radeonfb_display *dp = scr->scr_cookie; 2831 struct radeonfb_softc *sc = dp->rd_softc; 2832 struct wsdisplay_font *font = PICK_FONT(ri, c); 2833 uint32_t bg, fg, gmc; 2834 uint8_t *data; 2835 int w, h, xd, yd; 2836 int i, r, g, b, aval; 2837 int rf, gf, bf, rb, gb, bb; 2838 uint32_t pixel; 2839 int rv; 2840 2841 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2842 return; 2843 2844 if (!CHAR_IN_FONT(c, font)) 2845 return; 2846 2847 w = font->fontwidth; 2848 h = font->fontheight; 2849 2850 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2851 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2852 2853 xd = ri->ri_xorigin + col * w; 2854 yd = ri->ri_yorigin + row * h; 2855 2856 if (c == 0x20) { 2857 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2858 if (attr & 1) 2859 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2860 return; 2861 } 2862 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2863 if (rv == GC_OK) 2864 return; 2865 2866 data = WSFONT_GLYPH(c, font); 2867 2868 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2869 2870 radeonfb_wait_fifo(sc, 5); 2871 2872 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2873 RADEON_GMC_BRUSH_NONE | 2874 RADEON_GMC_SRC_DATATYPE_COLOR | 2875 RADEON_ROP3_S | 2876 RADEON_DP_SRC_SOURCE_HOST_DATA | 2877 RADEON_GMC_CLR_CMP_CNTL_DIS | 2878 RADEON_GMC_WR_MSK_DIS | 2879 gmc); 2880 2881 PUT32(sc, RADEON_DP_CNTL, 2882 RADEON_DST_X_LEFT_TO_RIGHT | 2883 RADEON_DST_Y_TOP_TO_BOTTOM); 2884 2885 PUT32(sc, RADEON_SRC_X_Y, 0); 2886 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2887 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2888 2889 rf = (fg >> 16) & 0xff; 2890 rb = (bg >> 16) & 0xff; 2891 gf = (fg >> 8) & 0xff; 2892 gb = (bg >> 8) & 0xff; 2893 bf = fg & 0xff; 2894 bb = bg & 0xff; 2895 2896 /* 2897 * I doubt we can upload data faster than even the slowest Radeon 2898 * could process them, especially when doing the alpha blending stuff 2899 * along the way, so just make sure there's some room in the FIFO and 2900 * then hammer away 2901 * As it turns out we can, so make periodic stops to let the FIFO 2902 * drain. 2903 */ 2904 radeonfb_wait_fifo(sc, 20); 2905 for (i = 0; i < ri->ri_fontscale; i++) { 2906 aval = *data; 2907 data++; 2908 if (aval == 0) { 2909 pixel = bg; 2910 } else if (aval == 255) { 2911 pixel = fg; 2912 } else { 2913 r = aval * rf + (255 - aval) * rb; 2914 g = aval * gf + (255 - aval) * gb; 2915 b = aval * bf + (255 - aval) * bb; 2916 pixel = (r & 0xff00) << 8 | 2917 (g & 0xff00) | 2918 (b & 0xff00) >> 8; 2919 } 2920 if (i & 16) 2921 radeonfb_wait_fifo(sc, 20); 2922 PUT32(sc, RADEON_HOST_DATA0, pixel); 2923 } 2924 if (rv == GC_ADD) { 2925 glyphcache_add(&dp->rd_gc, c, xd, yd); 2926 } else 2927 if (attr & 1) 2928 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2929 2930 } 2931 2932 static void 2933 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2934 { 2935 struct rasops_info *ri = cookie; 2936 struct vcons_screen *scr = ri->ri_hw; 2937 struct radeonfb_display *dp = scr->scr_cookie; 2938 struct radeonfb_softc *sc = dp->rd_softc; 2939 struct wsdisplay_font *font = PICK_FONT(ri, c); 2940 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2941 int i, x, y, wi, he, r, g, b, aval; 2942 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2943 uint8_t *data8; 2944 int rv, cnt; 2945 2946 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2947 return; 2948 2949 if (!CHAR_IN_FONT(c, font)) 2950 return; 2951 2952 wi = font->fontwidth; 2953 he = font->fontheight; 2954 2955 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2956 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2957 2958 x = ri->ri_xorigin + col * wi; 2959 y = ri->ri_yorigin + row * he; 2960 2961 if (c == 0x20) { 2962 radeonfb_rectfill(dp, x, y, wi, he, bg); 2963 if (attr & 1) 2964 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2965 return; 2966 } 2967 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2968 if (rv == GC_OK) 2969 return; 2970 2971 data8 = WSFONT_GLYPH(c, font); 2972 2973 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2974 2975 radeonfb_wait_fifo(sc, 5); 2976 2977 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2978 RADEON_GMC_BRUSH_NONE | 2979 RADEON_GMC_SRC_DATATYPE_COLOR | 2980 RADEON_ROP3_S | 2981 RADEON_DP_SRC_SOURCE_HOST_DATA | 2982 RADEON_GMC_CLR_CMP_CNTL_DIS | 2983 RADEON_GMC_WR_MSK_DIS | 2984 gmc); 2985 2986 PUT32(sc, RADEON_DP_CNTL, 2987 RADEON_DST_X_LEFT_TO_RIGHT | 2988 RADEON_DST_Y_TOP_TO_BOTTOM); 2989 2990 PUT32(sc, RADEON_SRC_X_Y, 0); 2991 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2992 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2993 2994 /* 2995 * we need the RGB colours here, so get offsets into rasops_cmap 2996 */ 2997 fgo = ((attr >> 24) & 0xf) * 3; 2998 bgo = ((attr >> 16) & 0xf) * 3; 2999 3000 r0 = rasops_cmap[bgo]; 3001 r1 = rasops_cmap[fgo]; 3002 g0 = rasops_cmap[bgo + 1]; 3003 g1 = rasops_cmap[fgo + 1]; 3004 b0 = rasops_cmap[bgo + 2]; 3005 b1 = rasops_cmap[fgo + 2]; 3006 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3007 bg8 = R3G3B2(r0, g0, b0); 3008 fg8 = R3G3B2(r1, g1, b1); 3009 3010 radeonfb_wait_fifo(sc, 20); 3011 cnt = 0; 3012 for (i = 0; i < ri->ri_fontscale; i++) { 3013 aval = *data8; 3014 if (aval == 0) { 3015 pixel = bg8; 3016 } else if (aval == 255) { 3017 pixel = fg8; 3018 } else { 3019 r = aval * r1 + (255 - aval) * r0; 3020 g = aval * g1 + (255 - aval) * g0; 3021 b = aval * b1 + (255 - aval) * b0; 3022 pixel = ((r & 0xe000) >> 8) | 3023 ((g & 0xe000) >> 11) | 3024 ((b & 0xc000) >> 14); 3025 } 3026 latch |= pixel << (8 * (i & 3)); 3027 /* write in 32bit chunks */ 3028 if ((i & 3) == 3) { 3029 PUT32(sc, RADEON_HOST_DATA0, latch); 3030 /* 3031 * not strictly necessary, old data should be shifted 3032 * out 3033 */ 3034 latch = 0; 3035 cnt++; 3036 if (cnt > 16) { 3037 cnt = 0; 3038 radeonfb_wait_fifo(sc, 20); 3039 } 3040 } 3041 data8++; 3042 } 3043 /* if we have pixels left in latch write them out */ 3044 if ((i & 3) != 0) { 3045 /* 3046 * radeon is weird - apparently leftover pixels are written 3047 * from the middle, not from the left as everything else 3048 */ 3049 PUT32(sc, RADEON_HOST_DATA0, latch); 3050 } 3051 3052 if (rv == GC_ADD) { 3053 glyphcache_add(&dp->rd_gc, c, x, y); 3054 } else 3055 if (attr & 1) 3056 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3057 3058 } 3059 3060 /* 3061 * wrapper for software character drawing 3062 * just sync the engine and call rasops*_putchar() 3063 */ 3064 3065 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3066 static void 3067 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3068 { 3069 struct rasops_info *ri = cookie; 3070 struct vcons_screen *scr = ri->ri_hw; 3071 struct radeonfb_display *dp = scr->scr_cookie; 3072 3073 radeonfb_engine_idle(dp->rd_softc); 3074 dp->rd_putchar(ri, row, col, c, attr); 3075 } 3076 #endif 3077 3078 static void 3079 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3080 { 3081 struct rasops_info *ri = cookie; 3082 struct vcons_screen *scr = ri->ri_hw; 3083 struct radeonfb_display *dp = scr->scr_cookie; 3084 uint32_t x, y, w, h, fg, bg, ul; 3085 3086 /* XXX: check for full emulation mode? */ 3087 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3088 x = ri->ri_xorigin; 3089 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3090 w = ri->ri_emuwidth; 3091 h = ri->ri_font->fontheight * nrows; 3092 3093 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3094 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3095 } 3096 } 3097 3098 static void 3099 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3100 { 3101 struct rasops_info *ri = cookie; 3102 struct vcons_screen *scr = ri->ri_hw; 3103 struct radeonfb_display *dp = scr->scr_cookie; 3104 uint32_t x, ys, yd, w, h; 3105 3106 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3107 x = ri->ri_xorigin; 3108 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3109 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3110 w = ri->ri_emuwidth; 3111 h = ri->ri_font->fontheight * nrows; 3112 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3113 RADEON_ROP3_S); 3114 } 3115 } 3116 3117 static void 3118 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3119 { 3120 struct rasops_info *ri = cookie; 3121 struct vcons_screen *scr = ri->ri_hw; 3122 struct radeonfb_display *dp = scr->scr_cookie; 3123 uint32_t xs, xd, y, w, h; 3124 3125 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3126 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3127 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3128 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3129 w = ri->ri_font->fontwidth * ncols; 3130 h = ri->ri_font->fontheight; 3131 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3132 RADEON_ROP3_S); 3133 } 3134 } 3135 3136 static void 3137 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3138 long fillattr) 3139 { 3140 struct rasops_info *ri = cookie; 3141 struct vcons_screen *scr = ri->ri_hw; 3142 struct radeonfb_display *dp = scr->scr_cookie; 3143 uint32_t x, y, w, h, fg, bg, ul; 3144 3145 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3146 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3147 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3148 w = ri->ri_font->fontwidth * ncols; 3149 h = ri->ri_font->fontheight; 3150 3151 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3152 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3153 } 3154 } 3155 3156 static void 3157 radeonfb_cursor(void *cookie, int on, int row, int col) 3158 { 3159 struct rasops_info *ri = cookie; 3160 struct vcons_screen *scr = ri->ri_hw; 3161 struct radeonfb_display *dp = scr->scr_cookie; 3162 int x, y, wi, he; 3163 3164 wi = ri->ri_font->fontwidth; 3165 he = ri->ri_font->fontheight; 3166 3167 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3168 x = ri->ri_ccol * wi + ri->ri_xorigin; 3169 y = ri->ri_crow * he + ri->ri_yorigin; 3170 /* first turn off the old cursor */ 3171 if (ri->ri_flg & RI_CURSOR) { 3172 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3173 RADEON_ROP3_Dn); 3174 ri->ri_flg &= ~RI_CURSOR; 3175 } 3176 ri->ri_crow = row; 3177 ri->ri_ccol = col; 3178 /* then (possibly) turn on the new one */ 3179 if (on) { 3180 x = ri->ri_ccol * wi + ri->ri_xorigin; 3181 y = ri->ri_crow * he + ri->ri_yorigin; 3182 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3183 RADEON_ROP3_Dn); 3184 ri->ri_flg |= RI_CURSOR; 3185 } 3186 } else { 3187 scr->scr_ri.ri_crow = row; 3188 scr->scr_ri.ri_ccol = col; 3189 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3190 } 3191 } 3192 3193 /* 3194 * Underlying acceleration support. 3195 */ 3196 3197 static void 3198 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3199 int width, int height, uint32_t color) 3200 { 3201 struct radeonfb_softc *sc = dp->rd_softc; 3202 uint32_t gmc; 3203 3204 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3205 3206 radeonfb_wait_fifo(sc, 6); 3207 3208 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3209 RADEON_GMC_BRUSH_SOLID_COLOR | 3210 RADEON_GMC_SRC_DATATYPE_COLOR | 3211 RADEON_GMC_CLR_CMP_CNTL_DIS | 3212 RADEON_ROP3_P | gmc); 3213 3214 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3215 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3216 PUT32(sc, RADEON_DP_CNTL, 3217 RADEON_DST_X_LEFT_TO_RIGHT | 3218 RADEON_DST_Y_TOP_TO_BOTTOM); 3219 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3220 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3221 3222 } 3223 3224 static void 3225 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3226 int width, int height, long attr) 3227 { 3228 struct radeonfb_display *dp = cookie; 3229 3230 radeonfb_rectfill(dp, dstx, dsty, width, height, 3231 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3232 } 3233 3234 static void 3235 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3236 int dstx, int dsty, int width, int height, int rop) 3237 { 3238 struct radeonfb_display *dp = cookie; 3239 struct radeonfb_softc *sc = dp->rd_softc; 3240 uint32_t gmc; 3241 uint32_t dir; 3242 3243 if (dsty < srcy) { 3244 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3245 } else { 3246 srcy += height - 1; 3247 dsty += height - 1; 3248 dir = 0; 3249 } 3250 if (dstx < srcx) { 3251 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3252 } else { 3253 srcx += width - 1; 3254 dstx += width - 1; 3255 } 3256 3257 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3258 3259 radeonfb_wait_fifo(sc, 6); 3260 3261 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3262 RADEON_GMC_BRUSH_SOLID_COLOR | 3263 RADEON_GMC_SRC_DATATYPE_COLOR | 3264 RADEON_GMC_CLR_CMP_CNTL_DIS | 3265 RADEON_DP_SRC_SOURCE_MEMORY | 3266 rop | gmc); 3267 3268 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3269 PUT32(sc, RADEON_DP_CNTL, dir); 3270 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3271 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3272 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3273 } 3274 3275 static void 3276 radeonfb_engine_idle(struct radeonfb_softc *sc) 3277 { 3278 3279 radeonfb_wait_fifo(sc, 64); 3280 while ((GET32(sc, RADEON_RBBM_STATUS) & 3281 RADEON_RBBM_ACTIVE) != 0); 3282 radeonfb_engine_flush(sc); 3283 } 3284 3285 static inline void 3286 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3287 { 3288 int i; 3289 3290 for (i = RADEON_TIMEOUT; i; i--) { 3291 if ((GET32(sc, RADEON_RBBM_STATUS) & 3292 RADEON_RBBM_FIFOCNT_MASK) >= n) 3293 return; 3294 } 3295 #ifdef DIAGNOSTIC 3296 if (!i) 3297 printf("%s: timed out waiting for fifo (%x)\n", 3298 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3299 #endif 3300 } 3301 3302 static void 3303 radeonfb_engine_flush(struct radeonfb_softc *sc) 3304 { 3305 int i = 0; 3306 3307 if (IS_R300(sc)) { 3308 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3309 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3310 i++; 3311 } 3312 } else { 3313 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3314 RADEON_RB2D_DC_FLUSH_ALL); 3315 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3316 RADEON_RB2D_DC_BUSY) { 3317 i++; 3318 } 3319 } 3320 #ifdef DIAGNOSTIC 3321 if (i > RADEON_TIMEOUT) 3322 printf("%s: engine flush timed out!\n", XNAME(sc)); 3323 #endif 3324 } 3325 3326 static inline void 3327 radeonfb_unclip(struct radeonfb_softc *sc) 3328 { 3329 3330 radeonfb_wait_fifo(sc, 2); 3331 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3332 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3333 } 3334 3335 static void 3336 radeonfb_engine_init(struct radeonfb_display *dp) 3337 { 3338 struct radeonfb_softc *sc = dp->rd_softc; 3339 uint32_t pitch; 3340 3341 /* no 3D */ 3342 PUT32(sc, RADEON_RB3D_CNTL, 0); 3343 3344 radeonfb_engine_reset(sc); 3345 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3346 3347 radeonfb_wait_fifo(sc, 1); 3348 if (!IS_R300(sc)) 3349 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3350 3351 radeonfb_wait_fifo(sc, 3); 3352 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3353 (pitch << 22) | (sc->sc_aperbase >> 10)); 3354 3355 3356 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3357 (pitch << 22) | (sc->sc_aperbase >> 10)); 3358 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3359 (pitch << 22) | (sc->sc_aperbase >> 10)); 3360 3361 (void)GET32(sc, RADEON_DP_DATATYPE); 3362 3363 /* default scissors -- no clipping */ 3364 radeonfb_wait_fifo(sc, 1); 3365 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3366 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3367 3368 radeonfb_wait_fifo(sc, 1); 3369 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3370 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3371 RADEON_GMC_CLR_CMP_CNTL_DIS | 3372 RADEON_GMC_BRUSH_SOLID_COLOR | 3373 RADEON_GMC_SRC_DATATYPE_COLOR); 3374 3375 radeonfb_wait_fifo(sc, 10); 3376 PUT32(sc, RADEON_DST_LINE_START, 0); 3377 PUT32(sc, RADEON_DST_LINE_END, 0); 3378 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3379 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3380 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3381 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3382 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3383 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3384 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3385 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3386 radeonfb_engine_idle(sc); 3387 } 3388 3389 static void 3390 radeonfb_engine_reset(struct radeonfb_softc *sc) 3391 { 3392 uint32_t hpc, rbbm, mclkcntl, clkindex; 3393 3394 radeonfb_engine_flush(sc); 3395 3396 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3397 if (HAS_R300CG(sc)) 3398 radeonfb_r300cg_workaround(sc); 3399 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3400 3401 /* 3402 * According to comments in XFree code, resetting the HDP via 3403 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3404 * So we use HOST_PATH_CNTL instead. 3405 */ 3406 3407 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3408 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3409 if (IS_R300(sc)) { 3410 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3411 RADEON_SOFT_RESET_CP | 3412 RADEON_SOFT_RESET_HI | 3413 RADEON_SOFT_RESET_E2); 3414 GET32(sc, RADEON_RBBM_SOFT_RESET); 3415 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3416 /* 3417 * XXX: this bit is not defined in any ATI docs I have, 3418 * nor in the XFree code, but XFree does it. Why? 3419 */ 3420 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3421 } else { 3422 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3423 RADEON_SOFT_RESET_CP | 3424 RADEON_SOFT_RESET_SE | 3425 RADEON_SOFT_RESET_RE | 3426 RADEON_SOFT_RESET_PP | 3427 RADEON_SOFT_RESET_E2 | 3428 RADEON_SOFT_RESET_RB); 3429 GET32(sc, RADEON_RBBM_SOFT_RESET); 3430 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3431 ~(RADEON_SOFT_RESET_CP | 3432 RADEON_SOFT_RESET_SE | 3433 RADEON_SOFT_RESET_RE | 3434 RADEON_SOFT_RESET_PP | 3435 RADEON_SOFT_RESET_E2 | 3436 RADEON_SOFT_RESET_RB)); 3437 GET32(sc, RADEON_RBBM_SOFT_RESET); 3438 } 3439 3440 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3441 GET32(sc, RADEON_HOST_PATH_CNTL); 3442 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3443 3444 if (IS_R300(sc)) 3445 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3446 3447 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3448 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3449 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3450 3451 if (HAS_R300CG(sc)) 3452 radeonfb_r300cg_workaround(sc); 3453 } 3454 3455 static int 3456 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3457 { 3458 int x, y; 3459 3460 x = pos->x; 3461 y = pos->y; 3462 3463 /* 3464 * This doesn't let a cursor move off the screen. I'm not 3465 * sure if this will have negative effects for e.g. Xinerama. 3466 * I'd guess Xinerama handles it by changing the cursor shape, 3467 * but that needs verification. 3468 */ 3469 if (x >= dp->rd_virtx) 3470 x = dp->rd_virtx - 1; 3471 if (x < 0) 3472 x = 0; 3473 if (y >= dp->rd_virty) 3474 y = dp->rd_virty - 1; 3475 if (y < 0) 3476 y = 0; 3477 3478 dp->rd_cursor.rc_pos.x = x; 3479 dp->rd_cursor.rc_pos.y = y; 3480 3481 radeonfb_cursor_position(dp); 3482 return 0; 3483 } 3484 3485 static int 3486 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3487 { 3488 unsigned flags; 3489 3490 uint8_t r[2], g[2], b[2]; 3491 unsigned index, count; 3492 int i, err; 3493 int pitch, size; 3494 struct radeonfb_cursor nc; 3495 3496 flags = wc->which; 3497 3498 /* copy old values */ 3499 nc = dp->rd_cursor; 3500 3501 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3502 index = wc->cmap.index; 3503 count = wc->cmap.count; 3504 3505 if (index >= 2 || (index + count) > 2) 3506 return EINVAL; 3507 3508 err = copyin(wc->cmap.red, &r[index], count); 3509 if (err) 3510 return err; 3511 err = copyin(wc->cmap.green, &g[index], count); 3512 if (err) 3513 return err; 3514 err = copyin(wc->cmap.blue, &b[index], count); 3515 if (err) 3516 return err; 3517 3518 for (i = index; i < index + count; i++) { 3519 nc.rc_cmap[i] = 3520 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3521 } 3522 } 3523 3524 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3525 if ((wc->size.x > RADEON_CURSORMAXX) || 3526 (wc->size.y > RADEON_CURSORMAXY)) 3527 return EINVAL; 3528 3529 /* figure bytes per line */ 3530 pitch = (wc->size.x + 7) / 8; 3531 size = pitch * wc->size.y; 3532 3533 /* clear the old cursor and mask */ 3534 memset(nc.rc_image, 0, 512); 3535 memset(nc.rc_mask, 0, 512); 3536 3537 nc.rc_size = wc->size; 3538 3539 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3540 return err; 3541 3542 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3543 return err; 3544 } 3545 3546 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3547 nc.rc_hot = wc->hot; 3548 if (nc.rc_hot.x >= nc.rc_size.x) 3549 nc.rc_hot.x = nc.rc_size.x - 1; 3550 if (nc.rc_hot.y >= nc.rc_size.y) 3551 nc.rc_hot.y = nc.rc_size.y - 1; 3552 } 3553 3554 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3555 nc.rc_pos = wc->pos; 3556 if (nc.rc_pos.x >= dp->rd_virtx) 3557 nc.rc_pos.x = dp->rd_virtx - 1; 3558 #if 0 3559 if (nc.rc_pos.x < 0) 3560 nc.rc_pos.x = 0; 3561 #endif 3562 if (nc.rc_pos.y >= dp->rd_virty) 3563 nc.rc_pos.y = dp->rd_virty - 1; 3564 #if 0 3565 if (nc.rc_pos.y < 0) 3566 nc.rc_pos.y = 0; 3567 #endif 3568 } 3569 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3570 nc.rc_visible = wc->enable; 3571 } 3572 3573 dp->rd_cursor = nc; 3574 radeonfb_cursor_update(dp, wc->which); 3575 3576 return 0; 3577 } 3578 3579 static uint8_t 3580 radeonfb_backwards(uint8_t d) 3581 { 3582 uint8_t l; 3583 3584 l = d << 7; 3585 l |= ((d & 0x02) << 5); 3586 l |= ((d & 0x04) << 3); 3587 l |= ((d & 0x08) << 1); 3588 l |= ((d & 0x10) >> 1); 3589 l |= ((d & 0x20) >> 3); 3590 l |= ((d & 0x40) >> 5); 3591 l |= ((d & 0x80) >> 7); 3592 return l; 3593 } 3594 3595 /* 3596 * Change the cursor shape. Call this with the cursor locked to avoid 3597 * flickering/tearing. 3598 */ 3599 static void 3600 radeonfb_cursor_shape(struct radeonfb_display *dp) 3601 { 3602 uint8_t and[512], xor[512]; 3603 int i, j, src, dst /* , pitch */; 3604 const uint8_t *msk = dp->rd_cursor.rc_mask; 3605 const uint8_t *img = dp->rd_cursor.rc_image; 3606 3607 /* 3608 * Radeon cursor data interleaves one line of AND data followed 3609 * by a line of XOR data. (Each line corresponds to a whole hardware 3610 * pitch - i.e. 64 pixels or 8 bytes.) 3611 * 3612 * The cursor is displayed using the following table: 3613 * 3614 * AND XOR Result 3615 * ---------------------- 3616 * 0 0 Cursor color 0 3617 * 0 1 Cursor color 1 3618 * 1 0 Transparent 3619 * 1 1 Complement of background 3620 * 3621 * Our masks are therefore different from what we were passed. 3622 * Passed in, I'm assuming the data represents either color 0 or 1, 3623 * and a mask, so the passed in table looks like: 3624 * 3625 * IMG Mask Result 3626 * ----------------------- 3627 * 0 0 Transparent 3628 * 0 1 Cursor color 0 3629 * 1 0 Transparent 3630 * 1 1 Cursor color 1 3631 * 3632 * IF mask bit == 1, AND = 0, XOR = color. 3633 * IF mask bit == 0, AND = 1, XOR = 0. 3634 * 3635 * hence: AND = ~(mask); XOR = color & ~(mask); 3636 */ 3637 3638 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3639 3640 /* start by assuming all bits are transparent */ 3641 memset(and, 0xff, 512); 3642 memset(xor, 0x00, 512); 3643 3644 src = 0; 3645 dst = 0; 3646 for (i = 0; i < 64; i++) { 3647 for (j = 0; j < 64; j += 8) { 3648 if ((i < dp->rd_cursor.rc_size.y) && 3649 (j < dp->rd_cursor.rc_size.x)) { 3650 3651 /* take care to leave odd bits alone */ 3652 and[dst] &= ~(msk[src]); 3653 xor[dst] = img[src] & msk[src]; 3654 src++; 3655 } 3656 dst++; 3657 } 3658 } 3659 3660 for (i = 0; i < 512; i++) { 3661 and[i] = radeonfb_backwards(and[i]); 3662 xor[i] = radeonfb_backwards(xor[i]); 3663 } 3664 3665 /* copy the image into place */ 3666 for (i = 0; i < 64; i++) { 3667 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3668 &and[i * 8], 8); 3669 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3670 &xor[i * 8], 8); 3671 } 3672 } 3673 3674 static void 3675 radeonfb_cursor_position(struct radeonfb_display *dp) 3676 { 3677 struct radeonfb_softc *sc = dp->rd_softc; 3678 uint32_t offset, hvoff, hvpos; /* registers */ 3679 uint32_t coff; /* cursor offset */ 3680 int i, x, y, xoff, yoff, crtcoff; 3681 3682 /* 3683 * XXX: this also needs to handle pan/scan 3684 */ 3685 for (i = 0; i < dp->rd_ncrtcs; i++) { 3686 3687 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3688 3689 if (rcp->rc_number) { 3690 offset = RADEON_CUR2_OFFSET; 3691 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3692 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3693 crtcoff = RADEON_CRTC2_OFFSET; 3694 } else { 3695 offset = RADEON_CUR_OFFSET; 3696 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3697 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3698 crtcoff = RADEON_CRTC_OFFSET; 3699 } 3700 3701 x = dp->rd_cursor.rc_pos.x; 3702 y = dp->rd_cursor.rc_pos.y; 3703 3704 while (y < rcp->rc_yoffset) { 3705 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3706 } 3707 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3708 rcp->rc_yoffset += RADEON_PANINCREMENT; 3709 } 3710 while (x < rcp->rc_xoffset) { 3711 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3712 } 3713 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3714 rcp->rc_xoffset += RADEON_PANINCREMENT; 3715 } 3716 3717 /* adjust for the cursor's hotspot */ 3718 x -= dp->rd_cursor.rc_hot.x; 3719 y -= dp->rd_cursor.rc_hot.y; 3720 xoff = yoff = 0; 3721 3722 if (x >= dp->rd_virtx) 3723 x = dp->rd_virtx - 1; 3724 if (y >= dp->rd_virty) 3725 y = dp->rd_virty - 1; 3726 3727 /* now adjust cursor so it is relative to viewport */ 3728 x -= rcp->rc_xoffset; 3729 y -= rcp->rc_yoffset; 3730 3731 /* 3732 * no need to check for fall off, because we should 3733 * never move off the screen entirely! 3734 */ 3735 coff = 0; 3736 if (x < 0) { 3737 xoff = -x; 3738 x = 0; 3739 } 3740 if (y < 0) { 3741 yoff = -y; 3742 y = 0; 3743 coff = (yoff * 2) * 8; 3744 } 3745 3746 /* pan the display */ 3747 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3748 rcp->rc_xoffset); 3749 3750 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3751 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3752 /* NB: this unlocks the cursor */ 3753 PUT32(sc, hvpos, (x << 16) | y); 3754 } 3755 } 3756 3757 static void 3758 radeonfb_cursor_visible(struct radeonfb_display *dp) 3759 { 3760 int i; 3761 uint32_t gencntl, bit; 3762 3763 for (i = 0; i < dp->rd_ncrtcs; i++) { 3764 if (dp->rd_crtcs[i].rc_number) { 3765 gencntl = RADEON_CRTC2_GEN_CNTL; 3766 bit = RADEON_CRTC2_CUR_EN; 3767 } else { 3768 gencntl = RADEON_CRTC_GEN_CNTL; 3769 bit = RADEON_CRTC_CUR_EN; 3770 } 3771 3772 if (dp->rd_cursor.rc_visible) 3773 SET32(dp->rd_softc, gencntl, bit); 3774 else 3775 CLR32(dp->rd_softc, gencntl, bit); 3776 } 3777 } 3778 3779 static void 3780 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3781 { 3782 int i; 3783 uint32_t c0reg, c1reg; 3784 struct radeonfb_softc *sc = dp->rd_softc; 3785 3786 for (i = 0; i < dp->rd_ncrtcs; i++) { 3787 if (dp->rd_crtcs[i].rc_number) { 3788 c0reg = RADEON_CUR2_CLR0; 3789 c1reg = RADEON_CUR2_CLR1; 3790 } else { 3791 c0reg = RADEON_CUR_CLR0; 3792 c1reg = RADEON_CUR_CLR1; 3793 } 3794 3795 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3796 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3797 } 3798 } 3799 3800 static void 3801 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3802 { 3803 struct radeonfb_softc *sc; 3804 int i; 3805 3806 sc = dp->rd_softc; 3807 for (i = 0; i < dp->rd_ncrtcs; i++) { 3808 if (dp->rd_crtcs[i].rc_number) { 3809 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3810 } else { 3811 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3812 } 3813 } 3814 3815 if (which & WSDISPLAY_CURSOR_DOCMAP) 3816 radeonfb_cursor_cmap(dp); 3817 3818 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3819 radeonfb_cursor_shape(dp); 3820 3821 if (which & WSDISPLAY_CURSOR_DOCUR) 3822 radeonfb_cursor_visible(dp); 3823 3824 /* this one is unconditional, because it updates other stuff */ 3825 radeonfb_cursor_position(dp); 3826 } 3827 3828 static struct videomode * 3829 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3830 { 3831 int r1, r2; 3832 3833 /* otherwise pick the higher refresh rate */ 3834 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3835 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3836 3837 return (r1 < r2 ? m2 : m1); 3838 } 3839 3840 static const struct videomode * 3841 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3842 int x, int y) 3843 { 3844 struct edid_info *ep = &rp->rp_edid; 3845 struct videomode *vmp = NULL; 3846 int i; 3847 3848 if (!rp->rp_edid_valid) { 3849 /* fallback to safe mode */ 3850 return radeonfb_modelookup(sc->sc_defaultmode); 3851 } 3852 3853 /* always choose the preferred mode first! */ 3854 if (ep->edid_preferred_mode) { 3855 3856 /* XXX: add auto-stretching support for native mode */ 3857 3858 /* this may want panning to occur, btw */ 3859 if ((ep->edid_preferred_mode->hdisplay <= x) && 3860 (ep->edid_preferred_mode->vdisplay <= y)) 3861 return ep->edid_preferred_mode; 3862 } 3863 3864 for (i = 0; i < ep->edid_nmodes; i++) { 3865 /* 3866 * We elect to pick a resolution that is too large for 3867 * the monitor than one that is too small. This means 3868 * that we will prefer to pan rather than to try to 3869 * center a smaller display on a larger screen. In 3870 * practice, this shouldn't matter because if a 3871 * monitor can support a larger resolution, it can 3872 * probably also support the smaller. A specific 3873 * exception is fixed format panels, but hopefully 3874 * they are properly dealt with by the "autostretch" 3875 * logic above. 3876 */ 3877 if ((ep->edid_modes[i].hdisplay > x) || 3878 (ep->edid_modes[i].vdisplay > y)) { 3879 continue; 3880 } 3881 3882 /* 3883 * at this point, the display mode is no larger than 3884 * what we've requested. 3885 */ 3886 if (vmp == NULL) 3887 vmp = &ep->edid_modes[i]; 3888 3889 /* eliminate smaller modes */ 3890 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3891 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3892 continue; 3893 3894 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3895 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3896 vmp = &ep->edid_modes[i]; 3897 continue; 3898 } 3899 3900 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3901 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3902 3903 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3904 } 3905 3906 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3907 } 3908 3909 static int 3910 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3911 { 3912 int i; 3913 3914 for (i = 0; i < nlist; i++) { 3915 if ((x == list[i].hdisplay) && 3916 (y == list[i].vdisplay)) { 3917 return 1; 3918 } 3919 } 3920 return 0; 3921 } 3922 3923 static void 3924 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3925 int pan) 3926 { 3927 struct radeonfb_port *rp; 3928 struct edid_info *ep; 3929 int i, j; 3930 3931 *x = 0; 3932 *y = 0; 3933 3934 if (pan) { 3935 for (i = 0; i < dp->rd_ncrtcs; i++) { 3936 rp = dp->rd_crtcs[i].rc_port; 3937 ep = &rp->rp_edid; 3938 if (!rp->rp_edid_valid) { 3939 /* monitor not present */ 3940 continue; 3941 } 3942 3943 /* 3944 * For now we are ignoring "conflict" that 3945 * could occur when mixing some modes like 3946 * 1280x1024 and 1400x800. It isn't clear 3947 * which is better, so the first one wins. 3948 */ 3949 for (j = 0; j < ep->edid_nmodes; j++) { 3950 /* 3951 * ignore resolutions that are too big for 3952 * the radeon 3953 */ 3954 if (ep->edid_modes[j].hdisplay > 3955 dp->rd_softc->sc_maxx) 3956 continue; 3957 if (ep->edid_modes[j].vdisplay > 3958 dp->rd_softc->sc_maxy) 3959 continue; 3960 3961 /* 3962 * pick largest resolution, the 3963 * smaller monitor will pan 3964 */ 3965 if ((ep->edid_modes[j].hdisplay >= *x) && 3966 (ep->edid_modes[j].vdisplay >= *y)) { 3967 *x = ep->edid_modes[j].hdisplay; 3968 *y = ep->edid_modes[j].vdisplay; 3969 } 3970 } 3971 } 3972 3973 } else { 3974 struct videomode modes[64]; 3975 int nmodes = 0; 3976 int valid = 0; 3977 3978 for (i = 0; i < dp->rd_ncrtcs; i++) { 3979 /* 3980 * pick the largest resolution in common. 3981 */ 3982 rp = dp->rd_crtcs[i].rc_port; 3983 ep = &rp->rp_edid; 3984 3985 if (!rp->rp_edid_valid) 3986 continue; 3987 3988 if (!valid) { 3989 /* 3990 * Pick the preferred mode for this port 3991 * if available. 3992 */ 3993 if (ep->edid_preferred_mode) { 3994 struct videomode *vmp = 3995 ep->edid_preferred_mode; 3996 3997 if ((vmp->hdisplay <= 3998 dp->rd_softc->sc_maxx) && 3999 (vmp->vdisplay <= 4000 dp->rd_softc->sc_maxy)) 4001 modes[nmodes++] = *vmp; 4002 } else { 4003 4004 /* initialize starting list */ 4005 for (j = 0; j < ep->edid_nmodes; j++) { 4006 /* 4007 * ignore resolutions that are 4008 * too big for the radeon 4009 */ 4010 if (ep->edid_modes[j].hdisplay > 4011 dp->rd_softc->sc_maxx) 4012 continue; 4013 if (ep->edid_modes[j].vdisplay > 4014 dp->rd_softc->sc_maxy) 4015 continue; 4016 4017 modes[nmodes] = 4018 ep->edid_modes[j]; 4019 nmodes++; 4020 } 4021 } 4022 valid = 1; 4023 } else { 4024 /* merge into preexisting list */ 4025 for (j = 0; j < nmodes; j++) { 4026 if (!radeonfb_hasres(ep->edid_modes, 4027 ep->edid_nmodes, 4028 modes[j].hdisplay, 4029 modes[j].vdisplay)) { 4030 modes[j] = modes[nmodes]; 4031 j--; 4032 nmodes--; 4033 } 4034 } 4035 } 4036 } 4037 4038 /* now we have to pick from the merged list */ 4039 for (i = 0; i < nmodes; i++) { 4040 if ((modes[i].hdisplay >= *x) && 4041 (modes[i].vdisplay >= *y)) { 4042 *x = modes[i].hdisplay; 4043 *y = modes[i].vdisplay; 4044 } 4045 } 4046 } 4047 4048 if ((*x == 0) || (*y == 0)) { 4049 /* fallback to safe mode */ 4050 *x = 640; 4051 *y = 480; 4052 } 4053 } 4054 4055 /* 4056 * backlight levels are linear on: 4057 * - RV200, RV250, RV280, RV350 4058 * - but NOT on PowerBook4,3 6,3 6,5 4059 * according to Linux' radeonfb 4060 */ 4061 4062 /* Get the current backlight level for the display. */ 4063 4064 static int 4065 radeonfb_get_backlight(struct radeonfb_display *dp) 4066 { 4067 int s; 4068 uint32_t level; 4069 4070 s = spltty(); 4071 4072 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4073 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4074 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4075 4076 /* 4077 * On some chips, we should negate the backlight level. 4078 * XXX Find out on which chips. 4079 */ 4080 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4081 level = RADEONFB_BACKLIGHT_MAX - level; 4082 4083 splx(s); 4084 4085 return level; 4086 } 4087 4088 /* Set the backlight to the given level for the display. */ 4089 static void 4090 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4091 { 4092 if (dp->rd_bl_on == on) 4093 return; 4094 dp->rd_bl_on = on; 4095 radeonfb_set_backlight(dp, dp->rd_bl_level); 4096 } 4097 4098 static int 4099 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4100 { 4101 struct radeonfb_softc *sc; 4102 int rlevel, s; 4103 uint32_t lvds; 4104 4105 s = spltty(); 4106 4107 dp->rd_bl_level = level; 4108 if (dp->rd_bl_on == 0) 4109 level = 0; 4110 4111 if (level < 0) 4112 level = 0; 4113 else if (level >= RADEONFB_BACKLIGHT_MAX) 4114 level = RADEONFB_BACKLIGHT_MAX; 4115 4116 sc = dp->rd_softc; 4117 4118 /* On some chips, we should negate the backlight level. */ 4119 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4120 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4121 } else 4122 rlevel = level; 4123 4124 callout_stop(&dp->rd_bl_lvds_co); 4125 radeonfb_engine_idle(sc); 4126 4127 /* 4128 * Turn off the display if the backlight is set to 0, since the 4129 * display is useless without backlight anyway. 4130 */ 4131 if (level == 0) 4132 radeonfb_blank(dp, 1); 4133 else if (radeonfb_get_backlight(dp) == 0) 4134 radeonfb_blank(dp, 0); 4135 4136 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4137 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4138 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4139 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4140 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4141 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4142 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4143 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4144 lvds |= RADEON_LVDS_ON; 4145 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4146 } else { 4147 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4148 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4149 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4150 } 4151 4152 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4153 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4154 /* XXX What is the correct delay? */ 4155 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4156 4157 splx(s); 4158 4159 return 0; 4160 } 4161 4162 /* 4163 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4164 * Set the delayed bits in the register, and clear the stored delayed 4165 * value. 4166 */ 4167 4168 static void radeonfb_lvds_callout(void *arg) 4169 { 4170 struct radeonfb_display *dp = arg; 4171 int s; 4172 4173 s = splhigh(); 4174 4175 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4176 dp->rd_bl_lvds_val); 4177 dp->rd_bl_lvds_val = 0; 4178 4179 splx(s); 4180 } 4181 4182 static void 4183 radeonfb_brightness_up(device_t dev) 4184 { 4185 struct radeonfb_softc *sc = device_private(dev); 4186 struct radeonfb_display *dp = &sc->sc_displays[0]; 4187 int level; 4188 4189 /* we assume the main display is the first one - need a better way */ 4190 if (sc->sc_ndisplays < 1) return; 4191 /* make sure pushing the hotkeys always has an effect */ 4192 dp->rd_bl_on = 1; 4193 level = dp->rd_bl_level; 4194 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4195 radeonfb_set_backlight(dp, level); 4196 } 4197 4198 static void 4199 radeonfb_brightness_down(device_t dev) 4200 { 4201 struct radeonfb_softc *sc = device_private(dev); 4202 struct radeonfb_display *dp = &sc->sc_displays[0]; 4203 int level; 4204 4205 /* we assume the main display is the first one - need a better way */ 4206 if (sc->sc_ndisplays < 1) return; 4207 /* make sure pushing the hotkeys always has an effect */ 4208 dp->rd_bl_on = 1; 4209 level = dp->rd_bl_level; 4210 level = max(0, level - 5); 4211 radeonfb_set_backlight(dp, level); 4212 } 4213
Indexes created Thu Sep 25 16:09:42 GMT 2025