radeonfb.c revision 1.87
1 /* $NetBSD: radeonfb.c,v 1.87 2014/10/21 09:07:07 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.87 2014/10/21 09:07:07 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 144 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 145 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 146 147 /* acceleration support */ 148 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 149 int width, int height, uint32_t color); 150 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 151 static void radeonfb_bitblt(void *, int srcx, int srcy, 152 int dstx, int dsty, int width, int height, int rop); 153 154 /* hw cursor support */ 155 static void radeonfb_cursor_cmap(struct radeonfb_display *); 156 static void radeonfb_cursor_shape(struct radeonfb_display *); 157 static void radeonfb_cursor_position(struct radeonfb_display *); 158 static void radeonfb_cursor_visible(struct radeonfb_display *); 159 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 160 161 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 162 static void radeonfb_engine_idle(struct radeonfb_softc *); 163 static void radeonfb_engine_flush(struct radeonfb_softc *); 164 static void radeonfb_engine_reset(struct radeonfb_softc *); 165 static void radeonfb_engine_init(struct radeonfb_display *); 166 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 167 168 static void radeonfb_eraserows(void *, int, int, long); 169 static void radeonfb_erasecols(void *, int, int, int, long); 170 static void radeonfb_copyrows(void *, int, int, int); 171 static void radeonfb_copycols(void *, int, int, int, int); 172 static void radeonfb_cursor(void *, int, int, int); 173 static void radeonfb_putchar(void *, int, int, unsigned, long); 174 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 175 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 176 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 177 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 178 #endif 179 180 static int radeonfb_set_backlight(struct radeonfb_display *, int); 181 static int radeonfb_get_backlight(struct radeonfb_display *); 182 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 183 static void radeonfb_lvds_callout(void *); 184 185 static void radeonfb_brightness_up(device_t); 186 static void radeonfb_brightness_down(device_t); 187 188 static struct videomode *radeonfb_best_refresh(struct videomode *, 189 struct videomode *); 190 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 191 uint16_t *, int); 192 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 193 struct radeonfb_port *, int, int); 194 195 static int radeonfb_drm_print(void *, const char *); 196 197 #ifdef RADEONFB_DEBUG 198 int radeon_debug = 1; 199 #define DPRINTF(x) \ 200 if (radeon_debug) printf x 201 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 202 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 203 #else 204 #define DPRINTF(x) 205 #define PRINTREG(r) 206 #define PRINTPLL(r) 207 #endif 208 209 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 210 211 #ifndef RADEON_DEFAULT_MODE 212 /* any reasonably modern display should handle this */ 213 #define RADEON_DEFAULT_MODE "1024x768x60" 214 #endif 215 216 extern const u_char rasops_cmap[768]; 217 218 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 219 220 static struct { 221 int size; /* minimum memory size (MB) */ 222 int maxx; /* maximum x dimension */ 223 int maxy; /* maximum y dimension */ 224 int maxbpp; /* maximum bpp */ 225 int maxdisp; /* maximum logical display count */ 226 } radeonfb_limits[] = { 227 { 32, 2048, 1536, 32, 2 }, 228 { 16, 1600, 1200, 32, 2 }, 229 { 8, 1600, 1200, 32, 1 }, 230 { 0, 0, 0, 0, 0 }, 231 }; 232 233 static struct wsscreen_descr radeonfb_stdscreen = { 234 "fb", /* name */ 235 0, 0, /* ncols, nrows */ 236 NULL, /* textops */ 237 8, 16, /* fontwidth, fontheight */ 238 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE, /* capabilities */ 239 0, /* modecookie */ 240 }; 241 242 struct wsdisplay_accessops radeonfb_accessops = { 243 radeonfb_ioctl, 244 radeonfb_mmap, 245 NULL, /* vcons_alloc_screen */ 246 NULL, /* vcons_free_screen */ 247 NULL, /* vcons_show_screen */ 248 NULL, /* load_font */ 249 NULL, /* pollc */ 250 NULL, /* scroll */ 251 }; 252 253 static struct { 254 uint16_t devid; 255 uint16_t family; 256 uint16_t flags; 257 } radeonfb_devices[] = 258 { 259 /* R100 family */ 260 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 264 265 /* RV100 family */ 266 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 267 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 270 271 /* RS100 family */ 272 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 274 275 /* RS200/RS250 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 280 281 /* R200 family */ 282 /* add more R200 products? , 5148 */ 283 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 288 289 /* RV200 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 294 295 /* RV250 family */ 296 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 299 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 301 302 /* RS300 family */ 303 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 307 308 /* RV280 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 316 317 /* R300 family */ 318 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 326 327 /* RV350/RV360 family */ 328 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 340 341 /* R350/R360 family */ 342 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 350 351 /* RV380/RV370 family */ 352 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 362 363 #if notyet 364 /* R420/R423 family */ 365 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 382 #endif 383 { 0, 0, 0 } 384 }; 385 386 static struct { 387 int divider; 388 int mask; 389 } radeonfb_dividers[] = { 390 { 16, 5 }, 391 { 12, 7 }, 392 { 8, 3 }, 393 { 6, 6 }, 394 { 4, 2 }, 395 { 3, 4 }, 396 { 2, 1 }, 397 { 1, 0 }, 398 { 0, 0 } 399 }; 400 401 /* 402 * This table taken from X11. 403 */ 404 static const struct { 405 int family; 406 struct radeon_tmds_pll plls[4]; 407 } radeonfb_tmds_pll[] = { 408 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 409 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 410 { RADEON_RS100, {{0, 0}}}, 411 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 412 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 413 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 414 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 415 { RADEON_RS300, {{0, 0}}}, 416 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 417 { RADEON_R300, {{-1, 0xb01cb}}}, 418 { RADEON_R350, {{-1, 0xb01cb}}}, 419 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 420 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 421 { RADEON_R420, {{-1, 0xb01cb}}}, 422 }; 423 424 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 425 426 427 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 428 radeonfb_match, radeonfb_attach, NULL, NULL); 429 430 static int 431 radeonfb_match(device_t parent, cfdata_t match, void *aux) 432 { 433 const struct pci_attach_args *pa = aux; 434 int i; 435 436 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 437 return 0; 438 439 for (i = 0; radeonfb_devices[i].devid; i++) { 440 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 441 return 100; /* high to defeat VGA/VESA */ 442 } 443 444 return 0; 445 } 446 447 static void 448 radeonfb_attach(device_t parent, device_t dev, void *aux) 449 { 450 struct radeonfb_softc *sc = device_private(dev); 451 const struct pci_attach_args *pa = aux; 452 const char *mptr; 453 bus_size_t bsz; 454 pcireg_t screg; 455 int i, j, fg, bg, ul, flags; 456 uint32_t v; 457 458 sc->sc_dev = dev; 459 sc->sc_id = pa->pa_id; 460 for (i = 0; radeonfb_devices[i].devid; i++) { 461 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 462 break; 463 } 464 465 pci_aprint_devinfo(pa, NULL); 466 467 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 468 469 KASSERT(radeonfb_devices[i].devid != 0); 470 sc->sc_pt = pa->pa_tag; 471 sc->sc_iot = pa->pa_iot; 472 sc->sc_pc = pa->pa_pc; 473 sc->sc_family = radeonfb_devices[i].family; 474 sc->sc_flags = radeonfb_devices[i].flags; 475 476 /* enable memory and IO access */ 477 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 478 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 479 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 480 481 /* 482 * Some flags are general to entire chip families, and rather 483 * than clutter up the table with them, we go ahead and set 484 * them here. 485 */ 486 switch (sc->sc_family) { 487 case RADEON_RS100: 488 case RADEON_RS200: 489 sc->sc_flags |= RFB_IGP | RFB_RV100; 490 break; 491 492 case RADEON_RV100: 493 case RADEON_RV200: 494 case RADEON_RV250: 495 case RADEON_RV280: 496 sc->sc_flags |= RFB_RV100; 497 break; 498 499 case RADEON_RS300: 500 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 501 break; 502 503 case RADEON_R300: 504 case RADEON_RV350: 505 case RADEON_R350: 506 case RADEON_RV380: 507 case RADEON_R420: 508 /* newer chips */ 509 sc->sc_flags |= RFB_R300; 510 break; 511 512 case RADEON_R100: 513 sc->sc_flags |= RFB_NCRTC2; 514 break; 515 } 516 517 if ((sc->sc_family == RADEON_RV200) || 518 (sc->sc_family == RADEON_RV250) || 519 (sc->sc_family == RADEON_RV280) || 520 (sc->sc_family == RADEON_RV350)) { 521 bool inverted = 0; 522 /* backlight level is linear */ 523 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 524 prop_dictionary_get_bool(device_properties(sc->sc_dev), 525 "backlight_level_reverted", &inverted); 526 if (inverted) { 527 DPRINTF(("nope, it's inverted\n")); 528 sc->sc_flags |= RFB_INV_BLIGHT; 529 } 530 } else 531 sc->sc_flags |= RFB_INV_BLIGHT; 532 533 /* 534 * XXX: to support true multihead, this must change. 535 */ 536 sc->sc_ndisplays = 1; 537 538 /* XXX: */ 539 if (!HAS_CRTC2(sc)) { 540 sc->sc_ndisplays = 1; 541 } 542 543 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 544 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 545 &sc->sc_regsz) != 0) { 546 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 547 goto error; 548 } 549 550 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 551 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 552 { 553 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 554 goto error; 555 } 556 sc->sc_romt = sc->sc_memt; 557 558 sc->sc_mapped = TRUE; 559 560 /* scratch register test... */ 561 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 562 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 563 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 564 goto error; 565 } 566 567 PRINTREG(RADEON_CRTC_EXT_CNTL); 568 PRINTREG(RADEON_CRTC_GEN_CNTL); 569 PRINTREG(RADEON_CRTC2_GEN_CNTL); 570 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 571 PRINTREG(RADEON_DAC_CNTL2); 572 PRINTREG(RADEON_FP_GEN_CNTL); 573 PRINTREG(RADEON_FP2_GEN_CNTL); 574 575 PRINTREG(RADEON_BIOS_4_SCRATCH); 576 PRINTREG(RADEON_FP_GEN_CNTL); 577 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 578 PRINTREG(RADEON_FP2_GEN_CNTL); 579 PRINTREG(RADEON_TMDS_CNTL); 580 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 581 PRINTREG(RADEON_TMDS_PLL_CNTL); 582 PRINTREG(RADEON_LVDS_GEN_CNTL); 583 PRINTREG(RADEON_FP_HORZ_STRETCH); 584 PRINTREG(RADEON_FP_VERT_STRETCH); 585 586 if (IS_RV100(sc)) 587 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 588 589 /* XXX 590 * according to xf86-video-radeon R3xx has this bit backwards 591 */ 592 if (IS_R300(sc)) { 593 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 594 0, 595 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 596 } else { 597 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 598 RADEON_TMDS_TRANSMITTER_PLLEN, 599 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 600 } 601 602 radeonfb_i2c_init(sc); 603 604 radeonfb_loadbios(sc, pa); 605 606 #ifdef RADEONFB_BIOS_INIT 607 if (radeonfb_bios_init(sc)) { 608 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 609 } 610 #endif 611 612 if (radeonfb_getclocks(sc)) { 613 aprint_error("%s: Unable to get reference clocks from BIOS\n", 614 XNAME(sc)); 615 goto error; 616 } 617 618 if (radeonfb_gettmds(sc)) { 619 aprint_error("%s: Unable to identify TMDS PLL settings\n", 620 XNAME(sc)); 621 goto error; 622 } 623 624 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 625 "minpll = %d, maxpll = %d\n", XNAME(sc), 626 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 627 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 628 629 radeonfb_getconnectors(sc); 630 631 radeonfb_set_fbloc(sc); 632 633 /* 64 MB should be enough -- more just wastes map entries */ 634 if (sc->sc_memsz > (64 << 20)) 635 sc->sc_memsz = (64 << 20); 636 637 for (i = 0; radeonfb_limits[i].size; i++) { 638 if (sc->sc_memsz >= radeonfb_limits[i].size) { 639 sc->sc_maxx = radeonfb_limits[i].maxx; 640 sc->sc_maxy = radeonfb_limits[i].maxy; 641 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 642 /* framebuffer offset, start at a 4K page */ 643 sc->sc_fboffset = sc->sc_memsz / 644 radeonfb_limits[i].maxdisp; 645 /* 646 * we use the fbsize to figure out where we can store 647 * things like cursor data. 648 */ 649 sc->sc_fbsize = 650 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 651 RADEON_STRIDEALIGN) * sc->sc_maxy, 652 4096); 653 break; 654 } 655 } 656 657 658 radeonfb_init_misc(sc); 659 660 /* program the DAC wirings */ 661 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 662 switch (sc->sc_ports[i].rp_dac_type) { 663 case RADEON_DAC_PRIMARY: 664 PATCH32(sc, RADEON_DAC_CNTL2, 665 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 666 ~RADEON_DAC2_DAC_CLK_SEL); 667 break; 668 case RADEON_DAC_TVDAC: 669 /* we always use the TVDAC to drive a secondary analog 670 * CRT for now. if we ever support TV-out this will 671 * have to change. 672 */ 673 SET32(sc, RADEON_DAC_CNTL2, 674 RADEON_DAC2_DAC2_CLK_SEL); 675 PATCH32(sc, RADEON_DISP_HW_DEBUG, 676 i ? 0 : RADEON_CRT2_DISP1_SEL, 677 ~RADEON_CRT2_DISP1_SEL); 678 /* we're using CRTC2 for the 2nd port */ 679 if (sc->sc_ports[i].rp_number == 1) { 680 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 681 RADEON_DISP_DAC2_SOURCE_CRTC2, 682 ~RADEON_DISP_DAC2_SOURCE_MASK); 683 } 684 685 break; 686 } 687 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 688 sc->sc_ports[i].rp_tmds_type)); 689 switch (sc->sc_ports[i].rp_tmds_type) { 690 case RADEON_TMDS_INT: 691 /* point FP0 at the CRTC this port uses */ 692 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 693 __func__, sc->sc_ports[i].rp_number)); 694 if (IS_R300(sc)) { 695 PATCH32(sc, RADEON_FP_GEN_CNTL, 696 sc->sc_ports[i].rp_number ? 697 R200_FP_SOURCE_SEL_CRTC2 : 698 R200_FP_SOURCE_SEL_CRTC1, 699 ~R200_FP_SOURCE_SEL_MASK); 700 } else { 701 PATCH32(sc, RADEON_FP_GEN_CNTL, 702 sc->sc_ports[i].rp_number ? 703 RADEON_FP_SEL_CRTC2 : 704 RADEON_FP_SEL_CRTC1, 705 ~RADEON_FP_SEL_MASK); 706 } 707 } 708 } 709 PRINTREG(RADEON_DAC_CNTL2); 710 PRINTREG(RADEON_DISP_HW_DEBUG); 711 712 /* other DAC programming */ 713 v = GET32(sc, RADEON_DAC_CNTL); 714 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 715 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 716 PUT32(sc, RADEON_DAC_CNTL, v); 717 PRINTREG(RADEON_DAC_CNTL); 718 719 /* XXX: this may need more investigation */ 720 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 721 PRINTREG(RADEON_TV_DAC_CNTL); 722 723 /* enable TMDS */ 724 SET32(sc, RADEON_FP_GEN_CNTL, 725 RADEON_FP_TMDS_EN | 726 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 727 RADEON_FP_CRTC_DONT_SHADOW_HEND); 728 /* 729 * XXX 730 * no idea why this is necessary - if I do not clear this bit on my 731 * iBook G4 the screen remains black, even though it's already clear. 732 * It needs to be set on my Sun XVR-100 for the DVI port to work 733 * TODO: 734 * see if this is still necessary now that CRTCs, DACs and outputs are 735 * getting wired up in a halfway sane way 736 */ 737 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 738 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 739 } else { 740 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 741 } 742 743 /* 744 * we use bus_space_map instead of pci_mapreg, because we don't 745 * need the full aperature space. no point in wasting virtual 746 * address space we don't intend to use, right? 747 */ 748 if ((sc->sc_memsz < (4096 * 1024)) || 749 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 750 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 751 (bsz < sc->sc_memsz)) { 752 sc->sc_memsz = 0; 753 aprint_error("%s: Bad frame buffer configuration\n", 754 XNAME(sc)); 755 goto error; 756 } 757 758 sc->sc_memt = pa->pa_memt; 759 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 760 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 761 sc->sc_memsz = 0; 762 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 763 goto error; 764 } 765 766 aprint_normal("%s: %d MB aperture at 0x%08x, " 767 "%d KB registers at 0x%08x\n", XNAME(sc), 768 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 769 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 770 771 /* setup default video mode from devprop (allows PROM override) */ 772 sc->sc_defaultmode = radeonfb_default_mode; 773 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 774 "videomode", &mptr)) { 775 776 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 777 sc->sc_defaultmode = sc->sc_modebuf; 778 } 779 780 /* initialize some basic display parameters */ 781 for (i = 0; i < sc->sc_ndisplays; i++) { 782 struct radeonfb_display *dp = &sc->sc_displays[i]; 783 struct rasops_info *ri; 784 long defattr; 785 struct wsemuldisplaydev_attach_args aa; 786 787 /* 788 * Figure out how many "displays" (desktops) we are going to 789 * support. If more than one, then each CRTC gets its own 790 * programming. 791 * 792 * XXX: this code needs to change to support mergedfb. 793 * XXX: would be nice to allow this to be overridden 794 */ 795 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 796 DPRINTF(("dual crtcs!\n")); 797 dp->rd_ncrtcs = 2; 798 dp->rd_crtcs[0].rc_port = 799 &sc->sc_ports[0]; 800 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 801 dp->rd_crtcs[1].rc_port = 802 &sc->sc_ports[1]; 803 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 804 } else { 805 dp->rd_ncrtcs = 1; 806 dp->rd_crtcs[0].rc_port = 807 &sc->sc_ports[i]; 808 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 809 } 810 811 dp->rd_softc = sc; 812 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 813 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 814 815 /* for text mode, we pick a resolution that won't 816 * require panning */ 817 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 818 819 aprint_normal("%s: display %d: " 820 "initial virtual resolution %dx%d at %d bpp\n", 821 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 822 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 823 sc->sc_fboffset >> 20); 824 /* now select the *video mode* that we will use */ 825 for (j = 0; j < dp->rd_ncrtcs; j++) { 826 const struct videomode *vmp; 827 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 828 dp->rd_virtx, dp->rd_virty); 829 830 /* 831 * virtual resolution should be at least as high as 832 * physical 833 */ 834 if (dp->rd_virtx < vmp->hdisplay || 835 dp->rd_virty < vmp->vdisplay) { 836 dp->rd_virtx = vmp->hdisplay; 837 dp->rd_virty = vmp->vdisplay; 838 } 839 840 dp->rd_crtcs[j].rc_videomode = *vmp; 841 printf("%s: port %d: physical %dx%d %dHz\n", 842 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 843 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 844 vmp->htotal), vmp->vtotal)); 845 } 846 847 /* N.B.: radeon wants 64-byte aligned stride */ 848 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 849 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 850 DPRINTF(("stride: %d\n", dp->rd_stride)); 851 852 dp->rd_offset = sc->sc_fboffset * i; 853 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 854 sc->sc_memh) + dp->rd_offset; 855 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 856 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 857 858 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 859 860 switch (dp->rd_bpp) { 861 case 8: 862 dp->rd_format = 2; 863 break; 864 case 32: 865 dp->rd_format = 6; 866 break; 867 default: 868 aprint_error("%s: bad depth %d\n", XNAME(sc), 869 dp->rd_bpp); 870 goto error; 871 } 872 873 DPRINTF(("init engine\n")); 874 /* XXX: this seems suspicious - per display engine 875 initialization? */ 876 radeonfb_engine_init(dp); 877 878 /* copy the template into place */ 879 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 880 dp->rd_wsscreens = dp->rd_wsscreens_storage; 881 882 /* and make up the list */ 883 dp->rd_wsscreenlist.nscreens = 1; 884 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 885 886 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 887 &radeonfb_accessops); 888 889 dp->rd_vd.init_screen = radeonfb_init_screen; 890 891 #ifdef RADEONFB_DEBUG 892 dp->rd_virty -= 200; 893 #endif 894 895 dp->rd_console = 0; 896 prop_dictionary_get_bool(device_properties(sc->sc_dev), 897 "is_console", &dp->rd_console); 898 899 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 900 901 902 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 903 dp->rd_console, &defattr); 904 905 ri = &dp->rd_vscreen.scr_ri; 906 907 /* clear the screen */ 908 rasops_unpack_attr(defattr, &fg, &bg, &ul); 909 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 910 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 911 dp->rd_bg); 912 913 dp->rd_wsscreens->textops = &ri->ri_ops; 914 dp->rd_wsscreens->capabilities = ri->ri_caps; 915 dp->rd_wsscreens->nrows = ri->ri_rows; 916 dp->rd_wsscreens->ncols = ri->ri_cols; 917 918 #ifdef SPLASHSCREEN 919 dp->rd_splash.si_depth = ri->ri_depth; 920 dp->rd_splash.si_bits = ri->ri_bits; 921 dp->rd_splash.si_hwbits = ri->ri_hwbits; 922 dp->rd_splash.si_width = ri->ri_width; 923 dp->rd_splash.si_height = ri->ri_height; 924 dp->rd_splash.si_stride = ri->ri_stride; 925 dp->rd_splash.si_fillrect = NULL; 926 #endif 927 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 928 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 929 dp->rd_gc.gc_rop = RADEON_ROP3_S; 930 dp->rd_gc.gc_blitcookie = dp; 931 /* 932 * use memory between framebuffer and cursor area as glyph 933 * cache, cap at 4096 lines 934 */ 935 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 936 min(4096, 937 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 938 dp->rd_virtx, 939 ri->ri_font->fontwidth, 940 ri->ri_font->fontheight, 941 defattr); 942 if (dp->rd_console) { 943 944 radeonfb_modeswitch(dp); 945 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 946 defattr); 947 #ifdef SPLASHSCREEN 948 if (splash_render(&dp->rd_splash, 949 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 950 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 951 else 952 #endif 953 vcons_replay_msgbuf(&dp->rd_vscreen); 954 } else { 955 956 /* 957 * since we're not the console we can postpone 958 * the rest until someone actually allocates a 959 * screen for us. but we do clear the screen 960 * at least. 961 */ 962 memset(ri->ri_bits, 0, 1024); 963 964 radeonfb_modeswitch(dp); 965 #ifdef SPLASHSCREEN 966 if (splash_render(&dp->rd_splash, 967 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 968 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 969 #endif 970 } 971 972 aa.console = dp->rd_console; 973 aa.scrdata = &dp->rd_wsscreenlist; 974 aa.accessops = &radeonfb_accessops; 975 aa.accesscookie = &dp->rd_vd; 976 977 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 978 979 radeonfb_blank(dp, 0); 980 981 /* Initialise delayed lvds operations for backlight. */ 982 callout_init(&dp->rd_bl_lvds_co, 0); 983 callout_setfunc(&dp->rd_bl_lvds_co, 984 radeonfb_lvds_callout, dp); 985 dp->rd_bl_on = 1; 986 dp->rd_bl_level = radeonfb_get_backlight(dp); 987 radeonfb_set_backlight(dp, dp->rd_bl_level); 988 } 989 990 for (i = 0; i < RADEON_NDISPLAYS; i++) 991 radeonfb_init_palette(&sc->sc_displays[i]); 992 993 if (HAS_CRTC2(sc)) { 994 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 995 } 996 997 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 998 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 999 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1000 radeonfb_brightness_up, TRUE); 1001 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1002 radeonfb_brightness_down, TRUE); 1003 1004 config_found_ia(dev, "drm", aux, radeonfb_drm_print); 1005 1006 PRINTREG(RADEON_CRTC_EXT_CNTL); 1007 PRINTREG(RADEON_CRTC_GEN_CNTL); 1008 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1009 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1010 PRINTREG(RADEON_DAC_CNTL2); 1011 PRINTREG(RADEON_FP_GEN_CNTL); 1012 PRINTREG(RADEON_FP2_GEN_CNTL); 1013 1014 return; 1015 1016 error: 1017 if (sc->sc_biossz) 1018 free(sc->sc_bios, M_DEVBUF); 1019 1020 if (sc->sc_regsz) 1021 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1022 1023 if (sc->sc_memsz) 1024 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1025 } 1026 1027 static void 1028 radeonfb_map(struct radeonfb_softc *sc) 1029 { 1030 if (!sc->sc_mapped) { 1031 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1032 &sc->sc_regh) != 0) { 1033 aprint_error_dev(sc->sc_dev, 1034 "unable to map registers!\n"); 1035 return; 1036 } 1037 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1038 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1039 sc->sc_memsz = 0; 1040 aprint_error_dev(sc->sc_dev, 1041 "Unable to map frame buffer\n"); 1042 return; 1043 } 1044 sc->sc_mapped = TRUE; 1045 } 1046 } 1047 1048 static void 1049 radeonfb_unmap(struct radeonfb_softc *sc) 1050 { 1051 if (sc->sc_mapped) { 1052 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1053 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1054 sc->sc_mapped = FALSE; 1055 } 1056 } 1057 1058 static int 1059 radeonfb_drm_print(void *aux, const char *pnp) 1060 { 1061 if (pnp) 1062 aprint_normal("drm at %s", pnp); 1063 return (UNCONF); 1064 } 1065 1066 int 1067 radeonfb_ioctl(void *v, void *vs, 1068 unsigned long cmd, void *d, int flag, struct lwp *l) 1069 { 1070 struct vcons_data *vd; 1071 struct radeonfb_display *dp; 1072 struct radeonfb_softc *sc; 1073 struct wsdisplay_param *param; 1074 struct vcons_screen *ms; 1075 1076 vd = (struct vcons_data *)v; 1077 ms = vd->active; 1078 dp = (struct radeonfb_display *)vd->cookie; 1079 sc = dp->rd_softc; 1080 1081 /* can't do these without registers being mapped */ 1082 if (!sc->sc_mapped) { 1083 switch (cmd) { 1084 case WSDISPLAYIO_GVIDEO: 1085 case WSDISPLAYIO_SVIDEO: 1086 case WSDISPLAYIO_GETCMAP: 1087 case WSDISPLAYIO_PUTCMAP: 1088 case WSDISPLAYIO_SCURSOR: 1089 case WSDISPLAYIO_GCURPOS: 1090 case WSDISPLAYIO_SCURPOS: 1091 case WSDISPLAYIO_SETPARAM: 1092 return EINVAL; 1093 } 1094 } 1095 1096 switch (cmd) { 1097 case WSDISPLAYIO_GTYPE: 1098 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1099 return 0; 1100 1101 case WSDISPLAYIO_GINFO: 1102 if (vd->active != NULL) { 1103 struct wsdisplay_fbinfo *fb; 1104 fb = (struct wsdisplay_fbinfo *)d; 1105 fb->width = dp->rd_virtx; 1106 fb->height = dp->rd_virty; 1107 fb->depth = dp->rd_bpp; 1108 fb->cmsize = 256; 1109 return 0; 1110 } else 1111 return ENODEV; 1112 case WSDISPLAYIO_GVIDEO: 1113 if (radeonfb_isblank(dp)) 1114 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1115 else 1116 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1117 return 0; 1118 1119 case WSDISPLAYIO_SVIDEO: 1120 radeonfb_blank(dp, 1121 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1122 return 0; 1123 1124 case WSDISPLAYIO_GETCMAP: 1125 if (dp->rd_bpp == 8) 1126 return radeonfb_getcmap(dp, 1127 (struct wsdisplay_cmap *)d); 1128 return EINVAL; 1129 1130 case WSDISPLAYIO_PUTCMAP: 1131 if (dp->rd_bpp == 8) 1132 return radeonfb_putcmap(dp, 1133 (struct wsdisplay_cmap *)d); 1134 return EINVAL; 1135 1136 case WSDISPLAYIO_LINEBYTES: 1137 *(unsigned *)d = dp->rd_stride; 1138 return 0; 1139 1140 case WSDISPLAYIO_SMODE: 1141 if (*(int *)d != dp->rd_wsmode) { 1142 dp->rd_wsmode = *(int *)d; 1143 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1144 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1145 radeonfb_map(sc); 1146 1147 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1148 (dp->rd_vd.active)) { 1149 radeonfb_engine_init(dp); 1150 glyphcache_wipe(&dp->rd_gc); 1151 radeonfb_init_palette(dp); 1152 radeonfb_modeswitch(dp); 1153 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1154 dp->rd_virty, dp->rd_bg); 1155 vcons_redraw_screen(dp->rd_vd.active); 1156 } 1157 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1158 radeonfb_unmap(sc); 1159 } 1160 return 0; 1161 1162 case WSDISPLAYIO_GCURMAX: 1163 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1164 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1165 return 0; 1166 1167 case WSDISPLAYIO_SCURSOR: 1168 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1169 1170 case WSDISPLAYIO_GCURSOR: 1171 return EPASSTHROUGH; 1172 1173 case WSDISPLAYIO_GCURPOS: 1174 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1175 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1176 return 0; 1177 1178 case WSDISPLAYIO_SCURPOS: 1179 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1180 1181 case WSDISPLAYIO_SSPLASH: 1182 #if defined(SPLASHSCREEN) 1183 if (*(int *)d == 1) { 1184 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1185 splash_render(&dp->rd_splash, 1186 SPLASH_F_CENTER|SPLASH_F_FILL); 1187 } else 1188 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1189 return 0; 1190 #else 1191 return ENODEV; 1192 #endif 1193 case WSDISPLAYIO_GETPARAM: 1194 param = (struct wsdisplay_param *)d; 1195 switch (param->param) { 1196 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1197 param->min = 0; 1198 param->max = 255; 1199 param->curval = dp->rd_bl_level; 1200 return 0; 1201 case WSDISPLAYIO_PARAM_BACKLIGHT: 1202 param->min = 0; 1203 param->max = RADEONFB_BACKLIGHT_MAX; 1204 param->curval = dp->rd_bl_on; 1205 return 0; 1206 } 1207 return EPASSTHROUGH; 1208 1209 case WSDISPLAYIO_SETPARAM: 1210 param = (struct wsdisplay_param *)d; 1211 switch (param->param) { 1212 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1213 radeonfb_set_backlight(dp, param->curval); 1214 return 0; 1215 case WSDISPLAYIO_PARAM_BACKLIGHT: 1216 radeonfb_switch_backlight(dp, param->curval); 1217 return 0; 1218 } 1219 return EPASSTHROUGH; 1220 1221 /* PCI config read/write passthrough. */ 1222 case PCI_IOC_CFGREAD: 1223 case PCI_IOC_CFGWRITE: 1224 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1225 1226 case WSDISPLAYIO_GET_BUSID: 1227 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1228 sc->sc_pt, d); 1229 1230 case WSDISPLAYIO_GET_EDID: { 1231 struct wsdisplayio_edid_info *ei = d; 1232 return wsdisplayio_get_edid(sc->sc_dev, ei); 1233 } 1234 1235 case WSDISPLAYIO_GET_FBINFO: { 1236 struct wsdisplayio_fbinfo *fbi = d; 1237 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1238 } 1239 1240 default: 1241 return EPASSTHROUGH; 1242 } 1243 } 1244 1245 paddr_t 1246 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1247 { 1248 struct vcons_data *vd; 1249 struct radeonfb_display *dp; 1250 struct radeonfb_softc *sc; 1251 paddr_t pa; 1252 1253 vd = (struct vcons_data *)v; 1254 dp = (struct radeonfb_display *)vd->cookie; 1255 sc = dp->rd_softc; 1256 1257 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1258 pa = bus_space_mmap(sc->sc_memt, 1259 sc->sc_memaddr + dp->rd_offset + offset, 0, 1260 prot, BUS_SPACE_MAP_LINEAR); 1261 return pa; 1262 } 1263 1264 /* 1265 * restrict all other mappings to processes with superuser privileges 1266 * or the kernel itself 1267 */ 1268 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1269 NULL, NULL, NULL, NULL) != 0) { 1270 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1271 return -1; 1272 } 1273 1274 if ((offset >= sc->sc_regaddr) && 1275 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1276 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1277 BUS_SPACE_MAP_LINEAR); 1278 } 1279 1280 if ((offset >= sc->sc_memaddr) && 1281 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1282 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1283 BUS_SPACE_MAP_LINEAR); 1284 } 1285 1286 if ((offset >= sc->sc_romaddr) && 1287 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1288 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1289 BUS_SPACE_MAP_LINEAR); 1290 } 1291 1292 #ifdef PCI_MAGIC_IO_RANGE 1293 /* allow mapping of IO space */ 1294 if ((offset >= PCI_MAGIC_IO_RANGE) && 1295 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1296 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1297 0, prot, 0); 1298 return pa; 1299 } 1300 #endif /* PCI_MAGIC_IO_RANGE */ 1301 1302 return -1; 1303 } 1304 1305 static void 1306 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1307 { 1308 bus_space_tag_t romt; 1309 bus_space_handle_t romh, biosh; 1310 bus_size_t romsz; 1311 bus_addr_t ptr; 1312 1313 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1314 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1315 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1316 return; 1317 } 1318 1319 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1320 &sc->sc_biossz); 1321 if (sc->sc_biossz == 0) { 1322 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1323 return; 1324 } 1325 1326 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1327 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1328 1329 /* unmap the PCI expansion rom */ 1330 bus_space_unmap(romt, romh, romsz); 1331 1332 /* turn off rom decoder now */ 1333 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1334 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1335 ~PCI_MAPREG_ROM_ENABLE); 1336 1337 ptr = GETBIOS16(sc, 0x48); 1338 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1339 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1340 sc->sc_flags |= RFB_ATOM; 1341 } 1342 1343 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1344 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1345 } 1346 1347 1348 uint32_t 1349 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1350 { 1351 1352 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1353 } 1354 1355 void 1356 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1357 { 1358 1359 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1360 } 1361 1362 void 1363 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1364 { 1365 1366 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1367 } 1368 1369 void 1370 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1371 uint32_t andmask, uint32_t ormask) 1372 { 1373 int s; 1374 uint32_t val; 1375 1376 s = splhigh(); 1377 val = radeonfb_get32(sc, reg); 1378 val = (val & andmask) | ormask; 1379 radeonfb_put32(sc, reg, val); 1380 splx(s); 1381 } 1382 1383 uint32_t 1384 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1385 { 1386 int s; 1387 uint32_t val; 1388 1389 s = splhigh(); 1390 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1391 val = radeonfb_get32(sc, RADEON_MM_DATA); 1392 splx(s); 1393 1394 return (val); 1395 } 1396 1397 void 1398 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1399 { 1400 int s; 1401 1402 s = splhigh(); 1403 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1404 radeonfb_put32(sc, RADEON_MM_DATA, val); 1405 splx(s); 1406 } 1407 1408 void 1409 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1410 uint32_t andmask, uint32_t ormask) 1411 { 1412 int s; 1413 uint32_t val; 1414 1415 s = splhigh(); 1416 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1417 val = radeonfb_get32(sc, RADEON_MM_DATA); 1418 val = (val & andmask) | ormask; 1419 radeonfb_put32(sc, RADEON_MM_DATA, val); 1420 splx(s); 1421 } 1422 1423 uint32_t 1424 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1425 { 1426 int s; 1427 uint32_t val; 1428 1429 s = splhigh(); 1430 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1431 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1432 if (HAS_R300CG(sc)) 1433 radeonfb_r300cg_workaround(sc); 1434 splx(s); 1435 1436 return (val); 1437 } 1438 1439 void 1440 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1441 { 1442 int s; 1443 1444 s = splhigh(); 1445 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1446 RADEON_PLL_WR_EN); 1447 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1448 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1449 splx(s); 1450 } 1451 1452 void 1453 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1454 uint32_t andmask, uint32_t ormask) 1455 { 1456 int s; 1457 uint32_t val; 1458 1459 s = splhigh(); 1460 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1461 RADEON_PLL_WR_EN); 1462 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1463 val = (val & andmask) | ormask; 1464 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1465 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1466 splx(s); 1467 } 1468 1469 int 1470 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1471 { 1472 uint32_t saved; 1473 1474 saved = GET32(sc, reg); 1475 PUT32(sc, reg, v); 1476 if (GET32(sc, reg) != v) { 1477 return -1; 1478 } 1479 PUT32(sc, reg, saved); 1480 return 0; 1481 } 1482 1483 uintmax_t 1484 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1485 uintmax_t defval) 1486 { 1487 prop_number_t pn; 1488 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1489 if (pn == NULL) { 1490 return defval; 1491 } 1492 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1493 return (prop_number_integer_value(pn)); 1494 } 1495 1496 int 1497 radeonfb_getclocks(struct radeonfb_softc *sc) 1498 { 1499 bus_addr_t ptr; 1500 int refclk = 0; 1501 int refdiv = 0; 1502 int minpll = 0; 1503 int maxpll = 0; 1504 1505 /* load initial property values if port/board provides them */ 1506 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1507 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1508 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1509 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1510 1511 PRINTPLL(RADEON_PPLL_REF_DIV); 1512 PRINTPLL(RADEON_PPLL_DIV_0); 1513 PRINTPLL(RADEON_PPLL_DIV_1); 1514 PRINTPLL(RADEON_PPLL_DIV_2); 1515 PRINTPLL(RADEON_PPLL_DIV_3); 1516 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1517 PRINTPLL(RADEON_P2PLL_REF_DIV); 1518 PRINTPLL(RADEON_P2PLL_DIV_0); 1519 1520 if (refclk && refdiv && minpll && maxpll) 1521 goto dontprobe; 1522 1523 if (!sc->sc_biossz) { 1524 /* no BIOS */ 1525 aprint_verbose("%s: No video BIOS, using default clocks\n", 1526 XNAME(sc)); 1527 if (IS_IGP(sc)) 1528 refclk = refclk ? refclk : 1432; 1529 else 1530 refclk = refclk ? refclk : 2700; 1531 refdiv = refdiv ? refdiv : 12; 1532 minpll = minpll ? minpll : 12500; 1533 /* XXX 1534 * Need to check if the firmware or something programmed a 1535 * higher value than this, and if so, bump it. 1536 * The RV280 in my iBook is unhappy if the PLL input is less 1537 * than 360MHz 1538 */ 1539 maxpll = maxpll ? maxpll : 40000/*35000*/; 1540 } else if (IS_ATOM(sc)) { 1541 /* ATOM BIOS */ 1542 ptr = GETBIOS16(sc, 0x48); 1543 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1544 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1545 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1546 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1547 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1548 /* 1549 * ATOM BIOS doesn't supply a reference divider, so we 1550 * have to probe for it. 1551 */ 1552 if (refdiv < 2) 1553 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1554 RADEON_PPLL_REF_DIV_MASK; 1555 /* 1556 * if probe is zero, just assume one that should work 1557 * for most parts 1558 */ 1559 if (refdiv < 2) 1560 refdiv = 12; 1561 1562 } else { 1563 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1564 /* Legacy BIOS */ 1565 ptr = GETBIOS16(sc, 0x48); 1566 ptr = GETBIOS16(sc, ptr + 0x30); 1567 if (IS_R300(sc)) { 1568 refdiv = refdiv ? refdiv : 1569 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1570 R300_PPLL_REF_DIV_ACC_SHIFT; 1571 } else { 1572 refdiv = refdiv ? refdiv : 1573 tmp & RADEON_PPLL_REF_DIV_MASK; 1574 } 1575 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1576 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1577 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1578 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1579 } 1580 1581 1582 dontprobe: 1583 sc->sc_refclk = refclk * 10; 1584 sc->sc_refdiv = refdiv; 1585 sc->sc_minpll = minpll * 10; 1586 sc->sc_maxpll = maxpll * 10; 1587 return 0; 1588 } 1589 1590 int 1591 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1592 uint32_t *postdivbit, uint32_t *feedbackdiv) 1593 { 1594 int i; 1595 uint32_t outfreq; 1596 int div; 1597 1598 DPRINTF(("dot clock: %u\n", dotclock)); 1599 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1600 outfreq = div * dotclock; 1601 if ((outfreq >= sc->sc_minpll) && 1602 (outfreq <= sc->sc_maxpll)) { 1603 DPRINTF(("outfreq: %u\n", outfreq)); 1604 *postdivbit = 1605 ((uint32_t)radeonfb_dividers[i].mask << 16); 1606 DPRINTF(("post divider: %d (mask %x)\n", div, 1607 *postdivbit)); 1608 break; 1609 } 1610 } 1611 1612 if (div == 0) 1613 return 1; 1614 1615 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1616 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1617 return 0; 1618 } 1619 1620 #if 0 1621 #ifdef RADEONFB_DEBUG 1622 static void 1623 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1624 { 1625 char asc[17]; 1626 unsigned ptr = (unsigned)buffer; 1627 char *start = (char *)(ptr & ~0xf); 1628 char *end = (char *)(ptr + size); 1629 1630 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1631 1632 if (pfx == NULL) { 1633 pfx = ""; 1634 } 1635 1636 while (start < end) { 1637 unsigned offset = (unsigned)start & 0xf; 1638 if (offset == 0) { 1639 printf("%s%x: ", pfx, (unsigned)start); 1640 } 1641 if (((unsigned)start < ptr) || 1642 ((unsigned)start >= (ptr + size))) { 1643 printf(" "); 1644 asc[offset] = ' '; 1645 } else { 1646 printf("%02x", *(unsigned char *)start); 1647 if ((*start >= ' ') && (*start <= '~')) { 1648 asc[offset] = *start; 1649 } else { 1650 asc[offset] = '.'; 1651 } 1652 } 1653 asc[offset + 1] = 0; 1654 if (offset % 2) { 1655 printf(" "); 1656 } 1657 if (offset == 15) { 1658 printf(" %s\n", asc); 1659 } 1660 start++; 1661 } 1662 } 1663 #endif 1664 #endif 1665 1666 int 1667 radeonfb_getconnectors(struct radeonfb_softc *sc) 1668 { 1669 int i; 1670 int found = 0; 1671 1672 for (i = 0; i < 2; i++) { 1673 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1674 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1675 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1676 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1677 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1678 } 1679 1680 /* 1681 * This logic is borrowed from Xorg's radeon driver. 1682 */ 1683 if (!sc->sc_biossz) 1684 goto nobios; 1685 1686 if (IS_ATOM(sc)) { 1687 /* not done yet */ 1688 } else { 1689 uint16_t ptr; 1690 int port = 0; 1691 1692 ptr = GETBIOS16(sc, 0x48); 1693 ptr = GETBIOS16(sc, ptr + 0x50); 1694 for (i = 1; i < 4; i++) { 1695 uint16_t entry; 1696 uint8_t conn, ddc, dac, tmds; 1697 1698 /* 1699 * Parse the connector table. From reading the code, 1700 * it appears to made up of 16-bit entries for each 1701 * connector. The 16-bits are defined as: 1702 * 1703 * bits 12-15 - connector type (0 == end of table) 1704 * bits 8-11 - DDC type 1705 * bits 5-7 - ??? 1706 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1707 * bits 1-3 - ??? 1708 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1709 */ 1710 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1711 break; 1712 entry = GETBIOS16(sc, ptr + i * 2); 1713 1714 conn = (entry >> 12) & 0xf; 1715 ddc = (entry >> 8) & 0xf; 1716 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1717 RADEON_DAC_PRIMARY; 1718 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1719 RADEON_TMDS_INT; 1720 1721 if (conn == RADEON_CONN_NONE) 1722 continue; /* no connector */ 1723 1724 if ((found > 0) && 1725 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1726 /* duplicate entry for same connector */ 1727 continue; 1728 } 1729 1730 /* internal DDC_DVI port gets priority */ 1731 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1732 port = 0; 1733 else 1734 port = 1; 1735 1736 sc->sc_ports[port].rp_ddc_type = 1737 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1738 sc->sc_ports[port].rp_dac_type = dac; 1739 sc->sc_ports[port].rp_conn_type = 1740 min(conn, RADEON_CONN_UNSUPPORTED) ; 1741 1742 sc->sc_ports[port].rp_tmds_type = tmds; 1743 1744 if ((conn != RADEON_CONN_DVI_I) && 1745 (conn != RADEON_CONN_DVI_D) && 1746 (tmds == RADEON_TMDS_INT)) 1747 sc->sc_ports[port].rp_tmds_type = 1748 RADEON_TMDS_UNKNOWN; 1749 sc->sc_ports[port].rp_number = i - 1; 1750 1751 found += (port + 1); 1752 } 1753 } 1754 1755 nobios: 1756 if (!found) { 1757 DPRINTF(("No connector info in BIOS!\n")); 1758 if IS_MOBILITY(sc) { 1759 /* default, port 0 = internal TMDS, port 1 = CRT */ 1760 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1761 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1762 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1763 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1764 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1765 sc->sc_ports[0].rp_number = 0; 1766 1767 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1768 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1769 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1770 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1771 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1772 sc->sc_ports[1].rp_number = 1; 1773 } else { 1774 /* default, port 0 = DVI, port 1 = CRT */ 1775 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1776 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1777 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1778 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1779 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1780 sc->sc_ports[0].rp_number = 1; 1781 1782 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1783 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1784 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1785 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1786 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1787 sc->sc_ports[1].rp_number = 0; 1788 } 1789 } 1790 1791 /* 1792 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1793 * these chips should use TVDAC for the VGA port. 1794 */ 1795 if (HAS_SDAC(sc)) { 1796 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1797 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1798 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1799 } else { 1800 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1801 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1802 } 1803 } else if (!HAS_CRTC2(sc)) { 1804 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1805 } 1806 1807 for (i = 0; i < 2; i++) { 1808 char edid[128]; 1809 uint8_t ddc; 1810 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1811 prop_data_t edid_data; 1812 1813 DPRINTF(("Port #%d:\n", i)); 1814 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1815 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1816 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1817 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1818 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1819 1820 sc->sc_ports[i].rp_edid_valid = 0; 1821 /* first look for static EDID data */ 1822 if ((edid_data = prop_dictionary_get(device_properties( 1823 sc->sc_dev), "EDID")) != NULL) { 1824 1825 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1826 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1827 if (edid_parse(edid, eip) == 0) { 1828 1829 sc->sc_ports[i].rp_edid_valid = 1; 1830 } 1831 } 1832 /* if we didn't find any we'll try to talk to the monitor */ 1833 if (sc->sc_ports[i].rp_edid_valid != 1) { 1834 1835 ddc = sc->sc_ports[i].rp_ddc_type; 1836 if (ddc != RADEON_DDC_NONE) { 1837 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1838 == 0) && (edid_parse(edid, eip) == 0)) { 1839 1840 sc->sc_ports[i].rp_edid_valid = 1; 1841 #ifdef RADEONFB_DEBUG 1842 edid_print(eip); 1843 #endif 1844 } 1845 } 1846 } 1847 } 1848 1849 return found; 1850 } 1851 1852 int 1853 radeonfb_gettmds(struct radeonfb_softc *sc) 1854 { 1855 int i; 1856 1857 if (!sc->sc_biossz) { 1858 goto nobios; 1859 } 1860 1861 if (IS_ATOM(sc)) { 1862 /* XXX: not done yet */ 1863 } else { 1864 uint16_t ptr; 1865 int n; 1866 1867 ptr = GETBIOS16(sc, 0x48); 1868 ptr = GETBIOS16(sc, ptr + 0x34); 1869 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1870 if (GETBIOS8(sc, ptr) == 3) { 1871 /* revision three table */ 1872 n = GETBIOS8(sc, ptr + 5) + 1; 1873 n = min(n, 4); 1874 1875 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1876 for (i = 0; i < n; i++) { 1877 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1878 ptr + i * 10 + 8); 1879 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1880 ptr + i * 10 + 0x10); 1881 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1882 sc->sc_tmds_pll[i].rtp_freq, 1883 sc->sc_tmds_pll[i].rtp_pll)); 1884 } 1885 return 0; 1886 } 1887 } 1888 1889 nobios: 1890 DPRINTF(("no suitable DFP table present\n")); 1891 for (i = 0; 1892 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1893 i++) { 1894 int j; 1895 1896 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1897 continue; 1898 1899 for (j = 0; j < 4; j++) { 1900 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1901 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1902 sc->sc_tmds_pll[j].rtp_freq, 1903 sc->sc_tmds_pll[j].rtp_pll)); 1904 } 1905 return 0; 1906 } 1907 1908 return -1; 1909 } 1910 1911 const struct videomode * 1912 radeonfb_modelookup(const char *name) 1913 { 1914 int i; 1915 1916 for (i = 0; i < videomode_count; i++) 1917 if (!strcmp(name, videomode_list[i].name)) 1918 return &videomode_list[i]; 1919 1920 return NULL; 1921 } 1922 1923 void 1924 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1925 { 1926 if (crtc) { 1927 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1928 RADEON_P2PLL_ATOMIC_UPDATE_R); 1929 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1930 } else { 1931 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1932 RADEON_PPLL_ATOMIC_UPDATE_R); 1933 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1934 } 1935 } 1936 1937 void 1938 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1939 { 1940 int i; 1941 1942 for (i = 10000; i; i--) { 1943 if (crtc) { 1944 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1945 RADEON_P2PLL_ATOMIC_UPDATE_R) 1946 break; 1947 } else { 1948 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1949 RADEON_PPLL_ATOMIC_UPDATE_R) 1950 break; 1951 } 1952 } 1953 } 1954 1955 void 1956 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1957 { 1958 uint32_t pbit = 0; 1959 uint32_t feed = 0; 1960 uint32_t data, refdiv, div0; 1961 1962 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1963 1964 if (crtc == 0) { 1965 1966 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 1967 if (IS_R300(sc)) { 1968 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 1969 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 1970 } else { 1971 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 1972 sc->sc_refdiv; 1973 } 1974 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 1975 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 1976 RADEON_PPLL_POST3_DIV_MASK); 1977 div0 |= pbit; 1978 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1979 1980 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 1981 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 1982 /* 1983 * nothing to do here, the PLL is already where we 1984 * want it 1985 */ 1986 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1987 ~RADEON_PLL_DIV_SEL); 1988 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 1989 return; 1990 } 1991 1992 /* alright, we do need to reprogram stuff */ 1993 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1994 RADEON_VCLK_SRC_SEL_CPUCLK, 1995 ~RADEON_VCLK_SRC_SEL_MASK); 1996 1997 /* put vclk into reset, use atomic updates */ 1998 SETPLL(sc, RADEON_PPLL_CNTL, 1999 RADEON_PPLL_REFCLK_SEL | 2000 RADEON_PPLL_FBCLK_SEL | 2001 RADEON_PPLL_RESET | 2002 RADEON_PPLL_ATOMIC_UPDATE_EN | 2003 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2004 2005 /* select clock 0 */ 2006 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2007 ~RADEON_PLL_DIV_SEL); 2008 2009 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2010 2011 /* xf86-video-radeon does this, not sure why */ 2012 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2013 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2014 2015 /* use the atomic update */ 2016 radeonfb_pllwriteupdate(sc, crtc); 2017 2018 /* and wait for it to complete */ 2019 radeonfb_pllwaitatomicread(sc, crtc); 2020 2021 /* program HTOTAL (why?) */ 2022 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2023 2024 /* drop reset */ 2025 CLRPLL(sc, RADEON_PPLL_CNTL, 2026 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2027 RADEON_PPLL_ATOMIC_UPDATE_EN | 2028 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2029 2030 PRINTPLL(RADEON_PPLL_CNTL); 2031 PRINTPLL(RADEON_PPLL_REF_DIV); 2032 PRINTPLL(RADEON_PPLL_DIV_3); 2033 2034 /* give clock time to lock */ 2035 delay(50000); 2036 2037 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2038 RADEON_VCLK_SRC_SEL_PPLLCLK, 2039 ~RADEON_VCLK_SRC_SEL_MASK); 2040 2041 } else { 2042 2043 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2044 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2045 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2046 2047 /* put vclk into reset, use atomic updates */ 2048 SETPLL(sc, RADEON_P2PLL_CNTL, 2049 RADEON_P2PLL_RESET | 2050 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2051 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2052 2053 /* program reference divider */ 2054 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2055 ~RADEON_P2PLL_REF_DIV_MASK); 2056 2057 /* program feedback and post dividers */ 2058 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2059 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2060 RADEON_P2PLL_POST0_DIV_MASK); 2061 data |= pbit; 2062 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2063 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2064 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2065 2066 PRINTPLL(RADEON_P2PLL_REF_DIV); 2067 PRINTPLL(RADEON_P2PLL_DIV_0); 2068 2069 /* use the atomic update */ 2070 radeonfb_pllwriteupdate(sc, crtc); 2071 2072 /* and wait for it to complete */ 2073 radeonfb_pllwaitatomicread(sc, crtc); 2074 2075 /* program HTOTAL (why?) */ 2076 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2077 2078 /* drop reset */ 2079 CLRPLL(sc, RADEON_P2PLL_CNTL, 2080 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2081 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2082 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2083 2084 /* allow time for clock to lock */ 2085 delay(50000); 2086 2087 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2088 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2089 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2090 } 2091 PRINTREG(RADEON_CRTC_MORE_CNTL); 2092 } 2093 2094 void 2095 radeonfb_modeswitch(struct radeonfb_display *dp) 2096 { 2097 struct radeonfb_softc *sc = dp->rd_softc; 2098 int i; 2099 2100 /* blank the display while we switch modes */ 2101 radeonfb_blank(dp, 1); 2102 2103 #if 0 2104 SET32(sc, RADEON_CRTC_EXT_CNTL, 2105 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2106 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2107 #endif 2108 2109 /* these registers might get in the way... */ 2110 PUT32(sc, RADEON_OVR_CLR, 0); 2111 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2112 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2113 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2114 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2115 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2116 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2117 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2118 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2119 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2120 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2121 2122 for (i = 0; i < dp->rd_ncrtcs; i++) 2123 radeonfb_setcrtc(dp, i); 2124 2125 /* activate the display */ 2126 radeonfb_blank(dp, 0); 2127 } 2128 2129 void 2130 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2131 { 2132 int crtc; 2133 struct videomode *mode; 2134 struct radeonfb_softc *sc; 2135 struct radeonfb_crtc *cp; 2136 uint32_t v; 2137 uint32_t gencntl; 2138 uint32_t htotaldisp; 2139 uint32_t hsyncstrt; 2140 uint32_t vtotaldisp; 2141 uint32_t vsyncstrt; 2142 uint32_t fphsyncstrt; 2143 uint32_t fpvsyncstrt; 2144 uint32_t fphtotaldisp; 2145 uint32_t fpvtotaldisp; 2146 uint32_t pitch; 2147 2148 sc = dp->rd_softc; 2149 cp = &dp->rd_crtcs[index]; 2150 crtc = cp->rc_number; 2151 mode = &cp->rc_videomode; 2152 2153 #if 1 2154 pitch = dp->rd_stride / dp->rd_bpp; 2155 #else 2156 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2157 (sc->sc_maxbpp * 8)); 2158 #endif 2159 switch (crtc) { 2160 case 0: 2161 gencntl = RADEON_CRTC_GEN_CNTL; 2162 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2163 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2164 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2165 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2166 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2167 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2168 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2169 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2170 break; 2171 case 1: 2172 gencntl = RADEON_CRTC2_GEN_CNTL; 2173 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2174 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2175 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2176 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2177 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2178 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2179 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2180 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2181 break; 2182 default: 2183 panic("Bad CRTC!"); 2184 break; 2185 } 2186 2187 /* 2188 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2189 */ 2190 /* only bother with 32bpp and 8bpp */ 2191 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2192 2193 if (crtc == 1) { 2194 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2195 } else { 2196 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2197 } 2198 2199 if (mode->flags & VID_DBLSCAN) 2200 v |= RADEON_CRTC2_DBL_SCAN_EN; 2201 2202 if (mode->flags & VID_INTERLACE) 2203 v |= RADEON_CRTC2_INTERLACE_EN; 2204 2205 if (mode->flags & VID_CSYNC) { 2206 v |= RADEON_CRTC2_CSYNC_EN; 2207 if (crtc == 1) 2208 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2209 } 2210 2211 PUT32(sc, gencntl, v); 2212 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2213 2214 /* 2215 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2216 */ 2217 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2218 if (crtc == 0) { 2219 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2220 RADEON_CRTC_DISPLAY_DIS); 2221 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2222 if (mode->flags & VID_CSYNC) 2223 v |= RADEON_CRTC_VSYNC_TRISTAT; 2224 } 2225 /* unconditional turn on CRT, in case first CRTC is DFP */ 2226 v |= RADEON_CRTC_CRT_ON; 2227 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2228 PRINTREG(RADEON_CRTC_EXT_CNTL); 2229 2230 /* 2231 * H_TOTAL_DISP 2232 */ 2233 v = ((mode->hdisplay / 8) - 1) << 16; 2234 v |= (mode->htotal / 8) - 1; 2235 PUT32(sc, htotaldisp, v); 2236 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2237 PUT32(sc, fphtotaldisp, v); 2238 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2239 2240 /* 2241 * H_SYNC_STRT_WID 2242 */ 2243 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2244 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2245 if (mode->flags & VID_NHSYNC) 2246 v |= RADEON_CRTC_H_SYNC_POL; 2247 PUT32(sc, hsyncstrt, v); 2248 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2249 PUT32(sc, fphsyncstrt, v); 2250 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2251 2252 /* 2253 * V_TOTAL_DISP 2254 */ 2255 v = ((mode->vdisplay - 1) << 16); 2256 v |= (mode->vtotal - 1); 2257 PUT32(sc, vtotaldisp, v); 2258 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2259 PUT32(sc, fpvtotaldisp, v); 2260 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2261 2262 /* 2263 * V_SYNC_STRT_WID 2264 */ 2265 v = ((mode->vsync_end - mode->vsync_start) << 16); 2266 v |= (mode->vsync_start - 1); 2267 if (mode->flags & VID_NVSYNC) 2268 v |= RADEON_CRTC_V_SYNC_POL; 2269 PUT32(sc, vsyncstrt, v); 2270 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2271 PUT32(sc, fpvsyncstrt, v); 2272 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2273 2274 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2275 2276 switch (crtc) { 2277 case 0: 2278 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2279 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2280 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2281 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2282 2283 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2284 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2285 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2286 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2287 PRINTREG(RADEON_CRTC_EXT_CNTL); 2288 PRINTREG(RADEON_CRTC_GEN_CNTL); 2289 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2290 break; 2291 2292 case 1: 2293 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2294 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2295 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2296 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2297 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2298 RADEON_CRTC2_VSYNC_DIS | 2299 RADEON_CRTC2_HSYNC_DIS | 2300 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2301 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2302 break; 2303 } 2304 } 2305 2306 int 2307 radeonfb_isblank(struct radeonfb_display *dp) 2308 { 2309 uint32_t reg, mask; 2310 2311 if(!dp->rd_softc->sc_mapped) 2312 return 1; 2313 2314 if (dp->rd_crtcs[0].rc_number) { 2315 reg = RADEON_CRTC2_GEN_CNTL; 2316 mask = RADEON_CRTC2_DISP_DIS; 2317 } else { 2318 reg = RADEON_CRTC_EXT_CNTL; 2319 mask = RADEON_CRTC_DISPLAY_DIS; 2320 } 2321 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2322 } 2323 2324 void 2325 radeonfb_blank(struct radeonfb_display *dp, int blank) 2326 { 2327 struct radeonfb_softc *sc = dp->rd_softc; 2328 uint32_t reg, mask; 2329 uint32_t fpreg, fpval; 2330 int i; 2331 2332 if (!sc->sc_mapped) 2333 return; 2334 2335 for (i = 0; i < dp->rd_ncrtcs; i++) { 2336 2337 if (dp->rd_crtcs[i].rc_number) { 2338 reg = RADEON_CRTC2_GEN_CNTL; 2339 mask = RADEON_CRTC2_DISP_DIS; 2340 fpreg = RADEON_FP2_GEN_CNTL; 2341 fpval = RADEON_FP2_ON; 2342 } else { 2343 reg = RADEON_CRTC_EXT_CNTL; 2344 mask = RADEON_CRTC_DISPLAY_DIS; 2345 fpreg = RADEON_FP_GEN_CNTL; 2346 fpval = RADEON_FP_FPON; 2347 } 2348 2349 if (blank) { 2350 SET32(sc, reg, mask); 2351 CLR32(sc, fpreg, fpval); 2352 } else { 2353 CLR32(sc, reg, mask); 2354 SET32(sc, fpreg, fpval); 2355 } 2356 } 2357 PRINTREG(RADEON_FP_GEN_CNTL); 2358 PRINTREG(RADEON_FP2_GEN_CNTL); 2359 } 2360 2361 void 2362 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2363 long *defattr) 2364 { 2365 struct radeonfb_display *dp = cookie; 2366 struct rasops_info *ri = &scr->scr_ri; 2367 2368 /* initialize font subsystem */ 2369 wsfont_init(); 2370 2371 DPRINTF(("init screen called, existing %d\n", existing)); 2372 2373 ri->ri_depth = dp->rd_bpp; 2374 ri->ri_width = dp->rd_virtx; 2375 ri->ri_height = dp->rd_virty; 2376 ri->ri_stride = dp->rd_stride; 2377 ri->ri_flg = RI_CENTER; 2378 switch (ri->ri_depth) { 2379 case 8: 2380 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB; 2381 break; 2382 case 32: 2383 ri->ri_flg |= RI_ENABLE_ALPHA; 2384 /* we run radeons in RGB even on SPARC hardware */ 2385 ri->ri_rnum = 8; 2386 ri->ri_gnum = 8; 2387 ri->ri_bnum = 8; 2388 ri->ri_rpos = 16; 2389 ri->ri_gpos = 8; 2390 ri->ri_bpos = 0; 2391 break; 2392 } 2393 2394 ri->ri_bits = (void *)dp->rd_fbptr; 2395 2396 #ifdef VCONS_DRAW_INTR 2397 scr->scr_flags |= VCONS_DONT_READ; 2398 #endif 2399 2400 if (existing) { 2401 ri->ri_flg |= RI_CLEAR; 2402 2403 /* start a modeswitch now */ 2404 radeonfb_modeswitch(dp); 2405 } 2406 2407 /* 2408 * XXX: font selection should be based on properties, with some 2409 * normal/reasonable default. 2410 */ 2411 2412 /* initialize and look for an initial font */ 2413 rasops_init(ri, 0, 0); 2414 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2415 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE; 2416 2417 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2418 dp->rd_virtx / ri->ri_font->fontwidth); 2419 2420 /* enable acceleration */ 2421 dp->rd_putchar = ri->ri_ops.putchar; 2422 ri->ri_ops.copyrows = radeonfb_copyrows; 2423 ri->ri_ops.copycols = radeonfb_copycols; 2424 ri->ri_ops.eraserows = radeonfb_eraserows; 2425 ri->ri_ops.erasecols = radeonfb_erasecols; 2426 /* pick a putchar method based on font and Radeon model */ 2427 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2428 /* got a bitmap font */ 2429 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2430 if (IS_R300(dp->rd_softc)) { 2431 /* 2432 * radeonfb_putchar() doesn't work right on some R3xx 2433 * so we use software drawing here, the wrapper just 2434 * makes sure the engine is idle before scribbling 2435 * into vram 2436 */ 2437 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2438 } else 2439 #endif 2440 ri->ri_ops.putchar = radeonfb_putchar; 2441 } else { 2442 /* got an alpha font */ 2443 switch(ri->ri_depth) { 2444 case 32: 2445 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2446 break; 2447 case 8: 2448 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2449 break; 2450 default: 2451 /* XXX this should never happen */ 2452 panic("%s: depth is not 8 or 32 but we got an" \ 2453 " alpha font?!", __func__); 2454 } 2455 } 2456 ri->ri_ops.cursor = radeonfb_cursor; 2457 } 2458 2459 void 2460 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2461 { 2462 uint32_t gen, ext, gen2 = 0; 2463 uint32_t agploc, aperbase, apersize, mcfbloc; 2464 2465 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2466 /* XXX */ 2467 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2468 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2469 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2470 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2471 2472 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2473 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2474 #if 0 2475 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2476 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2477 #endif 2478 2479 if (HAS_CRTC2(sc)) { 2480 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2481 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2482 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2483 } 2484 2485 delay(100000); 2486 2487 mcfbloc = (aperbase >> 16) | 2488 ((aperbase + (apersize - 1)) & 0xffff0000); 2489 2490 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2491 sc->sc_memsz = apersize; 2492 2493 if (((agploc & 0xffff) << 16) != 2494 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2495 agploc = mcfbloc & 0xffff0000U; 2496 agploc |= ((agploc + 0x10000) >> 16); 2497 } 2498 2499 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2500 2501 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2502 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2503 2504 DPRINTF(("aperbase = %u\n", aperbase)); 2505 PRINTREG(RADEON_MC_FB_LOCATION); 2506 PRINTREG(RADEON_MC_AGP_LOCATION); 2507 2508 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2509 2510 if (HAS_CRTC2(sc)) 2511 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2512 2513 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2514 2515 #if 0 2516 /* XXX: what is this AGP garbage? :-) */ 2517 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2518 #endif 2519 2520 delay(100000); 2521 2522 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2523 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2524 2525 if (HAS_CRTC2(sc)) 2526 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2527 } 2528 2529 void 2530 radeonfb_init_misc(struct radeonfb_softc *sc) 2531 { 2532 PUT32(sc, RADEON_BUS_CNTL, 2533 RADEON_BUS_MASTER_DIS | 2534 RADEON_BUS_PREFETCH_MODE_ACT | 2535 RADEON_BUS_PCI_READ_RETRY_EN | 2536 RADEON_BUS_PCI_WRT_RETRY_EN | 2537 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2538 RADEON_BUS_MSTR_RD_MULT | 2539 RADEON_BUS_MSTR_RD_LINE | 2540 RADEON_BUS_RD_DISCARD_EN | 2541 RADEON_BUS_MSTR_DISCONNECT_EN | 2542 RADEON_BUS_READ_BURST); 2543 2544 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2545 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2546 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2547 PUT32(sc, RADEON_RBBM_CNTL, 2548 (3 << RADEON_RB_SETTLE_SHIFT) | 2549 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2550 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2551 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2552 2553 /* XXX: figure out what these mean! */ 2554 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2555 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2556 #if 0 2557 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2558 #endif 2559 2560 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2561 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2562 } 2563 2564 static void 2565 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2566 { 2567 struct radeonfb_softc *sc = dp->rd_softc; 2568 int crtc, cc; 2569 uint32_t vclk; 2570 2571 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2572 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2573 2574 /* initialize the palette for every CRTC used by this display */ 2575 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2576 crtc = dp->rd_crtcs[cc].rc_number; 2577 DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2578 2579 if (crtc) 2580 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2581 else 2582 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2583 2584 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2585 PUT32(sc, RADEON_PALETTE_30_DATA, 2586 (r << 22) | (g << 12) | (b << 2)); 2587 } 2588 2589 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2590 } 2591 2592 /* 2593 * This loads a linear color map for true color. 2594 */ 2595 void 2596 radeonfb_init_palette(struct radeonfb_display *dp) 2597 { 2598 int i; 2599 2600 #define DAC_WIDTH ((1 << 10) - 1) 2601 #define CLUT_WIDTH ((1 << 8) - 1) 2602 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2603 2604 if (dp->rd_bpp == 8) { 2605 2606 /* R3G3B2 palette */ 2607 uint32_t tmp, r, g, b; 2608 2609 for (i = 0; i <= CLUT_WIDTH; ++i) { 2610 tmp = i & 0xe0; 2611 2612 /* 2613 * replicate bits so 0xe0 maps to a red value of 0xff 2614 * in order to make white look actually white 2615 */ 2616 tmp |= (tmp >> 3) | (tmp >> 6); 2617 r = tmp; 2618 2619 tmp = (i & 0x1c) << 3; 2620 tmp |= (tmp >> 3) | (tmp >> 6); 2621 g = tmp; 2622 2623 tmp = (i & 0x03) << 6; 2624 tmp |= tmp >> 2; 2625 tmp |= tmp >> 4; 2626 b = tmp; 2627 2628 radeonfb_putpal(dp, i, r, g, b); 2629 } 2630 } else { 2631 /* linear ramp */ 2632 for (i = 0; i <= CLUT_WIDTH; ++i) { 2633 radeonfb_putpal(dp, i, i, i, i); 2634 } 2635 } 2636 } 2637 2638 static int 2639 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2640 { 2641 u_char *r, *g, *b; 2642 u_int index = cm->index; 2643 u_int count = cm->count; 2644 int i, error; 2645 u_char rbuf[256], gbuf[256], bbuf[256]; 2646 2647 #ifdef GENFB_DEBUG 2648 aprint_debug("putcmap: %d %d\n",index, count); 2649 #endif 2650 if (cm->index >= 256 || cm->count > 256 || 2651 (cm->index + cm->count) > 256) 2652 return EINVAL; 2653 error = copyin(cm->red, &rbuf[index], count); 2654 if (error) 2655 return error; 2656 error = copyin(cm->green, &gbuf[index], count); 2657 if (error) 2658 return error; 2659 error = copyin(cm->blue, &bbuf[index], count); 2660 if (error) 2661 return error; 2662 2663 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2664 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2665 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2666 2667 r = &dp->rd_cmap_red[index]; 2668 g = &dp->rd_cmap_green[index]; 2669 b = &dp->rd_cmap_blue[index]; 2670 2671 for (i = 0; i < count; i++) { 2672 radeonfb_putpal(dp, index, *r, *g, *b); 2673 index++; 2674 r++, g++, b++; 2675 } 2676 return 0; 2677 } 2678 2679 static int 2680 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2681 { 2682 u_int index = cm->index; 2683 u_int count = cm->count; 2684 int error; 2685 2686 if (index >= 255 || count > 256 || index + count > 256) 2687 return EINVAL; 2688 2689 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2690 if (error) 2691 return error; 2692 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2693 if (error) 2694 return error; 2695 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2696 if (error) 2697 return error; 2698 2699 return 0; 2700 } 2701 2702 /* 2703 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2704 */ 2705 void 2706 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2707 { 2708 uint32_t tmp, save; 2709 2710 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2711 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2712 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2713 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2714 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2715 } 2716 2717 /* 2718 * Acceleration entry points. 2719 */ 2720 2721 /* this one draws characters using bitmap fonts */ 2722 static void 2723 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2724 { 2725 struct rasops_info *ri = cookie; 2726 struct vcons_screen *scr = ri->ri_hw; 2727 struct radeonfb_display *dp = scr->scr_cookie; 2728 struct radeonfb_softc *sc = dp->rd_softc; 2729 struct wsdisplay_font *font = PICK_FONT(ri, c); 2730 uint32_t w, h; 2731 int xd, yd, offset, i; 2732 uint32_t bg, fg, gmc; 2733 uint32_t reg; 2734 uint8_t *data8; 2735 uint16_t *data16; 2736 void *data; 2737 2738 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2739 return; 2740 2741 if (!CHAR_IN_FONT(c, font)) 2742 return; 2743 2744 w = font->fontwidth; 2745 h = font->fontheight; 2746 2747 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2748 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2749 2750 xd = ri->ri_xorigin + col * w; 2751 yd = ri->ri_yorigin + row * h; 2752 2753 if (c == 0x20) { 2754 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2755 return; 2756 } 2757 data = WSFONT_GLYPH(c, font); 2758 2759 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2760 2761 radeonfb_wait_fifo(sc, 9); 2762 2763 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2764 RADEON_GMC_BRUSH_NONE | 2765 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2766 RADEON_GMC_DST_CLIPPING | 2767 RADEON_ROP3_S | 2768 RADEON_DP_SRC_SOURCE_HOST_DATA | 2769 RADEON_GMC_CLR_CMP_CNTL_DIS | 2770 RADEON_GMC_WR_MSK_DIS | 2771 gmc); 2772 2773 PUT32(sc, RADEON_SC_LEFT, xd); 2774 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2775 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2776 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2777 PUT32(sc, RADEON_DP_CNTL, 2778 RADEON_DST_X_LEFT_TO_RIGHT | 2779 RADEON_DST_Y_TOP_TO_BOTTOM); 2780 2781 PUT32(sc, RADEON_SRC_X_Y, 0); 2782 offset = 32 - (font->stride << 3); 2783 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2784 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2785 2786 radeonfb_wait_fifo(sc, h); 2787 switch (font->stride) { 2788 case 1: { 2789 data8 = data; 2790 for (i = 0; i < h; i++) { 2791 reg = *data8; 2792 #if BYTE_ORDER == LITTLE_ENDIAN 2793 reg = reg << 24; 2794 #endif 2795 bus_space_write_stream_4(sc->sc_regt, 2796 sc->sc_regh, RADEON_HOST_DATA0, reg); 2797 data8++; 2798 } 2799 break; 2800 } 2801 case 2: { 2802 data16 = data; 2803 for (i = 0; i < h; i++) { 2804 reg = *data16; 2805 #if BYTE_ORDER == LITTLE_ENDIAN 2806 reg = reg << 16; 2807 #endif 2808 bus_space_write_stream_4(sc->sc_regt, 2809 sc->sc_regh, RADEON_HOST_DATA0, reg); 2810 data16++; 2811 } 2812 break; 2813 } 2814 } 2815 if (attr & 1) 2816 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2817 } 2818 2819 /* ... while this one is for anti-aliased ones */ 2820 static void 2821 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2822 { 2823 struct rasops_info *ri = cookie; 2824 struct vcons_screen *scr = ri->ri_hw; 2825 struct radeonfb_display *dp = scr->scr_cookie; 2826 struct radeonfb_softc *sc = dp->rd_softc; 2827 struct wsdisplay_font *font = PICK_FONT(ri, c); 2828 uint32_t bg, fg, gmc; 2829 uint8_t *data; 2830 int w, h, xd, yd; 2831 int i, r, g, b, aval; 2832 int rf, gf, bf, rb, gb, bb; 2833 uint32_t pixel; 2834 int rv; 2835 2836 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2837 return; 2838 2839 if (!CHAR_IN_FONT(c, font)) 2840 return; 2841 2842 w = font->fontwidth; 2843 h = font->fontheight; 2844 2845 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2846 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2847 2848 xd = ri->ri_xorigin + col * w; 2849 yd = ri->ri_yorigin + row * h; 2850 2851 if (c == 0x20) { 2852 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2853 if (attr & 1) 2854 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2855 return; 2856 } 2857 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2858 if (rv == GC_OK) 2859 return; 2860 2861 data = WSFONT_GLYPH(c, font); 2862 2863 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2864 2865 radeonfb_wait_fifo(sc, 5); 2866 2867 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2868 RADEON_GMC_BRUSH_NONE | 2869 RADEON_GMC_SRC_DATATYPE_COLOR | 2870 RADEON_ROP3_S | 2871 RADEON_DP_SRC_SOURCE_HOST_DATA | 2872 RADEON_GMC_CLR_CMP_CNTL_DIS | 2873 RADEON_GMC_WR_MSK_DIS | 2874 gmc); 2875 2876 PUT32(sc, RADEON_DP_CNTL, 2877 RADEON_DST_X_LEFT_TO_RIGHT | 2878 RADEON_DST_Y_TOP_TO_BOTTOM); 2879 2880 PUT32(sc, RADEON_SRC_X_Y, 0); 2881 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2882 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2883 2884 rf = (fg >> 16) & 0xff; 2885 rb = (bg >> 16) & 0xff; 2886 gf = (fg >> 8) & 0xff; 2887 gb = (bg >> 8) & 0xff; 2888 bf = fg & 0xff; 2889 bb = bg & 0xff; 2890 2891 /* 2892 * I doubt we can upload data faster than even the slowest Radeon 2893 * could process them, especially when doing the alpha blending stuff 2894 * along the way, so just make sure there's some room in the FIFO and 2895 * then hammer away 2896 * As it turns out we can, so make periodic stops to let the FIFO 2897 * drain. 2898 */ 2899 radeonfb_wait_fifo(sc, 20); 2900 for (i = 0; i < ri->ri_fontscale; i++) { 2901 aval = *data; 2902 data++; 2903 if (aval == 0) { 2904 pixel = bg; 2905 } else if (aval == 255) { 2906 pixel = fg; 2907 } else { 2908 r = aval * rf + (255 - aval) * rb; 2909 g = aval * gf + (255 - aval) * gb; 2910 b = aval * bf + (255 - aval) * bb; 2911 pixel = (r & 0xff00) << 8 | 2912 (g & 0xff00) | 2913 (b & 0xff00) >> 8; 2914 } 2915 if (i & 16) 2916 radeonfb_wait_fifo(sc, 20); 2917 PUT32(sc, RADEON_HOST_DATA0, pixel); 2918 } 2919 if (rv == GC_ADD) { 2920 glyphcache_add(&dp->rd_gc, c, xd, yd); 2921 } else 2922 if (attr & 1) 2923 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2924 2925 } 2926 2927 static void 2928 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2929 { 2930 struct rasops_info *ri = cookie; 2931 struct vcons_screen *scr = ri->ri_hw; 2932 struct radeonfb_display *dp = scr->scr_cookie; 2933 struct radeonfb_softc *sc = dp->rd_softc; 2934 struct wsdisplay_font *font = PICK_FONT(ri, c); 2935 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2936 int i, x, y, wi, he, r, g, b, aval; 2937 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2938 uint8_t *data8; 2939 int rv, cnt; 2940 2941 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2942 return; 2943 2944 if (!CHAR_IN_FONT(c, font)) 2945 return; 2946 2947 wi = font->fontwidth; 2948 he = font->fontheight; 2949 2950 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2951 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2952 2953 x = ri->ri_xorigin + col * wi; 2954 y = ri->ri_yorigin + row * he; 2955 2956 if (c == 0x20) { 2957 radeonfb_rectfill(dp, x, y, wi, he, bg); 2958 if (attr & 1) 2959 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2960 return; 2961 } 2962 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 2963 if (rv == GC_OK) 2964 return; 2965 2966 data8 = WSFONT_GLYPH(c, font); 2967 2968 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2969 2970 radeonfb_wait_fifo(sc, 5); 2971 2972 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2973 RADEON_GMC_BRUSH_NONE | 2974 RADEON_GMC_SRC_DATATYPE_COLOR | 2975 RADEON_ROP3_S | 2976 RADEON_DP_SRC_SOURCE_HOST_DATA | 2977 RADEON_GMC_CLR_CMP_CNTL_DIS | 2978 RADEON_GMC_WR_MSK_DIS | 2979 gmc); 2980 2981 PUT32(sc, RADEON_DP_CNTL, 2982 RADEON_DST_X_LEFT_TO_RIGHT | 2983 RADEON_DST_Y_TOP_TO_BOTTOM); 2984 2985 PUT32(sc, RADEON_SRC_X_Y, 0); 2986 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 2987 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 2988 2989 /* 2990 * we need the RGB colours here, so get offsets into rasops_cmap 2991 */ 2992 fgo = ((attr >> 24) & 0xf) * 3; 2993 bgo = ((attr >> 16) & 0xf) * 3; 2994 2995 r0 = rasops_cmap[bgo]; 2996 r1 = rasops_cmap[fgo]; 2997 g0 = rasops_cmap[bgo + 1]; 2998 g1 = rasops_cmap[fgo + 1]; 2999 b0 = rasops_cmap[bgo + 2]; 3000 b1 = rasops_cmap[fgo + 2]; 3001 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3002 bg8 = R3G3B2(r0, g0, b0); 3003 fg8 = R3G3B2(r1, g1, b1); 3004 3005 radeonfb_wait_fifo(sc, 20); 3006 cnt = 0; 3007 for (i = 0; i < ri->ri_fontscale; i++) { 3008 aval = *data8; 3009 if (aval == 0) { 3010 pixel = bg8; 3011 } else if (aval == 255) { 3012 pixel = fg8; 3013 } else { 3014 r = aval * r1 + (255 - aval) * r0; 3015 g = aval * g1 + (255 - aval) * g0; 3016 b = aval * b1 + (255 - aval) * b0; 3017 pixel = ((r & 0xe000) >> 8) | 3018 ((g & 0xe000) >> 11) | 3019 ((b & 0xc000) >> 14); 3020 } 3021 latch |= pixel << (8 * (i & 3)); 3022 /* write in 32bit chunks */ 3023 if ((i & 3) == 3) { 3024 PUT32(sc, RADEON_HOST_DATA0, latch); 3025 /* 3026 * not strictly necessary, old data should be shifted 3027 * out 3028 */ 3029 latch = 0; 3030 cnt++; 3031 if (cnt > 16) { 3032 cnt = 0; 3033 radeonfb_wait_fifo(sc, 20); 3034 } 3035 } 3036 data8++; 3037 } 3038 /* if we have pixels left in latch write them out */ 3039 if ((i & 3) != 0) { 3040 /* 3041 * radeon is weird - apparently leftover pixels are written 3042 * from the middle, not from the left as everything else 3043 */ 3044 PUT32(sc, RADEON_HOST_DATA0, latch); 3045 } 3046 3047 if (rv == GC_ADD) { 3048 glyphcache_add(&dp->rd_gc, c, x, y); 3049 } else 3050 if (attr & 1) 3051 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3052 3053 } 3054 3055 /* 3056 * wrapper for software character drawing 3057 * just sync the engine and call rasops*_putchar() 3058 */ 3059 3060 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3061 static void 3062 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3063 { 3064 struct rasops_info *ri = cookie; 3065 struct vcons_screen *scr = ri->ri_hw; 3066 struct radeonfb_display *dp = scr->scr_cookie; 3067 3068 radeonfb_engine_idle(dp->rd_softc); 3069 dp->rd_putchar(ri, row, col, c, attr); 3070 } 3071 #endif 3072 3073 static void 3074 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3075 { 3076 struct rasops_info *ri = cookie; 3077 struct vcons_screen *scr = ri->ri_hw; 3078 struct radeonfb_display *dp = scr->scr_cookie; 3079 uint32_t x, y, w, h, fg, bg, ul; 3080 3081 /* XXX: check for full emulation mode? */ 3082 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3083 x = ri->ri_xorigin; 3084 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3085 w = ri->ri_emuwidth; 3086 h = ri->ri_font->fontheight * nrows; 3087 3088 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3089 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3090 } 3091 } 3092 3093 static void 3094 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3095 { 3096 struct rasops_info *ri = cookie; 3097 struct vcons_screen *scr = ri->ri_hw; 3098 struct radeonfb_display *dp = scr->scr_cookie; 3099 uint32_t x, ys, yd, w, h; 3100 3101 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3102 x = ri->ri_xorigin; 3103 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3104 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3105 w = ri->ri_emuwidth; 3106 h = ri->ri_font->fontheight * nrows; 3107 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3108 RADEON_ROP3_S); 3109 } 3110 } 3111 3112 static void 3113 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3114 { 3115 struct rasops_info *ri = cookie; 3116 struct vcons_screen *scr = ri->ri_hw; 3117 struct radeonfb_display *dp = scr->scr_cookie; 3118 uint32_t xs, xd, y, w, h; 3119 3120 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3121 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3122 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3123 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3124 w = ri->ri_font->fontwidth * ncols; 3125 h = ri->ri_font->fontheight; 3126 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3127 RADEON_ROP3_S); 3128 } 3129 } 3130 3131 static void 3132 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3133 long fillattr) 3134 { 3135 struct rasops_info *ri = cookie; 3136 struct vcons_screen *scr = ri->ri_hw; 3137 struct radeonfb_display *dp = scr->scr_cookie; 3138 uint32_t x, y, w, h, fg, bg, ul; 3139 3140 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3141 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3142 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3143 w = ri->ri_font->fontwidth * ncols; 3144 h = ri->ri_font->fontheight; 3145 3146 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3147 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3148 } 3149 } 3150 3151 static void 3152 radeonfb_cursor(void *cookie, int on, int row, int col) 3153 { 3154 struct rasops_info *ri = cookie; 3155 struct vcons_screen *scr = ri->ri_hw; 3156 struct radeonfb_display *dp = scr->scr_cookie; 3157 int x, y, wi, he; 3158 3159 wi = ri->ri_font->fontwidth; 3160 he = ri->ri_font->fontheight; 3161 3162 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3163 x = ri->ri_ccol * wi + ri->ri_xorigin; 3164 y = ri->ri_crow * he + ri->ri_yorigin; 3165 /* first turn off the old cursor */ 3166 if (ri->ri_flg & RI_CURSOR) { 3167 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3168 RADEON_ROP3_Dn); 3169 ri->ri_flg &= ~RI_CURSOR; 3170 } 3171 ri->ri_crow = row; 3172 ri->ri_ccol = col; 3173 /* then (possibly) turn on the new one */ 3174 if (on) { 3175 x = ri->ri_ccol * wi + ri->ri_xorigin; 3176 y = ri->ri_crow * he + ri->ri_yorigin; 3177 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3178 RADEON_ROP3_Dn); 3179 ri->ri_flg |= RI_CURSOR; 3180 } 3181 } else { 3182 scr->scr_ri.ri_crow = row; 3183 scr->scr_ri.ri_ccol = col; 3184 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3185 } 3186 } 3187 3188 /* 3189 * Underlying acceleration support. 3190 */ 3191 3192 static void 3193 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3194 int width, int height, uint32_t color) 3195 { 3196 struct radeonfb_softc *sc = dp->rd_softc; 3197 uint32_t gmc; 3198 3199 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3200 3201 radeonfb_wait_fifo(sc, 6); 3202 3203 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3204 RADEON_GMC_BRUSH_SOLID_COLOR | 3205 RADEON_GMC_SRC_DATATYPE_COLOR | 3206 RADEON_GMC_CLR_CMP_CNTL_DIS | 3207 RADEON_ROP3_P | gmc); 3208 3209 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3210 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3211 PUT32(sc, RADEON_DP_CNTL, 3212 RADEON_DST_X_LEFT_TO_RIGHT | 3213 RADEON_DST_Y_TOP_TO_BOTTOM); 3214 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3215 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3216 3217 } 3218 3219 static void 3220 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3221 int width, int height, long attr) 3222 { 3223 struct radeonfb_display *dp = cookie; 3224 3225 radeonfb_rectfill(dp, dstx, dsty, width, height, 3226 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3227 } 3228 3229 static void 3230 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3231 int dstx, int dsty, int width, int height, int rop) 3232 { 3233 struct radeonfb_display *dp = cookie; 3234 struct radeonfb_softc *sc = dp->rd_softc; 3235 uint32_t gmc; 3236 uint32_t dir; 3237 3238 if (dsty < srcy) { 3239 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3240 } else { 3241 srcy += height - 1; 3242 dsty += height - 1; 3243 dir = 0; 3244 } 3245 if (dstx < srcx) { 3246 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3247 } else { 3248 srcx += width - 1; 3249 dstx += width - 1; 3250 } 3251 3252 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3253 3254 radeonfb_wait_fifo(sc, 6); 3255 3256 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3257 RADEON_GMC_BRUSH_SOLID_COLOR | 3258 RADEON_GMC_SRC_DATATYPE_COLOR | 3259 RADEON_GMC_CLR_CMP_CNTL_DIS | 3260 RADEON_DP_SRC_SOURCE_MEMORY | 3261 rop | gmc); 3262 3263 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3264 PUT32(sc, RADEON_DP_CNTL, dir); 3265 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3266 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3267 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3268 } 3269 3270 static void 3271 radeonfb_engine_idle(struct radeonfb_softc *sc) 3272 { 3273 3274 radeonfb_wait_fifo(sc, 64); 3275 while ((GET32(sc, RADEON_RBBM_STATUS) & 3276 RADEON_RBBM_ACTIVE) != 0); 3277 radeonfb_engine_flush(sc); 3278 } 3279 3280 static inline void 3281 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3282 { 3283 int i; 3284 3285 for (i = RADEON_TIMEOUT; i; i--) { 3286 if ((GET32(sc, RADEON_RBBM_STATUS) & 3287 RADEON_RBBM_FIFOCNT_MASK) >= n) 3288 return; 3289 } 3290 #ifdef DIAGNOSTIC 3291 if (!i) 3292 printf("%s: timed out waiting for fifo (%x)\n", 3293 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3294 #endif 3295 } 3296 3297 static void 3298 radeonfb_engine_flush(struct radeonfb_softc *sc) 3299 { 3300 int i = 0; 3301 3302 if (IS_R300(sc)) { 3303 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3304 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3305 i++; 3306 } 3307 } else { 3308 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3309 RADEON_RB2D_DC_FLUSH_ALL); 3310 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3311 RADEON_RB2D_DC_BUSY) { 3312 i++; 3313 } 3314 } 3315 #ifdef DIAGNOSTIC 3316 if (i > RADEON_TIMEOUT) 3317 printf("%s: engine flush timed out!\n", XNAME(sc)); 3318 #endif 3319 } 3320 3321 static inline void 3322 radeonfb_unclip(struct radeonfb_softc *sc) 3323 { 3324 3325 radeonfb_wait_fifo(sc, 2); 3326 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3327 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3328 } 3329 3330 static void 3331 radeonfb_engine_init(struct radeonfb_display *dp) 3332 { 3333 struct radeonfb_softc *sc = dp->rd_softc; 3334 uint32_t pitch; 3335 3336 /* no 3D */ 3337 PUT32(sc, RADEON_RB3D_CNTL, 0); 3338 3339 radeonfb_engine_reset(sc); 3340 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3341 3342 radeonfb_wait_fifo(sc, 1); 3343 if (!IS_R300(sc)) 3344 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3345 3346 radeonfb_wait_fifo(sc, 3); 3347 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3348 (pitch << 22) | (sc->sc_aperbase >> 10)); 3349 3350 3351 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3352 (pitch << 22) | (sc->sc_aperbase >> 10)); 3353 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3354 (pitch << 22) | (sc->sc_aperbase >> 10)); 3355 3356 (void)GET32(sc, RADEON_DP_DATATYPE); 3357 3358 /* default scissors -- no clipping */ 3359 radeonfb_wait_fifo(sc, 1); 3360 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3361 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3362 3363 radeonfb_wait_fifo(sc, 1); 3364 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3365 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3366 RADEON_GMC_CLR_CMP_CNTL_DIS | 3367 RADEON_GMC_BRUSH_SOLID_COLOR | 3368 RADEON_GMC_SRC_DATATYPE_COLOR); 3369 3370 radeonfb_wait_fifo(sc, 10); 3371 PUT32(sc, RADEON_DST_LINE_START, 0); 3372 PUT32(sc, RADEON_DST_LINE_END, 0); 3373 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3374 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3375 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3376 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3377 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3378 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3379 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3380 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3381 radeonfb_engine_idle(sc); 3382 } 3383 3384 static void 3385 radeonfb_engine_reset(struct radeonfb_softc *sc) 3386 { 3387 uint32_t hpc, rbbm, mclkcntl, clkindex; 3388 3389 radeonfb_engine_flush(sc); 3390 3391 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3392 if (HAS_R300CG(sc)) 3393 radeonfb_r300cg_workaround(sc); 3394 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3395 3396 /* 3397 * According to comments in XFree code, resetting the HDP via 3398 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3399 * So we use HOST_PATH_CNTL instead. 3400 */ 3401 3402 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3403 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3404 if (IS_R300(sc)) { 3405 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3406 RADEON_SOFT_RESET_CP | 3407 RADEON_SOFT_RESET_HI | 3408 RADEON_SOFT_RESET_E2); 3409 GET32(sc, RADEON_RBBM_SOFT_RESET); 3410 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3411 /* 3412 * XXX: this bit is not defined in any ATI docs I have, 3413 * nor in the XFree code, but XFree does it. Why? 3414 */ 3415 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3416 } else { 3417 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3418 RADEON_SOFT_RESET_CP | 3419 RADEON_SOFT_RESET_SE | 3420 RADEON_SOFT_RESET_RE | 3421 RADEON_SOFT_RESET_PP | 3422 RADEON_SOFT_RESET_E2 | 3423 RADEON_SOFT_RESET_RB); 3424 GET32(sc, RADEON_RBBM_SOFT_RESET); 3425 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3426 ~(RADEON_SOFT_RESET_CP | 3427 RADEON_SOFT_RESET_SE | 3428 RADEON_SOFT_RESET_RE | 3429 RADEON_SOFT_RESET_PP | 3430 RADEON_SOFT_RESET_E2 | 3431 RADEON_SOFT_RESET_RB)); 3432 GET32(sc, RADEON_RBBM_SOFT_RESET); 3433 } 3434 3435 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3436 GET32(sc, RADEON_HOST_PATH_CNTL); 3437 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3438 3439 if (IS_R300(sc)) 3440 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3441 3442 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3443 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3444 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3445 3446 if (HAS_R300CG(sc)) 3447 radeonfb_r300cg_workaround(sc); 3448 } 3449 3450 static int 3451 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3452 { 3453 int x, y; 3454 3455 x = pos->x; 3456 y = pos->y; 3457 3458 /* 3459 * This doesn't let a cursor move off the screen. I'm not 3460 * sure if this will have negative effects for e.g. Xinerama. 3461 * I'd guess Xinerama handles it by changing the cursor shape, 3462 * but that needs verification. 3463 */ 3464 if (x >= dp->rd_virtx) 3465 x = dp->rd_virtx - 1; 3466 if (x < 0) 3467 x = 0; 3468 if (y >= dp->rd_virty) 3469 y = dp->rd_virty - 1; 3470 if (y < 0) 3471 y = 0; 3472 3473 dp->rd_cursor.rc_pos.x = x; 3474 dp->rd_cursor.rc_pos.y = y; 3475 3476 radeonfb_cursor_position(dp); 3477 return 0; 3478 } 3479 3480 static int 3481 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3482 { 3483 unsigned flags; 3484 3485 uint8_t r[2], g[2], b[2]; 3486 unsigned index, count; 3487 int i, err; 3488 int pitch, size; 3489 struct radeonfb_cursor nc; 3490 3491 flags = wc->which; 3492 3493 /* copy old values */ 3494 nc = dp->rd_cursor; 3495 3496 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3497 index = wc->cmap.index; 3498 count = wc->cmap.count; 3499 3500 if (index >= 2 || (index + count) > 2) 3501 return EINVAL; 3502 3503 err = copyin(wc->cmap.red, &r[index], count); 3504 if (err) 3505 return err; 3506 err = copyin(wc->cmap.green, &g[index], count); 3507 if (err) 3508 return err; 3509 err = copyin(wc->cmap.blue, &b[index], count); 3510 if (err) 3511 return err; 3512 3513 for (i = index; i < index + count; i++) { 3514 nc.rc_cmap[i] = 3515 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3516 } 3517 } 3518 3519 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3520 if ((wc->size.x > RADEON_CURSORMAXX) || 3521 (wc->size.y > RADEON_CURSORMAXY)) 3522 return EINVAL; 3523 3524 /* figure bytes per line */ 3525 pitch = (wc->size.x + 7) / 8; 3526 size = pitch * wc->size.y; 3527 3528 /* clear the old cursor and mask */ 3529 memset(nc.rc_image, 0, 512); 3530 memset(nc.rc_mask, 0, 512); 3531 3532 nc.rc_size = wc->size; 3533 3534 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3535 return err; 3536 3537 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3538 return err; 3539 } 3540 3541 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3542 nc.rc_hot = wc->hot; 3543 if (nc.rc_hot.x >= nc.rc_size.x) 3544 nc.rc_hot.x = nc.rc_size.x - 1; 3545 if (nc.rc_hot.y >= nc.rc_size.y) 3546 nc.rc_hot.y = nc.rc_size.y - 1; 3547 } 3548 3549 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3550 nc.rc_pos = wc->pos; 3551 if (nc.rc_pos.x >= dp->rd_virtx) 3552 nc.rc_pos.x = dp->rd_virtx - 1; 3553 #if 0 3554 if (nc.rc_pos.x < 0) 3555 nc.rc_pos.x = 0; 3556 #endif 3557 if (nc.rc_pos.y >= dp->rd_virty) 3558 nc.rc_pos.y = dp->rd_virty - 1; 3559 #if 0 3560 if (nc.rc_pos.y < 0) 3561 nc.rc_pos.y = 0; 3562 #endif 3563 } 3564 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3565 nc.rc_visible = wc->enable; 3566 } 3567 3568 dp->rd_cursor = nc; 3569 radeonfb_cursor_update(dp, wc->which); 3570 3571 return 0; 3572 } 3573 3574 static uint8_t 3575 radeonfb_backwards(uint8_t d) 3576 { 3577 uint8_t l; 3578 3579 l = d << 7; 3580 l |= ((d & 0x02) << 5); 3581 l |= ((d & 0x04) << 3); 3582 l |= ((d & 0x08) << 1); 3583 l |= ((d & 0x10) >> 1); 3584 l |= ((d & 0x20) >> 3); 3585 l |= ((d & 0x40) >> 5); 3586 l |= ((d & 0x80) >> 7); 3587 return l; 3588 } 3589 3590 /* 3591 * Change the cursor shape. Call this with the cursor locked to avoid 3592 * flickering/tearing. 3593 */ 3594 static void 3595 radeonfb_cursor_shape(struct radeonfb_display *dp) 3596 { 3597 uint8_t and[512], xor[512]; 3598 int i, j, src, dst /* , pitch */; 3599 const uint8_t *msk = dp->rd_cursor.rc_mask; 3600 const uint8_t *img = dp->rd_cursor.rc_image; 3601 3602 /* 3603 * Radeon cursor data interleaves one line of AND data followed 3604 * by a line of XOR data. (Each line corresponds to a whole hardware 3605 * pitch - i.e. 64 pixels or 8 bytes.) 3606 * 3607 * The cursor is displayed using the following table: 3608 * 3609 * AND XOR Result 3610 * ---------------------- 3611 * 0 0 Cursor color 0 3612 * 0 1 Cursor color 1 3613 * 1 0 Transparent 3614 * 1 1 Complement of background 3615 * 3616 * Our masks are therefore different from what we were passed. 3617 * Passed in, I'm assuming the data represents either color 0 or 1, 3618 * and a mask, so the passed in table looks like: 3619 * 3620 * IMG Mask Result 3621 * ----------------------- 3622 * 0 0 Transparent 3623 * 0 1 Cursor color 0 3624 * 1 0 Transparent 3625 * 1 1 Cursor color 1 3626 * 3627 * IF mask bit == 1, AND = 0, XOR = color. 3628 * IF mask bit == 0, AND = 1, XOR = 0. 3629 * 3630 * hence: AND = ~(mask); XOR = color & ~(mask); 3631 */ 3632 3633 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3634 3635 /* start by assuming all bits are transparent */ 3636 memset(and, 0xff, 512); 3637 memset(xor, 0x00, 512); 3638 3639 src = 0; 3640 dst = 0; 3641 for (i = 0; i < 64; i++) { 3642 for (j = 0; j < 64; j += 8) { 3643 if ((i < dp->rd_cursor.rc_size.y) && 3644 (j < dp->rd_cursor.rc_size.x)) { 3645 3646 /* take care to leave odd bits alone */ 3647 and[dst] &= ~(msk[src]); 3648 xor[dst] = img[src] & msk[src]; 3649 src++; 3650 } 3651 dst++; 3652 } 3653 } 3654 3655 for (i = 0; i < 512; i++) { 3656 and[i] = radeonfb_backwards(and[i]); 3657 xor[i] = radeonfb_backwards(xor[i]); 3658 } 3659 3660 /* copy the image into place */ 3661 for (i = 0; i < 64; i++) { 3662 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3663 &and[i * 8], 8); 3664 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3665 &xor[i * 8], 8); 3666 } 3667 } 3668 3669 static void 3670 radeonfb_cursor_position(struct radeonfb_display *dp) 3671 { 3672 struct radeonfb_softc *sc = dp->rd_softc; 3673 uint32_t offset, hvoff, hvpos; /* registers */ 3674 uint32_t coff; /* cursor offset */ 3675 int i, x, y, xoff, yoff, crtcoff; 3676 3677 /* 3678 * XXX: this also needs to handle pan/scan 3679 */ 3680 for (i = 0; i < dp->rd_ncrtcs; i++) { 3681 3682 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3683 3684 if (rcp->rc_number) { 3685 offset = RADEON_CUR2_OFFSET; 3686 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3687 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3688 crtcoff = RADEON_CRTC2_OFFSET; 3689 } else { 3690 offset = RADEON_CUR_OFFSET; 3691 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3692 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3693 crtcoff = RADEON_CRTC_OFFSET; 3694 } 3695 3696 x = dp->rd_cursor.rc_pos.x; 3697 y = dp->rd_cursor.rc_pos.y; 3698 3699 while (y < rcp->rc_yoffset) { 3700 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3701 } 3702 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3703 rcp->rc_yoffset += RADEON_PANINCREMENT; 3704 } 3705 while (x < rcp->rc_xoffset) { 3706 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3707 } 3708 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3709 rcp->rc_xoffset += RADEON_PANINCREMENT; 3710 } 3711 3712 /* adjust for the cursor's hotspot */ 3713 x -= dp->rd_cursor.rc_hot.x; 3714 y -= dp->rd_cursor.rc_hot.y; 3715 xoff = yoff = 0; 3716 3717 if (x >= dp->rd_virtx) 3718 x = dp->rd_virtx - 1; 3719 if (y >= dp->rd_virty) 3720 y = dp->rd_virty - 1; 3721 3722 /* now adjust cursor so it is relative to viewport */ 3723 x -= rcp->rc_xoffset; 3724 y -= rcp->rc_yoffset; 3725 3726 /* 3727 * no need to check for fall off, because we should 3728 * never move off the screen entirely! 3729 */ 3730 coff = 0; 3731 if (x < 0) { 3732 xoff = -x; 3733 x = 0; 3734 } 3735 if (y < 0) { 3736 yoff = -y; 3737 y = 0; 3738 coff = (yoff * 2) * 8; 3739 } 3740 3741 /* pan the display */ 3742 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3743 rcp->rc_xoffset); 3744 3745 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3746 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3747 /* NB: this unlocks the cursor */ 3748 PUT32(sc, hvpos, (x << 16) | y); 3749 } 3750 } 3751 3752 static void 3753 radeonfb_cursor_visible(struct radeonfb_display *dp) 3754 { 3755 int i; 3756 uint32_t gencntl, bit; 3757 3758 for (i = 0; i < dp->rd_ncrtcs; i++) { 3759 if (dp->rd_crtcs[i].rc_number) { 3760 gencntl = RADEON_CRTC2_GEN_CNTL; 3761 bit = RADEON_CRTC2_CUR_EN; 3762 } else { 3763 gencntl = RADEON_CRTC_GEN_CNTL; 3764 bit = RADEON_CRTC_CUR_EN; 3765 } 3766 3767 if (dp->rd_cursor.rc_visible) 3768 SET32(dp->rd_softc, gencntl, bit); 3769 else 3770 CLR32(dp->rd_softc, gencntl, bit); 3771 } 3772 } 3773 3774 static void 3775 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3776 { 3777 int i; 3778 uint32_t c0reg, c1reg; 3779 struct radeonfb_softc *sc = dp->rd_softc; 3780 3781 for (i = 0; i < dp->rd_ncrtcs; i++) { 3782 if (dp->rd_crtcs[i].rc_number) { 3783 c0reg = RADEON_CUR2_CLR0; 3784 c1reg = RADEON_CUR2_CLR1; 3785 } else { 3786 c0reg = RADEON_CUR_CLR0; 3787 c1reg = RADEON_CUR_CLR1; 3788 } 3789 3790 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3791 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3792 } 3793 } 3794 3795 static void 3796 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3797 { 3798 struct radeonfb_softc *sc; 3799 int i; 3800 3801 sc = dp->rd_softc; 3802 for (i = 0; i < dp->rd_ncrtcs; i++) { 3803 if (dp->rd_crtcs[i].rc_number) { 3804 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3805 } else { 3806 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3807 } 3808 } 3809 3810 if (which & WSDISPLAY_CURSOR_DOCMAP) 3811 radeonfb_cursor_cmap(dp); 3812 3813 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3814 radeonfb_cursor_shape(dp); 3815 3816 if (which & WSDISPLAY_CURSOR_DOCUR) 3817 radeonfb_cursor_visible(dp); 3818 3819 /* this one is unconditional, because it updates other stuff */ 3820 radeonfb_cursor_position(dp); 3821 } 3822 3823 static struct videomode * 3824 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3825 { 3826 int r1, r2; 3827 3828 /* otherwise pick the higher refresh rate */ 3829 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3830 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3831 3832 return (r1 < r2 ? m2 : m1); 3833 } 3834 3835 static const struct videomode * 3836 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3837 int x, int y) 3838 { 3839 struct edid_info *ep = &rp->rp_edid; 3840 struct videomode *vmp = NULL; 3841 int i; 3842 3843 if (!rp->rp_edid_valid) { 3844 /* fallback to safe mode */ 3845 return radeonfb_modelookup(sc->sc_defaultmode); 3846 } 3847 3848 /* always choose the preferred mode first! */ 3849 if (ep->edid_preferred_mode) { 3850 3851 /* XXX: add auto-stretching support for native mode */ 3852 3853 /* this may want panning to occur, btw */ 3854 if ((ep->edid_preferred_mode->hdisplay <= x) && 3855 (ep->edid_preferred_mode->vdisplay <= y)) 3856 return ep->edid_preferred_mode; 3857 } 3858 3859 for (i = 0; i < ep->edid_nmodes; i++) { 3860 /* 3861 * We elect to pick a resolution that is too large for 3862 * the monitor than one that is too small. This means 3863 * that we will prefer to pan rather than to try to 3864 * center a smaller display on a larger screen. In 3865 * practice, this shouldn't matter because if a 3866 * monitor can support a larger resolution, it can 3867 * probably also support the smaller. A specific 3868 * exception is fixed format panels, but hopefully 3869 * they are properly dealt with by the "autostretch" 3870 * logic above. 3871 */ 3872 if ((ep->edid_modes[i].hdisplay > x) || 3873 (ep->edid_modes[i].vdisplay > y)) { 3874 continue; 3875 } 3876 3877 /* 3878 * at this point, the display mode is no larger than 3879 * what we've requested. 3880 */ 3881 if (vmp == NULL) 3882 vmp = &ep->edid_modes[i]; 3883 3884 /* eliminate smaller modes */ 3885 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3886 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3887 continue; 3888 3889 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3890 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3891 vmp = &ep->edid_modes[i]; 3892 continue; 3893 } 3894 3895 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3896 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3897 3898 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3899 } 3900 3901 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3902 } 3903 3904 static int 3905 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3906 { 3907 int i; 3908 3909 for (i = 0; i < nlist; i++) { 3910 if ((x == list[i].hdisplay) && 3911 (y == list[i].vdisplay)) { 3912 return 1; 3913 } 3914 } 3915 return 0; 3916 } 3917 3918 static void 3919 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3920 int pan) 3921 { 3922 struct radeonfb_port *rp; 3923 struct edid_info *ep; 3924 int i, j; 3925 3926 *x = 0; 3927 *y = 0; 3928 3929 if (pan) { 3930 for (i = 0; i < dp->rd_ncrtcs; i++) { 3931 rp = dp->rd_crtcs[i].rc_port; 3932 ep = &rp->rp_edid; 3933 if (!rp->rp_edid_valid) { 3934 /* monitor not present */ 3935 continue; 3936 } 3937 3938 /* 3939 * For now we are ignoring "conflict" that 3940 * could occur when mixing some modes like 3941 * 1280x1024 and 1400x800. It isn't clear 3942 * which is better, so the first one wins. 3943 */ 3944 for (j = 0; j < ep->edid_nmodes; j++) { 3945 /* 3946 * ignore resolutions that are too big for 3947 * the radeon 3948 */ 3949 if (ep->edid_modes[j].hdisplay > 3950 dp->rd_softc->sc_maxx) 3951 continue; 3952 if (ep->edid_modes[j].vdisplay > 3953 dp->rd_softc->sc_maxy) 3954 continue; 3955 3956 /* 3957 * pick largest resolution, the 3958 * smaller monitor will pan 3959 */ 3960 if ((ep->edid_modes[j].hdisplay >= *x) && 3961 (ep->edid_modes[j].vdisplay >= *y)) { 3962 *x = ep->edid_modes[j].hdisplay; 3963 *y = ep->edid_modes[j].vdisplay; 3964 } 3965 } 3966 } 3967 3968 } else { 3969 struct videomode modes[64]; 3970 int nmodes = 0; 3971 int valid = 0; 3972 3973 for (i = 0; i < dp->rd_ncrtcs; i++) { 3974 /* 3975 * pick the largest resolution in common. 3976 */ 3977 rp = dp->rd_crtcs[i].rc_port; 3978 ep = &rp->rp_edid; 3979 3980 if (!rp->rp_edid_valid) 3981 continue; 3982 3983 if (!valid) { 3984 /* 3985 * Pick the preferred mode for this port 3986 * if available. 3987 */ 3988 if (ep->edid_preferred_mode) { 3989 struct videomode *vmp = 3990 ep->edid_preferred_mode; 3991 3992 if ((vmp->hdisplay <= 3993 dp->rd_softc->sc_maxx) && 3994 (vmp->vdisplay <= 3995 dp->rd_softc->sc_maxy)) 3996 modes[nmodes++] = *vmp; 3997 } else { 3998 3999 /* initialize starting list */ 4000 for (j = 0; j < ep->edid_nmodes; j++) { 4001 /* 4002 * ignore resolutions that are 4003 * too big for the radeon 4004 */ 4005 if (ep->edid_modes[j].hdisplay > 4006 dp->rd_softc->sc_maxx) 4007 continue; 4008 if (ep->edid_modes[j].vdisplay > 4009 dp->rd_softc->sc_maxy) 4010 continue; 4011 4012 modes[nmodes] = 4013 ep->edid_modes[j]; 4014 nmodes++; 4015 } 4016 } 4017 valid = 1; 4018 } else { 4019 /* merge into preexisting list */ 4020 for (j = 0; j < nmodes; j++) { 4021 if (!radeonfb_hasres(ep->edid_modes, 4022 ep->edid_nmodes, 4023 modes[j].hdisplay, 4024 modes[j].vdisplay)) { 4025 modes[j] = modes[nmodes]; 4026 j--; 4027 nmodes--; 4028 } 4029 } 4030 } 4031 } 4032 4033 /* now we have to pick from the merged list */ 4034 for (i = 0; i < nmodes; i++) { 4035 if ((modes[i].hdisplay >= *x) && 4036 (modes[i].vdisplay >= *y)) { 4037 *x = modes[i].hdisplay; 4038 *y = modes[i].vdisplay; 4039 } 4040 } 4041 } 4042 4043 if ((*x == 0) || (*y == 0)) { 4044 /* fallback to safe mode */ 4045 *x = 640; 4046 *y = 480; 4047 } 4048 } 4049 4050 /* 4051 * backlight levels are linear on: 4052 * - RV200, RV250, RV280, RV350 4053 * - but NOT on PowerBook4,3 6,3 6,5 4054 * according to Linux' radeonfb 4055 */ 4056 4057 /* Get the current backlight level for the display. */ 4058 4059 static int 4060 radeonfb_get_backlight(struct radeonfb_display *dp) 4061 { 4062 int s; 4063 uint32_t level; 4064 4065 s = spltty(); 4066 4067 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4068 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4069 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4070 4071 /* 4072 * On some chips, we should negate the backlight level. 4073 * XXX Find out on which chips. 4074 */ 4075 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4076 level = RADEONFB_BACKLIGHT_MAX - level; 4077 4078 splx(s); 4079 4080 return level; 4081 } 4082 4083 /* Set the backlight to the given level for the display. */ 4084 static void 4085 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4086 { 4087 if (dp->rd_bl_on == on) 4088 return; 4089 dp->rd_bl_on = on; 4090 radeonfb_set_backlight(dp, dp->rd_bl_level); 4091 } 4092 4093 static int 4094 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4095 { 4096 struct radeonfb_softc *sc; 4097 int rlevel, s; 4098 uint32_t lvds; 4099 4100 s = spltty(); 4101 4102 dp->rd_bl_level = level; 4103 if (dp->rd_bl_on == 0) 4104 level = 0; 4105 4106 if (level < 0) 4107 level = 0; 4108 else if (level >= RADEONFB_BACKLIGHT_MAX) 4109 level = RADEONFB_BACKLIGHT_MAX; 4110 4111 sc = dp->rd_softc; 4112 4113 /* On some chips, we should negate the backlight level. */ 4114 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4115 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4116 } else 4117 rlevel = level; 4118 4119 callout_stop(&dp->rd_bl_lvds_co); 4120 radeonfb_engine_idle(sc); 4121 4122 /* 4123 * Turn off the display if the backlight is set to 0, since the 4124 * display is useless without backlight anyway. 4125 */ 4126 if (level == 0) 4127 radeonfb_blank(dp, 1); 4128 else if (radeonfb_get_backlight(dp) == 0) 4129 radeonfb_blank(dp, 0); 4130 4131 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4132 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4133 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4134 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4135 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4136 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4137 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4138 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4139 lvds |= RADEON_LVDS_ON; 4140 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4141 } else { 4142 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4143 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4144 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4145 } 4146 4147 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4148 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4149 /* XXX What is the correct delay? */ 4150 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4151 4152 splx(s); 4153 4154 return 0; 4155 } 4156 4157 /* 4158 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4159 * Set the delayed bits in the register, and clear the stored delayed 4160 * value. 4161 */ 4162 4163 static void radeonfb_lvds_callout(void *arg) 4164 { 4165 struct radeonfb_display *dp = arg; 4166 int s; 4167 4168 s = splhigh(); 4169 4170 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4171 dp->rd_bl_lvds_val); 4172 dp->rd_bl_lvds_val = 0; 4173 4174 splx(s); 4175 } 4176 4177 static void 4178 radeonfb_brightness_up(device_t dev) 4179 { 4180 struct radeonfb_softc *sc = device_private(dev); 4181 struct radeonfb_display *dp = &sc->sc_displays[0]; 4182 int level; 4183 4184 /* we assume the main display is the first one - need a better way */ 4185 if (sc->sc_ndisplays < 1) return; 4186 /* make sure pushing the hotkeys always has an effect */ 4187 dp->rd_bl_on = 1; 4188 level = dp->rd_bl_level; 4189 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4190 radeonfb_set_backlight(dp, level); 4191 } 4192 4193 static void 4194 radeonfb_brightness_down(device_t dev) 4195 { 4196 struct radeonfb_softc *sc = device_private(dev); 4197 struct radeonfb_display *dp = &sc->sc_displays[0]; 4198 int level; 4199 4200 /* we assume the main display is the first one - need a better way */ 4201 if (sc->sc_ndisplays < 1) return; 4202 /* make sure pushing the hotkeys always has an effect */ 4203 dp->rd_bl_on = 1; 4204 level = dp->rd_bl_level; 4205 level = max(0, level - 5); 4206 radeonfb_set_backlight(dp, level); 4207 } 4208
Indexes created Mon Oct 20 20:10:13 GMT 2025