radeonfb.c revision 1.9
1 /* $NetBSD: radeonfb.c,v 1.9 2007/01/03 19:47:17 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.9 2007/01/03 19:47:17 macallan Exp $"); 74 75 #define RADEONFB_DEFAULT_DEPTH 32 76 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/device.h> 80 #include <sys/malloc.h> 81 #include <machine/bus.h> 82 #include <sys/kernel.h> 83 #include <sys/lwp.h> 84 #include <sys/kauth.h> 85 86 #include <dev/wscons/wsdisplayvar.h> 87 #include <dev/wscons/wsconsio.h> 88 #include <dev/wsfont/wsfont.h> 89 #include <dev/rasops/rasops.h> 90 #include <dev/videomode/videomode.h> 91 #include <dev/videomode/edidvar.h> 92 #include <dev/wscons/wsdisplay_vconsvar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/radeonfbreg.h> 98 #include <dev/pci/radeonfbvar.h> 99 100 static int radeonfb_match(struct device *, struct cfdata *, void *); 101 static void radeonfb_attach(struct device *, struct device *, void *); 102 static int radeonfb_ioctl(void *, void *, unsigned long, caddr_t, int, 103 struct lwp *); 104 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 105 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 106 static void radeonfb_loadbios(struct radeonfb_softc *, 107 struct pci_attach_args *); 108 109 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 110 uintmax_t); 111 static int radeonfb_getclocks(struct radeonfb_softc *); 112 static int radeonfb_gettmds(struct radeonfb_softc *); 113 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 114 uint32_t *, uint32_t *); 115 static int radeonfb_getconnectors(struct radeonfb_softc *); 116 static const struct videomode *radeonfb_modelookup(const char *); 117 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 118 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 119 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 120 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 121 static void radeonfb_modeswitch(struct radeonfb_display *); 122 static void radeonfb_setcrtc(struct radeonfb_display *, int); 123 static void radeonfb_init_misc(struct radeonfb_softc *); 124 static void radeonfb_set_fbloc(struct radeonfb_softc *); 125 static void radeonfb_init_palette(struct radeonfb_softc *, int); 126 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 127 128 static int radeonfb_isblank(struct radeonfb_display *); 129 static void radeonfb_blank(struct radeonfb_display *, int); 130 static int radeonfb_set_cursor(struct radeonfb_display *, 131 struct wsdisplay_cursor *); 132 static int radeonfb_set_curpos(struct radeonfb_display *, 133 struct wsdisplay_curpos *); 134 135 /* acceleration support */ 136 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 137 int width, int height, uint32_t color); 138 static void radeonfb_bitblt(struct radeonfb_display *, int srcx, int srcy, 139 int dstx, int dsty, int width, int height, int rop, uint32_t mask); 140 static void radeonfb_feed_bytes(struct radeonfb_display *, int, uint8_t *); 141 static void radeonfb_setup_mono(struct radeonfb_display *, int, int, int, 142 int, uint32_t, uint32_t); 143 144 /* hw cursor support */ 145 static void radeonfb_cursor_cmap(struct radeonfb_display *); 146 static void radeonfb_cursor_shape(struct radeonfb_display *); 147 static void radeonfb_cursor_position(struct radeonfb_display *); 148 static void radeonfb_cursor_visible(struct radeonfb_display *); 149 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 150 151 static void radeonfb_wait_fifo(struct radeonfb_softc *, int); 152 static void radeonfb_engine_idle(struct radeonfb_softc *); 153 static void radeonfb_engine_flush(struct radeonfb_softc *); 154 static void radeonfb_engine_reset(struct radeonfb_softc *); 155 static void radeonfb_engine_init(struct radeonfb_display *); 156 static inline void radeonfb_unclip(struct radeonfb_softc *); 157 158 static void radeonfb_eraserows(void *, int, int, long); 159 static void radeonfb_erasecols(void *, int, int, int, long); 160 static void radeonfb_copyrows(void *, int, int, int); 161 static void radeonfb_copycols(void *, int, int, int, int); 162 static void radeonfb_cursor(void *, int, int, int); 163 static void radeonfb_putchar(void *, int, int, unsigned, long); 164 static int radeonfb_allocattr(void *, int, int, int, long *); 165 166 static int radeonfb_get_backlight(struct radeonfb_display *); 167 static int radeonfb_set_backlight(struct radeonfb_display *, int); 168 static void radeonfb_lvds_callout(void *); 169 170 static struct videomode *radeonfb_best_refresh(struct videomode *, 171 struct videomode *); 172 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 173 uint16_t *, int); 174 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 175 struct radeonfb_port *, int, int); 176 177 178 #define RADEON_DEBUG 179 #ifdef RADEON_DEBUG 180 int radeon_debug = 1; 181 #define DPRINTF(x) \ 182 if (radeon_debug) printf x 183 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 184 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 185 #else 186 #define DPRINTF(x) 187 #define PRINTREG(r) 188 #define PRINTPLL(r) 189 #endif 190 191 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 192 193 #ifndef RADEON_DEFAULT_MODE 194 /* any reasonably modern display should handle this */ 195 #define RADEON_DEFAULT_MODE "1024x768x60" 196 //#define RADEON_DEFAULT_MODE "1280x1024x60" 197 #endif 198 199 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 200 201 static struct { 202 int size; /* minimum memory size (MB) */ 203 int maxx; /* maximum x dimension */ 204 int maxy; /* maximum y dimension */ 205 int maxbpp; /* maximum bpp */ 206 int maxdisp; /* maximum logical display count */ 207 } radeonfb_limits[] = { 208 { 32, 2048, 1536, 32, 2 }, 209 { 16, 1600, 1200, 32, 2 }, 210 { 8, 1600, 1200, 32, 1 }, 211 { 0, 0, 0, 0, 0 }, 212 }; 213 214 static struct wsscreen_descr radeonfb_stdscreen = { 215 "fb", /* name */ 216 0, 0, /* ncols, nrows */ 217 NULL, /* textops */ 218 8, 16, /* fontwidth, fontheight */ 219 WSSCREEN_WSCOLORS, /* capabilities */ 220 0, /* modecookie */ 221 }; 222 223 struct wsdisplay_accessops radeonfb_accessops = { 224 radeonfb_ioctl, 225 radeonfb_mmap, 226 NULL, /* vcons_alloc_screen */ 227 NULL, /* vcons_free_screen */ 228 NULL, /* vcons_show_screen */ 229 NULL, /* load_font */ 230 NULL, /* pollc */ 231 NULL, /* scroll */ 232 }; 233 234 static struct { 235 uint16_t devid; 236 uint16_t family; 237 uint16_t flags; 238 } radeonfb_devices[] = 239 { 240 /* R100 family */ 241 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 242 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 243 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 244 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 245 246 /* RV100 family */ 247 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 248 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 249 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 250 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 251 252 /* RS100 family */ 253 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 254 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 255 256 /* RS200/RS250 family */ 257 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 258 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 259 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 260 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 261 262 /* R200 family */ 263 /* add more R200 products? , 5148 */ 264 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 267 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 268 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 269 270 /* RV200 family */ 271 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 272 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 273 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 274 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 275 276 /* RV250 family */ 277 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 279 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 281 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 282 283 /* RS300 family */ 284 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 288 289 /* RV280 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 291 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 292 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 294 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 295 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 296 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 297 298 /* R300 family */ 299 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 302 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 303 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 307 308 /* RV350/RV360 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 316 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 317 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 319 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 320 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 321 322 /* R350/R360 family */ 323 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 331 332 /* RV380/RV370 family */ 333 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 334 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 340 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 341 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 342 343 /* R420/R423 family */ 344 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 351 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 353 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 354 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 357 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 360 361 { 0, 0, 0 } 362 }; 363 364 static struct { 365 int divider; 366 int mask; 367 } radeonfb_dividers[] = { 368 { 1, 0 }, 369 { 2, 1 }, 370 { 3, 4 }, 371 { 4, 2 }, 372 { 6, 6 }, 373 { 8, 3 }, 374 { 12, 7 }, 375 { 0, 0 } 376 }; 377 378 /* 379 * This table taken from X11. 380 */ 381 static const struct { 382 int family; 383 struct radeon_tmds_pll plls[4]; 384 } radeonfb_tmds_pll[] = { 385 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 386 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 387 { RADEON_RS100, {{0, 0}}}, 388 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 389 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 390 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 391 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 392 { RADEON_RS300, {{0, 0}}}, 393 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 394 { RADEON_R300, {{-1, 0xb01cb}}}, 395 { RADEON_R350, {{-1, 0xb01cb}}}, 396 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 397 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 398 { RADEON_R420, {{-1, 0xb01cb}}}, 399 }; 400 401 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 402 403 404 CFATTACH_DECL(radeonfb, sizeof (struct radeonfb_softc), 405 radeonfb_match, radeonfb_attach, NULL, NULL); 406 407 static int 408 radeonfb_match(struct device *parent, struct cfdata *match, void *aux) 409 { 410 struct pci_attach_args *pa = aux; 411 int i; 412 413 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 414 return 0; 415 416 for (i = 0; radeonfb_devices[i].devid; i++) { 417 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 418 return 100; /* high to defeat VGA/VESA */ 419 } 420 421 return 0; 422 } 423 424 static void 425 radeonfb_attach(struct device *parent, struct device *dev, void *aux) 426 { 427 struct radeonfb_softc *sc = (struct radeonfb_softc *)dev; 428 struct pci_attach_args *pa = aux; 429 const char *mptr; 430 bus_size_t bsz; 431 pcireg_t screg; 432 int i, j, fg, bg, ul; 433 uint32_t v; 434 435 sc->sc_id = pa->pa_id; 436 for (i = 0; radeonfb_devices[i].devid; i++) { 437 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 438 break; 439 } 440 441 pci_devinfo(sc->sc_id, pa->pa_class, 0, sc->sc_devinfo, 442 sizeof(sc->sc_devinfo)); 443 444 aprint_naive("\n"); 445 aprint_normal(": %s\n", sc->sc_devinfo); 446 447 KASSERT(radeonfb_devices[i].devid != 0); 448 sc->sc_pt = pa->pa_tag; 449 sc->sc_pc = pa->pa_pc; 450 sc->sc_family = radeonfb_devices[i].family; 451 sc->sc_flags = radeonfb_devices[i].flags; 452 453 /* enable memory and IO access */ 454 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 455 screg |= PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 456 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 457 458 /* 459 * Some flags are general to entire chip families, and rather 460 * than clutter up the table with them, we go ahead and set 461 * them here. 462 */ 463 switch (sc->sc_family) { 464 case RADEON_RS100: 465 case RADEON_RS200: 466 sc->sc_flags |= RFB_IGP | RFB_RV100; 467 break; 468 469 case RADEON_RV100: 470 case RADEON_RV200: 471 case RADEON_RV250: 472 case RADEON_RV280: 473 sc->sc_flags |= RFB_RV100; 474 break; 475 476 case RADEON_RS300: 477 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 478 break; 479 480 case RADEON_R300: 481 case RADEON_RV350: 482 case RADEON_R350: 483 case RADEON_RV380: 484 case RADEON_R420: 485 /* newer chips */ 486 sc->sc_flags |= RFB_R300; 487 break; 488 489 case RADEON_R100: 490 sc->sc_flags |= RFB_NCRTC2; 491 break; 492 } 493 494 /* 495 * XXX: to support true multihead, this must change. 496 */ 497 sc->sc_ndisplays = 1; 498 499 /* XXX: */ 500 if (!HAS_CRTC2(sc)) { 501 sc->sc_ndisplays = 1; 502 } 503 504 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 505 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 506 &sc->sc_regsz) != 0) { 507 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 508 goto error; 509 } 510 511 if (pci_mapreg_map(pa, RADEON_MAPREG_IO, PCI_MAPREG_TYPE_IO, 0, 512 &sc->sc_iot, &sc->sc_ioh, &sc->sc_ioaddr, 513 &sc->sc_iosz) != 0) { 514 aprint_error("%s: unable to map IO registers!\n", XNAME(sc)); 515 } 516 517 /* scratch register test... */ 518 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 519 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 520 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 521 goto error; 522 } 523 524 PRINTREG(RADEON_BIOS_4_SCRATCH); 525 PRINTREG(RADEON_FP_GEN_CNTL); 526 PRINTREG(RADEON_FP2_GEN_CNTL); 527 PRINTREG(RADEON_TMDS_CNTL); 528 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 529 PRINTREG(RADEON_TMDS_PLL_CNTL); 530 PRINTREG(RADEON_LVDS_GEN_CNTL); 531 PRINTREG(RADEON_FP_HORZ_STRETCH); 532 PRINTREG(RADEON_FP_VERT_STRETCH); 533 534 /* XXX: RV100 specific */ 535 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 536 537 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 538 RADEON_TMDS_TRANSMITTER_PLLEN, 539 RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST); 540 541 radeonfb_i2c_init(sc); 542 543 radeonfb_loadbios(sc, pa); 544 545 #ifdef RADEON_BIOS_INIT 546 if (radeonfb_bios_init(sc)) { 547 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 548 goto error; 549 } 550 #endif 551 552 if (radeonfb_getclocks(sc)) { 553 aprint_error("%s: Unable to get reference clocks from BIOS\n", 554 XNAME(sc)); 555 goto error; 556 } 557 558 if (radeonfb_gettmds(sc)) { 559 aprint_error("%s: Unable to identify TMDS PLL settings\n", 560 XNAME(sc)); 561 goto error; 562 } 563 564 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 565 "minpll = %d, maxpll = %d\n", XNAME(sc), 566 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 567 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 568 569 radeonfb_getconnectors(sc); 570 571 radeonfb_set_fbloc(sc); 572 573 for (i = 0; radeonfb_limits[i].size; i++) { 574 if (sc->sc_memsz >= radeonfb_limits[i].size) { 575 sc->sc_maxx = radeonfb_limits[i].maxx; 576 sc->sc_maxy = radeonfb_limits[i].maxy; 577 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 578 /* framebuffer offset, start at a 4K page */ 579 sc->sc_fboffset = sc->sc_memsz / 580 radeonfb_limits[i].maxdisp; 581 /* 582 * we use the fbsize to figure out where we can store 583 * things like cursor data. 584 */ 585 sc->sc_fbsize = 586 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 587 RADEON_STRIDEALIGN) * sc->sc_maxy, 588 4096); 589 break; 590 } 591 } 592 593 594 radeonfb_init_misc(sc); 595 radeonfb_init_palette(sc, 0); 596 if (HAS_CRTC2(sc)) 597 radeonfb_init_palette(sc, 1); 598 599 /* program the DAC wirings */ 600 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 601 switch (sc->sc_ports[i].rp_dac_type) { 602 case RADEON_DAC_PRIMARY: 603 PATCH32(sc, RADEON_DAC_CNTL2, 604 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 605 ~RADEON_DAC2_DAC_CLK_SEL); 606 break; 607 case RADEON_DAC_TVDAC: 608 /* we always use the TVDAC to drive a secondary analog 609 * CRT for now. if we ever support TV-out this will 610 * have to change. 611 */ 612 SET32(sc, RADEON_DAC_CNTL2, 613 RADEON_DAC2_DAC2_CLK_SEL); 614 PATCH32(sc, RADEON_DISP_HW_DEBUG, 615 i ? 0 : RADEON_CRT2_DISP1_SEL, 616 ~RADEON_CRT2_DISP1_SEL); 617 break; 618 } 619 } 620 PRINTREG(RADEON_DAC_CNTL2); 621 PRINTREG(RADEON_DISP_HW_DEBUG); 622 623 /* other DAC programming */ 624 v = GET32(sc, RADEON_DAC_CNTL); 625 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 626 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 627 PUT32(sc, RADEON_DAC_CNTL, v); 628 PRINTREG(RADEON_DAC_CNTL); 629 630 /* XXX: this may need more investigation */ 631 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 632 PRINTREG(RADEON_TV_DAC_CNTL); 633 634 /* enable TMDS */ 635 SET32(sc, RADEON_FP_GEN_CNTL, 636 RADEON_FP_TMDS_EN | 637 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 638 RADEON_FP_CRTC_DONT_SHADOW_HEND); 639 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 640 if (HAS_CRTC2(sc)) 641 SET32(sc, RADEON_FP2_GEN_CNTL, RADEON_FP2_SRC_SEL_CRTC2); 642 643 /* 644 * we use bus_space_map instead of pci_mapreg, because we don't 645 * need the full aperature space. no point in wasting virtual 646 * address space we don't intend to use, right? 647 */ 648 if ((sc->sc_memsz < (4096 * 1024)) || 649 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 650 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 651 (bsz < sc->sc_memsz)) { 652 sc->sc_memsz = 0; 653 aprint_error("%s: Bad frame buffer configuration\n", 654 XNAME(sc)); 655 goto error; 656 } 657 658 /* 64 MB should be enough -- more just wastes map entries */ 659 if (sc->sc_memsz > (64 << 20)) 660 sc->sc_memsz = (64 << 20); 661 662 sc->sc_memt = pa->pa_memt; 663 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 664 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 665 sc->sc_memsz = 0; 666 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 667 goto error; 668 } 669 670 aprint_normal("%s: %d MB aperture at 0x%08x, " 671 "%d KB registers at 0x%08x\n", XNAME(sc), 672 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 673 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 674 675 /* setup default video mode from devprop (allows PROM override) */ 676 sc->sc_defaultmode = radeonfb_default_mode; 677 if (prop_dictionary_get_cstring_nocopy(device_properties(&sc->sc_dev), 678 "videomode", &mptr)) { 679 680 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 681 sc->sc_defaultmode = sc->sc_modebuf; 682 } 683 684 /* initialize some basic display parameters */ 685 for (i = 0; i < sc->sc_ndisplays; i++) { 686 struct radeonfb_display *dp = &sc->sc_displays[i]; 687 struct rasops_info *ri; 688 long defattr; 689 struct wsemuldisplaydev_attach_args aa; 690 691 /* 692 * Figure out how many "displays" (desktops) we are going to 693 * support. If more than one, then each CRTC gets its own 694 * programming. 695 * 696 * XXX: this code needs to change to support mergedfb. 697 * XXX: would be nice to allow this to be overridden 698 */ 699 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 700 DPRINTF(("dual crtcs!\n")); 701 dp->rd_ncrtcs = 2; 702 dp->rd_crtcs[0].rc_number = 0; 703 dp->rd_crtcs[1].rc_number = 1; 704 } else { 705 dp->rd_ncrtcs = 1; 706 dp->rd_crtcs[0].rc_number = i; 707 } 708 709 /* set up port pointer */ 710 for (j = 0; j < dp->rd_ncrtcs; j++) { 711 dp->rd_crtcs[j].rc_port = 712 &sc->sc_ports[dp->rd_crtcs[j].rc_number]; 713 } 714 715 dp->rd_softc = sc; 716 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 717 dp->rd_bg = WS_DEFAULT_BG; 718 #if 0 719 dp->rd_bpp = sc->sc_maxbpp; /* XXX: for now */ 720 #else 721 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 722 #endif 723 /* for text mode, we pick a resolution that won't 724 * require panning */ 725 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 726 727 aprint_normal("%s: display %d: " 728 "initial virtual resolution %dx%d at %d bpp\n", 729 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 730 731 /* now select the *video mode* that we will use */ 732 for (j = 0; j < dp->rd_ncrtcs; j++) { 733 const struct videomode *vmp; 734 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 735 dp->rd_virtx, dp->rd_virty); 736 737 /* 738 * virtual resolution should be at least as high as 739 * physical 740 */ 741 if (dp->rd_virtx < vmp->hdisplay || 742 dp->rd_virty < vmp->vdisplay) { 743 dp->rd_virtx = vmp->hdisplay; 744 dp->rd_virty = vmp->vdisplay; 745 } 746 747 dp->rd_crtcs[j].rc_videomode = *vmp; 748 printf("%s: port %d: physical %dx%d %dHz\n", 749 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 750 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 751 vmp->htotal), vmp->vtotal)); 752 } 753 754 /* N.B.: radeon wants 64-byte aligned stride */ 755 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 756 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 757 758 dp->rd_offset = sc->sc_fboffset * i; 759 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 760 sc->sc_memh) + dp->rd_offset; 761 dp->rd_curoff = sc->sc_fbsize; 762 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 763 764 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 765 766 switch (dp->rd_bpp) { 767 case 8: 768 dp->rd_format = 2; 769 break; 770 case 32: 771 dp->rd_format = 6; 772 break; 773 default: 774 aprint_error("%s: bad depth %d\n", XNAME(sc), 775 dp->rd_bpp); 776 goto error; 777 } 778 779 printf("init engine\n"); 780 /* XXX: this seems suspicious - per display engine 781 initialization? */ 782 radeonfb_engine_init(dp); 783 784 /* copy the template into place */ 785 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 786 dp->rd_wsscreens = dp->rd_wsscreens_storage; 787 788 /* and make up the list */ 789 dp->rd_wsscreenlist.nscreens = 1; 790 dp->rd_wsscreenlist.screens = 791 (const struct wsscreen_descr **)&dp->rd_wsscreens; 792 793 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 794 &radeonfb_accessops); 795 796 dp->rd_vd.init_screen = radeonfb_init_screen; 797 798 dp->rd_console = 1; 799 800 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 801 802 803 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 804 dp->rd_console, &defattr); 805 806 ri = &dp->rd_vscreen.scr_ri; 807 808 /* clear the screen */ 809 rasops_unpack_attr(defattr, &fg, &bg, &ul); 810 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 811 ri->ri_devcmap[bg & 0xf]); 812 813 dp->rd_wsscreens->textops = &ri->ri_ops; 814 dp->rd_wsscreens->capabilities = ri->ri_caps; 815 dp->rd_wsscreens->nrows = ri->ri_rows; 816 dp->rd_wsscreens->ncols = ri->ri_cols; 817 818 #ifdef SPLASHSCREEN 819 dp->rd_splash.si_depth = ri->ri_depth; 820 dp->rd_splash.si_bits = ri->ri_bits; 821 dp->rd_splash.si_hwbits = ri->ri_hwbits; 822 dp->rd_splash.si_width = ri->ri_width; 823 dp->rd_splash.si_height = ri->ri_height; 824 dp->rd_splash.si_stride = ri->ri_stride; 825 dp->rd_splash.si_fillrect = NULL; 826 #endif 827 if (dp->rd_console) { 828 829 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 830 defattr); 831 #ifdef SPLASHSCREEN 832 splash_render(&dp->rd_splash, 833 SPLASH_F_CENTER|SPLASH_F_FILL); 834 #endif 835 836 #ifdef SPLASHSCREEN_PROGRESS 837 dp->rd_progress.sp_top = (dp->rd_virty / 8) * 7; 838 dp->rd_progress.sp_width = (dp->rd_virtx / 4) * 3; 839 dp->rd_progress.sp_left = (dp->rd_virtx - 840 dp->rd_progress.sp_width) / 2; 841 dp->rd_progress.sp_height = 20; 842 dp->rd_progress.sp_state = -1; 843 dp->rd_progress.sp_si = &dp->rd_splash; 844 splash_progress_init(&dp->rd_progress); 845 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 846 #endif 847 848 } else { 849 850 /* 851 * since we're not the console we can postpone 852 * the rest until someone actually allocates a 853 * screen for us. but we do clear the screen 854 * at least. 855 */ 856 memset(ri->ri_bits, 0, 1024); 857 858 radeonfb_modeswitch(dp); 859 #ifdef SPLASHSCREEN 860 splash_render(&dp->rd_splash, 861 SPLASH_F_CENTER|SPLASH_F_FILL); 862 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 863 #endif 864 } 865 866 aa.console = dp->rd_console; 867 aa.scrdata = &dp->rd_wsscreenlist; 868 aa.accessops = &radeonfb_accessops; 869 aa.accesscookie = &dp->rd_vd; 870 871 config_found(&sc->sc_dev, &aa, wsemuldisplaydevprint); 872 radeonfb_blank(dp, 0); 873 874 /* Initialise delayed lvds operations for backlight. */ 875 callout_init(&dp->rd_bl_lvds_co); 876 callout_setfunc(&dp->rd_bl_lvds_co, 877 radeonfb_lvds_callout, dp); 878 } 879 880 return; 881 882 error: 883 if (sc->sc_biossz) 884 free(sc->sc_bios, M_DEVBUF); 885 886 if (sc->sc_regsz) 887 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 888 889 if (sc->sc_memsz) 890 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 891 } 892 893 int 894 radeonfb_ioctl(void *v, void *vs, 895 unsigned long cmd, caddr_t d, int flag, struct lwp *l) 896 { 897 struct vcons_data *vd; 898 struct radeonfb_display *dp; 899 struct radeonfb_softc *sc; 900 struct wsdisplay_param *param; 901 902 vd = (struct vcons_data *)v; 903 dp = (struct radeonfb_display *)vd->cookie; 904 sc = dp->rd_softc; 905 906 switch (cmd) { 907 case WSDISPLAYIO_GTYPE: 908 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 909 return 0; 910 911 case WSDISPLAYIO_GINFO: 912 if (vd->active != NULL) { 913 struct wsdisplay_fbinfo *fb; 914 fb = (struct wsdisplay_fbinfo *)d; 915 fb->width = dp->rd_virtx; 916 fb->height = dp->rd_virty; 917 fb->depth = dp->rd_bpp; 918 fb->cmsize = 256; 919 return 0; 920 } else 921 return ENODEV; 922 case WSDISPLAYIO_GVIDEO: 923 if (radeonfb_isblank(dp)) 924 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 925 else 926 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 927 return 0; 928 929 case WSDISPLAYIO_SVIDEO: 930 radeonfb_blank(dp, 931 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 932 return 0; 933 934 case WSDISPLAYIO_GETCMAP: 935 #if 0 936 if (dp->rd_bpp == 8) 937 return radeonfb_getcmap(sc, 938 (struct wsdisplay_cmap *)d); 939 #endif 940 return EINVAL; 941 942 case WSDISPLAYIO_PUTCMAP: 943 #if 0 944 if (dp->rd_bpp == 8) 945 return radeonfb_putcmap(sc, 946 (struct wsdisplay_cmap *)d); 947 #endif 948 return EINVAL; 949 950 case WSDISPLAYIO_LINEBYTES: 951 *(unsigned *)d = dp->rd_stride; 952 return 0; 953 954 case WSDISPLAYIO_SMODE: 955 if (*(int *)d != dp->rd_wsmode) { 956 dp->rd_wsmode = *(int *)d; 957 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 958 (dp->rd_vd.active)) { 959 vcons_redraw_screen(dp->rd_vd.active); 960 } 961 } 962 return 0; 963 964 case WSDISPLAYIO_GCURMAX: 965 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 966 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 967 return 0; 968 969 case WSDISPLAYIO_SCURSOR: 970 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 971 972 case WSDISPLAYIO_GCURSOR: 973 return EPASSTHROUGH; 974 975 case WSDISPLAYIO_GCURPOS: 976 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 977 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 978 return 0; 979 980 case WSDISPLAYIO_SCURPOS: 981 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 982 983 case WSDISPLAYIO_SSPLASH: 984 #if defined(SPLASHSCREEN) 985 if (*(int *)d == 1) { 986 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 987 splash_render(&dp->rd_splash, 988 SPLASH_F_CENTER|SPLASH_F_FILL); 989 } else 990 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 991 return 0; 992 #else 993 return ENODEV; 994 #endif 995 case WSDISPLAYIO_SPROGRESS: 996 #if defined(SPLASHSCREEN) && defined(SPLASHSCREEN_PROGRESS) 997 dp->rd_progress.sp_force = 1; 998 splash_progress_update(&dp->rd_progress); 999 dp->rd_progress.sp_force = 0; 1000 return 0; 1001 #else 1002 return ENODEV; 1003 #endif 1004 case WSDISPLAYIO_GETPARAM: 1005 param = (struct wsdisplay_param *)d; 1006 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1007 param->min = 0; 1008 param->max = RADEONFB_BACKLIGHT_MAX; 1009 param->curval = radeonfb_get_backlight(dp); 1010 return 0; 1011 } 1012 return EPASSTHROUGH; 1013 1014 case WSDISPLAYIO_SETPARAM: 1015 param = (struct wsdisplay_param *)d; 1016 if (param->param == WSDISPLAYIO_PARAM_BACKLIGHT) { 1017 return radeonfb_set_backlight(dp, param->curval); 1018 } 1019 return EPASSTHROUGH; 1020 1021 default: 1022 return EPASSTHROUGH; 1023 } 1024 } 1025 1026 paddr_t 1027 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1028 { 1029 struct vcons_data *vd; 1030 struct radeonfb_display *dp; 1031 struct radeonfb_softc *sc; 1032 #ifdef RADEONFB_MMAP_BARS 1033 struct lwp *me; 1034 #endif 1035 paddr_t pa; 1036 1037 vd = (struct vcons_data *)v; 1038 dp = (struct radeonfb_display *)vd->cookie; 1039 sc = dp->rd_softc; 1040 1041 /* XXX: note that we don't allow mapping of registers right now */ 1042 /* XXX: this means that the XFree86 radeon driver won't work */ 1043 1044 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1045 pa = bus_space_mmap(sc->sc_memt, 1046 sc->sc_memaddr + dp->rd_offset + offset, 0, 1047 prot, BUS_SPACE_MAP_LINEAR); 1048 return pa; 1049 } 1050 1051 #ifdef RADEONFB_MMAP_BARS 1052 /* 1053 * restrict all other mappings to processes with superuser privileges 1054 * or the kernel itself 1055 */ 1056 me = curlwp; 1057 if (me != NULL) { 1058 if (kauth_authorize_generic(me->l_cred, KAUTH_GENERIC_ISSUSER, 1059 NULL) != 0) { 1060 printf("%s: mmap() rejected.\n", sc->sc_dev.dv_xname); 1061 return -1; 1062 } 1063 } 1064 1065 if ((offset >= sc->sc_regaddr) && 1066 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1067 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1068 BUS_SPACE_MAP_LINEAR); 1069 } 1070 1071 if ((offset >= sc->sc_memaddr) && 1072 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1073 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1074 BUS_SPACE_MAP_LINEAR); 1075 } 1076 1077 #ifdef macppc 1078 /* allow mapping of IO space */ 1079 if ((offset >= 0xf2000000) && (offset < 0xf2800000)) { 1080 pa = bus_space_mmap(sc->sc_iot, offset-0xf2000000, 0, prot, 1081 BUS_SPACE_MAP_LINEAR); 1082 return pa; 1083 } 1084 #endif /* macppc */ 1085 1086 #endif /* RADEONFB_MMAP_BARS */ 1087 1088 return -1; 1089 } 1090 1091 static void 1092 radeonfb_loadbios(struct radeonfb_softc *sc, struct pci_attach_args *pa) 1093 { 1094 bus_space_tag_t romt; 1095 bus_space_handle_t romh, biosh; 1096 bus_size_t romsz; 1097 bus_addr_t ptr; 1098 1099 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1100 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1101 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1102 return; 1103 } 1104 1105 pci_find_rom(pa, romt, romh, PCI_ROM_CODE_TYPE_X86, &biosh, 1106 &sc->sc_biossz); 1107 if (sc->sc_biossz == 0) { 1108 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1109 return; 1110 } 1111 1112 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1113 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1114 1115 /* unmap the PCI expansion rom */ 1116 bus_space_unmap(romt, romh, romsz); 1117 1118 /* turn off rom decoder now */ 1119 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1120 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1121 ~PCI_MAPREG_ROM_ENABLE); 1122 1123 ptr = GETBIOS16(sc, 0x48); 1124 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1125 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1126 sc->sc_flags |= RFB_ATOM; 1127 } 1128 1129 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1130 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1131 } 1132 1133 1134 uint32_t 1135 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1136 { 1137 1138 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1139 } 1140 1141 void 1142 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1143 { 1144 1145 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1146 } 1147 1148 void 1149 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1150 uint32_t andmask, uint32_t ormask) 1151 { 1152 int s; 1153 uint32_t val; 1154 1155 s = splhigh(); 1156 val = radeonfb_get32(sc, reg); 1157 val = (val & andmask) | ormask; 1158 radeonfb_put32(sc, reg, val); 1159 splx(s); 1160 } 1161 1162 uint32_t 1163 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1164 { 1165 int s; 1166 uint32_t val; 1167 1168 s = splhigh(); 1169 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1170 val = radeonfb_get32(sc, RADEON_MM_DATA); 1171 splx(s); 1172 1173 return (val); 1174 } 1175 1176 void 1177 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1178 { 1179 int s; 1180 1181 s = splhigh(); 1182 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1183 radeonfb_put32(sc, RADEON_MM_DATA, val); 1184 splx(s); 1185 } 1186 1187 void 1188 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1189 uint32_t andmask, uint32_t ormask) 1190 { 1191 int s; 1192 uint32_t val; 1193 1194 s = splhigh(); 1195 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1196 val = radeonfb_get32(sc, RADEON_MM_DATA); 1197 val = (val & andmask) | ormask; 1198 radeonfb_put32(sc, RADEON_MM_DATA, val); 1199 splx(s); 1200 } 1201 1202 uint32_t 1203 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1204 { 1205 int s; 1206 uint32_t val; 1207 1208 s = splhigh(); 1209 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, idx & 0x3f); 1210 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1211 if (HAS_R300CG(sc)) 1212 radeonfb_r300cg_workaround(sc); 1213 splx(s); 1214 1215 return (val); 1216 } 1217 1218 void 1219 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1220 { 1221 int s; 1222 1223 s = splhigh(); 1224 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1225 RADEON_PLL_WR_EN); 1226 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1227 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1228 splx(s); 1229 } 1230 1231 void 1232 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1233 uint32_t andmask, uint32_t ormask) 1234 { 1235 int s; 1236 uint32_t val; 1237 1238 s = splhigh(); 1239 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1240 RADEON_PLL_WR_EN); 1241 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1242 val = (val & andmask) | ormask; 1243 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1244 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1245 splx(s); 1246 } 1247 1248 int 1249 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1250 { 1251 uint32_t saved; 1252 1253 saved = GET32(sc, reg); 1254 PUT32(sc, reg, v); 1255 if (GET32(sc, reg) != v) { 1256 return -1; 1257 } 1258 PUT32(sc, reg, saved); 1259 return 0; 1260 } 1261 1262 uintmax_t 1263 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1264 uintmax_t defval) 1265 { 1266 prop_number_t pn; 1267 pn = prop_dictionary_get(device_properties(&sc->sc_dev), name); 1268 if (pn == NULL) { 1269 return defval; 1270 } 1271 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1272 return (prop_number_integer_value(pn)); 1273 } 1274 1275 int 1276 radeonfb_getclocks(struct radeonfb_softc *sc) 1277 { 1278 bus_addr_t ptr; 1279 int refclk = 0; 1280 int refdiv = 0; 1281 int minpll = 0; 1282 int maxpll = 0; 1283 1284 /* load initial property values if port/board provides them */ 1285 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1286 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1287 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1288 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1289 1290 if (refclk && refdiv && minpll && maxpll) 1291 goto dontprobe; 1292 1293 if (!sc->sc_biossz) { 1294 /* no BIOS */ 1295 aprint_verbose("%s: No video BIOS, using default clocks\n", 1296 XNAME(sc)); 1297 if (IS_IGP(sc)) 1298 refclk = refclk ? refclk : 1432; 1299 else 1300 refclk = refclk ? refclk : 2700; 1301 refdiv = refdiv ? refdiv : 12; 1302 minpll = minpll ? minpll : 12500; 1303 maxpll = maxpll ? maxpll : 35000; 1304 } else if (IS_ATOM(sc)) { 1305 /* ATOM BIOS */ 1306 ptr = GETBIOS16(sc, 0x48); 1307 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1308 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1309 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1310 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1311 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1312 /* 1313 * ATOM BIOS doesn't supply a reference divider, so we 1314 * have to probe for it. 1315 */ 1316 if (refdiv < 2) 1317 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1318 RADEON_PPLL_REF_DIV_MASK; 1319 /* 1320 * if probe is zero, just assume one that should work 1321 * for most parts 1322 */ 1323 if (refdiv < 2) 1324 refdiv = 12; 1325 1326 } else { 1327 /* Legacy BIOS */ 1328 ptr = GETBIOS16(sc, 0x48); 1329 ptr = GETBIOS16(sc, ptr + 0x30); 1330 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1331 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1332 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1333 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1334 } 1335 1336 1337 dontprobe: 1338 sc->sc_refclk = refclk * 10; 1339 sc->sc_refdiv = refdiv; 1340 sc->sc_minpll = minpll * 10; 1341 sc->sc_maxpll = maxpll * 10; 1342 return 0; 1343 } 1344 1345 int 1346 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1347 uint32_t *postdivbit, uint32_t *feedbackdiv) 1348 { 1349 int i; 1350 uint32_t outfreq; 1351 int div; 1352 1353 DPRINTF(("dot clock: %u\n", dotclock)); 1354 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1355 outfreq = div * dotclock; 1356 if ((outfreq >= sc->sc_minpll) && 1357 (outfreq <= sc->sc_maxpll)) { 1358 DPRINTF(("outfreq: %u\n", outfreq)); 1359 *postdivbit = 1360 ((uint32_t)radeonfb_dividers[i].mask << 16); 1361 DPRINTF(("post divider: %d (mask %x)\n", div, 1362 *postdivbit)); 1363 break; 1364 } 1365 } 1366 1367 if (div == 0) 1368 return 1; 1369 1370 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1371 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1372 return 0; 1373 } 1374 1375 #if 0 1376 #ifdef RADEON_DEBUG 1377 static void 1378 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1379 { 1380 char asc[17]; 1381 unsigned ptr = (unsigned)buffer; 1382 char *start = (char *)(ptr & ~0xf); 1383 char *end = (char *)(ptr + size); 1384 1385 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1386 1387 if (pfx == NULL) { 1388 pfx = ""; 1389 } 1390 1391 while (start < end) { 1392 unsigned offset = (unsigned)start & 0xf; 1393 if (offset == 0) { 1394 printf("%s%x: ", pfx, (unsigned)start); 1395 } 1396 if (((unsigned)start < ptr) || 1397 ((unsigned)start >= (ptr + size))) { 1398 printf(" "); 1399 asc[offset] = ' '; 1400 } else { 1401 printf("%02x", *(unsigned char *)start); 1402 if ((*start >= ' ') && (*start <= '~')) { 1403 asc[offset] = *start; 1404 } else { 1405 asc[offset] = '.'; 1406 } 1407 } 1408 asc[offset + 1] = 0; 1409 if (offset % 2) { 1410 printf(" "); 1411 } 1412 if (offset == 15) { 1413 printf(" %s\n", asc); 1414 } 1415 start++; 1416 } 1417 } 1418 #endif 1419 #endif 1420 1421 int 1422 radeonfb_getconnectors(struct radeonfb_softc *sc) 1423 { 1424 int i; 1425 int found = 0; 1426 1427 for (i = 0; i < 2; i++) { 1428 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1429 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1430 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1431 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1432 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1433 } 1434 1435 /* 1436 * This logic is borrowed from Xorg's radeon driver. 1437 */ 1438 if (!sc->sc_biossz) 1439 goto nobios; 1440 1441 if (IS_ATOM(sc)) { 1442 /* not done yet */ 1443 } else { 1444 uint16_t ptr; 1445 int port = 0; 1446 1447 ptr = GETBIOS16(sc, 0x48); 1448 ptr = GETBIOS16(sc, ptr + 0x50); 1449 for (i = 1; i < 4; i++) { 1450 uint16_t entry; 1451 uint8_t conn, ddc, dac, tmds; 1452 1453 /* 1454 * Parse the connector table. From reading the code, 1455 * it appears to made up of 16-bit entries for each 1456 * connector. The 16-bits are defined as: 1457 * 1458 * bits 12-15 - connector type (0 == end of table) 1459 * bits 8-11 - DDC type 1460 * bits 5-7 - ??? 1461 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1462 * bits 1-3 - ??? 1463 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1464 */ 1465 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1466 break; 1467 entry = GETBIOS16(sc, ptr + i * 2); 1468 1469 conn = (entry >> 12) & 0xf; 1470 ddc = (entry >> 8) & 0xf; 1471 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1472 RADEON_DAC_PRIMARY; 1473 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1474 RADEON_TMDS_INT; 1475 1476 if (conn == RADEON_CONN_NONE) 1477 continue; /* no connector */ 1478 1479 if ((found > 0) && 1480 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1481 /* duplicate entry for same connector */ 1482 continue; 1483 } 1484 1485 /* internal DDC_DVI port gets priority */ 1486 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1487 port = 0; 1488 else 1489 port = 1; 1490 1491 sc->sc_ports[port].rp_ddc_type = 1492 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1493 sc->sc_ports[port].rp_dac_type = dac; 1494 sc->sc_ports[port].rp_conn_type = 1495 min(conn, RADEON_CONN_UNSUPPORTED) ; 1496 1497 sc->sc_ports[port].rp_tmds_type = tmds; 1498 1499 if ((conn != RADEON_CONN_DVI_I) && 1500 (conn != RADEON_CONN_DVI_D) && 1501 (tmds == RADEON_TMDS_INT)) 1502 sc->sc_ports[port].rp_tmds_type = 1503 RADEON_TMDS_UNKNOWN; 1504 1505 found += (port + 1); 1506 } 1507 } 1508 1509 nobios: 1510 if (!found) { 1511 DPRINTF(("No connector info in BIOS!\n")); 1512 /* default, port 0 = internal TMDS, port 1 = CRT */ 1513 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1514 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1515 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1516 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1517 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1518 1519 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1520 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1521 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1522 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1523 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1524 } 1525 1526 /* 1527 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1528 * these chips should use TVDAC for the VGA port. 1529 */ 1530 if (HAS_SDAC(sc)) { 1531 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1532 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1533 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1534 } else { 1535 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1536 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1537 } 1538 } else if (!HAS_CRTC2(sc)) { 1539 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1540 } 1541 1542 for (i = 0; i < 2; i++) { 1543 char edid[128]; 1544 uint8_t ddc; 1545 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1546 1547 DPRINTF(("Port #%d:\n", i)); 1548 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1549 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1550 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1551 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1552 1553 sc->sc_ports[i].rp_edid_valid = 0; 1554 ddc = sc->sc_ports[i].rp_ddc_type; 1555 if (ddc != RADEON_DDC_NONE) { 1556 if ((radeonfb_i2c_read_edid(sc, ddc, edid) == 0) && 1557 (edid_parse(edid, eip) == 0)) { 1558 sc->sc_ports[i].rp_edid_valid = 1; 1559 edid_print(eip); 1560 } 1561 } 1562 } 1563 1564 return found; 1565 } 1566 1567 int 1568 radeonfb_gettmds(struct radeonfb_softc *sc) 1569 { 1570 int i; 1571 1572 if (!sc->sc_biossz) { 1573 goto nobios; 1574 } 1575 1576 if (IS_ATOM(sc)) { 1577 /* XXX: not done yet */ 1578 } else { 1579 uint16_t ptr; 1580 int n; 1581 1582 ptr = GETBIOS16(sc, 0x48); 1583 ptr = GETBIOS16(sc, ptr + 0x34); 1584 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1585 if (GETBIOS8(sc, ptr) == 3) { 1586 /* revision three table */ 1587 n = GETBIOS8(sc, ptr + 5) + 1; 1588 n = min(n, 4); 1589 1590 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1591 for (i = 0; i < n; i++) { 1592 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1593 ptr + i * 10 + 8); 1594 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1595 ptr + i * 10 + 0x10); 1596 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1597 sc->sc_tmds_pll[i].rtp_freq, 1598 sc->sc_tmds_pll[i].rtp_pll)); 1599 } 1600 return 0; 1601 } 1602 } 1603 1604 nobios: 1605 DPRINTF(("no suitable DFP table present\n")); 1606 for (i = 0; 1607 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1608 i++) { 1609 int j; 1610 1611 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1612 continue; 1613 1614 for (j = 0; j < 4; j++) { 1615 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1616 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1617 sc->sc_tmds_pll[j].rtp_freq, 1618 sc->sc_tmds_pll[j].rtp_pll)); 1619 } 1620 return 0; 1621 } 1622 1623 return -1; 1624 } 1625 1626 const struct videomode * 1627 radeonfb_modelookup(const char *name) 1628 { 1629 int i; 1630 1631 for (i = 0; i < videomode_count; i++) 1632 if (!strcmp(name, videomode_list[i].name)) 1633 return &videomode_list[i]; 1634 1635 return NULL; 1636 } 1637 1638 void 1639 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1640 { 1641 if (crtc) { 1642 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1643 RADEON_P2PLL_ATOMIC_UPDATE_R); 1644 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1645 } else { 1646 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1647 RADEON_PPLL_ATOMIC_UPDATE_R); 1648 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1649 } 1650 } 1651 1652 void 1653 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1654 { 1655 int i; 1656 1657 for (i = 10000; i; i--) { 1658 if (crtc) { 1659 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1660 RADEON_P2PLL_ATOMIC_UPDATE_R) 1661 break; 1662 } else { 1663 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1664 RADEON_PPLL_ATOMIC_UPDATE_R) 1665 break; 1666 } 1667 } 1668 } 1669 1670 void 1671 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1672 { 1673 uint32_t pbit = 0; 1674 uint32_t feed = 0; 1675 uint32_t data; 1676 #if 1 1677 int i; 1678 #endif 1679 1680 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 1681 1682 if (crtc == 0) { 1683 1684 /* XXXX: mobility workaround missing */ 1685 /* XXXX: R300 stuff missing */ 1686 1687 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1688 RADEON_VCLK_SRC_SEL_CPUCLK, 1689 ~RADEON_VCLK_SRC_SEL_MASK); 1690 1691 /* put vclk into reset, use atomic updates */ 1692 SETPLL(sc, RADEON_PPLL_CNTL, 1693 RADEON_PPLL_REFCLK_SEL | 1694 RADEON_PPLL_FBCLK_SEL | 1695 RADEON_PPLL_RESET | 1696 RADEON_PPLL_ATOMIC_UPDATE_EN | 1697 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1698 1699 /* select clock 3 */ 1700 #if 0 1701 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_DIV_SEL, 1702 ~RADEON_PLL_DIV_SEL); 1703 #else 1704 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 1705 ~RADEON_PLL_DIV_SEL); 1706 #endif 1707 1708 /* XXX: R300 family -- program divider differently? */ 1709 1710 /* program reference divider */ 1711 PATCHPLL(sc, RADEON_PPLL_REF_DIV, sc->sc_refdiv, 1712 ~RADEON_PPLL_REF_DIV_MASK); 1713 PRINTPLL(RADEON_PPLL_REF_DIV); 1714 1715 #if 0 1716 data = GETPLL(sc, RADEON_PPLL_DIV_3); 1717 data &= ~(RADEON_PPLL_FB3_DIV_MASK | 1718 RADEON_PPLL_POST3_DIV_MASK); 1719 data |= pbit; 1720 data |= (feed & RADEON_PPLL_FB3_DIV_MASK); 1721 PUTPLL(sc, RADEON_PPLL_DIV_3, data); 1722 #else 1723 for (i = 0; i < 4; i++) { 1724 } 1725 #endif 1726 1727 /* use the atomic update */ 1728 radeonfb_pllwriteupdate(sc, crtc); 1729 1730 /* and wait for it to complete */ 1731 radeonfb_pllwaitatomicread(sc, crtc); 1732 1733 /* program HTOTAL (why?) */ 1734 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 1735 1736 /* drop reset */ 1737 CLRPLL(sc, RADEON_PPLL_CNTL, 1738 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 1739 RADEON_PPLL_ATOMIC_UPDATE_EN | 1740 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 1741 1742 PRINTPLL(RADEON_PPLL_CNTL); 1743 1744 /* give clock time to lock */ 1745 delay(50000); 1746 1747 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 1748 RADEON_VCLK_SRC_SEL_PPLLCLK, 1749 ~RADEON_VCLK_SRC_SEL_MASK); 1750 1751 } else { 1752 1753 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1754 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 1755 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1756 1757 /* put vclk into reset, use atomic updates */ 1758 SETPLL(sc, RADEON_P2PLL_CNTL, 1759 RADEON_P2PLL_RESET | 1760 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1761 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1762 1763 /* XXX: R300 family -- program divider differently? */ 1764 1765 /* program reference divider */ 1766 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 1767 ~RADEON_P2PLL_REF_DIV_MASK); 1768 1769 /* program feedback and post dividers */ 1770 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 1771 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 1772 RADEON_P2PLL_POST0_DIV_MASK); 1773 data |= pbit; 1774 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 1775 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 1776 1777 /* use the atomic update */ 1778 radeonfb_pllwriteupdate(sc, crtc); 1779 1780 /* and wait for it to complete */ 1781 radeonfb_pllwaitatomicread(sc, crtc); 1782 1783 /* program HTOTAL (why?) */ 1784 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 1785 1786 /* drop reset */ 1787 CLRPLL(sc, RADEON_P2PLL_CNTL, 1788 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 1789 RADEON_P2PLL_ATOMIC_UPDATE_EN | 1790 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 1791 1792 /* allow time for clock to lock */ 1793 delay(50000); 1794 1795 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 1796 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 1797 ~RADEON_PIX2CLK_SRC_SEL_MASK); 1798 } 1799 PRINTREG(RADEON_CRTC_MORE_CNTL); 1800 } 1801 1802 void 1803 radeonfb_modeswitch(struct radeonfb_display *dp) 1804 { 1805 struct radeonfb_softc *sc = dp->rd_softc; 1806 int i; 1807 1808 /* blank the display while we switch modes */ 1809 //radeonfb_blank(dp, 1); 1810 1811 #if 0 1812 SET32(sc, RADEON_CRTC_EXT_CNTL, 1813 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1814 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1815 #endif 1816 1817 /* these registers might get in the way... */ 1818 PUT32(sc, RADEON_OVR_CLR, 0); 1819 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 1820 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 1821 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 1822 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 1823 PUT32(sc, RADEON_VIPH_CONTROL, 0); 1824 PUT32(sc, RADEON_I2C_CNTL_1, 0); 1825 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 1826 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 1827 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 1828 PUT32(sc, RADEON_SURFACE_CNTL, 0); 1829 1830 for (i = 0; i < dp->rd_ncrtcs; i++) 1831 radeonfb_setcrtc(dp, i); 1832 1833 /* activate the display */ 1834 //radeonfb_blank(dp, 0); 1835 } 1836 1837 void 1838 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 1839 { 1840 int crtc; 1841 struct videomode *mode; 1842 struct radeonfb_softc *sc; 1843 struct radeonfb_crtc *cp; 1844 uint32_t v; 1845 uint32_t gencntl; 1846 uint32_t htotaldisp; 1847 uint32_t hsyncstrt; 1848 uint32_t vtotaldisp; 1849 uint32_t vsyncstrt; 1850 uint32_t fphsyncstrt; 1851 uint32_t fpvsyncstrt; 1852 uint32_t fphtotaldisp; 1853 uint32_t fpvtotaldisp; 1854 uint32_t pitch; 1855 1856 sc = dp->rd_softc; 1857 cp = &dp->rd_crtcs[index]; 1858 crtc = cp->rc_number; 1859 mode = &cp->rc_videomode; 1860 1861 #if 1 1862 pitch = (((dp->rd_virtx * dp->rd_bpp) + ((dp->rd_bpp * 8) - 1)) / 1863 (dp->rd_bpp * 8)); 1864 #else 1865 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 1866 (sc->sc_maxbpp * 8)); 1867 #endif 1868 //pitch = pitch | (pitch << 16); 1869 1870 switch (crtc) { 1871 case 0: 1872 gencntl = RADEON_CRTC_GEN_CNTL; 1873 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 1874 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 1875 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 1876 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 1877 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 1878 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 1879 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 1880 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 1881 break; 1882 case 1: 1883 gencntl = RADEON_CRTC2_GEN_CNTL; 1884 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 1885 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 1886 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 1887 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 1888 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 1889 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 1890 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 1891 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 1892 break; 1893 default: 1894 panic("Bad CRTC!"); 1895 break; 1896 } 1897 1898 /* 1899 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 1900 */ 1901 /* only bother with 32bpp and 8bpp */ 1902 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 1903 1904 if (crtc == 1) { 1905 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 1906 } else { 1907 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 1908 } 1909 1910 if (mode->flags & VID_DBLSCAN) 1911 v |= RADEON_CRTC2_DBL_SCAN_EN; 1912 1913 if (mode->flags & VID_INTERLACE) 1914 v |= RADEON_CRTC2_INTERLACE_EN; 1915 1916 if (mode->flags & VID_CSYNC) { 1917 v |= RADEON_CRTC2_CSYNC_EN; 1918 if (crtc == 1) 1919 v |= RADEON_CRTC2_VSYNC_TRISTAT; 1920 } 1921 1922 PUT32(sc, gencntl, v); 1923 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 1924 1925 /* 1926 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 1927 */ 1928 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 1929 if (crtc == 0) { 1930 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1931 RADEON_CRTC_DISPLAY_DIS); 1932 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 1933 if (mode->flags & VID_CSYNC) 1934 v |= RADEON_CRTC_VSYNC_TRISTAT; 1935 } 1936 /* unconditional turn on CRT, in case first CRTC is DFP */ 1937 v |= RADEON_CRTC_CRT_ON; 1938 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 1939 PRINTREG(RADEON_CRTC_EXT_CNTL); 1940 1941 /* 1942 * H_TOTAL_DISP 1943 */ 1944 v = ((mode->hdisplay / 8) - 1) << 16; 1945 v |= (mode->htotal / 8) - 1; 1946 PUT32(sc, htotaldisp, v); 1947 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1948 PUT32(sc, fphtotaldisp, v); 1949 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1950 1951 /* 1952 * H_SYNC_STRT_WID 1953 */ 1954 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 1955 v |= mode->hsync_start; 1956 if (mode->flags & VID_NHSYNC) 1957 v |= RADEON_CRTC_H_SYNC_POL; 1958 PUT32(sc, hsyncstrt, v); 1959 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1960 PUT32(sc, fphsyncstrt, v); 1961 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1962 1963 /* 1964 * V_TOTAL_DISP 1965 */ 1966 v = ((mode->vdisplay - 1) << 16); 1967 v |= (mode->vtotal - 1); 1968 PUT32(sc, vtotaldisp, v); 1969 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1970 PUT32(sc, fpvtotaldisp, v); 1971 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 1972 1973 /* 1974 * V_SYNC_STRT_WID 1975 */ 1976 v = ((mode->vsync_end - mode->vsync_start) << 16); 1977 v |= (mode->vsync_start - 1); 1978 if (mode->flags & VID_NVSYNC) 1979 v |= RADEON_CRTC_V_SYNC_POL; 1980 PUT32(sc, vsyncstrt, v); 1981 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1982 PUT32(sc, fpvsyncstrt, v); 1983 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 1984 1985 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 1986 1987 switch (crtc) { 1988 case 0: 1989 PUT32(sc, RADEON_CRTC_OFFSET, 0); 1990 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 1991 PUT32(sc, RADEON_CRTC_PITCH, pitch); 1992 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 1993 1994 CLR32(sc, RADEON_CRTC_EXT_CNTL, 1995 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 1996 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 1997 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 1998 PRINTREG(RADEON_CRTC_EXT_CNTL); 1999 PRINTREG(RADEON_CRTC_GEN_CNTL); 2000 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2001 break; 2002 2003 case 1: 2004 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2005 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2006 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2007 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2008 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2009 RADEON_CRTC2_VSYNC_DIS | 2010 RADEON_CRTC2_HSYNC_DIS | 2011 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2012 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2013 break; 2014 } 2015 } 2016 2017 int 2018 radeonfb_isblank(struct radeonfb_display *dp) 2019 { 2020 uint32_t reg, mask; 2021 2022 if (dp->rd_crtcs[0].rc_number) { 2023 reg = RADEON_CRTC2_GEN_CNTL; 2024 mask = RADEON_CRTC2_DISP_DIS; 2025 } else { 2026 reg = RADEON_CRTC_EXT_CNTL; 2027 mask = RADEON_CRTC_DISPLAY_DIS; 2028 } 2029 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2030 } 2031 2032 void 2033 radeonfb_blank(struct radeonfb_display *dp, int blank) 2034 { 2035 struct radeonfb_softc *sc = dp->rd_softc; 2036 uint32_t reg, mask; 2037 uint32_t fpreg, fpval; 2038 int i; 2039 2040 for (i = 0; i < dp->rd_ncrtcs; i++) { 2041 2042 if (dp->rd_crtcs[i].rc_number) { 2043 reg = RADEON_CRTC2_GEN_CNTL; 2044 mask = RADEON_CRTC2_DISP_DIS; 2045 fpreg = RADEON_FP2_GEN_CNTL; 2046 fpval = RADEON_FP2_ON; 2047 } else { 2048 reg = RADEON_CRTC_EXT_CNTL; 2049 mask = RADEON_CRTC_DISPLAY_DIS; 2050 fpreg = RADEON_FP_GEN_CNTL; 2051 fpval = RADEON_FP_FPON; 2052 } 2053 2054 if (blank) { 2055 SET32(sc, reg, mask); 2056 CLR32(sc, fpreg, fpval); 2057 } else { 2058 CLR32(sc, reg, mask); 2059 SET32(sc, fpreg, fpval); 2060 } 2061 } 2062 PRINTREG(RADEON_FP_GEN_CNTL); 2063 PRINTREG(RADEON_FP2_GEN_CNTL); 2064 } 2065 2066 void 2067 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2068 long *defattr) 2069 { 2070 struct radeonfb_display *dp = cookie; 2071 struct rasops_info *ri = &scr->scr_ri; 2072 2073 /* initialize font subsystem */ 2074 wsfont_init(); 2075 2076 DPRINTF(("init screen called, existing %d\n", existing)); 2077 2078 ri->ri_depth = dp->rd_bpp; 2079 ri->ri_width = dp->rd_virtx; 2080 ri->ri_height = dp->rd_virty; 2081 ri->ri_stride = dp->rd_stride; 2082 ri->ri_flg = RI_CENTER; 2083 ri->ri_bits = (void *)dp->rd_fbptr; 2084 2085 /* XXX: 32 bpp only */ 2086 /* this is rgb in "big-endian order..." */ 2087 ri->ri_rnum = 8; 2088 ri->ri_gnum = 8; 2089 ri->ri_bnum = 8; 2090 ri->ri_rpos = 16; 2091 ri->ri_gpos = 8; 2092 ri->ri_bpos = 0; 2093 2094 if (existing) { 2095 ri->ri_flg |= RI_CLEAR; 2096 2097 /* start a modeswitch now */ 2098 radeonfb_modeswitch(dp); 2099 } 2100 2101 /* 2102 * XXX: font selection should be based on properties, with some 2103 * normal/reasonable default. 2104 */ 2105 ri->ri_caps = WSSCREEN_WSCOLORS; 2106 2107 /* initialize and look for an initial font */ 2108 rasops_init(ri, dp->rd_virty/8, dp->rd_virtx/8); 2109 2110 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2111 dp->rd_virtx / ri->ri_font->fontwidth); 2112 2113 /* enable acceleration */ 2114 ri->ri_ops.copyrows = radeonfb_copyrows; 2115 ri->ri_ops.copycols = radeonfb_copycols; 2116 ri->ri_ops.eraserows = radeonfb_eraserows; 2117 ri->ri_ops.erasecols = radeonfb_erasecols; 2118 ri->ri_ops.allocattr = radeonfb_allocattr; 2119 if (!IS_R300(dp->rd_softc)) { 2120 ri->ri_ops.putchar = radeonfb_putchar; 2121 } 2122 ri->ri_ops.cursor = radeonfb_cursor; 2123 } 2124 2125 void 2126 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2127 { 2128 uint32_t gen, ext, gen2 = 0; 2129 uint32_t agploc, aperbase, apersize, mcfbloc; 2130 2131 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2132 ext = GET32(sc, RADEON_CRTC_EXT_CNTL); 2133 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2134 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2135 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2136 2137 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2138 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2139 //PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2140 //PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2141 2142 if (HAS_CRTC2(sc)) { 2143 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2144 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2145 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2146 } 2147 2148 delay(100000); 2149 2150 mcfbloc = (aperbase >> 16) | 2151 ((aperbase + (apersize - 1)) & 0xffff0000); 2152 2153 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2154 sc->sc_memsz = apersize; 2155 2156 if (((agploc & 0xffff) << 16) != 2157 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2158 agploc = mcfbloc & 0xffff0000U; 2159 agploc |= ((agploc + 0x10000) >> 16); 2160 } 2161 2162 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2163 2164 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2165 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2166 2167 DPRINTF(("aperbase = %u\n", aperbase)); 2168 PRINTREG(RADEON_MC_FB_LOCATION); 2169 PRINTREG(RADEON_MC_AGP_LOCATION); 2170 2171 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2172 2173 if (HAS_CRTC2(sc)) 2174 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2175 2176 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2177 2178 #if 0 2179 /* XXX: what is this AGP garbage? :-) */ 2180 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2181 #endif 2182 2183 delay(100000); 2184 2185 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2186 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2187 2188 if (HAS_CRTC2(sc)) 2189 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2190 } 2191 2192 void 2193 radeonfb_init_misc(struct radeonfb_softc *sc) 2194 { 2195 PUT32(sc, RADEON_BUS_CNTL, 2196 RADEON_BUS_MASTER_DIS | 2197 RADEON_BUS_PREFETCH_MODE_ACT | 2198 RADEON_BUS_PCI_READ_RETRY_EN | 2199 RADEON_BUS_PCI_WRT_RETRY_EN | 2200 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2201 RADEON_BUS_MSTR_RD_MULT | 2202 RADEON_BUS_MSTR_RD_LINE | 2203 RADEON_BUS_RD_DISCARD_EN | 2204 RADEON_BUS_MSTR_DISCONNECT_EN | 2205 RADEON_BUS_READ_BURST); 2206 2207 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2208 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2209 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2210 PUT32(sc, RADEON_RBBM_CNTL, 2211 (3 << RADEON_RB_SETTLE_SHIFT) | 2212 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2213 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2214 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2215 2216 /* XXX: figure out what these mean! */ 2217 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2218 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2219 //PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2220 2221 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2222 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2223 } 2224 2225 /* 2226 * This loads a linear color map for true color. 2227 */ 2228 void 2229 radeonfb_init_palette(struct radeonfb_softc *sc, int crtc) 2230 { 2231 int i; 2232 uint32_t vclk; 2233 2234 #define DAC_WIDTH ((1 << 10) - 1) 2235 #define CLUT_WIDTH ((1 << 8) - 1) 2236 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2237 2238 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2239 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2240 2241 if (crtc) 2242 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2243 else 2244 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2245 2246 PUT32(sc, RADEON_PALETTE_INDEX, 0); 2247 for (i = 0; i <= CLUT_WIDTH; ++i) { 2248 PUT32(sc, RADEON_PALETTE_30_DATA, 2249 (CLUT_COLOR(i) << 10) | 2250 (CLUT_COLOR(i) << 20) | 2251 (CLUT_COLOR(i))); 2252 } 2253 2254 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2255 PRINTREG(RADEON_DAC_CNTL2); 2256 2257 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2258 } 2259 2260 /* 2261 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2262 */ 2263 void 2264 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2265 { 2266 uint32_t tmp, save; 2267 2268 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2269 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2270 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2271 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2272 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2273 } 2274 2275 /* 2276 * Acceleration entry points. 2277 */ 2278 static void 2279 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2280 { 2281 struct rasops_info *ri = cookie; 2282 struct vcons_screen *scr = ri->ri_hw; 2283 struct radeonfb_display *dp = scr->scr_cookie; 2284 uint32_t x, y, w, h; 2285 uint32_t bg, fg; 2286 uint8_t *data; 2287 2288 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2289 return; 2290 2291 if (!CHAR_IN_FONT(c, ri->ri_font)) 2292 return; 2293 2294 w = ri->ri_font->fontwidth; 2295 h = ri->ri_font->fontheight; 2296 2297 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2298 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2299 2300 x = ri->ri_xorigin + col * w; 2301 y = ri->ri_yorigin + row * h; 2302 2303 if (c == 0x20) { 2304 radeonfb_rectfill(dp, x, y, w, h, bg); 2305 } else { 2306 data = (uint8_t *)ri->ri_font->data + 2307 (c - ri->ri_font->firstchar) * ri->ri_fontscale; 2308 2309 radeonfb_setup_mono(dp, x, y, w, h, fg, bg); 2310 radeonfb_feed_bytes(dp, ri->ri_fontscale, data); 2311 } 2312 } 2313 2314 static void 2315 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 2316 { 2317 struct rasops_info *ri = cookie; 2318 struct vcons_screen *scr = ri->ri_hw; 2319 struct radeonfb_display *dp = scr->scr_cookie; 2320 uint32_t x, y, w, h, fg, bg, ul; 2321 2322 /* XXX: check for full emulation mode? */ 2323 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2324 x = ri->ri_xorigin; 2325 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2326 w = ri->ri_emuwidth; 2327 h = ri->ri_font->fontheight * nrows; 2328 2329 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2330 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2331 } 2332 } 2333 2334 static void 2335 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 2336 { 2337 struct rasops_info *ri = cookie; 2338 struct vcons_screen *scr = ri->ri_hw; 2339 struct radeonfb_display *dp = scr->scr_cookie; 2340 uint32_t x, ys, yd, w, h; 2341 2342 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2343 x = ri->ri_xorigin; 2344 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 2345 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 2346 w = ri->ri_emuwidth; 2347 h = ri->ri_font->fontheight * nrows; 2348 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 2349 RADEON_ROP3_S, 0xffffffff); 2350 } 2351 } 2352 2353 static void 2354 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 2355 { 2356 struct rasops_info *ri = cookie; 2357 struct vcons_screen *scr = ri->ri_hw; 2358 struct radeonfb_display *dp = scr->scr_cookie; 2359 uint32_t xs, xd, y, w, h; 2360 2361 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2362 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 2363 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 2364 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2365 w = ri->ri_font->fontwidth * ncols; 2366 h = ri->ri_font->fontheight; 2367 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 2368 RADEON_ROP3_S, 0xffffffff); 2369 } 2370 } 2371 2372 static void 2373 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 2374 long fillattr) 2375 { 2376 struct rasops_info *ri = cookie; 2377 struct vcons_screen *scr = ri->ri_hw; 2378 struct radeonfb_display *dp = scr->scr_cookie; 2379 uint32_t x, y, w, h, fg, bg, ul; 2380 2381 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2382 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 2383 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 2384 w = ri->ri_font->fontwidth * ncols; 2385 h = ri->ri_font->fontheight; 2386 2387 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 2388 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 2389 } 2390 } 2391 2392 static void 2393 radeonfb_cursor(void *cookie, int on, int row, int col) 2394 { 2395 struct rasops_info *ri = cookie; 2396 struct vcons_screen *scr = ri->ri_hw; 2397 struct radeonfb_display *dp = scr->scr_cookie; 2398 int x, y, wi, he; 2399 2400 wi = ri->ri_font->fontwidth; 2401 he = ri->ri_font->fontheight; 2402 2403 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 2404 x = ri->ri_ccol * wi + ri->ri_xorigin; 2405 y = ri->ri_crow * he + ri->ri_yorigin; 2406 /* first turn off the old cursor */ 2407 if (ri->ri_flg & RI_CURSOR) { 2408 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2409 RADEON_ROP3_Dn, 0xffffffff); 2410 ri->ri_flg &= ~RI_CURSOR; 2411 } 2412 ri->ri_crow = row; 2413 ri->ri_ccol = col; 2414 /* then (possibly) turn on the new one */ 2415 if (on) { 2416 x = ri->ri_ccol * wi + ri->ri_xorigin; 2417 y = ri->ri_crow * he + ri->ri_yorigin; 2418 radeonfb_bitblt(dp, x, y, x, y, wi, he, 2419 RADEON_ROP3_Dn, 0xffffffff); 2420 ri->ri_flg |= RI_CURSOR; 2421 } 2422 } else { 2423 scr->scr_ri.ri_crow = row; 2424 scr->scr_ri.ri_ccol = col; 2425 scr->scr_ri.ri_flg &= ~RI_CURSOR; 2426 } 2427 } 2428 2429 static int 2430 radeonfb_allocattr(void *cookie, int fg, int bg, int flags, long *attrp) 2431 { 2432 if ((fg == 0) && (bg == 0)) { 2433 fg = WS_DEFAULT_FG; 2434 bg = WS_DEFAULT_BG; 2435 } 2436 *attrp = ((fg & 0xf) << 24) | ((bg & 0xf) << 16) | (flags & 0xff) << 8; 2437 return 0; 2438 } 2439 2440 /* 2441 * Underlying acceleration support. 2442 */ 2443 static void 2444 radeonfb_setup_mono(struct radeonfb_display *dp, int xd, int yd, int width, 2445 int height, uint32_t fg, uint32_t bg) 2446 { 2447 struct radeonfb_softc *sc = dp->rd_softc; 2448 uint32_t gmc; 2449 uint32_t padded_width = (width+7) & 0xfff8; 2450 uint32_t topleft, bottomright; 2451 2452 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2453 2454 if (width != padded_width) { 2455 2456 radeonfb_wait_fifo(sc, 2); 2457 topleft = ((yd << 16) & 0x1fff0000) | (xd & 0x1fff); 2458 bottomright = (((yd + height) << 16) & 0x1fff0000) | 2459 ((xd + width) & 0x1fff); 2460 PUT32(sc, RADEON_SC_TOP_LEFT, topleft); 2461 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, bottomright); 2462 } 2463 2464 radeonfb_wait_fifo(sc, 5); 2465 2466 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2467 RADEON_GMC_BRUSH_NONE | 2468 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2469 //RADEON_GMC_BYTE_LSB_TO_MSB | 2470 RADEON_GMC_DST_CLIPPING | 2471 RADEON_ROP3_S | 2472 RADEON_DP_SRC_SOURCE_HOST_DATA | 2473 RADEON_GMC_CLR_CMP_CNTL_DIS | 2474 RADEON_GMC_WR_MSK_DIS | 2475 gmc); 2476 2477 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2478 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2479 2480 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2481 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (padded_width << 16) | height); 2482 2483 } 2484 2485 static void 2486 radeonfb_feed_bytes(struct radeonfb_display *dp, int count, uint8_t *data) 2487 { 2488 struct radeonfb_softc *sc = dp->rd_softc; 2489 int i; 2490 uint32_t latch = 0; 2491 int shift = 0; 2492 2493 for (i = 0; i < count; i++) { 2494 latch |= (data[i] << shift); 2495 if (shift == 24) { 2496 radeonfb_wait_fifo(sc, 1); 2497 PUT32(sc, RADEON_HOST_DATA0, latch); 2498 latch = 0; 2499 shift = 0; 2500 } else 2501 shift += 8; 2502 } 2503 if (shift != 0) { 2504 radeonfb_wait_fifo(sc, 1); 2505 PUT32(sc, RADEON_HOST_DATA0, latch); 2506 } 2507 radeonfb_unclip(sc); 2508 } 2509 2510 static void 2511 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 2512 int width, int height, uint32_t color) 2513 { 2514 struct radeonfb_softc *sc = dp->rd_softc; 2515 uint32_t gmc; 2516 2517 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2518 2519 radeonfb_wait_fifo(sc, 6); 2520 2521 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2522 RADEON_GMC_BRUSH_SOLID_COLOR | 2523 RADEON_GMC_SRC_DATATYPE_COLOR | 2524 RADEON_GMC_CLR_CMP_CNTL_DIS | 2525 RADEON_ROP3_P | gmc); 2526 2527 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 2528 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2529 PUT32(sc, RADEON_DP_CNTL, 2530 RADEON_DST_X_LEFT_TO_RIGHT | 2531 RADEON_DST_Y_TOP_TO_BOTTOM); 2532 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2533 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2534 2535 /* 2536 * XXX: we don't wait for the fifo to empty -- that would slow 2537 * things down! The linux radeonfb driver waits, but xfree doesn't 2538 */ 2539 /* XXX: for now we do, to make it safe for direct drawing */ 2540 radeonfb_engine_idle(sc); 2541 } 2542 2543 static void 2544 radeonfb_bitblt(struct radeonfb_display *dp, int srcx, int srcy, 2545 int dstx, int dsty, int width, int height, int rop, uint32_t mask) 2546 { 2547 struct radeonfb_softc *sc = dp->rd_softc; 2548 uint32_t gmc; 2549 uint32_t dir; 2550 2551 if (dsty < srcy) { 2552 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 2553 } else { 2554 srcy += height - 1; 2555 dsty += height - 1; 2556 dir = 0; 2557 } 2558 if (dstx < srcx) { 2559 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 2560 } else { 2561 srcx += width - 1; 2562 dstx += width - 1; 2563 } 2564 2565 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2566 2567 radeonfb_wait_fifo(sc, 6); 2568 2569 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2570 //RADEON_GMC_SRC_CLIPPING | 2571 RADEON_GMC_BRUSH_SOLID_COLOR | 2572 RADEON_GMC_SRC_DATATYPE_COLOR | 2573 RADEON_GMC_CLR_CMP_CNTL_DIS | 2574 RADEON_DP_SRC_SOURCE_MEMORY | 2575 rop | gmc); 2576 2577 PUT32(sc, RADEON_DP_WRITE_MASK, mask); 2578 PUT32(sc, RADEON_DP_CNTL, dir); 2579 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 2580 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 2581 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 2582 2583 /* 2584 * XXX: we don't wait for the fifo to empty -- that would slow 2585 * things down! The linux radeonfb driver waits, but xfree doesn't 2586 */ 2587 /* XXX: for now we do, to make it safe for direct drawing */ 2588 radeonfb_engine_idle(sc); 2589 } 2590 2591 static void 2592 radeonfb_engine_idle(struct radeonfb_softc *sc) 2593 { 2594 int i; 2595 2596 radeonfb_wait_fifo(sc, 64); 2597 for (i = RADEON_TIMEOUT; i; i--) { 2598 if ((GET32(sc, RADEON_RBBM_STATUS) & 2599 RADEON_RBBM_ACTIVE) == 0) { 2600 radeonfb_engine_flush(sc); 2601 break; 2602 } 2603 } 2604 } 2605 2606 static void 2607 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 2608 { 2609 int i; 2610 2611 for (i = RADEON_TIMEOUT; i; i--) { 2612 if ((GET32(sc, RADEON_RBBM_STATUS) & 2613 RADEON_RBBM_FIFOCNT_MASK) >= n) 2614 return; 2615 } 2616 #ifdef DIAGNOSTIC 2617 if (!i) 2618 printf("%s: timed out waiting for fifo (%x)\n", 2619 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 2620 #endif 2621 } 2622 2623 static void 2624 radeonfb_engine_flush(struct radeonfb_softc *sc) 2625 { 2626 int i; 2627 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL); 2628 for (i = RADEON_TIMEOUT; i; i--) { 2629 if ((GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 2630 RADEON_RB2D_DC_BUSY) == 0) 2631 break; 2632 } 2633 #ifdef DIAGNOSTIC 2634 if (!i) 2635 printf("%s: engine flush timed out!\n", XNAME(sc)); 2636 #endif 2637 } 2638 2639 static inline void 2640 radeonfb_unclip(struct radeonfb_softc *sc) 2641 { 2642 2643 radeonfb_wait_fifo(sc, 2); 2644 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 2645 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 2646 } 2647 2648 static void 2649 radeonfb_engine_init(struct radeonfb_display *dp) 2650 { 2651 struct radeonfb_softc *sc = dp->rd_softc; 2652 uint32_t pitch; 2653 2654 /* no 3D */ 2655 PUT32(sc, RADEON_RB3D_CNTL, 0); 2656 2657 radeonfb_engine_reset(sc); 2658 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 2659 //pitch = ((sc->sc_maxx * (sc->sc_maxbpp / 8) + 0x3f)) >> 6; 2660 2661 radeonfb_wait_fifo(sc, 1); 2662 if (!IS_R300(sc)) 2663 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 2664 2665 radeonfb_wait_fifo(sc, 3); 2666 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 2667 (pitch << 22) | (sc->sc_aperbase >> 10)); 2668 2669 2670 PUT32(sc, RADEON_DST_PITCH_OFFSET, 2671 (pitch << 22) | (sc->sc_aperbase >> 10)); 2672 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 2673 (pitch << 22) | (sc->sc_aperbase >> 10)); 2674 2675 radeonfb_wait_fifo(sc, 1); 2676 #if _BYTE_ORDER == _BIG_ENDIAN 2677 SET32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2678 #else 2679 CLR32(sc, RADEON_DP_DATATYPE, RADEON_HOST_BIG_ENDIAN_EN); 2680 #endif 2681 2682 /* default scissors -- no clipping */ 2683 radeonfb_wait_fifo(sc, 1); 2684 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 2685 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 2686 2687 radeonfb_wait_fifo(sc, 1); 2688 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2689 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 2690 RADEON_GMC_CLR_CMP_CNTL_DIS | 2691 RADEON_GMC_BRUSH_SOLID_COLOR | 2692 RADEON_GMC_SRC_DATATYPE_COLOR); 2693 2694 radeonfb_wait_fifo(sc, 7); 2695 PUT32(sc, RADEON_DST_LINE_START, 0); 2696 PUT32(sc, RADEON_DST_LINE_END, 0); 2697 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 2698 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 2699 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 2700 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 2701 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 2702 2703 radeonfb_engine_idle(sc); 2704 } 2705 2706 static void 2707 radeonfb_engine_reset(struct radeonfb_softc *sc) 2708 { 2709 uint32_t hpc, rbbm, mclkcntl, clkindex; 2710 2711 radeonfb_engine_flush(sc); 2712 2713 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2714 if (HAS_R300CG(sc)) 2715 radeonfb_r300cg_workaround(sc); 2716 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 2717 2718 /* 2719 * According to comments in XFree code, resetting the HDP via 2720 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 2721 * So we use HOST_PATH_CNTL instead. 2722 */ 2723 2724 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 2725 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 2726 if (IS_R300(sc)) { 2727 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2728 RADEON_SOFT_RESET_CP | 2729 RADEON_SOFT_RESET_HI | 2730 RADEON_SOFT_RESET_E2); 2731 GET32(sc, RADEON_RBBM_SOFT_RESET); 2732 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 2733 /* 2734 * XXX: this bit is not defined in any ATI docs I have, 2735 * nor in the XFree code, but XFree does it. Why? 2736 */ 2737 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 2738 } else { 2739 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 2740 RADEON_SOFT_RESET_CP | 2741 RADEON_SOFT_RESET_SE | 2742 RADEON_SOFT_RESET_RE | 2743 RADEON_SOFT_RESET_PP | 2744 RADEON_SOFT_RESET_E2 | 2745 RADEON_SOFT_RESET_RB); 2746 GET32(sc, RADEON_RBBM_SOFT_RESET); 2747 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 2748 ~(RADEON_SOFT_RESET_CP | 2749 RADEON_SOFT_RESET_SE | 2750 RADEON_SOFT_RESET_RE | 2751 RADEON_SOFT_RESET_PP | 2752 RADEON_SOFT_RESET_E2 | 2753 RADEON_SOFT_RESET_RB)); 2754 GET32(sc, RADEON_RBBM_SOFT_RESET); 2755 } 2756 2757 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 2758 GET32(sc, RADEON_HOST_PATH_CNTL); 2759 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 2760 2761 if (IS_R300(sc)) 2762 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 2763 2764 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 2765 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 2766 2767 if (HAS_R300CG(sc)) 2768 radeonfb_r300cg_workaround(sc); 2769 } 2770 2771 static int 2772 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 2773 { 2774 int x, y; 2775 2776 x = pos->x; 2777 y = pos->y; 2778 2779 /* 2780 * This doesn't let a cursor move off the screen. I'm not 2781 * sure if this will have negative effects for e.g. Xinerama. 2782 * I'd guess Xinerama handles it by changing the cursor shape, 2783 * but that needs verification. 2784 */ 2785 if (x >= dp->rd_virtx) 2786 x = dp->rd_virtx - 1; 2787 if (x < 0) 2788 x = 0; 2789 if (y >= dp->rd_virty) 2790 y = dp->rd_virty - 1; 2791 if (y < 0) 2792 y = 0; 2793 2794 dp->rd_cursor.rc_pos.x = x; 2795 dp->rd_cursor.rc_pos.y = y; 2796 2797 radeonfb_cursor_position(dp); 2798 return 0; 2799 } 2800 2801 static int 2802 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 2803 { 2804 unsigned flags; 2805 2806 uint8_t r[2], g[2], b[2]; 2807 unsigned index, count; 2808 int i, err; 2809 int pitch, size; 2810 struct radeonfb_cursor nc; 2811 2812 flags = wc->which; 2813 2814 /* copy old values */ 2815 nc = dp->rd_cursor; 2816 2817 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 2818 index = wc->cmap.index; 2819 count = wc->cmap.count; 2820 2821 if (index >= 2 || (index + count) > 2) 2822 return EINVAL; 2823 2824 err = copyin(wc->cmap.red, &r[index], count); 2825 if (err) 2826 return err; 2827 err = copyin(wc->cmap.green, &g[index], count); 2828 if (err) 2829 return err; 2830 err = copyin(wc->cmap.blue, &b[index], count); 2831 if (err) 2832 return err; 2833 2834 for (i = index; i < index + count; i++) { 2835 nc.rc_cmap[i] = 2836 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 2837 } 2838 } 2839 2840 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 2841 if ((wc->size.x > RADEON_CURSORMAXX) || 2842 (wc->size.y > RADEON_CURSORMAXY)) 2843 return EINVAL; 2844 2845 /* figure bytes per line */ 2846 pitch = (wc->size.x + 7) / 8; 2847 size = pitch * wc->size.y; 2848 2849 /* clear the old cursor and mask */ 2850 memset(nc.rc_image, 0, 512); 2851 memset(nc.rc_mask, 0, 512); 2852 2853 nc.rc_size = wc->size; 2854 2855 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 2856 return err; 2857 2858 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 2859 return err; 2860 } 2861 2862 if (flags & WSDISPLAY_CURSOR_DOHOT) { 2863 nc.rc_hot = wc->hot; 2864 if (nc.rc_hot.x >= nc.rc_size.x) 2865 nc.rc_hot.x = nc.rc_size.x - 1; 2866 if (nc.rc_hot.y >= nc.rc_size.y) 2867 nc.rc_hot.y = nc.rc_size.y - 1; 2868 } 2869 2870 if (flags & WSDISPLAY_CURSOR_DOPOS) { 2871 nc.rc_pos = wc->pos; 2872 if (nc.rc_pos.x >= dp->rd_virtx) 2873 nc.rc_pos.x = dp->rd_virtx - 1; 2874 #if 0 2875 if (nc.rc_pos.x < 0) 2876 nc.rc_pos.x = 0; 2877 #endif 2878 if (nc.rc_pos.y >= dp->rd_virty) 2879 nc.rc_pos.y = dp->rd_virty - 1; 2880 #if 0 2881 if (nc.rc_pos.y < 0) 2882 nc.rc_pos.y = 0; 2883 #endif 2884 } 2885 if (flags & WSDISPLAY_CURSOR_DOCUR) { 2886 nc.rc_visible = wc->enable; 2887 } 2888 2889 dp->rd_cursor = nc; 2890 radeonfb_cursor_update(dp, wc->which); 2891 2892 return 0; 2893 } 2894 2895 /* 2896 * Change the cursor shape. Call this with the cursor locked to avoid 2897 * flickering/tearing. 2898 */ 2899 static void 2900 radeonfb_cursor_shape(struct radeonfb_display *dp) 2901 { 2902 uint8_t and[512], xor[512]; 2903 int i, j, src, dst, pitch; 2904 const uint8_t *msk = dp->rd_cursor.rc_mask; 2905 const uint8_t *img = dp->rd_cursor.rc_image; 2906 2907 /* 2908 * Radeon cursor data interleaves one line of AND data followed 2909 * by a line of XOR data. (Each line corresponds to a whole hardware 2910 * pitch - i.e. 64 pixels or 8 bytes.) 2911 * 2912 * The cursor is displayed using the following table: 2913 * 2914 * AND XOR Result 2915 * ---------------------- 2916 * 0 0 Cursor color 0 2917 * 0 1 Cursor color 1 2918 * 1 0 Transparent 2919 * 1 1 Complement of background 2920 * 2921 * Our masks are therefore different from what we were passed. 2922 * Passed in, I'm assuming the data represents either color 0 or 1, 2923 * and a mask, so the passed in table looks like: 2924 * 2925 * IMG Mask Result 2926 * ----------------------- 2927 * 0 0 Transparent 2928 * 0 1 Cursor color 0 2929 * 1 0 Transparent 2930 * 1 1 Cursor color 1 2931 * 2932 * IF mask bit == 1, AND = 0, XOR = color. 2933 * IF mask bit == 0, AND = 1, XOR = 0. 2934 * 2935 * hence: AND = ~(mask); XOR = color & ~(mask); 2936 */ 2937 2938 pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); 2939 2940 /* start by assuming all bits are transparent */ 2941 memset(and, 0xff, 512); 2942 memset(xor, 0x00, 512); 2943 2944 src = 0; 2945 dst = 0; 2946 for (i = 0; i < 64; i++) { 2947 for (j = 0; j < 64; j += 8) { 2948 if ((i < dp->rd_cursor.rc_size.y) && 2949 (j < dp->rd_cursor.rc_size.x)) { 2950 2951 /* take care to leave odd bits alone */ 2952 and[dst] &= ~(msk[src]); 2953 xor[dst] = img[src] & msk[src]; 2954 src++; 2955 } 2956 dst++; 2957 } 2958 } 2959 2960 /* copy the image into place */ 2961 for (i = 0; i < 64; i++) { 2962 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 2963 &and[i * 8], 8); 2964 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 2965 &xor[i * 8], 8); 2966 } 2967 } 2968 2969 static void 2970 radeonfb_cursor_position(struct radeonfb_display *dp) 2971 { 2972 struct radeonfb_softc *sc = dp->rd_softc; 2973 uint32_t offset, hvoff, hvpos; /* registers */ 2974 uint32_t coff; /* cursor offset */ 2975 int i, x, y, xoff, yoff, crtcoff; 2976 2977 /* 2978 * XXX: this also needs to handle pan/scan 2979 */ 2980 for (i = 0; i < dp->rd_ncrtcs; i++) { 2981 2982 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 2983 2984 if (rcp->rc_number) { 2985 offset = RADEON_CUR2_OFFSET; 2986 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 2987 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 2988 crtcoff = RADEON_CRTC2_OFFSET; 2989 } else { 2990 offset = RADEON_CUR_OFFSET; 2991 hvoff = RADEON_CUR_HORZ_VERT_OFF; 2992 hvpos = RADEON_CUR_HORZ_VERT_POSN; 2993 crtcoff = RADEON_CRTC_OFFSET; 2994 } 2995 2996 x = dp->rd_cursor.rc_pos.x; 2997 y = dp->rd_cursor.rc_pos.y; 2998 2999 while (y < rcp->rc_yoffset) { 3000 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3001 } 3002 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3003 rcp->rc_yoffset += RADEON_PANINCREMENT; 3004 } 3005 while (x < rcp->rc_xoffset) { 3006 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3007 } 3008 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3009 rcp->rc_xoffset += RADEON_PANINCREMENT; 3010 } 3011 3012 /* adjust for the cursor's hotspot */ 3013 x -= dp->rd_cursor.rc_hot.x; 3014 y -= dp->rd_cursor.rc_hot.y; 3015 xoff = yoff = 0; 3016 3017 if (x >= dp->rd_virtx) 3018 x = dp->rd_virtx - 1; 3019 if (y >= dp->rd_virty) 3020 y = dp->rd_virty - 1; 3021 3022 /* now adjust cursor so it is relative to viewport */ 3023 x -= rcp->rc_xoffset; 3024 y -= rcp->rc_yoffset; 3025 3026 /* 3027 * no need to check for fall off, because we should 3028 * never move off the screen entirely! 3029 */ 3030 coff = 0; 3031 if (x < 0) { 3032 xoff = -x; 3033 x = 0; 3034 } 3035 if (y < 0) { 3036 yoff = -y; 3037 y = 0; 3038 coff = (yoff * 2) * 8; 3039 } 3040 3041 /* pan the display */ 3042 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3043 rcp->rc_xoffset); 3044 3045 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3046 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3047 /* NB: this unlocks the cursor */ 3048 PUT32(sc, hvpos, (x << 16) | y); 3049 } 3050 } 3051 3052 static void 3053 radeonfb_cursor_visible(struct radeonfb_display *dp) 3054 { 3055 int i; 3056 uint32_t gencntl, bit; 3057 3058 for (i = 0; i < dp->rd_ncrtcs; i++) { 3059 if (dp->rd_crtcs[i].rc_number) { 3060 gencntl = RADEON_CRTC2_GEN_CNTL; 3061 bit = RADEON_CRTC2_CUR_EN; 3062 } else { 3063 gencntl = RADEON_CRTC_GEN_CNTL; 3064 bit = RADEON_CRTC_CUR_EN; 3065 } 3066 3067 if (dp->rd_cursor.rc_visible) 3068 SET32(dp->rd_softc, gencntl, bit); 3069 else 3070 CLR32(dp->rd_softc, gencntl, bit); 3071 } 3072 } 3073 3074 static void 3075 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3076 { 3077 int i; 3078 uint32_t c0reg, c1reg; 3079 struct radeonfb_softc *sc = dp->rd_softc; 3080 3081 for (i = 0; i < dp->rd_ncrtcs; i++) { 3082 if (dp->rd_crtcs[i].rc_number) { 3083 c0reg = RADEON_CUR2_CLR0; 3084 c1reg = RADEON_CUR2_CLR1; 3085 } else { 3086 c0reg = RADEON_CUR_CLR0; 3087 c1reg = RADEON_CUR_CLR1; 3088 } 3089 3090 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3091 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3092 } 3093 } 3094 3095 static void 3096 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3097 { 3098 struct radeonfb_softc *sc; 3099 int i; 3100 3101 sc = dp->rd_softc; 3102 for (i = 0; i < dp->rd_ncrtcs; i++) { 3103 if (dp->rd_crtcs[i].rc_number) { 3104 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3105 } else { 3106 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3107 } 3108 } 3109 3110 if (which & WSDISPLAY_CURSOR_DOCMAP) 3111 radeonfb_cursor_cmap(dp); 3112 3113 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3114 radeonfb_cursor_shape(dp); 3115 3116 if (which & WSDISPLAY_CURSOR_DOCUR) 3117 radeonfb_cursor_visible(dp); 3118 3119 /* this one is unconditional, because it updates other stuff */ 3120 radeonfb_cursor_position(dp); 3121 } 3122 3123 static struct videomode * 3124 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3125 { 3126 int r1, r2; 3127 3128 /* otherwise pick the higher refresh rate */ 3129 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3130 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3131 3132 return (r1 < r2 ? m2 : m1); 3133 } 3134 3135 static const struct videomode * 3136 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3137 int x, int y) 3138 { 3139 struct edid_info *ep = &rp->rp_edid; 3140 struct videomode *vmp = NULL; 3141 int i; 3142 3143 if (!rp->rp_edid_valid) { 3144 /* fallback to safe mode */ 3145 return radeonfb_modelookup(sc->sc_defaultmode); 3146 } 3147 3148 /* always choose the preferred mode first! */ 3149 if (ep->edid_preferred_mode) { 3150 3151 /* XXX: add auto-stretching support for native mode */ 3152 3153 /* this may want panning to occur, btw */ 3154 if ((ep->edid_preferred_mode->hdisplay <= x) && 3155 (ep->edid_preferred_mode->vdisplay <= y)) 3156 return ep->edid_preferred_mode; 3157 } 3158 3159 for (i = 0; i < ep->edid_nmodes; i++) { 3160 /* 3161 * We elect to pick a resolution that is too large for 3162 * the monitor than one that is too small. This means 3163 * that we will prefer to pan rather than to try to 3164 * center a smaller display on a larger screen. In 3165 * practice, this shouldn't matter because if a 3166 * monitor can support a larger resolution, it can 3167 * probably also support the smaller. A specific 3168 * exception is fixed format panels, but hopefully 3169 * they are properly dealt with by the "autostretch" 3170 * logic above. 3171 */ 3172 if ((ep->edid_modes[i].hdisplay > x) || 3173 (ep->edid_modes[i].vdisplay > y)) { 3174 continue; 3175 } 3176 3177 /* 3178 * at this point, the display mode is no larger than 3179 * what we've requested. 3180 */ 3181 if (vmp == NULL) 3182 vmp = &ep->edid_modes[i]; 3183 3184 /* eliminate smaller modes */ 3185 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3186 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3187 continue; 3188 3189 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3190 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3191 vmp = &ep->edid_modes[i]; 3192 continue; 3193 } 3194 3195 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3196 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3197 3198 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3199 } 3200 3201 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3202 } 3203 3204 static int 3205 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3206 { 3207 int i; 3208 3209 for (i = 0; i < nlist; i++) { 3210 if ((x == list[i].hdisplay) && 3211 (y == list[i].vdisplay)) { 3212 return 1; 3213 } 3214 } 3215 return 0; 3216 } 3217 3218 static void 3219 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3220 int pan) 3221 { 3222 struct radeonfb_port *rp; 3223 struct edid_info *ep; 3224 int i, j; 3225 3226 *x = 0; 3227 *y = 0; 3228 3229 if (pan) { 3230 for (i = 0; i < dp->rd_ncrtcs; i++) { 3231 rp = dp->rd_crtcs[i].rc_port; 3232 ep = &rp->rp_edid; 3233 if (!rp->rp_edid_valid) { 3234 /* monitor not present */ 3235 continue; 3236 } 3237 3238 /* 3239 * For now we are ignoring "conflict" that 3240 * could occur when mixing some modes like 3241 * 1280x1024 and 1400x800. It isn't clear 3242 * which is better, so the first one wins. 3243 */ 3244 for (j = 0; j < ep->edid_nmodes; j++) { 3245 /* 3246 * ignore resolutions that are too big for 3247 * the radeon 3248 */ 3249 if (ep->edid_modes[j].hdisplay > 3250 dp->rd_softc->sc_maxx) 3251 continue; 3252 if (ep->edid_modes[j].vdisplay > 3253 dp->rd_softc->sc_maxy) 3254 continue; 3255 3256 /* 3257 * pick largest resolution, the 3258 * smaller monitor will pan 3259 */ 3260 if ((ep->edid_modes[j].hdisplay >= *x) && 3261 (ep->edid_modes[j].vdisplay >= *y)) { 3262 *x = ep->edid_modes[j].hdisplay; 3263 *y = ep->edid_modes[j].vdisplay; 3264 } 3265 } 3266 } 3267 3268 } else { 3269 struct videomode modes[64]; 3270 int nmodes = 0; 3271 int valid = 0; 3272 3273 for (i = 0; i < dp->rd_ncrtcs; i++) { 3274 /* 3275 * pick the largest resolution in common. 3276 */ 3277 rp = dp->rd_crtcs[i].rc_port; 3278 ep = &rp->rp_edid; 3279 3280 if (!rp->rp_edid_valid) 3281 continue; 3282 3283 if (!valid) { 3284 /* initialize starting list */ 3285 for (j = 0; j < ep->edid_nmodes; j++) { 3286 /* 3287 * ignore resolutions that are 3288 * too big for the radeon 3289 */ 3290 if (ep->edid_modes[j].hdisplay > 3291 dp->rd_softc->sc_maxx) 3292 continue; 3293 if (ep->edid_modes[j].vdisplay > 3294 dp->rd_softc->sc_maxy) 3295 continue; 3296 3297 modes[nmodes] = ep->edid_modes[j]; 3298 nmodes++; 3299 } 3300 valid = 1; 3301 } else { 3302 /* merge into preexisting list */ 3303 for (j = 0; j < nmodes; j++) { 3304 if (!radeonfb_hasres(ep->edid_modes, 3305 ep->edid_nmodes, 3306 modes[j].hdisplay, 3307 modes[j].vdisplay)) { 3308 modes[j] = modes[nmodes]; 3309 j--; 3310 nmodes--; 3311 } 3312 } 3313 } 3314 } 3315 3316 /* now we have to pick from the merged list */ 3317 for (i = 0; i < nmodes; i++) { 3318 if ((modes[i].hdisplay >= *x) && 3319 (modes[i].vdisplay >= *y)) { 3320 *x = modes[i].hdisplay; 3321 *y = modes[i].vdisplay; 3322 } 3323 } 3324 } 3325 3326 if ((*x == 0) || (*y == 0)) { 3327 /* fallback to safe mode */ 3328 *x = 640; 3329 *y = 480; 3330 } 3331 } 3332 3333 3334 /* Get the current backlight level for the display. */ 3335 3336 static int 3337 radeonfb_get_backlight(struct radeonfb_display *dp) 3338 { 3339 int s; 3340 uint32_t level; 3341 3342 s = spltty(); 3343 3344 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 3345 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 3346 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 3347 3348 /* 3349 * On some chips, we should negate the backlight level. 3350 * XXX Find out on which chips. 3351 */ 3352 #ifdef RADEONFB_BACKLIGHT_NEGATED 3353 level = RADEONFB_BACKLIGHT_MAX - level; 3354 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3355 3356 splx(s); 3357 3358 return level; 3359 } 3360 3361 /* Set the backlight to the given level for the display. */ 3362 3363 static int 3364 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 3365 { 3366 struct radeonfb_softc *sc; 3367 int rlevel, s; 3368 uint32_t lvds; 3369 3370 s = spltty(); 3371 3372 if (level < 0) 3373 level = 0; 3374 else if (level >= RADEONFB_BACKLIGHT_MAX) 3375 level = RADEONFB_BACKLIGHT_MAX; 3376 3377 sc = dp->rd_softc; 3378 3379 /* On some chips, we should negate the backlight level. */ 3380 #ifdef RADEONFB_BACKLIGHT_NEGATED 3381 rlevel = RADEONFB_BACKLIGHT_MAX - level; 3382 #else 3383 rlevel = level; 3384 #endif /* RADEONFB_BACKLIGHT_NEGATED */ 3385 3386 callout_stop(&dp->rd_bl_lvds_co); 3387 radeonfb_engine_idle(sc); 3388 3389 /* 3390 * Turn off the display if the backlight is set to 0, since the 3391 * display is useless without backlight anyway. 3392 */ 3393 if (level == 0) 3394 radeonfb_blank(dp, 1); 3395 else if (radeonfb_get_backlight(dp) == 0) 3396 radeonfb_blank(dp, 0); 3397 3398 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 3399 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 3400 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 3401 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 3402 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 3403 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3404 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3405 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3406 lvds |= RADEON_LVDS_ON; 3407 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 3408 } else { 3409 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 3410 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 3411 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 3412 } 3413 3414 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 3415 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 3416 /* XXX What is the correct delay? */ 3417 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 3418 3419 splx(s); 3420 3421 return 0; 3422 } 3423 3424 /* 3425 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 3426 * Set the delayed bits in the register, and clear the stored delayed 3427 * value. 3428 */ 3429 3430 static void radeonfb_lvds_callout(void *arg) 3431 { 3432 struct radeonfb_display *dp = arg; 3433 int s; 3434 3435 s = splhigh(); 3436 3437 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 3438 dp->rd_bl_lvds_val); 3439 dp->rd_bl_lvds_val = 0; 3440 3441 splx(s); 3442 } 3443
Indexes created Tue Sep 23 22:09:46 GMT 2025