radeonfb.c revision 1.90
1 /* $NetBSD: radeonfb.c,v 1.90 2017/08/11 22:59:05 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.90 2017/08/11 22:59:05 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *); 124 static int radeonfb_getconnectors(struct radeonfb_softc *); 125 static const struct videomode *radeonfb_modelookup(const char *); 126 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 127 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 128 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 129 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int); 130 static void radeonfb_modeswitch(struct radeonfb_display *); 131 static void radeonfb_setcrtc(struct radeonfb_display *, int); 132 static void radeonfb_init_misc(struct radeonfb_softc *); 133 static void radeonfb_set_fbloc(struct radeonfb_softc *); 134 static void radeonfb_init_palette(struct radeonfb_display *); 135 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 136 137 static int radeonfb_isblank(struct radeonfb_display *); 138 static void radeonfb_blank(struct radeonfb_display *, int); 139 static int radeonfb_set_cursor(struct radeonfb_display *, 140 struct wsdisplay_cursor *); 141 static int radeonfb_set_curpos(struct radeonfb_display *, 142 struct wsdisplay_curpos *); 143 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 144 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 145 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 146 147 /* acceleration support */ 148 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 149 int width, int height, uint32_t color); 150 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 151 static void radeonfb_bitblt(void *, int srcx, int srcy, 152 int dstx, int dsty, int width, int height, int rop); 153 154 /* hw cursor support */ 155 static void radeonfb_cursor_cmap(struct radeonfb_display *); 156 static void radeonfb_cursor_shape(struct radeonfb_display *); 157 static void radeonfb_cursor_position(struct radeonfb_display *); 158 static void radeonfb_cursor_visible(struct radeonfb_display *); 159 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 160 161 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 162 static void radeonfb_engine_idle(struct radeonfb_softc *); 163 static void radeonfb_engine_flush(struct radeonfb_softc *); 164 static void radeonfb_engine_reset(struct radeonfb_softc *); 165 static void radeonfb_engine_init(struct radeonfb_display *); 166 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 167 168 static void radeonfb_eraserows(void *, int, int, long); 169 static void radeonfb_erasecols(void *, int, int, int, long); 170 static void radeonfb_copyrows(void *, int, int, int); 171 static void radeonfb_copycols(void *, int, int, int, int); 172 static void radeonfb_cursor(void *, int, int, int); 173 static void radeonfb_putchar(void *, int, int, unsigned, long); 174 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 175 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 176 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 177 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 178 #endif 179 180 static int radeonfb_set_backlight(struct radeonfb_display *, int); 181 static int radeonfb_get_backlight(struct radeonfb_display *); 182 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 183 static void radeonfb_lvds_callout(void *); 184 185 static void radeonfb_brightness_up(device_t); 186 static void radeonfb_brightness_down(device_t); 187 188 static struct videomode *radeonfb_best_refresh(struct videomode *, 189 struct videomode *); 190 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 191 uint16_t *, int); 192 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 193 struct radeonfb_port *, int, int); 194 195 static int radeonfb_drm_print(void *, const char *); 196 197 #ifdef RADEONFB_DEBUG 198 int radeon_debug = 1; 199 #define DPRINTF(x) \ 200 if (radeon_debug) printf x 201 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 202 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 203 #else 204 #define DPRINTF(x) 205 #define PRINTREG(r) 206 #define PRINTPLL(r) 207 #endif 208 209 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 210 211 #ifndef RADEON_DEFAULT_MODE 212 /* any reasonably modern display should handle this */ 213 #define RADEON_DEFAULT_MODE "1024x768x60" 214 #endif 215 216 extern const u_char rasops_cmap[768]; 217 218 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 219 220 static struct { 221 int size; /* minimum memory size (MB) */ 222 int maxx; /* maximum x dimension */ 223 int maxy; /* maximum y dimension */ 224 int maxbpp; /* maximum bpp */ 225 int maxdisp; /* maximum logical display count */ 226 } radeonfb_limits[] = { 227 { 32, 2048, 1536, 32, 2 }, 228 { 16, 1600, 1200, 32, 2 }, 229 { 8, 1600, 1200, 32, 1 }, 230 { 0, 0, 0, 0, 0 }, 231 }; 232 233 static struct wsscreen_descr radeonfb_stdscreen = { 234 "fb", /* name */ 235 0, 0, /* ncols, nrows */ 236 NULL, /* textops */ 237 8, 16, /* fontwidth, fontheight */ 238 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 239 0, /* modecookie */ 240 }; 241 242 struct wsdisplay_accessops radeonfb_accessops = { 243 radeonfb_ioctl, 244 radeonfb_mmap, 245 NULL, /* vcons_alloc_screen */ 246 NULL, /* vcons_free_screen */ 247 NULL, /* vcons_show_screen */ 248 NULL, /* load_font */ 249 NULL, /* pollc */ 250 NULL, /* scroll */ 251 }; 252 253 static struct { 254 uint16_t devid; 255 uint16_t family; 256 uint16_t flags; 257 } radeonfb_devices[] = 258 { 259 /* R100 family */ 260 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 261 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 262 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 263 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 264 265 /* RV100 family */ 266 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 267 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 268 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 269 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 270 271 /* RS100 family */ 272 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 273 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 274 275 /* RS200/RS250 family */ 276 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 277 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 278 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 279 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 280 281 /* R200 family */ 282 /* add more R200 products? , 5148 */ 283 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 284 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 285 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 286 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 288 289 /* RV200 family */ 290 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 291 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 292 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 293 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 294 295 /* RV250 family */ 296 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 297 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 298 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 299 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 301 302 /* RS300 family */ 303 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 304 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 305 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 306 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 307 308 /* RV280 family */ 309 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 310 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 311 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 312 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 316 317 /* R300 family */ 318 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 319 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 320 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 321 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 326 327 /* RV350/RV360 family */ 328 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 329 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 330 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 331 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 340 341 /* R350/R360 family */ 342 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 343 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 344 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 345 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 350 351 /* RV380/RV370 family */ 352 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 353 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 354 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 355 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 356 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 358 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 362 363 #if notyet 364 /* R420/R423 family */ 365 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 366 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 367 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 368 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 375 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 382 383 /* R5xx family */ 384 { 0x7240, RADEON_R420, 0 }, 385 #endif 386 { 0, 0, 0 } 387 }; 388 389 static struct { 390 int divider; 391 int mask; 392 } radeonfb_dividers[] = { 393 { 16, 5 }, 394 { 12, 7 }, 395 { 8, 3 }, 396 { 6, 6 }, 397 { 4, 2 }, 398 { 3, 4 }, 399 { 2, 1 }, 400 { 1, 0 }, 401 { 0, 0 } 402 }; 403 404 /* 405 * This table taken from X11. 406 */ 407 static const struct { 408 int family; 409 struct radeon_tmds_pll plls[4]; 410 } radeonfb_tmds_pll[] = { 411 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 412 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 413 { RADEON_RS100, {{0, 0}}}, 414 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 417 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 418 { RADEON_RS300, {{0, 0}}}, 419 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}}}, 420 { RADEON_R300, {{-1, 0xb01cb}}}, 421 { RADEON_R350, {{-1, 0xb01cb}}}, 422 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 423 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 424 { RADEON_R420, {{-1, 0xb01cb}}}, 425 }; 426 427 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 428 429 430 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 431 radeonfb_match, radeonfb_attach, NULL, NULL); 432 433 static int 434 radeonfb_match(device_t parent, cfdata_t match, void *aux) 435 { 436 const struct pci_attach_args *pa = aux; 437 int i; 438 439 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 440 return 0; 441 442 for (i = 0; radeonfb_devices[i].devid; i++) { 443 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 444 return 100; /* high to defeat VGA/VESA */ 445 } 446 447 return 0; 448 } 449 450 static void 451 radeonfb_attach(device_t parent, device_t dev, void *aux) 452 { 453 struct radeonfb_softc *sc = device_private(dev); 454 const struct pci_attach_args *pa = aux; 455 const char *mptr; 456 bus_size_t bsz; 457 pcireg_t screg; 458 int i, j, fg, bg, ul, flags; 459 uint32_t v; 460 461 sc->sc_dev = dev; 462 sc->sc_id = pa->pa_id; 463 for (i = 0; radeonfb_devices[i].devid; i++) { 464 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 465 break; 466 } 467 468 pci_aprint_devinfo(pa, NULL); 469 470 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 471 472 KASSERT(radeonfb_devices[i].devid != 0); 473 sc->sc_pt = pa->pa_tag; 474 sc->sc_iot = pa->pa_iot; 475 sc->sc_pc = pa->pa_pc; 476 sc->sc_family = radeonfb_devices[i].family; 477 sc->sc_flags = radeonfb_devices[i].flags; 478 479 /* enable memory and IO access */ 480 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 481 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 482 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 483 484 /* 485 * Some flags are general to entire chip families, and rather 486 * than clutter up the table with them, we go ahead and set 487 * them here. 488 */ 489 switch (sc->sc_family) { 490 case RADEON_RS100: 491 case RADEON_RS200: 492 sc->sc_flags |= RFB_IGP | RFB_RV100; 493 break; 494 495 case RADEON_RV100: 496 case RADEON_RV200: 497 case RADEON_RV250: 498 case RADEON_RV280: 499 sc->sc_flags |= RFB_RV100; 500 break; 501 502 case RADEON_RS300: 503 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 504 break; 505 506 case RADEON_R300: 507 case RADEON_RV350: 508 case RADEON_R350: 509 case RADEON_RV380: 510 case RADEON_R420: 511 /* newer chips */ 512 sc->sc_flags |= RFB_R300; 513 break; 514 515 case RADEON_R100: 516 sc->sc_flags |= RFB_NCRTC2; 517 break; 518 } 519 520 if ((sc->sc_family == RADEON_RV200) || 521 (sc->sc_family == RADEON_RV250) || 522 (sc->sc_family == RADEON_RV280) || 523 (sc->sc_family == RADEON_RV350)) { 524 bool inverted = 0; 525 /* backlight level is linear */ 526 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 527 prop_dictionary_get_bool(device_properties(sc->sc_dev), 528 "backlight_level_reverted", &inverted); 529 if (inverted) { 530 DPRINTF(("nope, it's inverted\n")); 531 sc->sc_flags |= RFB_INV_BLIGHT; 532 } 533 } else 534 sc->sc_flags |= RFB_INV_BLIGHT; 535 536 /* 537 * XXX: to support true multihead, this must change. 538 */ 539 sc->sc_ndisplays = 1; 540 541 /* XXX: */ 542 if (!HAS_CRTC2(sc)) { 543 sc->sc_ndisplays = 1; 544 } 545 546 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 547 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 548 &sc->sc_regsz) != 0) { 549 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 550 goto error; 551 } 552 553 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 554 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 555 { 556 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 557 goto error; 558 } 559 sc->sc_romt = sc->sc_memt; 560 561 sc->sc_mapped = TRUE; 562 563 /* scratch register test... */ 564 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 565 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 566 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 567 goto error; 568 } 569 570 PRINTREG(RADEON_CRTC_EXT_CNTL); 571 PRINTREG(RADEON_CRTC_GEN_CNTL); 572 PRINTREG(RADEON_CRTC2_GEN_CNTL); 573 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 574 PRINTREG(RADEON_DAC_CNTL2); 575 PRINTREG(RADEON_FP_GEN_CNTL); 576 PRINTREG(RADEON_FP2_GEN_CNTL); 577 578 PRINTREG(RADEON_BIOS_4_SCRATCH); 579 PRINTREG(RADEON_FP_GEN_CNTL); 580 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 581 PRINTREG(RADEON_FP2_GEN_CNTL); 582 PRINTREG(RADEON_TMDS_CNTL); 583 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 584 PRINTREG(RADEON_TMDS_PLL_CNTL); 585 PRINTREG(RADEON_LVDS_GEN_CNTL); 586 PRINTREG(RADEON_FP_HORZ_STRETCH); 587 PRINTREG(RADEON_FP_VERT_STRETCH); 588 589 if (IS_RV100(sc)) 590 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 591 592 /* XXX 593 * according to xf86-video-radeon R3xx has this bit backwards 594 */ 595 if (IS_R300(sc)) { 596 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 597 0, 598 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 599 } else { 600 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 601 RADEON_TMDS_TRANSMITTER_PLLEN, 602 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 603 } 604 605 radeonfb_i2c_init(sc); 606 607 radeonfb_loadbios(sc, pa); 608 609 #ifdef RADEONFB_BIOS_INIT 610 if (radeonfb_bios_init(sc)) { 611 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 612 } 613 #endif 614 615 if (radeonfb_getclocks(sc)) { 616 aprint_error("%s: Unable to get reference clocks from BIOS\n", 617 XNAME(sc)); 618 goto error; 619 } 620 621 if (radeonfb_gettmds(sc)) { 622 aprint_error("%s: Unable to identify TMDS PLL settings\n", 623 XNAME(sc)); 624 goto error; 625 } 626 627 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 628 "minpll = %d, maxpll = %d\n", XNAME(sc), 629 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 630 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 631 632 radeonfb_getconnectors(sc); 633 634 radeonfb_set_fbloc(sc); 635 636 /* 64 MB should be enough -- more just wastes map entries */ 637 if (sc->sc_memsz > (64 << 20)) 638 sc->sc_memsz = (64 << 20); 639 640 for (i = 0; radeonfb_limits[i].size; i++) { 641 if (sc->sc_memsz >= radeonfb_limits[i].size) { 642 sc->sc_maxx = radeonfb_limits[i].maxx; 643 sc->sc_maxy = radeonfb_limits[i].maxy; 644 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 645 /* framebuffer offset, start at a 4K page */ 646 sc->sc_fboffset = sc->sc_memsz / 647 radeonfb_limits[i].maxdisp; 648 /* 649 * we use the fbsize to figure out where we can store 650 * things like cursor data. 651 */ 652 sc->sc_fbsize = 653 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 654 RADEON_STRIDEALIGN) * sc->sc_maxy, 655 4096); 656 break; 657 } 658 } 659 660 661 radeonfb_init_misc(sc); 662 663 /* program the DAC wirings */ 664 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 665 switch (sc->sc_ports[i].rp_dac_type) { 666 case RADEON_DAC_PRIMARY: 667 PATCH32(sc, RADEON_DAC_CNTL2, 668 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 669 ~RADEON_DAC2_DAC_CLK_SEL); 670 break; 671 case RADEON_DAC_TVDAC: 672 /* we always use the TVDAC to drive a secondary analog 673 * CRT for now. if we ever support TV-out this will 674 * have to change. 675 */ 676 SET32(sc, RADEON_DAC_CNTL2, 677 RADEON_DAC2_DAC2_CLK_SEL); 678 PATCH32(sc, RADEON_DISP_HW_DEBUG, 679 i ? 0 : RADEON_CRT2_DISP1_SEL, 680 ~RADEON_CRT2_DISP1_SEL); 681 /* we're using CRTC2 for the 2nd port */ 682 if (sc->sc_ports[i].rp_number == 1) { 683 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 684 RADEON_DISP_DAC2_SOURCE_CRTC2, 685 ~RADEON_DISP_DAC2_SOURCE_MASK); 686 } 687 688 break; 689 } 690 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 691 sc->sc_ports[i].rp_tmds_type)); 692 switch (sc->sc_ports[i].rp_tmds_type) { 693 case RADEON_TMDS_INT: 694 /* point FP0 at the CRTC this port uses */ 695 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 696 __func__, sc->sc_ports[i].rp_number)); 697 if (IS_R300(sc)) { 698 PATCH32(sc, RADEON_FP_GEN_CNTL, 699 sc->sc_ports[i].rp_number ? 700 R200_FP_SOURCE_SEL_CRTC2 : 701 R200_FP_SOURCE_SEL_CRTC1, 702 ~R200_FP_SOURCE_SEL_MASK); 703 } else { 704 PATCH32(sc, RADEON_FP_GEN_CNTL, 705 sc->sc_ports[i].rp_number ? 706 RADEON_FP_SEL_CRTC2 : 707 RADEON_FP_SEL_CRTC1, 708 ~RADEON_FP_SEL_MASK); 709 } 710 } 711 } 712 PRINTREG(RADEON_DAC_CNTL2); 713 PRINTREG(RADEON_DISP_HW_DEBUG); 714 715 /* other DAC programming */ 716 v = GET32(sc, RADEON_DAC_CNTL); 717 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 718 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 719 PUT32(sc, RADEON_DAC_CNTL, v); 720 PRINTREG(RADEON_DAC_CNTL); 721 722 /* XXX: this may need more investigation */ 723 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 724 PRINTREG(RADEON_TV_DAC_CNTL); 725 726 /* enable TMDS */ 727 SET32(sc, RADEON_FP_GEN_CNTL, 728 RADEON_FP_TMDS_EN | 729 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 730 RADEON_FP_CRTC_DONT_SHADOW_HEND); 731 /* 732 * XXX 733 * no idea why this is necessary - if I do not clear this bit on my 734 * iBook G4 the screen remains black, even though it's already clear. 735 * It needs to be set on my Sun XVR-100 for the DVI port to work 736 * TODO: 737 * see if this is still necessary now that CRTCs, DACs and outputs are 738 * getting wired up in a halfway sane way 739 */ 740 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 741 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 742 } else { 743 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 744 } 745 746 /* 747 * we use bus_space_map instead of pci_mapreg, because we don't 748 * need the full aperature space. no point in wasting virtual 749 * address space we don't intend to use, right? 750 */ 751 if ((sc->sc_memsz < (4096 * 1024)) || 752 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 753 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 754 (bsz < sc->sc_memsz)) { 755 sc->sc_memsz = 0; 756 aprint_error("%s: Bad frame buffer configuration\n", 757 XNAME(sc)); 758 goto error; 759 } 760 761 sc->sc_memt = pa->pa_memt; 762 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 763 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 764 sc->sc_memsz = 0; 765 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 766 goto error; 767 } 768 769 aprint_normal("%s: %d MB aperture at 0x%08x, " 770 "%d KB registers at 0x%08x\n", XNAME(sc), 771 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 772 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 773 774 /* setup default video mode from devprop (allows PROM override) */ 775 sc->sc_defaultmode = radeonfb_default_mode; 776 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 777 "videomode", &mptr)) { 778 779 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 780 sc->sc_defaultmode = sc->sc_modebuf; 781 } 782 783 /* initialize some basic display parameters */ 784 for (i = 0; i < sc->sc_ndisplays; i++) { 785 struct radeonfb_display *dp = &sc->sc_displays[i]; 786 struct rasops_info *ri; 787 long defattr; 788 struct wsemuldisplaydev_attach_args aa; 789 790 /* 791 * Figure out how many "displays" (desktops) we are going to 792 * support. If more than one, then each CRTC gets its own 793 * programming. 794 * 795 * XXX: this code needs to change to support mergedfb. 796 * XXX: would be nice to allow this to be overridden 797 */ 798 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 799 DPRINTF(("dual crtcs!\n")); 800 dp->rd_ncrtcs = 2; 801 dp->rd_crtcs[0].rc_port = 802 &sc->sc_ports[0]; 803 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 804 dp->rd_crtcs[1].rc_port = 805 &sc->sc_ports[1]; 806 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 807 } else { 808 dp->rd_ncrtcs = 1; 809 dp->rd_crtcs[0].rc_port = 810 &sc->sc_ports[i]; 811 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 812 } 813 814 dp->rd_softc = sc; 815 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 816 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 817 818 /* for text mode, we pick a resolution that won't 819 * require panning */ 820 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 821 822 aprint_normal("%s: display %d: " 823 "initial virtual resolution %dx%d at %d bpp\n", 824 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 825 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 826 sc->sc_fboffset >> 20); 827 /* now select the *video mode* that we will use */ 828 for (j = 0; j < dp->rd_ncrtcs; j++) { 829 const struct videomode *vmp; 830 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 831 dp->rd_virtx, dp->rd_virty); 832 833 /* 834 * virtual resolution should be at least as high as 835 * physical 836 */ 837 if (dp->rd_virtx < vmp->hdisplay || 838 dp->rd_virty < vmp->vdisplay) { 839 dp->rd_virtx = vmp->hdisplay; 840 dp->rd_virty = vmp->vdisplay; 841 } 842 843 dp->rd_crtcs[j].rc_videomode = *vmp; 844 printf("%s: port %d: physical %dx%d %dHz\n", 845 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 846 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 847 vmp->htotal), vmp->vtotal)); 848 } 849 850 /* N.B.: radeon wants 64-byte aligned stride */ 851 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 852 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 853 DPRINTF(("stride: %d\n", dp->rd_stride)); 854 855 dp->rd_offset = sc->sc_fboffset * i; 856 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 857 sc->sc_memh) + dp->rd_offset; 858 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 859 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 860 861 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 862 863 switch (dp->rd_bpp) { 864 case 8: 865 dp->rd_format = 2; 866 break; 867 case 32: 868 dp->rd_format = 6; 869 break; 870 default: 871 aprint_error("%s: bad depth %d\n", XNAME(sc), 872 dp->rd_bpp); 873 goto error; 874 } 875 876 DPRINTF(("init engine\n")); 877 /* XXX: this seems suspicious - per display engine 878 initialization? */ 879 radeonfb_engine_init(dp); 880 881 /* copy the template into place */ 882 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 883 dp->rd_wsscreens = dp->rd_wsscreens_storage; 884 885 /* and make up the list */ 886 dp->rd_wsscreenlist.nscreens = 1; 887 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 888 889 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 890 &radeonfb_accessops); 891 892 dp->rd_vd.init_screen = radeonfb_init_screen; 893 894 #ifdef RADEONFB_DEBUG 895 dp->rd_virty -= 200; 896 #endif 897 898 dp->rd_console = 0; 899 prop_dictionary_get_bool(device_properties(sc->sc_dev), 900 "is_console", &dp->rd_console); 901 902 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 903 904 905 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 906 dp->rd_console, &defattr); 907 908 ri = &dp->rd_vscreen.scr_ri; 909 910 /* clear the screen */ 911 rasops_unpack_attr(defattr, &fg, &bg, &ul); 912 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 913 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 914 dp->rd_bg); 915 916 dp->rd_wsscreens->textops = &ri->ri_ops; 917 dp->rd_wsscreens->capabilities = ri->ri_caps; 918 dp->rd_wsscreens->nrows = ri->ri_rows; 919 dp->rd_wsscreens->ncols = ri->ri_cols; 920 921 #ifdef SPLASHSCREEN 922 dp->rd_splash.si_depth = ri->ri_depth; 923 dp->rd_splash.si_bits = ri->ri_bits; 924 dp->rd_splash.si_hwbits = ri->ri_hwbits; 925 dp->rd_splash.si_width = ri->ri_width; 926 dp->rd_splash.si_height = ri->ri_height; 927 dp->rd_splash.si_stride = ri->ri_stride; 928 dp->rd_splash.si_fillrect = NULL; 929 #endif 930 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 931 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 932 dp->rd_gc.gc_rop = RADEON_ROP3_S; 933 dp->rd_gc.gc_blitcookie = dp; 934 /* 935 * use memory between framebuffer and cursor area as glyph 936 * cache, cap at 4096 lines 937 */ 938 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 939 min(4096, 940 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 941 dp->rd_virtx, 942 ri->ri_font->fontwidth, 943 ri->ri_font->fontheight, 944 defattr); 945 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 946 dp->rd_vd.show_screen_cb = glyphcache_adapt; 947 948 if (dp->rd_console) { 949 950 radeonfb_modeswitch(dp); 951 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 952 defattr); 953 #ifdef SPLASHSCREEN 954 if (splash_render(&dp->rd_splash, 955 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 956 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 957 else 958 #endif 959 vcons_replay_msgbuf(&dp->rd_vscreen); 960 } else { 961 962 /* 963 * since we're not the console we can postpone 964 * the rest until someone actually allocates a 965 * screen for us. but we do clear the screen 966 * at least. 967 */ 968 memset(ri->ri_bits, 0, 1024); 969 970 radeonfb_modeswitch(dp); 971 #ifdef SPLASHSCREEN 972 if (splash_render(&dp->rd_splash, 973 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 974 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 975 #endif 976 } 977 978 aa.console = dp->rd_console; 979 aa.scrdata = &dp->rd_wsscreenlist; 980 aa.accessops = &radeonfb_accessops; 981 aa.accesscookie = &dp->rd_vd; 982 983 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 984 985 radeonfb_blank(dp, 0); 986 987 /* Initialise delayed lvds operations for backlight. */ 988 callout_init(&dp->rd_bl_lvds_co, 0); 989 callout_setfunc(&dp->rd_bl_lvds_co, 990 radeonfb_lvds_callout, dp); 991 dp->rd_bl_on = 1; 992 dp->rd_bl_level = radeonfb_get_backlight(dp); 993 radeonfb_set_backlight(dp, dp->rd_bl_level); 994 } 995 996 for (i = 0; i < RADEON_NDISPLAYS; i++) 997 radeonfb_init_palette(&sc->sc_displays[i]); 998 999 if (HAS_CRTC2(sc)) { 1000 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1001 } 1002 1003 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1004 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1005 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1006 radeonfb_brightness_up, TRUE); 1007 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1008 radeonfb_brightness_down, TRUE); 1009 1010 /* 1011 * if we attach a DRM we need to unmap registers in 1012 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1013 * screen blanking we only do it if needed 1014 */ 1015 sc->sc_needs_unmap = 1016 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1017 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1018 1019 PRINTREG(RADEON_CRTC_EXT_CNTL); 1020 PRINTREG(RADEON_CRTC_GEN_CNTL); 1021 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1022 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1023 PRINTREG(RADEON_DAC_CNTL2); 1024 PRINTREG(RADEON_FP_GEN_CNTL); 1025 PRINTREG(RADEON_FP2_GEN_CNTL); 1026 1027 return; 1028 1029 error: 1030 if (sc->sc_biossz) 1031 free(sc->sc_bios, M_DEVBUF); 1032 1033 if (sc->sc_regsz) 1034 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1035 1036 if (sc->sc_memsz) 1037 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1038 } 1039 1040 static void 1041 radeonfb_map(struct radeonfb_softc *sc) 1042 { 1043 if (!sc->sc_mapped) { 1044 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1045 &sc->sc_regh) != 0) { 1046 aprint_error_dev(sc->sc_dev, 1047 "unable to map registers!\n"); 1048 return; 1049 } 1050 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1051 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1052 sc->sc_memsz = 0; 1053 aprint_error_dev(sc->sc_dev, 1054 "Unable to map frame buffer\n"); 1055 return; 1056 } 1057 sc->sc_mapped = TRUE; 1058 } 1059 } 1060 1061 static void 1062 radeonfb_unmap(struct radeonfb_softc *sc) 1063 { 1064 if (!sc->sc_needs_unmap) 1065 return; 1066 1067 if (sc->sc_mapped) { 1068 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1069 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1070 sc->sc_mapped = FALSE; 1071 } 1072 } 1073 1074 static int 1075 radeonfb_drm_print(void *aux, const char *pnp) 1076 { 1077 if (pnp) 1078 aprint_normal("drm at %s", pnp); 1079 return (UNCONF); 1080 } 1081 1082 int 1083 radeonfb_ioctl(void *v, void *vs, 1084 unsigned long cmd, void *d, int flag, struct lwp *l) 1085 { 1086 struct vcons_data *vd; 1087 struct radeonfb_display *dp; 1088 struct radeonfb_softc *sc; 1089 struct wsdisplay_param *param; 1090 struct vcons_screen *ms; 1091 1092 vd = (struct vcons_data *)v; 1093 ms = vd->active; 1094 dp = (struct radeonfb_display *)vd->cookie; 1095 sc = dp->rd_softc; 1096 1097 /* can't do these without registers being mapped */ 1098 if (!sc->sc_mapped) { 1099 switch (cmd) { 1100 case WSDISPLAYIO_GVIDEO: 1101 case WSDISPLAYIO_SVIDEO: 1102 case WSDISPLAYIO_GETCMAP: 1103 case WSDISPLAYIO_PUTCMAP: 1104 case WSDISPLAYIO_SCURSOR: 1105 case WSDISPLAYIO_GCURPOS: 1106 case WSDISPLAYIO_SCURPOS: 1107 case WSDISPLAYIO_SETPARAM: 1108 return EINVAL; 1109 } 1110 } 1111 1112 switch (cmd) { 1113 case WSDISPLAYIO_GTYPE: 1114 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1115 return 0; 1116 1117 case WSDISPLAYIO_GINFO: 1118 if (vd->active != NULL) { 1119 struct wsdisplay_fbinfo *fb; 1120 fb = (struct wsdisplay_fbinfo *)d; 1121 fb->width = dp->rd_virtx; 1122 fb->height = dp->rd_virty; 1123 fb->depth = dp->rd_bpp; 1124 fb->cmsize = 256; 1125 return 0; 1126 } else 1127 return ENODEV; 1128 case WSDISPLAYIO_GVIDEO: 1129 if (radeonfb_isblank(dp)) 1130 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1131 else 1132 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1133 return 0; 1134 1135 case WSDISPLAYIO_SVIDEO: 1136 radeonfb_blank(dp, 1137 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1138 radeonfb_switch_backlight(dp, 1139 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1140 return 0; 1141 1142 case WSDISPLAYIO_GETCMAP: 1143 if (dp->rd_bpp == 8) 1144 return radeonfb_getcmap(dp, 1145 (struct wsdisplay_cmap *)d); 1146 return EINVAL; 1147 1148 case WSDISPLAYIO_PUTCMAP: 1149 if (dp->rd_bpp == 8) 1150 return radeonfb_putcmap(dp, 1151 (struct wsdisplay_cmap *)d); 1152 return EINVAL; 1153 1154 case WSDISPLAYIO_LINEBYTES: 1155 *(unsigned *)d = dp->rd_stride; 1156 return 0; 1157 1158 case WSDISPLAYIO_SMODE: 1159 if (*(int *)d != dp->rd_wsmode) { 1160 dp->rd_wsmode = *(int *)d; 1161 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1162 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1163 radeonfb_map(sc); 1164 1165 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1166 (dp->rd_vd.active)) { 1167 radeonfb_engine_init(dp); 1168 glyphcache_wipe(&dp->rd_gc); 1169 radeonfb_init_palette(dp); 1170 radeonfb_modeswitch(dp); 1171 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1172 dp->rd_virty, dp->rd_bg); 1173 vcons_redraw_screen(dp->rd_vd.active); 1174 } 1175 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1176 radeonfb_unmap(sc); 1177 } 1178 return 0; 1179 1180 case WSDISPLAYIO_GCURMAX: 1181 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1182 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1183 return 0; 1184 1185 case WSDISPLAYIO_SCURSOR: 1186 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1187 1188 case WSDISPLAYIO_GCURSOR: 1189 return EPASSTHROUGH; 1190 1191 case WSDISPLAYIO_GCURPOS: 1192 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1193 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1194 return 0; 1195 1196 case WSDISPLAYIO_SCURPOS: 1197 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1198 1199 case WSDISPLAYIO_SSPLASH: 1200 #if defined(SPLASHSCREEN) 1201 if (*(int *)d == 1) { 1202 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1203 splash_render(&dp->rd_splash, 1204 SPLASH_F_CENTER|SPLASH_F_FILL); 1205 } else 1206 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1207 return 0; 1208 #else 1209 return ENODEV; 1210 #endif 1211 case WSDISPLAYIO_GETPARAM: 1212 param = (struct wsdisplay_param *)d; 1213 switch (param->param) { 1214 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1215 param->min = 0; 1216 param->max = 255; 1217 param->curval = dp->rd_bl_level; 1218 return 0; 1219 case WSDISPLAYIO_PARAM_BACKLIGHT: 1220 param->min = 0; 1221 param->max = RADEONFB_BACKLIGHT_MAX; 1222 param->curval = dp->rd_bl_on; 1223 return 0; 1224 } 1225 return EPASSTHROUGH; 1226 1227 case WSDISPLAYIO_SETPARAM: 1228 param = (struct wsdisplay_param *)d; 1229 switch (param->param) { 1230 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1231 radeonfb_set_backlight(dp, param->curval); 1232 return 0; 1233 case WSDISPLAYIO_PARAM_BACKLIGHT: 1234 radeonfb_switch_backlight(dp, param->curval); 1235 return 0; 1236 } 1237 return EPASSTHROUGH; 1238 1239 /* PCI config read/write passthrough. */ 1240 case PCI_IOC_CFGREAD: 1241 case PCI_IOC_CFGWRITE: 1242 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1243 1244 case WSDISPLAYIO_GET_BUSID: 1245 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1246 sc->sc_pt, d); 1247 1248 case WSDISPLAYIO_GET_EDID: { 1249 struct wsdisplayio_edid_info *ei = d; 1250 return wsdisplayio_get_edid(sc->sc_dev, ei); 1251 } 1252 1253 case WSDISPLAYIO_GET_FBINFO: { 1254 struct wsdisplayio_fbinfo *fbi = d; 1255 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1256 } 1257 1258 default: 1259 return EPASSTHROUGH; 1260 } 1261 } 1262 1263 paddr_t 1264 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1265 { 1266 struct vcons_data *vd; 1267 struct radeonfb_display *dp; 1268 struct radeonfb_softc *sc; 1269 paddr_t pa; 1270 1271 vd = (struct vcons_data *)v; 1272 dp = (struct radeonfb_display *)vd->cookie; 1273 sc = dp->rd_softc; 1274 1275 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1276 pa = bus_space_mmap(sc->sc_memt, 1277 sc->sc_memaddr + dp->rd_offset + offset, 0, 1278 prot, BUS_SPACE_MAP_LINEAR); 1279 return pa; 1280 } 1281 1282 /* 1283 * restrict all other mappings to processes with superuser privileges 1284 * or the kernel itself 1285 */ 1286 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1287 NULL, NULL, NULL, NULL) != 0) { 1288 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1289 return -1; 1290 } 1291 1292 if ((offset >= sc->sc_regaddr) && 1293 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1294 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1295 BUS_SPACE_MAP_LINEAR); 1296 } 1297 1298 if ((offset >= sc->sc_memaddr) && 1299 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1300 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1301 BUS_SPACE_MAP_LINEAR); 1302 } 1303 1304 if ((offset >= sc->sc_romaddr) && 1305 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1306 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1307 BUS_SPACE_MAP_LINEAR); 1308 } 1309 1310 #ifdef PCI_MAGIC_IO_RANGE 1311 /* allow mapping of IO space */ 1312 if ((offset >= PCI_MAGIC_IO_RANGE) && 1313 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1314 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1315 0, prot, 0); 1316 return pa; 1317 } 1318 #endif /* PCI_MAGIC_IO_RANGE */ 1319 1320 return -1; 1321 } 1322 1323 static void 1324 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1325 { 1326 bus_space_tag_t romt; 1327 bus_space_handle_t romh, biosh; 1328 bus_size_t romsz; 1329 bus_addr_t ptr; 1330 1331 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1332 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1333 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1334 return; 1335 } 1336 1337 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1338 &sc->sc_biossz); 1339 if (sc->sc_biossz == 0) { 1340 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1341 return; 1342 } 1343 1344 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1345 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1346 1347 /* unmap the PCI expansion rom */ 1348 bus_space_unmap(romt, romh, romsz); 1349 1350 /* turn off rom decoder now */ 1351 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1352 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1353 ~PCI_MAPREG_ROM_ENABLE); 1354 1355 ptr = GETBIOS16(sc, 0x48); 1356 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1357 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1358 sc->sc_flags |= RFB_ATOM; 1359 } 1360 1361 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1362 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1363 } 1364 1365 1366 uint32_t 1367 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1368 { 1369 1370 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1371 } 1372 1373 void 1374 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1375 { 1376 1377 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1378 } 1379 1380 void 1381 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1382 { 1383 1384 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1385 } 1386 1387 void 1388 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1389 uint32_t andmask, uint32_t ormask) 1390 { 1391 int s; 1392 uint32_t val; 1393 1394 s = splhigh(); 1395 val = radeonfb_get32(sc, reg); 1396 val = (val & andmask) | ormask; 1397 radeonfb_put32(sc, reg, val); 1398 splx(s); 1399 } 1400 1401 uint32_t 1402 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1403 { 1404 int s; 1405 uint32_t val; 1406 1407 s = splhigh(); 1408 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1409 val = radeonfb_get32(sc, RADEON_MM_DATA); 1410 splx(s); 1411 1412 return (val); 1413 } 1414 1415 void 1416 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1417 { 1418 int s; 1419 1420 s = splhigh(); 1421 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1422 radeonfb_put32(sc, RADEON_MM_DATA, val); 1423 splx(s); 1424 } 1425 1426 void 1427 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1428 uint32_t andmask, uint32_t ormask) 1429 { 1430 int s; 1431 uint32_t val; 1432 1433 s = splhigh(); 1434 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1435 val = radeonfb_get32(sc, RADEON_MM_DATA); 1436 val = (val & andmask) | ormask; 1437 radeonfb_put32(sc, RADEON_MM_DATA, val); 1438 splx(s); 1439 } 1440 1441 uint32_t 1442 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1443 { 1444 int s; 1445 uint32_t val; 1446 1447 s = splhigh(); 1448 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1449 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1450 if (HAS_R300CG(sc)) 1451 radeonfb_r300cg_workaround(sc); 1452 splx(s); 1453 1454 return (val); 1455 } 1456 1457 void 1458 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1459 { 1460 int s; 1461 1462 s = splhigh(); 1463 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1464 RADEON_PLL_WR_EN); 1465 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1466 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1467 splx(s); 1468 } 1469 1470 void 1471 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1472 uint32_t andmask, uint32_t ormask) 1473 { 1474 int s; 1475 uint32_t val; 1476 1477 s = splhigh(); 1478 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1479 RADEON_PLL_WR_EN); 1480 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1481 val = (val & andmask) | ormask; 1482 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1483 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1484 splx(s); 1485 } 1486 1487 int 1488 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1489 { 1490 uint32_t saved; 1491 1492 saved = GET32(sc, reg); 1493 PUT32(sc, reg, v); 1494 if (GET32(sc, reg) != v) { 1495 return -1; 1496 } 1497 PUT32(sc, reg, saved); 1498 return 0; 1499 } 1500 1501 uintmax_t 1502 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1503 uintmax_t defval) 1504 { 1505 prop_number_t pn; 1506 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1507 if (pn == NULL) { 1508 return defval; 1509 } 1510 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1511 return (prop_number_integer_value(pn)); 1512 } 1513 1514 int 1515 radeonfb_getclocks(struct radeonfb_softc *sc) 1516 { 1517 bus_addr_t ptr; 1518 int refclk = 0; 1519 int refdiv = 0; 1520 int minpll = 0; 1521 int maxpll = 0; 1522 1523 /* load initial property values if port/board provides them */ 1524 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1525 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1526 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1527 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1528 1529 PRINTPLL(RADEON_PPLL_REF_DIV); 1530 PRINTPLL(RADEON_PPLL_DIV_0); 1531 PRINTPLL(RADEON_PPLL_DIV_1); 1532 PRINTPLL(RADEON_PPLL_DIV_2); 1533 PRINTPLL(RADEON_PPLL_DIV_3); 1534 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1535 PRINTPLL(RADEON_P2PLL_REF_DIV); 1536 PRINTPLL(RADEON_P2PLL_DIV_0); 1537 1538 if (refclk && refdiv && minpll && maxpll) 1539 goto dontprobe; 1540 1541 if (!sc->sc_biossz) { 1542 /* no BIOS */ 1543 aprint_verbose("%s: No video BIOS, using default clocks\n", 1544 XNAME(sc)); 1545 if (IS_IGP(sc)) 1546 refclk = refclk ? refclk : 1432; 1547 else 1548 refclk = refclk ? refclk : 2700; 1549 refdiv = refdiv ? refdiv : 12; 1550 minpll = minpll ? minpll : 12500; 1551 /* XXX 1552 * Need to check if the firmware or something programmed a 1553 * higher value than this, and if so, bump it. 1554 * The RV280 in my iBook is unhappy if the PLL input is less 1555 * than 360MHz 1556 */ 1557 maxpll = maxpll ? maxpll : 40000/*35000*/; 1558 } else if (IS_ATOM(sc)) { 1559 /* ATOM BIOS */ 1560 ptr = GETBIOS16(sc, 0x48); 1561 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1562 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1563 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1564 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1565 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1566 /* 1567 * ATOM BIOS doesn't supply a reference divider, so we 1568 * have to probe for it. 1569 */ 1570 if (refdiv < 2) 1571 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1572 RADEON_PPLL_REF_DIV_MASK; 1573 /* 1574 * if probe is zero, just assume one that should work 1575 * for most parts 1576 */ 1577 if (refdiv < 2) 1578 refdiv = 12; 1579 1580 } else { 1581 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1582 /* Legacy BIOS */ 1583 ptr = GETBIOS16(sc, 0x48); 1584 ptr = GETBIOS16(sc, ptr + 0x30); 1585 if (IS_R300(sc)) { 1586 refdiv = refdiv ? refdiv : 1587 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1588 R300_PPLL_REF_DIV_ACC_SHIFT; 1589 } else { 1590 refdiv = refdiv ? refdiv : 1591 tmp & RADEON_PPLL_REF_DIV_MASK; 1592 } 1593 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1594 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1595 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1596 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1597 } 1598 1599 1600 dontprobe: 1601 sc->sc_refclk = refclk * 10; 1602 sc->sc_refdiv = refdiv; 1603 sc->sc_minpll = minpll * 10; 1604 sc->sc_maxpll = maxpll * 10; 1605 return 0; 1606 } 1607 1608 int 1609 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1610 uint32_t *postdivbit, uint32_t *feedbackdiv) 1611 { 1612 int i; 1613 uint32_t outfreq; 1614 int div; 1615 1616 DPRINTF(("dot clock: %u\n", dotclock)); 1617 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1618 outfreq = div * dotclock; 1619 if ((outfreq >= sc->sc_minpll) && 1620 (outfreq <= sc->sc_maxpll)) { 1621 DPRINTF(("outfreq: %u\n", outfreq)); 1622 *postdivbit = 1623 ((uint32_t)radeonfb_dividers[i].mask << 16); 1624 DPRINTF(("post divider: %d (mask %x)\n", div, 1625 *postdivbit)); 1626 break; 1627 } 1628 } 1629 1630 if (div == 0) 1631 return 1; 1632 1633 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1634 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1635 return 0; 1636 } 1637 1638 #if 0 1639 #ifdef RADEONFB_DEBUG 1640 static void 1641 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1642 { 1643 char asc[17]; 1644 unsigned ptr = (unsigned)buffer; 1645 char *start = (char *)(ptr & ~0xf); 1646 char *end = (char *)(ptr + size); 1647 1648 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1649 1650 if (pfx == NULL) { 1651 pfx = ""; 1652 } 1653 1654 while (start < end) { 1655 unsigned offset = (unsigned)start & 0xf; 1656 if (offset == 0) { 1657 printf("%s%x: ", pfx, (unsigned)start); 1658 } 1659 if (((unsigned)start < ptr) || 1660 ((unsigned)start >= (ptr + size))) { 1661 printf(" "); 1662 asc[offset] = ' '; 1663 } else { 1664 printf("%02x", *(unsigned char *)start); 1665 if ((*start >= ' ') && (*start <= '~')) { 1666 asc[offset] = *start; 1667 } else { 1668 asc[offset] = '.'; 1669 } 1670 } 1671 asc[offset + 1] = 0; 1672 if (offset % 2) { 1673 printf(" "); 1674 } 1675 if (offset == 15) { 1676 printf(" %s\n", asc); 1677 } 1678 start++; 1679 } 1680 } 1681 #endif 1682 #endif 1683 1684 int 1685 radeonfb_getconnectors(struct radeonfb_softc *sc) 1686 { 1687 int i; 1688 int found = 0; 1689 1690 for (i = 0; i < 2; i++) { 1691 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1692 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1693 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1694 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1695 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1696 } 1697 1698 /* 1699 * This logic is borrowed from Xorg's radeon driver. 1700 */ 1701 if (!sc->sc_biossz) 1702 goto nobios; 1703 1704 if (IS_ATOM(sc)) { 1705 /* not done yet */ 1706 } else { 1707 uint16_t ptr; 1708 int port = 0; 1709 1710 ptr = GETBIOS16(sc, 0x48); 1711 ptr = GETBIOS16(sc, ptr + 0x50); 1712 for (i = 1; i < 4; i++) { 1713 uint16_t entry; 1714 uint8_t conn, ddc, dac, tmds; 1715 1716 /* 1717 * Parse the connector table. From reading the code, 1718 * it appears to made up of 16-bit entries for each 1719 * connector. The 16-bits are defined as: 1720 * 1721 * bits 12-15 - connector type (0 == end of table) 1722 * bits 8-11 - DDC type 1723 * bits 5-7 - ??? 1724 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1725 * bits 1-3 - ??? 1726 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1727 */ 1728 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1729 break; 1730 entry = GETBIOS16(sc, ptr + i * 2); 1731 1732 conn = (entry >> 12) & 0xf; 1733 ddc = (entry >> 8) & 0xf; 1734 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1735 RADEON_DAC_PRIMARY; 1736 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1737 RADEON_TMDS_INT; 1738 1739 if (conn == RADEON_CONN_NONE) 1740 continue; /* no connector */ 1741 1742 if ((found > 0) && 1743 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1744 /* duplicate entry for same connector */ 1745 continue; 1746 } 1747 1748 /* internal DDC_DVI port gets priority */ 1749 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1750 port = 0; 1751 else 1752 port = 1; 1753 1754 sc->sc_ports[port].rp_ddc_type = 1755 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1756 sc->sc_ports[port].rp_dac_type = dac; 1757 sc->sc_ports[port].rp_conn_type = 1758 min(conn, RADEON_CONN_UNSUPPORTED) ; 1759 1760 sc->sc_ports[port].rp_tmds_type = tmds; 1761 1762 if ((conn != RADEON_CONN_DVI_I) && 1763 (conn != RADEON_CONN_DVI_D) && 1764 (tmds == RADEON_TMDS_INT)) 1765 sc->sc_ports[port].rp_tmds_type = 1766 RADEON_TMDS_UNKNOWN; 1767 sc->sc_ports[port].rp_number = i - 1; 1768 1769 found += (port + 1); 1770 } 1771 } 1772 1773 nobios: 1774 if (!found) { 1775 bool dvi_ext = FALSE, dvi_int = FALSE; 1776 DPRINTF(("No connector info in BIOS!\n")); 1777 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1778 "dvi-internal", &dvi_int); 1779 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1780 "dvi-external", &dvi_ext); 1781 if (dvi_ext) { 1782 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1783 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1784 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1785 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1786 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; 1787 sc->sc_ports[0].rp_number = 1; 1788 } else if (dvi_int) { 1789 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1790 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1791 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1792 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1793 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1794 sc->sc_ports[0].rp_number = 1; 1795 } else if IS_MOBILITY(sc) { 1796 /* default, port 0 = internal TMDS, port 1 = CRT */ 1797 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1798 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1799 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1800 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1801 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1802 sc->sc_ports[0].rp_number = 0; 1803 1804 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1805 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1806 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1807 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1808 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1809 sc->sc_ports[1].rp_number = 1; 1810 } else { 1811 /* default, port 0 = DVI, port 1 = CRT */ 1812 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1813 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1814 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1815 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1816 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1817 sc->sc_ports[0].rp_number = 1; 1818 1819 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1820 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1821 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1822 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1823 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1824 sc->sc_ports[1].rp_number = 0; 1825 } 1826 } 1827 1828 /* 1829 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1830 * these chips should use TVDAC for the VGA port. 1831 */ 1832 if (HAS_SDAC(sc)) { 1833 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1834 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1835 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1836 } else { 1837 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1838 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1839 } 1840 } else if (!HAS_CRTC2(sc)) { 1841 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1842 } 1843 1844 for (i = 0; i < 2; i++) { 1845 char edid[128]; 1846 uint8_t ddc; 1847 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1848 prop_data_t edid_data; 1849 1850 DPRINTF(("Port #%d:\n", i)); 1851 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1852 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1853 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1854 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1855 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1856 1857 sc->sc_ports[i].rp_edid_valid = 0; 1858 /* first look for static EDID data */ 1859 if ((edid_data = prop_dictionary_get(device_properties( 1860 sc->sc_dev), "EDID")) != NULL) { 1861 1862 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1863 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1864 if (edid_parse(edid, eip) == 0) { 1865 1866 sc->sc_ports[i].rp_edid_valid = 1; 1867 } 1868 } 1869 /* if we didn't find any we'll try to talk to the monitor */ 1870 if (sc->sc_ports[i].rp_edid_valid != 1) { 1871 1872 ddc = sc->sc_ports[i].rp_ddc_type; 1873 if (ddc != RADEON_DDC_NONE) { 1874 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1875 == 0) && (edid_parse(edid, eip) == 0)) { 1876 1877 sc->sc_ports[i].rp_edid_valid = 1; 1878 #ifdef RADEONFB_DEBUG 1879 edid_print(eip); 1880 #endif 1881 } 1882 } 1883 } 1884 } 1885 1886 return found; 1887 } 1888 1889 int 1890 radeonfb_gettmds(struct radeonfb_softc *sc) 1891 { 1892 int i; 1893 1894 if (!sc->sc_biossz) { 1895 goto nobios; 1896 } 1897 1898 if (IS_ATOM(sc)) { 1899 /* XXX: not done yet */ 1900 } else { 1901 uint16_t ptr; 1902 int n; 1903 1904 ptr = GETBIOS16(sc, 0x48); 1905 ptr = GETBIOS16(sc, ptr + 0x34); 1906 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1907 if (GETBIOS8(sc, ptr) == 3) { 1908 /* revision three table */ 1909 n = GETBIOS8(sc, ptr + 5) + 1; 1910 n = min(n, 4); 1911 1912 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1913 for (i = 0; i < n; i++) { 1914 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1915 ptr + i * 10 + 8); 1916 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1917 ptr + i * 10 + 0x10); 1918 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1919 sc->sc_tmds_pll[i].rtp_freq, 1920 sc->sc_tmds_pll[i].rtp_pll)); 1921 } 1922 return 0; 1923 } 1924 } 1925 1926 nobios: 1927 DPRINTF(("no suitable DFP table present\n")); 1928 for (i = 0; 1929 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1930 i++) { 1931 int j; 1932 1933 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1934 continue; 1935 1936 for (j = 0; j < 4; j++) { 1937 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1938 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1939 sc->sc_tmds_pll[j].rtp_freq, 1940 sc->sc_tmds_pll[j].rtp_pll)); 1941 } 1942 return 0; 1943 } 1944 1945 return -1; 1946 } 1947 1948 const struct videomode * 1949 radeonfb_modelookup(const char *name) 1950 { 1951 int i; 1952 1953 for (i = 0; i < videomode_count; i++) 1954 if (!strcmp(name, videomode_list[i].name)) 1955 return &videomode_list[i]; 1956 1957 return NULL; 1958 } 1959 1960 void 1961 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 1962 { 1963 if (crtc) { 1964 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1965 RADEON_P2PLL_ATOMIC_UPDATE_R); 1966 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 1967 } else { 1968 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1969 RADEON_PPLL_ATOMIC_UPDATE_R); 1970 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 1971 } 1972 } 1973 1974 void 1975 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 1976 { 1977 int i; 1978 1979 for (i = 10000; i; i--) { 1980 if (crtc) { 1981 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 1982 RADEON_P2PLL_ATOMIC_UPDATE_R) 1983 break; 1984 } else { 1985 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 1986 RADEON_PPLL_ATOMIC_UPDATE_R) 1987 break; 1988 } 1989 } 1990 } 1991 1992 void 1993 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc) 1994 { 1995 uint32_t pbit = 0; 1996 uint32_t feed = 0; 1997 uint32_t data, refdiv, div0; 1998 1999 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed); 2000 2001 if (crtc == 0) { 2002 2003 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2004 if (IS_R300(sc)) { 2005 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2006 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2007 } else { 2008 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2009 sc->sc_refdiv; 2010 } 2011 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2012 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2013 RADEON_PPLL_POST3_DIV_MASK); 2014 div0 |= pbit; 2015 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2016 2017 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2018 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2019 /* 2020 * nothing to do here, the PLL is already where we 2021 * want it 2022 */ 2023 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2024 ~RADEON_PLL_DIV_SEL); 2025 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2026 return; 2027 } 2028 2029 /* alright, we do need to reprogram stuff */ 2030 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2031 RADEON_VCLK_SRC_SEL_CPUCLK, 2032 ~RADEON_VCLK_SRC_SEL_MASK); 2033 2034 /* put vclk into reset, use atomic updates */ 2035 SETPLL(sc, RADEON_PPLL_CNTL, 2036 RADEON_PPLL_REFCLK_SEL | 2037 RADEON_PPLL_FBCLK_SEL | 2038 RADEON_PPLL_RESET | 2039 RADEON_PPLL_ATOMIC_UPDATE_EN | 2040 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2041 2042 /* select clock 0 */ 2043 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2044 ~RADEON_PLL_DIV_SEL); 2045 2046 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2047 2048 /* xf86-video-radeon does this, not sure why */ 2049 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2050 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2051 2052 /* use the atomic update */ 2053 radeonfb_pllwriteupdate(sc, crtc); 2054 2055 /* and wait for it to complete */ 2056 radeonfb_pllwaitatomicread(sc, crtc); 2057 2058 /* program HTOTAL (why?) */ 2059 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2060 2061 /* drop reset */ 2062 CLRPLL(sc, RADEON_PPLL_CNTL, 2063 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2064 RADEON_PPLL_ATOMIC_UPDATE_EN | 2065 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2066 2067 PRINTPLL(RADEON_PPLL_CNTL); 2068 PRINTPLL(RADEON_PPLL_REF_DIV); 2069 PRINTPLL(RADEON_PPLL_DIV_3); 2070 2071 /* give clock time to lock */ 2072 delay(50000); 2073 2074 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2075 RADEON_VCLK_SRC_SEL_PPLLCLK, 2076 ~RADEON_VCLK_SRC_SEL_MASK); 2077 2078 } else { 2079 2080 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2081 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2082 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2083 2084 /* put vclk into reset, use atomic updates */ 2085 SETPLL(sc, RADEON_P2PLL_CNTL, 2086 RADEON_P2PLL_RESET | 2087 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2088 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2089 2090 /* program reference divider */ 2091 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2092 ~RADEON_P2PLL_REF_DIV_MASK); 2093 2094 /* program feedback and post dividers */ 2095 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2096 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2097 RADEON_P2PLL_POST0_DIV_MASK); 2098 data |= pbit; 2099 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2100 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2101 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2102 2103 PRINTPLL(RADEON_P2PLL_REF_DIV); 2104 PRINTPLL(RADEON_P2PLL_DIV_0); 2105 2106 /* use the atomic update */ 2107 radeonfb_pllwriteupdate(sc, crtc); 2108 2109 /* and wait for it to complete */ 2110 radeonfb_pllwaitatomicread(sc, crtc); 2111 2112 /* program HTOTAL (why?) */ 2113 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2114 2115 /* drop reset */ 2116 CLRPLL(sc, RADEON_P2PLL_CNTL, 2117 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2118 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2119 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2120 2121 /* allow time for clock to lock */ 2122 delay(50000); 2123 2124 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2125 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2126 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2127 } 2128 PRINTREG(RADEON_CRTC_MORE_CNTL); 2129 } 2130 2131 void 2132 radeonfb_modeswitch(struct radeonfb_display *dp) 2133 { 2134 struct radeonfb_softc *sc = dp->rd_softc; 2135 int i; 2136 2137 /* blank the display while we switch modes */ 2138 radeonfb_blank(dp, 1); 2139 2140 #if 0 2141 SET32(sc, RADEON_CRTC_EXT_CNTL, 2142 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2143 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2144 #endif 2145 2146 /* these registers might get in the way... */ 2147 PUT32(sc, RADEON_OVR_CLR, 0); 2148 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2149 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2150 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2151 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2152 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2153 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2154 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2155 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2156 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2157 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2158 2159 for (i = 0; i < dp->rd_ncrtcs; i++) 2160 radeonfb_setcrtc(dp, i); 2161 2162 /* activate the display */ 2163 radeonfb_blank(dp, 0); 2164 } 2165 2166 void 2167 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2168 { 2169 int crtc; 2170 struct videomode *mode; 2171 struct radeonfb_softc *sc; 2172 struct radeonfb_crtc *cp; 2173 uint32_t v; 2174 uint32_t gencntl; 2175 uint32_t htotaldisp; 2176 uint32_t hsyncstrt; 2177 uint32_t vtotaldisp; 2178 uint32_t vsyncstrt; 2179 uint32_t fphsyncstrt; 2180 uint32_t fpvsyncstrt; 2181 uint32_t fphtotaldisp; 2182 uint32_t fpvtotaldisp; 2183 uint32_t pitch; 2184 2185 sc = dp->rd_softc; 2186 cp = &dp->rd_crtcs[index]; 2187 crtc = cp->rc_number; 2188 mode = &cp->rc_videomode; 2189 2190 #if 1 2191 pitch = dp->rd_stride / dp->rd_bpp; 2192 #else 2193 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2194 (sc->sc_maxbpp * 8)); 2195 #endif 2196 switch (crtc) { 2197 case 0: 2198 gencntl = RADEON_CRTC_GEN_CNTL; 2199 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2200 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2201 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2202 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2203 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2204 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2205 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2206 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2207 break; 2208 case 1: 2209 gencntl = RADEON_CRTC2_GEN_CNTL; 2210 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2211 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2212 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2213 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2214 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2215 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2216 fpvtotaldisp = RADEON_FP_CRTC2_V_TOTAL_DISP; 2217 fphtotaldisp = RADEON_FP_CRTC2_H_TOTAL_DISP; 2218 break; 2219 default: 2220 panic("Bad CRTC!"); 2221 break; 2222 } 2223 2224 /* 2225 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2226 */ 2227 /* only bother with 32bpp and 8bpp */ 2228 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2229 2230 if (crtc == 1) { 2231 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2232 } else { 2233 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2234 } 2235 2236 if (mode->flags & VID_DBLSCAN) 2237 v |= RADEON_CRTC2_DBL_SCAN_EN; 2238 2239 if (mode->flags & VID_INTERLACE) 2240 v |= RADEON_CRTC2_INTERLACE_EN; 2241 2242 if (mode->flags & VID_CSYNC) { 2243 v |= RADEON_CRTC2_CSYNC_EN; 2244 if (crtc == 1) 2245 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2246 } 2247 2248 PUT32(sc, gencntl, v); 2249 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2250 2251 /* 2252 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2253 */ 2254 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2255 if (crtc == 0) { 2256 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2257 RADEON_CRTC_DISPLAY_DIS); 2258 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2259 if (mode->flags & VID_CSYNC) 2260 v |= RADEON_CRTC_VSYNC_TRISTAT; 2261 } 2262 /* unconditional turn on CRT, in case first CRTC is DFP */ 2263 v |= RADEON_CRTC_CRT_ON; 2264 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2265 PRINTREG(RADEON_CRTC_EXT_CNTL); 2266 2267 /* 2268 * H_TOTAL_DISP 2269 */ 2270 v = ((mode->hdisplay / 8) - 1) << 16; 2271 v |= (mode->htotal / 8) - 1; 2272 PUT32(sc, htotaldisp, v); 2273 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2274 PUT32(sc, fphtotaldisp, v); 2275 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2276 2277 /* 2278 * H_SYNC_STRT_WID 2279 */ 2280 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2281 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2282 if (mode->flags & VID_NHSYNC) 2283 v |= RADEON_CRTC_H_SYNC_POL; 2284 PUT32(sc, hsyncstrt, v); 2285 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2286 PUT32(sc, fphsyncstrt, v); 2287 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2288 2289 /* 2290 * V_TOTAL_DISP 2291 */ 2292 v = ((mode->vdisplay - 1) << 16); 2293 v |= (mode->vtotal - 1); 2294 PUT32(sc, vtotaldisp, v); 2295 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2296 PUT32(sc, fpvtotaldisp, v); 2297 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2298 2299 /* 2300 * V_SYNC_STRT_WID 2301 */ 2302 v = ((mode->vsync_end - mode->vsync_start) << 16); 2303 v |= (mode->vsync_start - 1); 2304 if (mode->flags & VID_NVSYNC) 2305 v |= RADEON_CRTC_V_SYNC_POL; 2306 PUT32(sc, vsyncstrt, v); 2307 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2308 PUT32(sc, fpvsyncstrt, v); 2309 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2310 2311 radeonfb_program_vclk(sc, mode->dot_clock, crtc); 2312 2313 switch (crtc) { 2314 case 0: 2315 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2316 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2317 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2318 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2319 2320 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2321 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2322 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2323 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2324 PRINTREG(RADEON_CRTC_EXT_CNTL); 2325 PRINTREG(RADEON_CRTC_GEN_CNTL); 2326 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2327 break; 2328 2329 case 1: 2330 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2331 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2332 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2333 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2334 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2335 RADEON_CRTC2_VSYNC_DIS | 2336 RADEON_CRTC2_HSYNC_DIS | 2337 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2338 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2339 break; 2340 } 2341 } 2342 2343 int 2344 radeonfb_isblank(struct radeonfb_display *dp) 2345 { 2346 uint32_t reg, mask; 2347 2348 if(!dp->rd_softc->sc_mapped) 2349 return 1; 2350 2351 if (dp->rd_crtcs[0].rc_number) { 2352 reg = RADEON_CRTC2_GEN_CNTL; 2353 mask = RADEON_CRTC2_DISP_DIS; 2354 } else { 2355 reg = RADEON_CRTC_EXT_CNTL; 2356 mask = RADEON_CRTC_DISPLAY_DIS; 2357 } 2358 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2359 } 2360 2361 void 2362 radeonfb_blank(struct radeonfb_display *dp, int blank) 2363 { 2364 struct radeonfb_softc *sc = dp->rd_softc; 2365 uint32_t reg, mask; 2366 uint32_t fpreg, fpval; 2367 int i; 2368 2369 if (!sc->sc_mapped) 2370 return; 2371 2372 for (i = 0; i < dp->rd_ncrtcs; i++) { 2373 2374 if (dp->rd_crtcs[i].rc_number) { 2375 reg = RADEON_CRTC2_GEN_CNTL; 2376 mask = RADEON_CRTC2_DISP_DIS; 2377 fpreg = RADEON_FP2_GEN_CNTL; 2378 fpval = RADEON_FP2_ON; 2379 } else { 2380 reg = RADEON_CRTC_EXT_CNTL; 2381 mask = RADEON_CRTC_DISPLAY_DIS; 2382 fpreg = RADEON_FP_GEN_CNTL; 2383 fpval = RADEON_FP_FPON; 2384 } 2385 2386 if (blank) { 2387 SET32(sc, reg, mask); 2388 CLR32(sc, fpreg, fpval); 2389 } else { 2390 CLR32(sc, reg, mask); 2391 SET32(sc, fpreg, fpval); 2392 } 2393 } 2394 PRINTREG(RADEON_FP_GEN_CNTL); 2395 PRINTREG(RADEON_FP2_GEN_CNTL); 2396 } 2397 2398 void 2399 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2400 long *defattr) 2401 { 2402 struct radeonfb_display *dp = cookie; 2403 struct rasops_info *ri = &scr->scr_ri; 2404 2405 /* initialize font subsystem */ 2406 wsfont_init(); 2407 2408 scr->scr_flags |= VCONS_LOADFONT; 2409 2410 DPRINTF(("init screen called, existing %d\n", existing)); 2411 2412 ri->ri_depth = dp->rd_bpp; 2413 ri->ri_width = dp->rd_virtx; 2414 ri->ri_height = dp->rd_virty; 2415 ri->ri_stride = dp->rd_stride; 2416 ri->ri_flg = RI_CENTER; 2417 switch (ri->ri_depth) { 2418 case 8: 2419 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2420 break; 2421 case 32: 2422 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2423 /* we run radeons in RGB even on SPARC hardware */ 2424 ri->ri_rnum = 8; 2425 ri->ri_gnum = 8; 2426 ri->ri_bnum = 8; 2427 ri->ri_rpos = 16; 2428 ri->ri_gpos = 8; 2429 ri->ri_bpos = 0; 2430 break; 2431 } 2432 2433 ri->ri_bits = (void *)dp->rd_fbptr; 2434 2435 #ifdef VCONS_DRAW_INTR 2436 scr->scr_flags |= VCONS_DONT_READ; 2437 #endif 2438 2439 if (existing) { 2440 ri->ri_flg |= RI_CLEAR; 2441 2442 /* start a modeswitch now */ 2443 radeonfb_modeswitch(dp); 2444 } 2445 2446 /* 2447 * XXX: font selection should be based on properties, with some 2448 * normal/reasonable default. 2449 */ 2450 2451 /* initialize and look for an initial font */ 2452 rasops_init(ri, 0, 0); 2453 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2454 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2455 2456 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2457 dp->rd_virtx / ri->ri_font->fontwidth); 2458 2459 /* enable acceleration */ 2460 dp->rd_putchar = ri->ri_ops.putchar; 2461 ri->ri_ops.copyrows = radeonfb_copyrows; 2462 ri->ri_ops.copycols = radeonfb_copycols; 2463 ri->ri_ops.eraserows = radeonfb_eraserows; 2464 ri->ri_ops.erasecols = radeonfb_erasecols; 2465 /* pick a putchar method based on font and Radeon model */ 2466 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2467 /* got a bitmap font */ 2468 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2469 if (IS_R300(dp->rd_softc)) { 2470 /* 2471 * radeonfb_putchar() doesn't work right on some R3xx 2472 * so we use software drawing here, the wrapper just 2473 * makes sure the engine is idle before scribbling 2474 * into vram 2475 */ 2476 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2477 } else 2478 #endif 2479 ri->ri_ops.putchar = radeonfb_putchar; 2480 } else { 2481 /* got an alpha font */ 2482 switch(ri->ri_depth) { 2483 case 32: 2484 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2485 break; 2486 case 8: 2487 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2488 break; 2489 default: 2490 /* XXX this should never happen */ 2491 panic("%s: depth is not 8 or 32 but we got an" \ 2492 " alpha font?!", __func__); 2493 } 2494 } 2495 ri->ri_ops.cursor = radeonfb_cursor; 2496 } 2497 2498 void 2499 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2500 { 2501 uint32_t gen, ext, gen2 = 0; 2502 uint32_t agploc, aperbase, apersize, mcfbloc; 2503 2504 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2505 /* XXX */ 2506 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2507 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2508 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2509 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2510 2511 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2512 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2513 #if 0 2514 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2515 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2516 #endif 2517 2518 if (HAS_CRTC2(sc)) { 2519 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2520 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2521 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2522 } 2523 2524 delay(100000); 2525 2526 mcfbloc = (aperbase >> 16) | 2527 ((aperbase + (apersize - 1)) & 0xffff0000); 2528 2529 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2530 sc->sc_memsz = apersize; 2531 2532 if (((agploc & 0xffff) << 16) != 2533 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2534 agploc = mcfbloc & 0xffff0000U; 2535 agploc |= ((agploc + 0x10000) >> 16); 2536 } 2537 2538 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2539 2540 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2541 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2542 2543 DPRINTF(("aperbase = %u\n", aperbase)); 2544 PRINTREG(RADEON_MC_FB_LOCATION); 2545 PRINTREG(RADEON_MC_AGP_LOCATION); 2546 2547 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2548 2549 if (HAS_CRTC2(sc)) 2550 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2551 2552 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2553 2554 #if 0 2555 /* XXX: what is this AGP garbage? :-) */ 2556 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2557 #endif 2558 2559 delay(100000); 2560 2561 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2562 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2563 2564 if (HAS_CRTC2(sc)) 2565 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2566 } 2567 2568 void 2569 radeonfb_init_misc(struct radeonfb_softc *sc) 2570 { 2571 PUT32(sc, RADEON_BUS_CNTL, 2572 RADEON_BUS_MASTER_DIS | 2573 RADEON_BUS_PREFETCH_MODE_ACT | 2574 RADEON_BUS_PCI_READ_RETRY_EN | 2575 RADEON_BUS_PCI_WRT_RETRY_EN | 2576 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2577 RADEON_BUS_MSTR_RD_MULT | 2578 RADEON_BUS_MSTR_RD_LINE | 2579 RADEON_BUS_RD_DISCARD_EN | 2580 RADEON_BUS_MSTR_DISCONNECT_EN | 2581 RADEON_BUS_READ_BURST); 2582 2583 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2584 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2585 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2586 PUT32(sc, RADEON_RBBM_CNTL, 2587 (3 << RADEON_RB_SETTLE_SHIFT) | 2588 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2589 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2590 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2591 2592 /* XXX: figure out what these mean! */ 2593 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2594 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2595 #if 0 2596 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2597 #endif 2598 2599 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2600 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2601 } 2602 2603 static void 2604 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2605 { 2606 struct radeonfb_softc *sc = dp->rd_softc; 2607 int crtc, cc; 2608 uint32_t vclk; 2609 2610 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2611 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2612 2613 /* initialize the palette for every CRTC used by this display */ 2614 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2615 crtc = dp->rd_crtcs[cc].rc_number; 2616 //DPRINTF(("%s: doing crtc %d %d\n", __func__, cc, crtc)); 2617 2618 if (crtc) 2619 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2620 else 2621 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2622 2623 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2624 PUT32(sc, RADEON_PALETTE_30_DATA, 2625 (r << 22) | (g << 12) | (b << 2)); 2626 } 2627 2628 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2629 } 2630 2631 /* 2632 * This loads a linear color map for true color. 2633 */ 2634 void 2635 radeonfb_init_palette(struct radeonfb_display *dp) 2636 { 2637 int i; 2638 2639 #define DAC_WIDTH ((1 << 10) - 1) 2640 #define CLUT_WIDTH ((1 << 8) - 1) 2641 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2642 2643 if (dp->rd_bpp == 8) { 2644 2645 /* R3G3B2 palette */ 2646 uint32_t tmp, r, g, b; 2647 2648 for (i = 0; i <= CLUT_WIDTH; ++i) { 2649 tmp = i & 0xe0; 2650 2651 /* 2652 * replicate bits so 0xe0 maps to a red value of 0xff 2653 * in order to make white look actually white 2654 */ 2655 tmp |= (tmp >> 3) | (tmp >> 6); 2656 r = tmp; 2657 2658 tmp = (i & 0x1c) << 3; 2659 tmp |= (tmp >> 3) | (tmp >> 6); 2660 g = tmp; 2661 2662 tmp = (i & 0x03) << 6; 2663 tmp |= tmp >> 2; 2664 tmp |= tmp >> 4; 2665 b = tmp; 2666 2667 radeonfb_putpal(dp, i, r, g, b); 2668 } 2669 } else { 2670 /* linear ramp */ 2671 for (i = 0; i <= CLUT_WIDTH; ++i) { 2672 radeonfb_putpal(dp, i, i, i, i); 2673 } 2674 } 2675 } 2676 2677 static int 2678 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2679 { 2680 u_char *r, *g, *b; 2681 u_int index = cm->index; 2682 u_int count = cm->count; 2683 int i, error; 2684 u_char rbuf[256], gbuf[256], bbuf[256]; 2685 2686 #ifdef GENFB_DEBUG 2687 aprint_debug("putcmap: %d %d\n",index, count); 2688 #endif 2689 if (cm->index >= 256 || cm->count > 256 || 2690 (cm->index + cm->count) > 256) 2691 return EINVAL; 2692 error = copyin(cm->red, &rbuf[index], count); 2693 if (error) 2694 return error; 2695 error = copyin(cm->green, &gbuf[index], count); 2696 if (error) 2697 return error; 2698 error = copyin(cm->blue, &bbuf[index], count); 2699 if (error) 2700 return error; 2701 2702 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2703 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2704 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2705 2706 r = &dp->rd_cmap_red[index]; 2707 g = &dp->rd_cmap_green[index]; 2708 b = &dp->rd_cmap_blue[index]; 2709 2710 for (i = 0; i < count; i++) { 2711 radeonfb_putpal(dp, index, *r, *g, *b); 2712 index++; 2713 r++, g++, b++; 2714 } 2715 return 0; 2716 } 2717 2718 static int 2719 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2720 { 2721 u_int index = cm->index; 2722 u_int count = cm->count; 2723 int error; 2724 2725 if (index >= 255 || count > 256 || index + count > 256) 2726 return EINVAL; 2727 2728 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2729 if (error) 2730 return error; 2731 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2732 if (error) 2733 return error; 2734 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2735 if (error) 2736 return error; 2737 2738 return 0; 2739 } 2740 2741 /* 2742 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2743 */ 2744 void 2745 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2746 { 2747 uint32_t tmp, save; 2748 2749 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2750 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2751 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2752 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2753 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2754 } 2755 2756 /* 2757 * Acceleration entry points. 2758 */ 2759 2760 /* this one draws characters using bitmap fonts */ 2761 static void 2762 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2763 { 2764 struct rasops_info *ri = cookie; 2765 struct vcons_screen *scr = ri->ri_hw; 2766 struct radeonfb_display *dp = scr->scr_cookie; 2767 struct radeonfb_softc *sc = dp->rd_softc; 2768 struct wsdisplay_font *font = PICK_FONT(ri, c); 2769 uint32_t w, h; 2770 int xd, yd, offset, i; 2771 uint32_t bg, fg, gmc; 2772 uint32_t reg; 2773 uint8_t *data8; 2774 uint16_t *data16; 2775 void *data; 2776 2777 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2778 return; 2779 2780 if (!CHAR_IN_FONT(c, font)) 2781 return; 2782 2783 w = font->fontwidth; 2784 h = font->fontheight; 2785 2786 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2787 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2788 2789 xd = ri->ri_xorigin + col * w; 2790 yd = ri->ri_yorigin + row * h; 2791 2792 if (c == 0x20) { 2793 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2794 return; 2795 } 2796 data = WSFONT_GLYPH(c, font); 2797 2798 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2799 2800 radeonfb_wait_fifo(sc, 9); 2801 2802 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2803 RADEON_GMC_BRUSH_NONE | 2804 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2805 RADEON_GMC_DST_CLIPPING | 2806 RADEON_ROP3_S | 2807 RADEON_DP_SRC_SOURCE_HOST_DATA | 2808 RADEON_GMC_CLR_CMP_CNTL_DIS | 2809 RADEON_GMC_WR_MSK_DIS | 2810 gmc); 2811 2812 PUT32(sc, RADEON_SC_LEFT, xd); 2813 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2814 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2815 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2816 PUT32(sc, RADEON_DP_CNTL, 2817 RADEON_DST_X_LEFT_TO_RIGHT | 2818 RADEON_DST_Y_TOP_TO_BOTTOM); 2819 2820 PUT32(sc, RADEON_SRC_X_Y, 0); 2821 offset = 32 - (font->stride << 3); 2822 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2823 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2824 2825 radeonfb_wait_fifo(sc, h); 2826 switch (font->stride) { 2827 case 1: { 2828 data8 = data; 2829 for (i = 0; i < h; i++) { 2830 reg = *data8; 2831 #if BYTE_ORDER == LITTLE_ENDIAN 2832 reg = reg << 24; 2833 #endif 2834 bus_space_write_stream_4(sc->sc_regt, 2835 sc->sc_regh, RADEON_HOST_DATA0, reg); 2836 data8++; 2837 } 2838 break; 2839 } 2840 case 2: { 2841 data16 = data; 2842 for (i = 0; i < h; i++) { 2843 reg = *data16; 2844 #if BYTE_ORDER == LITTLE_ENDIAN 2845 reg = reg << 16; 2846 #endif 2847 bus_space_write_stream_4(sc->sc_regt, 2848 sc->sc_regh, RADEON_HOST_DATA0, reg); 2849 data16++; 2850 } 2851 break; 2852 } 2853 } 2854 if (attr & 1) 2855 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2856 } 2857 2858 /* ... while this one is for anti-aliased ones */ 2859 static void 2860 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2861 { 2862 struct rasops_info *ri = cookie; 2863 struct vcons_screen *scr = ri->ri_hw; 2864 struct radeonfb_display *dp = scr->scr_cookie; 2865 struct radeonfb_softc *sc = dp->rd_softc; 2866 struct wsdisplay_font *font = PICK_FONT(ri, c); 2867 uint32_t bg, fg, gmc; 2868 uint8_t *data; 2869 int w, h, xd, yd; 2870 int i, r, g, b, aval; 2871 int rf, gf, bf, rb, gb, bb; 2872 uint32_t pixel; 2873 int rv; 2874 2875 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2876 return; 2877 2878 if (!CHAR_IN_FONT(c, font)) 2879 return; 2880 2881 w = font->fontwidth; 2882 h = font->fontheight; 2883 2884 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2885 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2886 2887 xd = ri->ri_xorigin + col * w; 2888 yd = ri->ri_yorigin + row * h; 2889 2890 if (c == 0x20) { 2891 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2892 if (attr & 1) 2893 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2894 return; 2895 } 2896 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2897 if (rv == GC_OK) 2898 return; 2899 2900 data = WSFONT_GLYPH(c, font); 2901 2902 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2903 2904 radeonfb_wait_fifo(sc, 5); 2905 2906 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2907 RADEON_GMC_BRUSH_NONE | 2908 RADEON_GMC_SRC_DATATYPE_COLOR | 2909 RADEON_ROP3_S | 2910 RADEON_DP_SRC_SOURCE_HOST_DATA | 2911 RADEON_GMC_CLR_CMP_CNTL_DIS | 2912 RADEON_GMC_WR_MSK_DIS | 2913 gmc); 2914 2915 PUT32(sc, RADEON_DP_CNTL, 2916 RADEON_DST_X_LEFT_TO_RIGHT | 2917 RADEON_DST_Y_TOP_TO_BOTTOM); 2918 2919 PUT32(sc, RADEON_SRC_X_Y, 0); 2920 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2921 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2922 2923 rf = (fg >> 16) & 0xff; 2924 rb = (bg >> 16) & 0xff; 2925 gf = (fg >> 8) & 0xff; 2926 gb = (bg >> 8) & 0xff; 2927 bf = fg & 0xff; 2928 bb = bg & 0xff; 2929 2930 /* 2931 * I doubt we can upload data faster than even the slowest Radeon 2932 * could process them, especially when doing the alpha blending stuff 2933 * along the way, so just make sure there's some room in the FIFO and 2934 * then hammer away 2935 * As it turns out we can, so make periodic stops to let the FIFO 2936 * drain. 2937 */ 2938 radeonfb_wait_fifo(sc, 20); 2939 for (i = 0; i < ri->ri_fontscale; i++) { 2940 aval = *data; 2941 data++; 2942 if (aval == 0) { 2943 pixel = bg; 2944 } else if (aval == 255) { 2945 pixel = fg; 2946 } else { 2947 r = aval * rf + (255 - aval) * rb; 2948 g = aval * gf + (255 - aval) * gb; 2949 b = aval * bf + (255 - aval) * bb; 2950 pixel = (r & 0xff00) << 8 | 2951 (g & 0xff00) | 2952 (b & 0xff00) >> 8; 2953 } 2954 if (i & 16) 2955 radeonfb_wait_fifo(sc, 20); 2956 PUT32(sc, RADEON_HOST_DATA0, pixel); 2957 } 2958 if (rv == GC_ADD) { 2959 glyphcache_add(&dp->rd_gc, c, xd, yd); 2960 } else 2961 if (attr & 1) 2962 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2963 2964 } 2965 2966 static void 2967 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 2968 { 2969 struct rasops_info *ri = cookie; 2970 struct vcons_screen *scr = ri->ri_hw; 2971 struct radeonfb_display *dp = scr->scr_cookie; 2972 struct radeonfb_softc *sc = dp->rd_softc; 2973 struct wsdisplay_font *font = PICK_FONT(ri, c); 2974 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 2975 int i, x, y, wi, he, r, g, b, aval; 2976 int r1, g1, b1, r0, g0, b0, fgo, bgo; 2977 uint8_t *data8; 2978 int rv, cnt; 2979 2980 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2981 return; 2982 2983 if (!CHAR_IN_FONT(c, font)) 2984 return; 2985 2986 wi = font->fontwidth; 2987 he = font->fontheight; 2988 2989 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2990 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2991 2992 x = ri->ri_xorigin + col * wi; 2993 y = ri->ri_yorigin + row * he; 2994 2995 if (c == 0x20) { 2996 radeonfb_rectfill(dp, x, y, wi, he, bg); 2997 if (attr & 1) 2998 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 2999 return; 3000 } 3001 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3002 if (rv == GC_OK) 3003 return; 3004 3005 data8 = WSFONT_GLYPH(c, font); 3006 3007 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3008 3009 radeonfb_wait_fifo(sc, 5); 3010 3011 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3012 RADEON_GMC_BRUSH_NONE | 3013 RADEON_GMC_SRC_DATATYPE_COLOR | 3014 RADEON_ROP3_S | 3015 RADEON_DP_SRC_SOURCE_HOST_DATA | 3016 RADEON_GMC_CLR_CMP_CNTL_DIS | 3017 RADEON_GMC_WR_MSK_DIS | 3018 gmc); 3019 3020 PUT32(sc, RADEON_DP_CNTL, 3021 RADEON_DST_X_LEFT_TO_RIGHT | 3022 RADEON_DST_Y_TOP_TO_BOTTOM); 3023 3024 PUT32(sc, RADEON_SRC_X_Y, 0); 3025 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3026 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3027 3028 /* 3029 * we need the RGB colours here, so get offsets into rasops_cmap 3030 */ 3031 fgo = ((attr >> 24) & 0xf) * 3; 3032 bgo = ((attr >> 16) & 0xf) * 3; 3033 3034 r0 = rasops_cmap[bgo]; 3035 r1 = rasops_cmap[fgo]; 3036 g0 = rasops_cmap[bgo + 1]; 3037 g1 = rasops_cmap[fgo + 1]; 3038 b0 = rasops_cmap[bgo + 2]; 3039 b1 = rasops_cmap[fgo + 2]; 3040 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3041 bg8 = R3G3B2(r0, g0, b0); 3042 fg8 = R3G3B2(r1, g1, b1); 3043 3044 radeonfb_wait_fifo(sc, 20); 3045 cnt = 0; 3046 for (i = 0; i < ri->ri_fontscale; i++) { 3047 aval = *data8; 3048 if (aval == 0) { 3049 pixel = bg8; 3050 } else if (aval == 255) { 3051 pixel = fg8; 3052 } else { 3053 r = aval * r1 + (255 - aval) * r0; 3054 g = aval * g1 + (255 - aval) * g0; 3055 b = aval * b1 + (255 - aval) * b0; 3056 pixel = ((r & 0xe000) >> 8) | 3057 ((g & 0xe000) >> 11) | 3058 ((b & 0xc000) >> 14); 3059 } 3060 latch |= pixel << (8 * (i & 3)); 3061 /* write in 32bit chunks */ 3062 if ((i & 3) == 3) { 3063 PUT32(sc, RADEON_HOST_DATA0, latch); 3064 /* 3065 * not strictly necessary, old data should be shifted 3066 * out 3067 */ 3068 latch = 0; 3069 cnt++; 3070 if (cnt > 16) { 3071 cnt = 0; 3072 radeonfb_wait_fifo(sc, 20); 3073 } 3074 } 3075 data8++; 3076 } 3077 /* if we have pixels left in latch write them out */ 3078 if ((i & 3) != 0) { 3079 /* 3080 * radeon is weird - apparently leftover pixels are written 3081 * from the middle, not from the left as everything else 3082 */ 3083 PUT32(sc, RADEON_HOST_DATA0, latch); 3084 } 3085 3086 if (rv == GC_ADD) { 3087 glyphcache_add(&dp->rd_gc, c, x, y); 3088 } else 3089 if (attr & 1) 3090 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3091 3092 } 3093 3094 /* 3095 * wrapper for software character drawing 3096 * just sync the engine and call rasops*_putchar() 3097 */ 3098 3099 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3100 static void 3101 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3102 { 3103 struct rasops_info *ri = cookie; 3104 struct vcons_screen *scr = ri->ri_hw; 3105 struct radeonfb_display *dp = scr->scr_cookie; 3106 3107 radeonfb_engine_idle(dp->rd_softc); 3108 dp->rd_putchar(ri, row, col, c, attr); 3109 } 3110 #endif 3111 3112 static void 3113 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3114 { 3115 struct rasops_info *ri = cookie; 3116 struct vcons_screen *scr = ri->ri_hw; 3117 struct radeonfb_display *dp = scr->scr_cookie; 3118 uint32_t x, y, w, h, fg, bg, ul; 3119 3120 /* XXX: check for full emulation mode? */ 3121 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3122 x = ri->ri_xorigin; 3123 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3124 w = ri->ri_emuwidth; 3125 h = ri->ri_font->fontheight * nrows; 3126 3127 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3128 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3129 } 3130 } 3131 3132 static void 3133 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3134 { 3135 struct rasops_info *ri = cookie; 3136 struct vcons_screen *scr = ri->ri_hw; 3137 struct radeonfb_display *dp = scr->scr_cookie; 3138 uint32_t x, ys, yd, w, h; 3139 3140 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3141 x = ri->ri_xorigin; 3142 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3143 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3144 w = ri->ri_emuwidth; 3145 h = ri->ri_font->fontheight * nrows; 3146 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3147 RADEON_ROP3_S); 3148 } 3149 } 3150 3151 static void 3152 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3153 { 3154 struct rasops_info *ri = cookie; 3155 struct vcons_screen *scr = ri->ri_hw; 3156 struct radeonfb_display *dp = scr->scr_cookie; 3157 uint32_t xs, xd, y, w, h; 3158 3159 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3160 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3161 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3162 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3163 w = ri->ri_font->fontwidth * ncols; 3164 h = ri->ri_font->fontheight; 3165 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3166 RADEON_ROP3_S); 3167 } 3168 } 3169 3170 static void 3171 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3172 long fillattr) 3173 { 3174 struct rasops_info *ri = cookie; 3175 struct vcons_screen *scr = ri->ri_hw; 3176 struct radeonfb_display *dp = scr->scr_cookie; 3177 uint32_t x, y, w, h, fg, bg, ul; 3178 3179 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3180 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3181 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3182 w = ri->ri_font->fontwidth * ncols; 3183 h = ri->ri_font->fontheight; 3184 3185 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3186 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3187 } 3188 } 3189 3190 static void 3191 radeonfb_cursor(void *cookie, int on, int row, int col) 3192 { 3193 struct rasops_info *ri = cookie; 3194 struct vcons_screen *scr = ri->ri_hw; 3195 struct radeonfb_display *dp = scr->scr_cookie; 3196 int x, y, wi, he; 3197 3198 wi = ri->ri_font->fontwidth; 3199 he = ri->ri_font->fontheight; 3200 3201 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3202 x = ri->ri_ccol * wi + ri->ri_xorigin; 3203 y = ri->ri_crow * he + ri->ri_yorigin; 3204 /* first turn off the old cursor */ 3205 if (ri->ri_flg & RI_CURSOR) { 3206 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3207 RADEON_ROP3_Dn); 3208 ri->ri_flg &= ~RI_CURSOR; 3209 } 3210 ri->ri_crow = row; 3211 ri->ri_ccol = col; 3212 /* then (possibly) turn on the new one */ 3213 if (on) { 3214 x = ri->ri_ccol * wi + ri->ri_xorigin; 3215 y = ri->ri_crow * he + ri->ri_yorigin; 3216 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3217 RADEON_ROP3_Dn); 3218 ri->ri_flg |= RI_CURSOR; 3219 } 3220 } else { 3221 scr->scr_ri.ri_crow = row; 3222 scr->scr_ri.ri_ccol = col; 3223 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3224 } 3225 } 3226 3227 /* 3228 * Underlying acceleration support. 3229 */ 3230 3231 static void 3232 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3233 int width, int height, uint32_t color) 3234 { 3235 struct radeonfb_softc *sc = dp->rd_softc; 3236 uint32_t gmc; 3237 3238 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3239 3240 radeonfb_wait_fifo(sc, 6); 3241 3242 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3243 RADEON_GMC_BRUSH_SOLID_COLOR | 3244 RADEON_GMC_SRC_DATATYPE_COLOR | 3245 RADEON_GMC_CLR_CMP_CNTL_DIS | 3246 RADEON_ROP3_P | gmc); 3247 3248 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3249 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3250 PUT32(sc, RADEON_DP_CNTL, 3251 RADEON_DST_X_LEFT_TO_RIGHT | 3252 RADEON_DST_Y_TOP_TO_BOTTOM); 3253 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3254 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3255 3256 } 3257 3258 static void 3259 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3260 int width, int height, long attr) 3261 { 3262 struct radeonfb_display *dp = cookie; 3263 3264 radeonfb_rectfill(dp, dstx, dsty, width, height, 3265 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3266 } 3267 3268 static void 3269 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3270 int dstx, int dsty, int width, int height, int rop) 3271 { 3272 struct radeonfb_display *dp = cookie; 3273 struct radeonfb_softc *sc = dp->rd_softc; 3274 uint32_t gmc; 3275 uint32_t dir; 3276 3277 if (dsty < srcy) { 3278 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3279 } else { 3280 srcy += height - 1; 3281 dsty += height - 1; 3282 dir = 0; 3283 } 3284 if (dstx < srcx) { 3285 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3286 } else { 3287 srcx += width - 1; 3288 dstx += width - 1; 3289 } 3290 3291 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3292 3293 radeonfb_wait_fifo(sc, 6); 3294 3295 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3296 RADEON_GMC_BRUSH_SOLID_COLOR | 3297 RADEON_GMC_SRC_DATATYPE_COLOR | 3298 RADEON_GMC_CLR_CMP_CNTL_DIS | 3299 RADEON_DP_SRC_SOURCE_MEMORY | 3300 rop | gmc); 3301 3302 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3303 PUT32(sc, RADEON_DP_CNTL, dir); 3304 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3305 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3306 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3307 } 3308 3309 static void 3310 radeonfb_engine_idle(struct radeonfb_softc *sc) 3311 { 3312 3313 radeonfb_wait_fifo(sc, 64); 3314 while ((GET32(sc, RADEON_RBBM_STATUS) & 3315 RADEON_RBBM_ACTIVE) != 0); 3316 radeonfb_engine_flush(sc); 3317 } 3318 3319 static inline void 3320 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3321 { 3322 int i; 3323 3324 for (i = RADEON_TIMEOUT; i; i--) { 3325 if ((GET32(sc, RADEON_RBBM_STATUS) & 3326 RADEON_RBBM_FIFOCNT_MASK) >= n) 3327 return; 3328 } 3329 #ifdef DIAGNOSTIC 3330 if (!i) 3331 printf("%s: timed out waiting for fifo (%x)\n", 3332 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3333 #endif 3334 } 3335 3336 static void 3337 radeonfb_engine_flush(struct radeonfb_softc *sc) 3338 { 3339 int i = 0; 3340 3341 if (IS_R300(sc)) { 3342 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3343 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3344 i++; 3345 } 3346 } else { 3347 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3348 RADEON_RB2D_DC_FLUSH_ALL); 3349 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3350 RADEON_RB2D_DC_BUSY) { 3351 i++; 3352 } 3353 } 3354 #ifdef DIAGNOSTIC 3355 if (i > RADEON_TIMEOUT) 3356 printf("%s: engine flush timed out!\n", XNAME(sc)); 3357 #endif 3358 } 3359 3360 static inline void 3361 radeonfb_unclip(struct radeonfb_softc *sc) 3362 { 3363 3364 radeonfb_wait_fifo(sc, 2); 3365 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3366 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3367 } 3368 3369 static void 3370 radeonfb_engine_init(struct radeonfb_display *dp) 3371 { 3372 struct radeonfb_softc *sc = dp->rd_softc; 3373 uint32_t pitch; 3374 3375 /* no 3D */ 3376 PUT32(sc, RADEON_RB3D_CNTL, 0); 3377 3378 radeonfb_engine_reset(sc); 3379 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3380 3381 radeonfb_wait_fifo(sc, 1); 3382 if (!IS_R300(sc)) 3383 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3384 3385 radeonfb_wait_fifo(sc, 3); 3386 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3387 (pitch << 22) | (sc->sc_aperbase >> 10)); 3388 3389 3390 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3391 (pitch << 22) | (sc->sc_aperbase >> 10)); 3392 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3393 (pitch << 22) | (sc->sc_aperbase >> 10)); 3394 3395 (void)GET32(sc, RADEON_DP_DATATYPE); 3396 3397 /* default scissors -- no clipping */ 3398 radeonfb_wait_fifo(sc, 1); 3399 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3400 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3401 3402 radeonfb_wait_fifo(sc, 1); 3403 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3404 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3405 RADEON_GMC_CLR_CMP_CNTL_DIS | 3406 RADEON_GMC_BRUSH_SOLID_COLOR | 3407 RADEON_GMC_SRC_DATATYPE_COLOR); 3408 3409 radeonfb_wait_fifo(sc, 10); 3410 PUT32(sc, RADEON_DST_LINE_START, 0); 3411 PUT32(sc, RADEON_DST_LINE_END, 0); 3412 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3413 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3414 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3415 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3416 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3417 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3418 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3419 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3420 radeonfb_engine_idle(sc); 3421 } 3422 3423 static void 3424 radeonfb_engine_reset(struct radeonfb_softc *sc) 3425 { 3426 uint32_t hpc, rbbm, mclkcntl, clkindex; 3427 3428 radeonfb_engine_flush(sc); 3429 3430 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3431 if (HAS_R300CG(sc)) 3432 radeonfb_r300cg_workaround(sc); 3433 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3434 3435 /* 3436 * According to comments in XFree code, resetting the HDP via 3437 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3438 * So we use HOST_PATH_CNTL instead. 3439 */ 3440 3441 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3442 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3443 if (IS_R300(sc)) { 3444 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3445 RADEON_SOFT_RESET_CP | 3446 RADEON_SOFT_RESET_HI | 3447 RADEON_SOFT_RESET_E2); 3448 GET32(sc, RADEON_RBBM_SOFT_RESET); 3449 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3450 /* 3451 * XXX: this bit is not defined in any ATI docs I have, 3452 * nor in the XFree code, but XFree does it. Why? 3453 */ 3454 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3455 } else { 3456 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3457 RADEON_SOFT_RESET_CP | 3458 RADEON_SOFT_RESET_SE | 3459 RADEON_SOFT_RESET_RE | 3460 RADEON_SOFT_RESET_PP | 3461 RADEON_SOFT_RESET_E2 | 3462 RADEON_SOFT_RESET_RB); 3463 GET32(sc, RADEON_RBBM_SOFT_RESET); 3464 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3465 ~(RADEON_SOFT_RESET_CP | 3466 RADEON_SOFT_RESET_SE | 3467 RADEON_SOFT_RESET_RE | 3468 RADEON_SOFT_RESET_PP | 3469 RADEON_SOFT_RESET_E2 | 3470 RADEON_SOFT_RESET_RB)); 3471 GET32(sc, RADEON_RBBM_SOFT_RESET); 3472 } 3473 3474 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3475 GET32(sc, RADEON_HOST_PATH_CNTL); 3476 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3477 3478 if (IS_R300(sc)) 3479 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3480 3481 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3482 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3483 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3484 3485 if (HAS_R300CG(sc)) 3486 radeonfb_r300cg_workaround(sc); 3487 } 3488 3489 static int 3490 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3491 { 3492 int x, y; 3493 3494 x = pos->x; 3495 y = pos->y; 3496 3497 /* 3498 * This doesn't let a cursor move off the screen. I'm not 3499 * sure if this will have negative effects for e.g. Xinerama. 3500 * I'd guess Xinerama handles it by changing the cursor shape, 3501 * but that needs verification. 3502 */ 3503 if (x >= dp->rd_virtx) 3504 x = dp->rd_virtx - 1; 3505 if (x < 0) 3506 x = 0; 3507 if (y >= dp->rd_virty) 3508 y = dp->rd_virty - 1; 3509 if (y < 0) 3510 y = 0; 3511 3512 dp->rd_cursor.rc_pos.x = x; 3513 dp->rd_cursor.rc_pos.y = y; 3514 3515 radeonfb_cursor_position(dp); 3516 return 0; 3517 } 3518 3519 static int 3520 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3521 { 3522 unsigned flags; 3523 3524 uint8_t r[2], g[2], b[2]; 3525 unsigned index, count; 3526 int i, err; 3527 int pitch, size; 3528 struct radeonfb_cursor nc; 3529 3530 flags = wc->which; 3531 3532 /* copy old values */ 3533 nc = dp->rd_cursor; 3534 3535 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3536 index = wc->cmap.index; 3537 count = wc->cmap.count; 3538 3539 if (index >= 2 || (index + count) > 2) 3540 return EINVAL; 3541 3542 err = copyin(wc->cmap.red, &r[index], count); 3543 if (err) 3544 return err; 3545 err = copyin(wc->cmap.green, &g[index], count); 3546 if (err) 3547 return err; 3548 err = copyin(wc->cmap.blue, &b[index], count); 3549 if (err) 3550 return err; 3551 3552 for (i = index; i < index + count; i++) { 3553 nc.rc_cmap[i] = 3554 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3555 } 3556 } 3557 3558 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3559 if ((wc->size.x > RADEON_CURSORMAXX) || 3560 (wc->size.y > RADEON_CURSORMAXY)) 3561 return EINVAL; 3562 3563 /* figure bytes per line */ 3564 pitch = (wc->size.x + 7) / 8; 3565 size = pitch * wc->size.y; 3566 3567 /* clear the old cursor and mask */ 3568 memset(nc.rc_image, 0, 512); 3569 memset(nc.rc_mask, 0, 512); 3570 3571 nc.rc_size = wc->size; 3572 3573 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3574 return err; 3575 3576 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3577 return err; 3578 } 3579 3580 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3581 nc.rc_hot = wc->hot; 3582 if (nc.rc_hot.x >= nc.rc_size.x) 3583 nc.rc_hot.x = nc.rc_size.x - 1; 3584 if (nc.rc_hot.y >= nc.rc_size.y) 3585 nc.rc_hot.y = nc.rc_size.y - 1; 3586 } 3587 3588 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3589 nc.rc_pos = wc->pos; 3590 if (nc.rc_pos.x >= dp->rd_virtx) 3591 nc.rc_pos.x = dp->rd_virtx - 1; 3592 #if 0 3593 if (nc.rc_pos.x < 0) 3594 nc.rc_pos.x = 0; 3595 #endif 3596 if (nc.rc_pos.y >= dp->rd_virty) 3597 nc.rc_pos.y = dp->rd_virty - 1; 3598 #if 0 3599 if (nc.rc_pos.y < 0) 3600 nc.rc_pos.y = 0; 3601 #endif 3602 } 3603 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3604 nc.rc_visible = wc->enable; 3605 } 3606 3607 dp->rd_cursor = nc; 3608 radeonfb_cursor_update(dp, wc->which); 3609 3610 return 0; 3611 } 3612 3613 static uint8_t 3614 radeonfb_backwards(uint8_t d) 3615 { 3616 uint8_t l; 3617 3618 l = d << 7; 3619 l |= ((d & 0x02) << 5); 3620 l |= ((d & 0x04) << 3); 3621 l |= ((d & 0x08) << 1); 3622 l |= ((d & 0x10) >> 1); 3623 l |= ((d & 0x20) >> 3); 3624 l |= ((d & 0x40) >> 5); 3625 l |= ((d & 0x80) >> 7); 3626 return l; 3627 } 3628 3629 /* 3630 * Change the cursor shape. Call this with the cursor locked to avoid 3631 * flickering/tearing. 3632 */ 3633 static void 3634 radeonfb_cursor_shape(struct radeonfb_display *dp) 3635 { 3636 uint8_t and[512], xor[512]; 3637 int i, j, src, dst /* , pitch */; 3638 const uint8_t *msk = dp->rd_cursor.rc_mask; 3639 const uint8_t *img = dp->rd_cursor.rc_image; 3640 3641 /* 3642 * Radeon cursor data interleaves one line of AND data followed 3643 * by a line of XOR data. (Each line corresponds to a whole hardware 3644 * pitch - i.e. 64 pixels or 8 bytes.) 3645 * 3646 * The cursor is displayed using the following table: 3647 * 3648 * AND XOR Result 3649 * ---------------------- 3650 * 0 0 Cursor color 0 3651 * 0 1 Cursor color 1 3652 * 1 0 Transparent 3653 * 1 1 Complement of background 3654 * 3655 * Our masks are therefore different from what we were passed. 3656 * Passed in, I'm assuming the data represents either color 0 or 1, 3657 * and a mask, so the passed in table looks like: 3658 * 3659 * IMG Mask Result 3660 * ----------------------- 3661 * 0 0 Transparent 3662 * 0 1 Cursor color 0 3663 * 1 0 Transparent 3664 * 1 1 Cursor color 1 3665 * 3666 * IF mask bit == 1, AND = 0, XOR = color. 3667 * IF mask bit == 0, AND = 1, XOR = 0. 3668 * 3669 * hence: AND = ~(mask); XOR = color & ~(mask); 3670 */ 3671 3672 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3673 3674 /* start by assuming all bits are transparent */ 3675 memset(and, 0xff, 512); 3676 memset(xor, 0x00, 512); 3677 3678 src = 0; 3679 dst = 0; 3680 for (i = 0; i < 64; i++) { 3681 for (j = 0; j < 64; j += 8) { 3682 if ((i < dp->rd_cursor.rc_size.y) && 3683 (j < dp->rd_cursor.rc_size.x)) { 3684 3685 /* take care to leave odd bits alone */ 3686 and[dst] &= ~(msk[src]); 3687 xor[dst] = img[src] & msk[src]; 3688 src++; 3689 } 3690 dst++; 3691 } 3692 } 3693 3694 for (i = 0; i < 512; i++) { 3695 and[i] = radeonfb_backwards(and[i]); 3696 xor[i] = radeonfb_backwards(xor[i]); 3697 } 3698 3699 /* copy the image into place */ 3700 for (i = 0; i < 64; i++) { 3701 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3702 &and[i * 8], 8); 3703 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3704 &xor[i * 8], 8); 3705 } 3706 } 3707 3708 static void 3709 radeonfb_cursor_position(struct radeonfb_display *dp) 3710 { 3711 struct radeonfb_softc *sc = dp->rd_softc; 3712 uint32_t offset, hvoff, hvpos; /* registers */ 3713 uint32_t coff; /* cursor offset */ 3714 int i, x, y, xoff, yoff, crtcoff; 3715 3716 /* 3717 * XXX: this also needs to handle pan/scan 3718 */ 3719 for (i = 0; i < dp->rd_ncrtcs; i++) { 3720 3721 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3722 3723 if (rcp->rc_number) { 3724 offset = RADEON_CUR2_OFFSET; 3725 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3726 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3727 crtcoff = RADEON_CRTC2_OFFSET; 3728 } else { 3729 offset = RADEON_CUR_OFFSET; 3730 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3731 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3732 crtcoff = RADEON_CRTC_OFFSET; 3733 } 3734 3735 x = dp->rd_cursor.rc_pos.x; 3736 y = dp->rd_cursor.rc_pos.y; 3737 3738 while (y < rcp->rc_yoffset) { 3739 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3740 } 3741 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3742 rcp->rc_yoffset += RADEON_PANINCREMENT; 3743 } 3744 while (x < rcp->rc_xoffset) { 3745 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3746 } 3747 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3748 rcp->rc_xoffset += RADEON_PANINCREMENT; 3749 } 3750 3751 /* adjust for the cursor's hotspot */ 3752 x -= dp->rd_cursor.rc_hot.x; 3753 y -= dp->rd_cursor.rc_hot.y; 3754 xoff = yoff = 0; 3755 3756 if (x >= dp->rd_virtx) 3757 x = dp->rd_virtx - 1; 3758 if (y >= dp->rd_virty) 3759 y = dp->rd_virty - 1; 3760 3761 /* now adjust cursor so it is relative to viewport */ 3762 x -= rcp->rc_xoffset; 3763 y -= rcp->rc_yoffset; 3764 3765 /* 3766 * no need to check for fall off, because we should 3767 * never move off the screen entirely! 3768 */ 3769 coff = 0; 3770 if (x < 0) { 3771 xoff = -x; 3772 x = 0; 3773 } 3774 if (y < 0) { 3775 yoff = -y; 3776 y = 0; 3777 coff = (yoff * 2) * 8; 3778 } 3779 3780 /* pan the display */ 3781 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3782 rcp->rc_xoffset); 3783 3784 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3785 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3786 /* NB: this unlocks the cursor */ 3787 PUT32(sc, hvpos, (x << 16) | y); 3788 } 3789 } 3790 3791 static void 3792 radeonfb_cursor_visible(struct radeonfb_display *dp) 3793 { 3794 int i; 3795 uint32_t gencntl, bit; 3796 3797 for (i = 0; i < dp->rd_ncrtcs; i++) { 3798 if (dp->rd_crtcs[i].rc_number) { 3799 gencntl = RADEON_CRTC2_GEN_CNTL; 3800 bit = RADEON_CRTC2_CUR_EN; 3801 } else { 3802 gencntl = RADEON_CRTC_GEN_CNTL; 3803 bit = RADEON_CRTC_CUR_EN; 3804 } 3805 3806 if (dp->rd_cursor.rc_visible) 3807 SET32(dp->rd_softc, gencntl, bit); 3808 else 3809 CLR32(dp->rd_softc, gencntl, bit); 3810 } 3811 } 3812 3813 static void 3814 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3815 { 3816 int i; 3817 uint32_t c0reg, c1reg; 3818 struct radeonfb_softc *sc = dp->rd_softc; 3819 3820 for (i = 0; i < dp->rd_ncrtcs; i++) { 3821 if (dp->rd_crtcs[i].rc_number) { 3822 c0reg = RADEON_CUR2_CLR0; 3823 c1reg = RADEON_CUR2_CLR1; 3824 } else { 3825 c0reg = RADEON_CUR_CLR0; 3826 c1reg = RADEON_CUR_CLR1; 3827 } 3828 3829 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3830 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3831 } 3832 } 3833 3834 static void 3835 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3836 { 3837 struct radeonfb_softc *sc; 3838 int i; 3839 3840 sc = dp->rd_softc; 3841 for (i = 0; i < dp->rd_ncrtcs; i++) { 3842 if (dp->rd_crtcs[i].rc_number) { 3843 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3844 } else { 3845 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3846 } 3847 } 3848 3849 if (which & WSDISPLAY_CURSOR_DOCMAP) 3850 radeonfb_cursor_cmap(dp); 3851 3852 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3853 radeonfb_cursor_shape(dp); 3854 3855 if (which & WSDISPLAY_CURSOR_DOCUR) 3856 radeonfb_cursor_visible(dp); 3857 3858 /* this one is unconditional, because it updates other stuff */ 3859 radeonfb_cursor_position(dp); 3860 } 3861 3862 static struct videomode * 3863 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3864 { 3865 int r1, r2; 3866 3867 /* otherwise pick the higher refresh rate */ 3868 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3869 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3870 3871 return (r1 < r2 ? m2 : m1); 3872 } 3873 3874 static const struct videomode * 3875 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3876 int x, int y) 3877 { 3878 struct edid_info *ep = &rp->rp_edid; 3879 struct videomode *vmp = NULL; 3880 int i; 3881 3882 if (!rp->rp_edid_valid) { 3883 /* fallback to safe mode */ 3884 return radeonfb_modelookup(sc->sc_defaultmode); 3885 } 3886 3887 /* always choose the preferred mode first! */ 3888 if (ep->edid_preferred_mode) { 3889 3890 /* XXX: add auto-stretching support for native mode */ 3891 3892 /* this may want panning to occur, btw */ 3893 if ((ep->edid_preferred_mode->hdisplay <= x) && 3894 (ep->edid_preferred_mode->vdisplay <= y)) 3895 return ep->edid_preferred_mode; 3896 } 3897 3898 for (i = 0; i < ep->edid_nmodes; i++) { 3899 /* 3900 * We elect to pick a resolution that is too large for 3901 * the monitor than one that is too small. This means 3902 * that we will prefer to pan rather than to try to 3903 * center a smaller display on a larger screen. In 3904 * practice, this shouldn't matter because if a 3905 * monitor can support a larger resolution, it can 3906 * probably also support the smaller. A specific 3907 * exception is fixed format panels, but hopefully 3908 * they are properly dealt with by the "autostretch" 3909 * logic above. 3910 */ 3911 if ((ep->edid_modes[i].hdisplay > x) || 3912 (ep->edid_modes[i].vdisplay > y)) { 3913 continue; 3914 } 3915 3916 /* 3917 * at this point, the display mode is no larger than 3918 * what we've requested. 3919 */ 3920 if (vmp == NULL) 3921 vmp = &ep->edid_modes[i]; 3922 3923 /* eliminate smaller modes */ 3924 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3925 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3926 continue; 3927 3928 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3929 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3930 vmp = &ep->edid_modes[i]; 3931 continue; 3932 } 3933 3934 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 3935 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 3936 3937 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 3938 } 3939 3940 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 3941 } 3942 3943 static int 3944 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 3945 { 3946 int i; 3947 3948 for (i = 0; i < nlist; i++) { 3949 if ((x == list[i].hdisplay) && 3950 (y == list[i].vdisplay)) { 3951 return 1; 3952 } 3953 } 3954 return 0; 3955 } 3956 3957 static void 3958 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 3959 int pan) 3960 { 3961 struct radeonfb_port *rp; 3962 struct edid_info *ep; 3963 int i, j; 3964 3965 *x = 0; 3966 *y = 0; 3967 3968 if (pan) { 3969 for (i = 0; i < dp->rd_ncrtcs; i++) { 3970 rp = dp->rd_crtcs[i].rc_port; 3971 ep = &rp->rp_edid; 3972 if (!rp->rp_edid_valid) { 3973 /* monitor not present */ 3974 continue; 3975 } 3976 3977 /* 3978 * For now we are ignoring "conflict" that 3979 * could occur when mixing some modes like 3980 * 1280x1024 and 1400x800. It isn't clear 3981 * which is better, so the first one wins. 3982 */ 3983 for (j = 0; j < ep->edid_nmodes; j++) { 3984 /* 3985 * ignore resolutions that are too big for 3986 * the radeon 3987 */ 3988 if (ep->edid_modes[j].hdisplay > 3989 dp->rd_softc->sc_maxx) 3990 continue; 3991 if (ep->edid_modes[j].vdisplay > 3992 dp->rd_softc->sc_maxy) 3993 continue; 3994 3995 /* 3996 * pick largest resolution, the 3997 * smaller monitor will pan 3998 */ 3999 if ((ep->edid_modes[j].hdisplay >= *x) && 4000 (ep->edid_modes[j].vdisplay >= *y)) { 4001 *x = ep->edid_modes[j].hdisplay; 4002 *y = ep->edid_modes[j].vdisplay; 4003 } 4004 } 4005 } 4006 4007 } else { 4008 struct videomode modes[64]; 4009 int nmodes = 0; 4010 int valid = 0; 4011 4012 for (i = 0; i < dp->rd_ncrtcs; i++) { 4013 /* 4014 * pick the largest resolution in common. 4015 */ 4016 rp = dp->rd_crtcs[i].rc_port; 4017 ep = &rp->rp_edid; 4018 4019 if (!rp->rp_edid_valid) 4020 continue; 4021 4022 if (!valid) { 4023 /* 4024 * Pick the preferred mode for this port 4025 * if available. 4026 */ 4027 if (ep->edid_preferred_mode) { 4028 struct videomode *vmp = 4029 ep->edid_preferred_mode; 4030 4031 if ((vmp->hdisplay <= 4032 dp->rd_softc->sc_maxx) && 4033 (vmp->vdisplay <= 4034 dp->rd_softc->sc_maxy)) 4035 modes[nmodes++] = *vmp; 4036 } else { 4037 4038 /* initialize starting list */ 4039 for (j = 0; j < ep->edid_nmodes; j++) { 4040 /* 4041 * ignore resolutions that are 4042 * too big for the radeon 4043 */ 4044 if (ep->edid_modes[j].hdisplay > 4045 dp->rd_softc->sc_maxx) 4046 continue; 4047 if (ep->edid_modes[j].vdisplay > 4048 dp->rd_softc->sc_maxy) 4049 continue; 4050 4051 modes[nmodes] = 4052 ep->edid_modes[j]; 4053 nmodes++; 4054 } 4055 } 4056 valid = 1; 4057 } else { 4058 /* merge into preexisting list */ 4059 for (j = 0; j < nmodes; j++) { 4060 if (!radeonfb_hasres(ep->edid_modes, 4061 ep->edid_nmodes, 4062 modes[j].hdisplay, 4063 modes[j].vdisplay)) { 4064 modes[j] = modes[nmodes]; 4065 j--; 4066 nmodes--; 4067 } 4068 } 4069 } 4070 } 4071 4072 /* now we have to pick from the merged list */ 4073 for (i = 0; i < nmodes; i++) { 4074 if ((modes[i].hdisplay >= *x) && 4075 (modes[i].vdisplay >= *y)) { 4076 *x = modes[i].hdisplay; 4077 *y = modes[i].vdisplay; 4078 } 4079 } 4080 } 4081 4082 if ((*x == 0) || (*y == 0)) { 4083 /* fallback to safe mode */ 4084 *x = 640; 4085 *y = 480; 4086 } 4087 } 4088 4089 /* 4090 * backlight levels are linear on: 4091 * - RV200, RV250, RV280, RV350 4092 * - but NOT on PowerBook4,3 6,3 6,5 4093 * according to Linux' radeonfb 4094 */ 4095 4096 /* Get the current backlight level for the display. */ 4097 4098 static int 4099 radeonfb_get_backlight(struct radeonfb_display *dp) 4100 { 4101 int s; 4102 uint32_t level; 4103 4104 s = spltty(); 4105 4106 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4107 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4108 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4109 4110 /* 4111 * On some chips, we should negate the backlight level. 4112 * XXX Find out on which chips. 4113 */ 4114 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4115 level = RADEONFB_BACKLIGHT_MAX - level; 4116 4117 splx(s); 4118 4119 return level; 4120 } 4121 4122 /* Set the backlight to the given level for the display. */ 4123 static void 4124 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4125 { 4126 if (dp->rd_bl_on == on) 4127 return; 4128 dp->rd_bl_on = on; 4129 radeonfb_set_backlight(dp, dp->rd_bl_level); 4130 } 4131 4132 static int 4133 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4134 { 4135 struct radeonfb_softc *sc = dp->rd_softc;; 4136 int rlevel, s; 4137 uint32_t lvds; 4138 4139 if(!sc->sc_mapped) 4140 return 0; 4141 4142 s = spltty(); 4143 4144 dp->rd_bl_level = level; 4145 if (dp->rd_bl_on == 0) 4146 level = 0; 4147 4148 if (level < 0) 4149 level = 0; 4150 else if (level >= RADEONFB_BACKLIGHT_MAX) 4151 level = RADEONFB_BACKLIGHT_MAX; 4152 4153 /* On some chips, we should negate the backlight level. */ 4154 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4155 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4156 } else 4157 rlevel = level; 4158 4159 callout_stop(&dp->rd_bl_lvds_co); 4160 radeonfb_engine_idle(sc); 4161 4162 /* 4163 * Turn off the display if the backlight is set to 0, since the 4164 * display is useless without backlight anyway. 4165 */ 4166 if (level == 0) 4167 radeonfb_blank(dp, 1); 4168 else if (radeonfb_get_backlight(dp) == 0) 4169 radeonfb_blank(dp, 0); 4170 4171 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4172 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4173 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4174 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4175 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4176 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4177 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4178 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4179 lvds |= RADEON_LVDS_ON; 4180 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4181 } else { 4182 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4183 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4184 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4185 } 4186 4187 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4188 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4189 /* XXX What is the correct delay? */ 4190 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4191 4192 splx(s); 4193 4194 return 0; 4195 } 4196 4197 /* 4198 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4199 * Set the delayed bits in the register, and clear the stored delayed 4200 * value. 4201 */ 4202 4203 static void radeonfb_lvds_callout(void *arg) 4204 { 4205 struct radeonfb_display *dp = arg; 4206 int s; 4207 4208 s = splhigh(); 4209 4210 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4211 dp->rd_bl_lvds_val); 4212 dp->rd_bl_lvds_val = 0; 4213 4214 splx(s); 4215 } 4216 4217 static void 4218 radeonfb_brightness_up(device_t dev) 4219 { 4220 struct radeonfb_softc *sc = device_private(dev); 4221 struct radeonfb_display *dp = &sc->sc_displays[0]; 4222 int level; 4223 4224 /* we assume the main display is the first one - need a better way */ 4225 if (sc->sc_ndisplays < 1) return; 4226 /* make sure pushing the hotkeys always has an effect */ 4227 dp->rd_bl_on = 1; 4228 level = dp->rd_bl_level; 4229 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4230 radeonfb_set_backlight(dp, level); 4231 } 4232 4233 static void 4234 radeonfb_brightness_down(device_t dev) 4235 { 4236 struct radeonfb_softc *sc = device_private(dev); 4237 struct radeonfb_display *dp = &sc->sc_displays[0]; 4238 int level; 4239 4240 /* we assume the main display is the first one - need a better way */ 4241 if (sc->sc_ndisplays < 1) return; 4242 /* make sure pushing the hotkeys always has an effect */ 4243 dp->rd_bl_on = 1; 4244 level = dp->rd_bl_level; 4245 level = max(0, level - 5); 4246 radeonfb_set_backlight(dp, level); 4247 } 4248
Indexes created Fri Sep 26 20:09:58 GMT 2025