radeonfb.c revision 1.92
1 /* $NetBSD: radeonfb.c,v 1.92 2017/08/25 22:45:33 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.92 2017/08/25 22:45:33 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 482 /* enable memory and IO access */ 483 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 484 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 485 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 486 487 /* 488 * Some flags are general to entire chip families, and rather 489 * than clutter up the table with them, we go ahead and set 490 * them here. 491 */ 492 switch (sc->sc_family) { 493 case RADEON_RS100: 494 case RADEON_RS200: 495 sc->sc_flags |= RFB_IGP | RFB_RV100; 496 break; 497 498 case RADEON_RV100: 499 case RADEON_RV200: 500 case RADEON_RV250: 501 case RADEON_RV280: 502 sc->sc_flags |= RFB_RV100; 503 break; 504 505 case RADEON_RS300: 506 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 507 break; 508 509 case RADEON_R300: 510 case RADEON_RV350: 511 case RADEON_R350: 512 case RADEON_RV380: 513 case RADEON_R420: 514 /* newer chips */ 515 sc->sc_flags |= RFB_R300; 516 break; 517 518 case RADEON_R100: 519 sc->sc_flags |= RFB_NCRTC2; 520 break; 521 } 522 523 if ((sc->sc_family == RADEON_RV200) || 524 (sc->sc_family == RADEON_RV250) || 525 (sc->sc_family == RADEON_RV280) || 526 (sc->sc_family == RADEON_RV350)) { 527 bool inverted = 0; 528 /* backlight level is linear */ 529 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 530 prop_dictionary_get_bool(device_properties(sc->sc_dev), 531 "backlight_level_reverted", &inverted); 532 if (inverted) { 533 DPRINTF(("nope, it's inverted\n")); 534 sc->sc_flags |= RFB_INV_BLIGHT; 535 } 536 } else 537 sc->sc_flags |= RFB_INV_BLIGHT; 538 539 /* 540 * XXX: to support true multihead, this must change. 541 */ 542 sc->sc_ndisplays = 1; 543 544 /* XXX: */ 545 if (!HAS_CRTC2(sc)) { 546 sc->sc_ndisplays = 1; 547 } 548 549 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 550 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 551 &sc->sc_regsz) != 0) { 552 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 553 goto error; 554 } 555 556 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 557 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 558 { 559 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 560 goto error; 561 } 562 sc->sc_romt = sc->sc_memt; 563 564 sc->sc_mapped = TRUE; 565 566 /* scratch register test... */ 567 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 568 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 569 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 570 goto error; 571 } 572 573 PRINTREG(RADEON_CRTC_EXT_CNTL); 574 PRINTREG(RADEON_CRTC_GEN_CNTL); 575 PRINTREG(RADEON_CRTC2_GEN_CNTL); 576 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 577 PRINTREG(RADEON_DAC_CNTL2); 578 PRINTREG(RADEON_BIOS_4_SCRATCH); 579 PRINTREG(RADEON_FP_GEN_CNTL); 580 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 581 PRINTREG(RADEON_FP2_GEN_CNTL); 582 PRINTREG(RADEON_TMDS_CNTL); 583 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 584 PRINTREG(RADEON_TMDS_PLL_CNTL); 585 PRINTREG(RADEON_LVDS_GEN_CNTL); 586 PRINTREG(RADEON_DISP_HW_DEBUG); 587 PRINTREG(RADEON_PIXCLKS_CNTL); 588 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 589 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 590 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 592 if (IS_RV100(sc)) 593 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 594 595 /* XXX 596 * according to xf86-video-radeon R3xx has this bit backwards 597 */ 598 if (IS_R300(sc)) { 599 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 600 0, 601 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 602 } else { 603 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 604 RADEON_TMDS_TRANSMITTER_PLLEN, 605 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 606 } 607 608 radeonfb_i2c_init(sc); 609 610 radeonfb_loadbios(sc, pa); 611 612 #ifdef RADEONFB_BIOS_INIT 613 if (radeonfb_bios_init(sc)) { 614 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 615 } 616 #endif 617 618 if (radeonfb_getclocks(sc)) { 619 aprint_error("%s: Unable to get reference clocks from BIOS\n", 620 XNAME(sc)); 621 goto error; 622 } 623 624 if (radeonfb_gettmds(sc)) { 625 aprint_error("%s: Unable to identify TMDS PLL settings\n", 626 XNAME(sc)); 627 goto error; 628 } 629 630 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 631 "minpll = %d, maxpll = %d\n", XNAME(sc), 632 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 633 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 634 635 radeonfb_getconnectors(sc); 636 637 radeonfb_set_fbloc(sc); 638 639 /* 64 MB should be enough -- more just wastes map entries */ 640 if (sc->sc_memsz > (64 << 20)) 641 sc->sc_memsz = (64 << 20); 642 643 for (i = 0; radeonfb_limits[i].size; i++) { 644 if (sc->sc_memsz >= radeonfb_limits[i].size) { 645 sc->sc_maxx = radeonfb_limits[i].maxx; 646 sc->sc_maxy = radeonfb_limits[i].maxy; 647 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 648 /* framebuffer offset, start at a 4K page */ 649 sc->sc_fboffset = sc->sc_memsz / 650 radeonfb_limits[i].maxdisp; 651 /* 652 * we use the fbsize to figure out where we can store 653 * things like cursor data. 654 */ 655 sc->sc_fbsize = 656 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 657 RADEON_STRIDEALIGN) * sc->sc_maxy, 658 4096); 659 break; 660 } 661 } 662 663 664 radeonfb_init_misc(sc); 665 666 /* program the DAC wirings */ 667 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 668 switch (sc->sc_ports[i].rp_dac_type) { 669 case RADEON_DAC_PRIMARY: 670 PATCH32(sc, RADEON_DAC_CNTL2, 671 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 672 ~RADEON_DAC2_DAC_CLK_SEL); 673 break; 674 case RADEON_DAC_TVDAC: 675 /* we always use the TVDAC to drive a secondary analog 676 * CRT for now. if we ever support TV-out this will 677 * have to change. 678 */ 679 SET32(sc, RADEON_DAC_CNTL2, 680 RADEON_DAC2_DAC2_CLK_SEL); 681 PATCH32(sc, RADEON_DISP_HW_DEBUG, 682 i ? 0 : RADEON_CRT2_DISP1_SEL, 683 ~RADEON_CRT2_DISP1_SEL); 684 /* we're using CRTC2 for the 2nd port */ 685 if (sc->sc_ports[i].rp_number == 1) { 686 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 687 RADEON_DISP_DAC2_SOURCE_CRTC2, 688 ~RADEON_DISP_DAC2_SOURCE_MASK); 689 } 690 691 break; 692 } 693 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 694 sc->sc_ports[i].rp_tmds_type)); 695 switch (sc->sc_ports[i].rp_tmds_type) { 696 case RADEON_TMDS_INT: 697 /* point FP0 at the CRTC this port uses */ 698 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 699 __func__, sc->sc_ports[i].rp_number)); 700 if (IS_R300(sc)) { 701 PATCH32(sc, RADEON_FP_GEN_CNTL, 702 sc->sc_ports[i].rp_number ? 703 R200_FP_SOURCE_SEL_CRTC2 : 704 R200_FP_SOURCE_SEL_CRTC1, 705 ~R200_FP_SOURCE_SEL_MASK); 706 } else { 707 PATCH32(sc, RADEON_FP_GEN_CNTL, 708 sc->sc_ports[i].rp_number ? 709 RADEON_FP_SEL_CRTC2 : 710 RADEON_FP_SEL_CRTC1, 711 ~RADEON_FP_SEL_MASK); 712 } 713 case RADEON_TMDS_EXT: 714 /* point FP2 at the CRTC this port uses */ 715 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 716 __func__, sc->sc_ports[i].rp_number)); 717 if (IS_R300(sc)) { 718 PATCH32(sc, RADEON_FP2_GEN_CNTL, 719 sc->sc_ports[i].rp_number ? 720 R200_FP2_SOURCE_SEL_CRTC2 : 721 R200_FP2_SOURCE_SEL_CRTC1, 722 ~R200_FP2_SOURCE_SEL_CRTC2); 723 } else { 724 PATCH32(sc, RADEON_FP2_GEN_CNTL, 725 sc->sc_ports[i].rp_number ? 726 RADEON_FP2_SRC_SEL_CRTC2 : 727 RADEON_FP2_SRC_SEL_CRTC1, 728 ~RADEON_FP2_SRC_SEL_CRTC2); 729 } 730 } 731 } 732 PRINTREG(RADEON_DAC_CNTL2); 733 PRINTREG(RADEON_DISP_HW_DEBUG); 734 735 PRINTREG(RADEON_DAC_CNTL); 736 /* other DAC programming */ 737 v = GET32(sc, RADEON_DAC_CNTL); 738 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 739 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 740 PUT32(sc, RADEON_DAC_CNTL, v); 741 PRINTREG(RADEON_DAC_CNTL); 742 743 /* XXX: this may need more investigation */ 744 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 745 PRINTREG(RADEON_TV_DAC_CNTL); 746 747 /* enable TMDS */ 748 SET32(sc, RADEON_FP_GEN_CNTL, 749 RADEON_FP_TMDS_EN | 750 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 751 RADEON_FP_CRTC_DONT_SHADOW_HEND); 752 /* 753 * XXX 754 * no idea why this is necessary - if I do not clear this bit on my 755 * iBook G4 the screen remains black, even though it's already clear. 756 * It needs to be set on my Sun XVR-100 for the DVI port to work 757 * TODO: 758 * see if this is still necessary now that CRTCs, DACs and outputs are 759 * getting wired up in a halfway sane way 760 */ 761 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 762 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 763 } else { 764 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 765 } 766 767 /* 768 * we use bus_space_map instead of pci_mapreg, because we don't 769 * need the full aperature space. no point in wasting virtual 770 * address space we don't intend to use, right? 771 */ 772 if ((sc->sc_memsz < (4096 * 1024)) || 773 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 774 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 775 (bsz < sc->sc_memsz)) { 776 sc->sc_memsz = 0; 777 aprint_error("%s: Bad frame buffer configuration\n", 778 XNAME(sc)); 779 goto error; 780 } 781 782 sc->sc_memt = pa->pa_memt; 783 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 784 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 785 sc->sc_memsz = 0; 786 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 787 goto error; 788 } 789 790 aprint_normal("%s: %d MB aperture at 0x%08x, " 791 "%d KB registers at 0x%08x\n", XNAME(sc), 792 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 793 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 794 795 /* setup default video mode from devprop (allows PROM override) */ 796 sc->sc_defaultmode = radeonfb_default_mode; 797 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 798 "videomode", &mptr)) { 799 800 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 801 sc->sc_defaultmode = sc->sc_modebuf; 802 } 803 804 /* initialize some basic display parameters */ 805 for (i = 0; i < sc->sc_ndisplays; i++) { 806 struct radeonfb_display *dp = &sc->sc_displays[i]; 807 struct rasops_info *ri; 808 long defattr; 809 struct wsemuldisplaydev_attach_args aa; 810 811 /* 812 * Figure out how many "displays" (desktops) we are going to 813 * support. If more than one, then each CRTC gets its own 814 * programming. 815 * 816 * XXX: this code needs to change to support mergedfb. 817 * XXX: would be nice to allow this to be overridden 818 */ 819 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 820 DPRINTF(("dual crtcs!\n")); 821 dp->rd_ncrtcs = 2; 822 dp->rd_crtcs[0].rc_port = 823 &sc->sc_ports[0]; 824 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 825 dp->rd_crtcs[1].rc_port = 826 &sc->sc_ports[1]; 827 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 828 } else { 829 dp->rd_ncrtcs = 1; 830 dp->rd_crtcs[0].rc_port = 831 &sc->sc_ports[i]; 832 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 833 } 834 835 dp->rd_softc = sc; 836 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 837 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 838 839 /* for text mode, we pick a resolution that won't 840 * require panning */ 841 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 842 843 aprint_normal("%s: display %d: " 844 "initial virtual resolution %dx%d at %d bpp\n", 845 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 846 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 847 sc->sc_fboffset >> 20); 848 /* now select the *video mode* that we will use */ 849 for (j = 0; j < dp->rd_ncrtcs; j++) { 850 const struct videomode *vmp; 851 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 852 dp->rd_virtx, dp->rd_virty); 853 854 /* 855 * virtual resolution should be at least as high as 856 * physical 857 */ 858 if (dp->rd_virtx < vmp->hdisplay || 859 dp->rd_virty < vmp->vdisplay) { 860 dp->rd_virtx = vmp->hdisplay; 861 dp->rd_virty = vmp->vdisplay; 862 } 863 864 dp->rd_crtcs[j].rc_videomode = *vmp; 865 printf("%s: port %d: physical %dx%d %dHz\n", 866 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 867 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 868 vmp->htotal), vmp->vtotal)); 869 } 870 871 /* N.B.: radeon wants 64-byte aligned stride */ 872 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 873 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 874 DPRINTF(("stride: %d\n", dp->rd_stride)); 875 876 dp->rd_offset = sc->sc_fboffset * i; 877 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 878 sc->sc_memh) + dp->rd_offset; 879 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 880 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 881 882 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 883 884 switch (dp->rd_bpp) { 885 case 8: 886 dp->rd_format = 2; 887 break; 888 case 32: 889 dp->rd_format = 6; 890 break; 891 default: 892 aprint_error("%s: bad depth %d\n", XNAME(sc), 893 dp->rd_bpp); 894 goto error; 895 } 896 897 DPRINTF(("init engine\n")); 898 /* XXX: this seems suspicious - per display engine 899 initialization? */ 900 radeonfb_engine_init(dp); 901 902 /* copy the template into place */ 903 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 904 dp->rd_wsscreens = dp->rd_wsscreens_storage; 905 906 /* and make up the list */ 907 dp->rd_wsscreenlist.nscreens = 1; 908 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 909 910 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 911 &radeonfb_accessops); 912 913 dp->rd_vd.init_screen = radeonfb_init_screen; 914 915 #ifdef RADEONFB_DEBUG 916 dp->rd_virty -= 200; 917 #endif 918 919 dp->rd_console = 0; 920 prop_dictionary_get_bool(device_properties(sc->sc_dev), 921 "is_console", &dp->rd_console); 922 923 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 924 925 926 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 927 dp->rd_console, &defattr); 928 929 ri = &dp->rd_vscreen.scr_ri; 930 931 /* clear the screen */ 932 rasops_unpack_attr(defattr, &fg, &bg, &ul); 933 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 934 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 935 dp->rd_bg); 936 937 dp->rd_wsscreens->textops = &ri->ri_ops; 938 dp->rd_wsscreens->capabilities = ri->ri_caps; 939 dp->rd_wsscreens->nrows = ri->ri_rows; 940 dp->rd_wsscreens->ncols = ri->ri_cols; 941 942 #ifdef SPLASHSCREEN 943 dp->rd_splash.si_depth = ri->ri_depth; 944 dp->rd_splash.si_bits = ri->ri_bits; 945 dp->rd_splash.si_hwbits = ri->ri_hwbits; 946 dp->rd_splash.si_width = ri->ri_width; 947 dp->rd_splash.si_height = ri->ri_height; 948 dp->rd_splash.si_stride = ri->ri_stride; 949 dp->rd_splash.si_fillrect = NULL; 950 #endif 951 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 952 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 953 dp->rd_gc.gc_rop = RADEON_ROP3_S; 954 dp->rd_gc.gc_blitcookie = dp; 955 /* 956 * use memory between framebuffer and cursor area as glyph 957 * cache, cap at 4096 lines 958 */ 959 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 960 min(4096, 961 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 962 dp->rd_virtx, 963 ri->ri_font->fontwidth, 964 ri->ri_font->fontheight, 965 defattr); 966 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 967 dp->rd_vd.show_screen_cb = glyphcache_adapt; 968 969 if (dp->rd_console) { 970 971 radeonfb_modeswitch(dp); 972 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 973 defattr); 974 #ifdef SPLASHSCREEN 975 if (splash_render(&dp->rd_splash, 976 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 977 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 978 else 979 #endif 980 vcons_replay_msgbuf(&dp->rd_vscreen); 981 } else { 982 983 /* 984 * since we're not the console we can postpone 985 * the rest until someone actually allocates a 986 * screen for us. but we do clear the screen 987 * at least. 988 */ 989 memset(ri->ri_bits, 0, 1024); 990 991 radeonfb_modeswitch(dp); 992 #ifdef SPLASHSCREEN 993 if (splash_render(&dp->rd_splash, 994 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 995 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 996 #endif 997 } 998 999 aa.console = dp->rd_console; 1000 aa.scrdata = &dp->rd_wsscreenlist; 1001 aa.accessops = &radeonfb_accessops; 1002 aa.accesscookie = &dp->rd_vd; 1003 1004 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1005 1006 radeonfb_blank(dp, 0); 1007 1008 /* Initialise delayed lvds operations for backlight. */ 1009 callout_init(&dp->rd_bl_lvds_co, 0); 1010 callout_setfunc(&dp->rd_bl_lvds_co, 1011 radeonfb_lvds_callout, dp); 1012 dp->rd_bl_on = 1; 1013 dp->rd_bl_level = radeonfb_get_backlight(dp); 1014 radeonfb_set_backlight(dp, dp->rd_bl_level); 1015 } 1016 1017 for (i = 0; i < RADEON_NDISPLAYS; i++) 1018 radeonfb_init_palette(&sc->sc_displays[i]); 1019 1020 if (HAS_CRTC2(sc)) { 1021 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1022 } 1023 1024 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1025 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1026 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1027 radeonfb_brightness_up, TRUE); 1028 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1029 radeonfb_brightness_down, TRUE); 1030 1031 /* 1032 * if we attach a DRM we need to unmap registers in 1033 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1034 * screen blanking we only do it if needed 1035 */ 1036 sc->sc_needs_unmap = 1037 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1038 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1039 1040 PRINTREG(RADEON_CRTC_EXT_CNTL); 1041 PRINTREG(RADEON_CRTC_GEN_CNTL); 1042 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1043 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1044 PRINTREG(RADEON_DAC_CNTL2); 1045 PRINTREG(RADEON_FP_GEN_CNTL); 1046 PRINTREG(RADEON_FP2_GEN_CNTL); 1047 PRINTREG(RADEON_TMDS_CNTL); 1048 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1049 PRINTREG(RADEON_TMDS_PLL_CNTL); 1050 PRINTREG(RADEON_PIXCLKS_CNTL); 1051 1052 return; 1053 1054 error: 1055 if (sc->sc_biossz) 1056 free(sc->sc_bios, M_DEVBUF); 1057 1058 if (sc->sc_regsz) 1059 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1060 1061 if (sc->sc_memsz) 1062 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1063 } 1064 1065 static void 1066 radeonfb_map(struct radeonfb_softc *sc) 1067 { 1068 if (!sc->sc_mapped) { 1069 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1070 &sc->sc_regh) != 0) { 1071 aprint_error_dev(sc->sc_dev, 1072 "unable to map registers!\n"); 1073 return; 1074 } 1075 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1076 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1077 sc->sc_memsz = 0; 1078 aprint_error_dev(sc->sc_dev, 1079 "Unable to map frame buffer\n"); 1080 return; 1081 } 1082 sc->sc_mapped = TRUE; 1083 } 1084 } 1085 1086 static void 1087 radeonfb_unmap(struct radeonfb_softc *sc) 1088 { 1089 if (!sc->sc_needs_unmap) 1090 return; 1091 1092 if (sc->sc_mapped) { 1093 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1094 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1095 sc->sc_mapped = FALSE; 1096 } 1097 } 1098 1099 static int 1100 radeonfb_drm_print(void *aux, const char *pnp) 1101 { 1102 if (pnp) 1103 aprint_normal("drm at %s", pnp); 1104 return (UNCONF); 1105 } 1106 1107 int 1108 radeonfb_ioctl(void *v, void *vs, 1109 unsigned long cmd, void *d, int flag, struct lwp *l) 1110 { 1111 struct vcons_data *vd; 1112 struct radeonfb_display *dp; 1113 struct radeonfb_softc *sc; 1114 struct wsdisplay_param *param; 1115 struct vcons_screen *ms; 1116 1117 vd = (struct vcons_data *)v; 1118 ms = vd->active; 1119 dp = (struct radeonfb_display *)vd->cookie; 1120 sc = dp->rd_softc; 1121 1122 /* can't do these without registers being mapped */ 1123 if (!sc->sc_mapped) { 1124 switch (cmd) { 1125 case WSDISPLAYIO_GVIDEO: 1126 case WSDISPLAYIO_SVIDEO: 1127 case WSDISPLAYIO_GETCMAP: 1128 case WSDISPLAYIO_PUTCMAP: 1129 case WSDISPLAYIO_SCURSOR: 1130 case WSDISPLAYIO_GCURPOS: 1131 case WSDISPLAYIO_SCURPOS: 1132 case WSDISPLAYIO_SETPARAM: 1133 return EINVAL; 1134 } 1135 } 1136 1137 switch (cmd) { 1138 case WSDISPLAYIO_GTYPE: 1139 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1140 return 0; 1141 1142 case WSDISPLAYIO_GINFO: 1143 if (vd->active != NULL) { 1144 struct wsdisplay_fbinfo *fb; 1145 fb = (struct wsdisplay_fbinfo *)d; 1146 fb->width = dp->rd_virtx; 1147 fb->height = dp->rd_virty; 1148 fb->depth = dp->rd_bpp; 1149 fb->cmsize = 256; 1150 return 0; 1151 } else 1152 return ENODEV; 1153 case WSDISPLAYIO_GVIDEO: 1154 if (radeonfb_isblank(dp)) 1155 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1156 else 1157 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1158 return 0; 1159 1160 case WSDISPLAYIO_SVIDEO: 1161 radeonfb_blank(dp, 1162 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1163 radeonfb_switch_backlight(dp, 1164 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1165 return 0; 1166 1167 case WSDISPLAYIO_GETCMAP: 1168 if (dp->rd_bpp == 8) 1169 return radeonfb_getcmap(dp, 1170 (struct wsdisplay_cmap *)d); 1171 return EINVAL; 1172 1173 case WSDISPLAYIO_PUTCMAP: 1174 if (dp->rd_bpp == 8) 1175 return radeonfb_putcmap(dp, 1176 (struct wsdisplay_cmap *)d); 1177 return EINVAL; 1178 1179 case WSDISPLAYIO_LINEBYTES: 1180 *(unsigned *)d = dp->rd_stride; 1181 return 0; 1182 1183 case WSDISPLAYIO_SMODE: 1184 if (*(int *)d != dp->rd_wsmode) { 1185 dp->rd_wsmode = *(int *)d; 1186 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1187 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1188 radeonfb_map(sc); 1189 1190 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1191 (dp->rd_vd.active)) { 1192 radeonfb_engine_init(dp); 1193 glyphcache_wipe(&dp->rd_gc); 1194 radeonfb_init_palette(dp); 1195 radeonfb_modeswitch(dp); 1196 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1197 dp->rd_virty, dp->rd_bg); 1198 vcons_redraw_screen(dp->rd_vd.active); 1199 } 1200 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1201 radeonfb_unmap(sc); 1202 } 1203 return 0; 1204 1205 case WSDISPLAYIO_GCURMAX: 1206 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1207 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1208 return 0; 1209 1210 case WSDISPLAYIO_SCURSOR: 1211 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1212 1213 case WSDISPLAYIO_GCURSOR: 1214 return EPASSTHROUGH; 1215 1216 case WSDISPLAYIO_GCURPOS: 1217 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1218 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1219 return 0; 1220 1221 case WSDISPLAYIO_SCURPOS: 1222 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1223 1224 case WSDISPLAYIO_SSPLASH: 1225 #if defined(SPLASHSCREEN) 1226 if (*(int *)d == 1) { 1227 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1228 splash_render(&dp->rd_splash, 1229 SPLASH_F_CENTER|SPLASH_F_FILL); 1230 } else 1231 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1232 return 0; 1233 #else 1234 return ENODEV; 1235 #endif 1236 case WSDISPLAYIO_GETPARAM: 1237 param = (struct wsdisplay_param *)d; 1238 switch (param->param) { 1239 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1240 param->min = 0; 1241 param->max = 255; 1242 param->curval = dp->rd_bl_level; 1243 return 0; 1244 case WSDISPLAYIO_PARAM_BACKLIGHT: 1245 param->min = 0; 1246 param->max = RADEONFB_BACKLIGHT_MAX; 1247 param->curval = dp->rd_bl_on; 1248 return 0; 1249 } 1250 return EPASSTHROUGH; 1251 1252 case WSDISPLAYIO_SETPARAM: 1253 param = (struct wsdisplay_param *)d; 1254 switch (param->param) { 1255 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1256 radeonfb_set_backlight(dp, param->curval); 1257 return 0; 1258 case WSDISPLAYIO_PARAM_BACKLIGHT: 1259 radeonfb_switch_backlight(dp, param->curval); 1260 return 0; 1261 } 1262 return EPASSTHROUGH; 1263 1264 /* PCI config read/write passthrough. */ 1265 case PCI_IOC_CFGREAD: 1266 case PCI_IOC_CFGWRITE: 1267 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1268 1269 case WSDISPLAYIO_GET_BUSID: 1270 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1271 sc->sc_pt, d); 1272 1273 case WSDISPLAYIO_GET_EDID: { 1274 struct wsdisplayio_edid_info *ei = d; 1275 return wsdisplayio_get_edid(sc->sc_dev, ei); 1276 } 1277 1278 case WSDISPLAYIO_GET_FBINFO: { 1279 struct wsdisplayio_fbinfo *fbi = d; 1280 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1281 } 1282 1283 default: 1284 return EPASSTHROUGH; 1285 } 1286 } 1287 1288 paddr_t 1289 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1290 { 1291 struct vcons_data *vd; 1292 struct radeonfb_display *dp; 1293 struct radeonfb_softc *sc; 1294 paddr_t pa; 1295 1296 vd = (struct vcons_data *)v; 1297 dp = (struct radeonfb_display *)vd->cookie; 1298 sc = dp->rd_softc; 1299 1300 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1301 pa = bus_space_mmap(sc->sc_memt, 1302 sc->sc_memaddr + dp->rd_offset + offset, 0, 1303 prot, BUS_SPACE_MAP_LINEAR); 1304 return pa; 1305 } 1306 1307 /* 1308 * restrict all other mappings to processes with superuser privileges 1309 * or the kernel itself 1310 */ 1311 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1312 NULL, NULL, NULL, NULL) != 0) { 1313 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1314 return -1; 1315 } 1316 1317 if ((offset >= sc->sc_regaddr) && 1318 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1319 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1320 BUS_SPACE_MAP_LINEAR); 1321 } 1322 1323 if ((offset >= sc->sc_memaddr) && 1324 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1325 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1326 BUS_SPACE_MAP_LINEAR); 1327 } 1328 1329 if ((offset >= sc->sc_romaddr) && 1330 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1331 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1332 BUS_SPACE_MAP_LINEAR); 1333 } 1334 1335 #ifdef PCI_MAGIC_IO_RANGE 1336 /* allow mapping of IO space */ 1337 if ((offset >= PCI_MAGIC_IO_RANGE) && 1338 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1339 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1340 0, prot, 0); 1341 return pa; 1342 } 1343 #endif /* PCI_MAGIC_IO_RANGE */ 1344 1345 return -1; 1346 } 1347 1348 static void 1349 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1350 { 1351 bus_space_tag_t romt; 1352 bus_space_handle_t romh, biosh; 1353 bus_size_t romsz; 1354 bus_addr_t ptr; 1355 1356 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1357 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1358 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1359 return; 1360 } 1361 1362 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1363 &sc->sc_biossz); 1364 if (sc->sc_biossz == 0) { 1365 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1366 return; 1367 } 1368 1369 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1370 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1371 1372 /* unmap the PCI expansion rom */ 1373 bus_space_unmap(romt, romh, romsz); 1374 1375 /* turn off rom decoder now */ 1376 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1377 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1378 ~PCI_MAPREG_ROM_ENABLE); 1379 1380 ptr = GETBIOS16(sc, 0x48); 1381 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1382 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1383 sc->sc_flags |= RFB_ATOM; 1384 } 1385 1386 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1387 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1388 } 1389 1390 1391 uint32_t 1392 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1393 { 1394 1395 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1396 } 1397 1398 void 1399 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1400 { 1401 1402 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1403 } 1404 1405 void 1406 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1407 { 1408 1409 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1410 } 1411 1412 void 1413 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1414 uint32_t andmask, uint32_t ormask) 1415 { 1416 int s; 1417 uint32_t val; 1418 1419 s = splhigh(); 1420 val = radeonfb_get32(sc, reg); 1421 val = (val & andmask) | ormask; 1422 radeonfb_put32(sc, reg, val); 1423 splx(s); 1424 } 1425 1426 uint32_t 1427 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1428 { 1429 int s; 1430 uint32_t val; 1431 1432 s = splhigh(); 1433 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1434 val = radeonfb_get32(sc, RADEON_MM_DATA); 1435 splx(s); 1436 1437 return (val); 1438 } 1439 1440 void 1441 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1442 { 1443 int s; 1444 1445 s = splhigh(); 1446 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1447 radeonfb_put32(sc, RADEON_MM_DATA, val); 1448 splx(s); 1449 } 1450 1451 void 1452 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1453 uint32_t andmask, uint32_t ormask) 1454 { 1455 int s; 1456 uint32_t val; 1457 1458 s = splhigh(); 1459 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1460 val = radeonfb_get32(sc, RADEON_MM_DATA); 1461 val = (val & andmask) | ormask; 1462 radeonfb_put32(sc, RADEON_MM_DATA, val); 1463 splx(s); 1464 } 1465 1466 uint32_t 1467 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1468 { 1469 int s; 1470 uint32_t val; 1471 1472 s = splhigh(); 1473 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1474 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1475 if (HAS_R300CG(sc)) 1476 radeonfb_r300cg_workaround(sc); 1477 splx(s); 1478 1479 return (val); 1480 } 1481 1482 void 1483 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1484 { 1485 int s; 1486 1487 s = splhigh(); 1488 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1489 RADEON_PLL_WR_EN); 1490 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1491 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1492 splx(s); 1493 } 1494 1495 void 1496 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1497 uint32_t andmask, uint32_t ormask) 1498 { 1499 int s; 1500 uint32_t val; 1501 1502 s = splhigh(); 1503 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1504 RADEON_PLL_WR_EN); 1505 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1506 val = (val & andmask) | ormask; 1507 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1508 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1509 splx(s); 1510 } 1511 1512 int 1513 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1514 { 1515 uint32_t saved; 1516 1517 saved = GET32(sc, reg); 1518 PUT32(sc, reg, v); 1519 if (GET32(sc, reg) != v) { 1520 return -1; 1521 } 1522 PUT32(sc, reg, saved); 1523 return 0; 1524 } 1525 1526 uintmax_t 1527 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1528 uintmax_t defval) 1529 { 1530 prop_number_t pn; 1531 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1532 if (pn == NULL) { 1533 return defval; 1534 } 1535 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1536 return (prop_number_integer_value(pn)); 1537 } 1538 1539 int 1540 radeonfb_getclocks(struct radeonfb_softc *sc) 1541 { 1542 bus_addr_t ptr; 1543 int refclk = 0; 1544 int refdiv = 0; 1545 int minpll = 0; 1546 int maxpll = 0; 1547 1548 /* load initial property values if port/board provides them */ 1549 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1550 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1551 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1552 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1553 1554 PRINTPLL(RADEON_PPLL_REF_DIV); 1555 PRINTPLL(RADEON_PPLL_DIV_0); 1556 PRINTPLL(RADEON_PPLL_DIV_1); 1557 PRINTPLL(RADEON_PPLL_DIV_2); 1558 PRINTPLL(RADEON_PPLL_DIV_3); 1559 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1560 PRINTPLL(RADEON_P2PLL_REF_DIV); 1561 PRINTPLL(RADEON_P2PLL_DIV_0); 1562 1563 if (refclk && refdiv && minpll && maxpll) 1564 goto dontprobe; 1565 1566 if (!sc->sc_biossz) { 1567 /* no BIOS */ 1568 aprint_verbose("%s: No video BIOS, using default clocks\n", 1569 XNAME(sc)); 1570 if (IS_IGP(sc)) 1571 refclk = refclk ? refclk : 1432; 1572 else 1573 refclk = refclk ? refclk : 2700; 1574 refdiv = refdiv ? refdiv : 12; 1575 minpll = minpll ? minpll : 12500; 1576 /* XXX 1577 * Need to check if the firmware or something programmed a 1578 * higher value than this, and if so, bump it. 1579 * The RV280 in my iBook is unhappy if the PLL input is less 1580 * than 360MHz 1581 */ 1582 maxpll = maxpll ? maxpll : 40000/*35000*/; 1583 } else if (IS_ATOM(sc)) { 1584 /* ATOM BIOS */ 1585 ptr = GETBIOS16(sc, 0x48); 1586 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1587 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1588 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1589 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1590 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1591 /* 1592 * ATOM BIOS doesn't supply a reference divider, so we 1593 * have to probe for it. 1594 */ 1595 if (refdiv < 2) 1596 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1597 RADEON_PPLL_REF_DIV_MASK; 1598 /* 1599 * if probe is zero, just assume one that should work 1600 * for most parts 1601 */ 1602 if (refdiv < 2) 1603 refdiv = 12; 1604 1605 } else { 1606 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1607 /* Legacy BIOS */ 1608 ptr = GETBIOS16(sc, 0x48); 1609 ptr = GETBIOS16(sc, ptr + 0x30); 1610 if (IS_R300(sc)) { 1611 refdiv = refdiv ? refdiv : 1612 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1613 R300_PPLL_REF_DIV_ACC_SHIFT; 1614 } else { 1615 refdiv = refdiv ? refdiv : 1616 tmp & RADEON_PPLL_REF_DIV_MASK; 1617 } 1618 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1619 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1620 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1621 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1622 } 1623 1624 1625 dontprobe: 1626 sc->sc_refclk = refclk * 10; 1627 sc->sc_refdiv = refdiv; 1628 sc->sc_minpll = minpll * 10; 1629 sc->sc_maxpll = maxpll * 10; 1630 return 0; 1631 } 1632 1633 int 1634 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1635 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1636 { 1637 int i; 1638 uint32_t outfreq; 1639 int div; 1640 1641 DPRINTF(("dot clock: %u\n", dotclock)); 1642 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1643 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) continue; 1644 outfreq = div * dotclock; 1645 if ((outfreq >= sc->sc_minpll) && 1646 (outfreq <= sc->sc_maxpll)) { 1647 DPRINTF(("outfreq: %u\n", outfreq)); 1648 *postdivbit = 1649 ((uint32_t)radeonfb_dividers[i].mask << 16); 1650 DPRINTF(("post divider: %d (mask %x)\n", div, 1651 *postdivbit)); 1652 break; 1653 } 1654 } 1655 1656 if (div == 0) 1657 return 1; 1658 1659 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1660 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1661 return 0; 1662 } 1663 1664 #if 0 1665 #ifdef RADEONFB_DEBUG 1666 static void 1667 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1668 { 1669 char asc[17]; 1670 unsigned ptr = (unsigned)buffer; 1671 char *start = (char *)(ptr & ~0xf); 1672 char *end = (char *)(ptr + size); 1673 1674 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1675 1676 if (pfx == NULL) { 1677 pfx = ""; 1678 } 1679 1680 while (start < end) { 1681 unsigned offset = (unsigned)start & 0xf; 1682 if (offset == 0) { 1683 printf("%s%x: ", pfx, (unsigned)start); 1684 } 1685 if (((unsigned)start < ptr) || 1686 ((unsigned)start >= (ptr + size))) { 1687 printf(" "); 1688 asc[offset] = ' '; 1689 } else { 1690 printf("%02x", *(unsigned char *)start); 1691 if ((*start >= ' ') && (*start <= '~')) { 1692 asc[offset] = *start; 1693 } else { 1694 asc[offset] = '.'; 1695 } 1696 } 1697 asc[offset + 1] = 0; 1698 if (offset % 2) { 1699 printf(" "); 1700 } 1701 if (offset == 15) { 1702 printf(" %s\n", asc); 1703 } 1704 start++; 1705 } 1706 } 1707 #endif 1708 #endif 1709 1710 int 1711 radeonfb_getconnectors(struct radeonfb_softc *sc) 1712 { 1713 int i; 1714 int found = 0; 1715 1716 for (i = 0; i < 2; i++) { 1717 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1718 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1719 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1720 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1721 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1722 } 1723 1724 /* 1725 * This logic is borrowed from Xorg's radeon driver. 1726 */ 1727 if (!sc->sc_biossz) 1728 goto nobios; 1729 1730 if (IS_ATOM(sc)) { 1731 /* not done yet */ 1732 } else { 1733 uint16_t ptr; 1734 int port = 0; 1735 1736 ptr = GETBIOS16(sc, 0x48); 1737 ptr = GETBIOS16(sc, ptr + 0x50); 1738 for (i = 1; i < 4; i++) { 1739 uint16_t entry; 1740 uint8_t conn, ddc, dac, tmds; 1741 1742 /* 1743 * Parse the connector table. From reading the code, 1744 * it appears to made up of 16-bit entries for each 1745 * connector. The 16-bits are defined as: 1746 * 1747 * bits 12-15 - connector type (0 == end of table) 1748 * bits 8-11 - DDC type 1749 * bits 5-7 - ??? 1750 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1751 * bits 1-3 - ??? 1752 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1753 */ 1754 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1755 break; 1756 entry = GETBIOS16(sc, ptr + i * 2); 1757 1758 conn = (entry >> 12) & 0xf; 1759 ddc = (entry >> 8) & 0xf; 1760 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1761 RADEON_DAC_PRIMARY; 1762 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1763 RADEON_TMDS_INT; 1764 1765 if (conn == RADEON_CONN_NONE) 1766 continue; /* no connector */ 1767 1768 1769 1770 /* 1771 * XXX 1772 * both Mac Mini variants have both outputs wired to 1773 * the same connector and share the DDC lines 1774 */ 1775 if ((found > 0) && 1776 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1777 /* duplicate entry for same connector */ 1778 continue; 1779 } 1780 1781 /* internal DDC_DVI port gets priority */ 1782 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1783 port = 0; 1784 else 1785 port = 1; 1786 1787 sc->sc_ports[port].rp_ddc_type = 1788 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1789 sc->sc_ports[port].rp_dac_type = dac; 1790 sc->sc_ports[port].rp_conn_type = 1791 min(conn, RADEON_CONN_UNSUPPORTED) ; 1792 1793 sc->sc_ports[port].rp_tmds_type = tmds; 1794 1795 if ((conn != RADEON_CONN_DVI_I) && 1796 (conn != RADEON_CONN_DVI_D) && 1797 (tmds == RADEON_TMDS_INT)) 1798 sc->sc_ports[port].rp_tmds_type = 1799 RADEON_TMDS_UNKNOWN; 1800 sc->sc_ports[port].rp_number = i - 1; 1801 1802 found += (port + 1); 1803 } 1804 } 1805 1806 nobios: 1807 if (!found) { 1808 bool dvi_ext = FALSE, dvi_int = FALSE; 1809 DPRINTF(("No connector info in BIOS!\n")); 1810 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1811 "dvi-internal", &dvi_int); 1812 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1813 "dvi-external", &dvi_ext); 1814 if (dvi_ext) { 1815 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1816 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1817 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1818 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1819 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1820 sc->sc_ports[0].rp_number = 0; 1821 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1822 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1823 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1824 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1825 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1826 sc->sc_ports[1].rp_number = 1; 1827 } else if (dvi_int) { 1828 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1829 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1830 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1831 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1832 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1833 sc->sc_ports[0].rp_number = 0; 1834 } else if IS_MOBILITY(sc) { 1835 /* default, port 0 = internal TMDS, port 1 = CRT */ 1836 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1837 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1838 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1839 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1840 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1841 sc->sc_ports[0].rp_number = 0; 1842 1843 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1844 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1845 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1846 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1847 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1848 sc->sc_ports[1].rp_number = 1; 1849 } else { 1850 /* default, port 0 = DVI, port 1 = CRT */ 1851 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1852 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1853 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1854 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1855 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1856 sc->sc_ports[0].rp_number = 1; 1857 1858 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1859 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1860 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1861 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1862 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1863 sc->sc_ports[1].rp_number = 0; 1864 } 1865 } 1866 1867 /* 1868 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1869 * these chips should use TVDAC for the VGA port. 1870 */ 1871 if (HAS_SDAC(sc)) { 1872 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1873 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1874 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1875 } else { 1876 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1877 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1878 } 1879 } else if (!HAS_CRTC2(sc)) { 1880 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1881 } 1882 1883 for (i = 0; i < 2; i++) { 1884 char edid[128]; 1885 uint8_t ddc; 1886 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1887 prop_data_t edid_data; 1888 1889 DPRINTF(("Port #%d:\n", i)); 1890 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1891 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1892 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1893 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1894 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1895 1896 sc->sc_ports[i].rp_edid_valid = 0; 1897 /* first look for static EDID data */ 1898 if ((edid_data = prop_dictionary_get(device_properties( 1899 sc->sc_dev), "EDID")) != NULL) { 1900 1901 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1902 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1903 if (edid_parse(edid, eip) == 0) { 1904 1905 sc->sc_ports[i].rp_edid_valid = 1; 1906 } 1907 } 1908 /* if we didn't find any we'll try to talk to the monitor */ 1909 if (sc->sc_ports[i].rp_edid_valid != 1) { 1910 1911 ddc = sc->sc_ports[i].rp_ddc_type; 1912 if (ddc != RADEON_DDC_NONE) { 1913 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1914 == 0) && (edid_parse(edid, eip) == 0)) { 1915 1916 sc->sc_ports[i].rp_edid_valid = 1; 1917 #ifdef RADEONFB_DEBUG 1918 edid_print(eip); 1919 #endif 1920 } 1921 } 1922 } 1923 } 1924 1925 return found; 1926 } 1927 1928 int 1929 radeonfb_gettmds(struct radeonfb_softc *sc) 1930 { 1931 int i; 1932 1933 if (!sc->sc_biossz) { 1934 goto nobios; 1935 } 1936 1937 if (IS_ATOM(sc)) { 1938 /* XXX: not done yet */ 1939 } else { 1940 uint16_t ptr; 1941 int n; 1942 1943 ptr = GETBIOS16(sc, 0x48); 1944 ptr = GETBIOS16(sc, ptr + 0x34); 1945 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1946 if (GETBIOS8(sc, ptr) == 3) { 1947 /* revision three table */ 1948 n = GETBIOS8(sc, ptr + 5) + 1; 1949 n = min(n, 4); 1950 1951 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1952 for (i = 0; i < n; i++) { 1953 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1954 ptr + i * 10 + 8); 1955 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1956 ptr + i * 10 + 0x10); 1957 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1958 sc->sc_tmds_pll[i].rtp_freq, 1959 sc->sc_tmds_pll[i].rtp_pll)); 1960 } 1961 return 0; 1962 } 1963 } 1964 1965 nobios: 1966 DPRINTF(("no suitable DFP table present\n")); 1967 for (i = 0; 1968 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1969 i++) { 1970 int j; 1971 1972 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1973 continue; 1974 1975 for (j = 0; j < 4; j++) { 1976 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1977 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1978 sc->sc_tmds_pll[j].rtp_freq, 1979 sc->sc_tmds_pll[j].rtp_pll)); 1980 } 1981 return 0; 1982 } 1983 1984 return -1; 1985 } 1986 1987 const struct videomode * 1988 radeonfb_modelookup(const char *name) 1989 { 1990 int i; 1991 1992 for (i = 0; i < videomode_count; i++) 1993 if (!strcmp(name, videomode_list[i].name)) 1994 return &videomode_list[i]; 1995 1996 return NULL; 1997 } 1998 1999 void 2000 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2001 { 2002 if (crtc) { 2003 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2004 RADEON_P2PLL_ATOMIC_UPDATE_R); 2005 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2006 } else { 2007 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2008 RADEON_PPLL_ATOMIC_UPDATE_R); 2009 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2010 } 2011 } 2012 2013 void 2014 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2015 { 2016 int i; 2017 2018 for (i = 10000; i; i--) { 2019 if (crtc) { 2020 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2021 RADEON_P2PLL_ATOMIC_UPDATE_R) 2022 break; 2023 } else { 2024 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2025 RADEON_PPLL_ATOMIC_UPDATE_R) 2026 break; 2027 } 2028 } 2029 } 2030 2031 void 2032 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2033 { 2034 uint32_t pbit = 0; 2035 uint32_t feed = 0; 2036 uint32_t data, refdiv, div0; 2037 2038 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2039 2040 if (crtc == 0) { 2041 2042 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2043 if (IS_R300(sc)) { 2044 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2045 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2046 } else { 2047 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2048 sc->sc_refdiv; 2049 } 2050 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2051 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2052 RADEON_PPLL_POST3_DIV_MASK); 2053 div0 |= pbit; 2054 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2055 2056 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2057 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2058 /* 2059 * nothing to do here, the PLL is already where we 2060 * want it 2061 */ 2062 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2063 ~RADEON_PLL_DIV_SEL); 2064 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2065 return; 2066 } 2067 2068 /* alright, we do need to reprogram stuff */ 2069 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2070 RADEON_VCLK_SRC_SEL_CPUCLK, 2071 ~RADEON_VCLK_SRC_SEL_MASK); 2072 2073 /* put vclk into reset, use atomic updates */ 2074 SETPLL(sc, RADEON_PPLL_CNTL, 2075 RADEON_PPLL_REFCLK_SEL | 2076 RADEON_PPLL_FBCLK_SEL | 2077 RADEON_PPLL_RESET | 2078 RADEON_PPLL_ATOMIC_UPDATE_EN | 2079 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2080 2081 /* select clock 0 */ 2082 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2083 ~RADEON_PLL_DIV_SEL); 2084 2085 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2086 2087 /* xf86-video-radeon does this, not sure why */ 2088 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2089 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2090 2091 /* use the atomic update */ 2092 radeonfb_pllwriteupdate(sc, crtc); 2093 2094 /* and wait for it to complete */ 2095 radeonfb_pllwaitatomicread(sc, crtc); 2096 2097 /* program HTOTAL (why?) */ 2098 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2099 2100 /* drop reset */ 2101 CLRPLL(sc, RADEON_PPLL_CNTL, 2102 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2103 RADEON_PPLL_ATOMIC_UPDATE_EN | 2104 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2105 2106 PRINTPLL(RADEON_PPLL_CNTL); 2107 PRINTPLL(RADEON_PPLL_REF_DIV); 2108 PRINTPLL(RADEON_PPLL_DIV_3); 2109 2110 /* give clock time to lock */ 2111 delay(50000); 2112 2113 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2114 RADEON_VCLK_SRC_SEL_PPLLCLK, 2115 ~RADEON_VCLK_SRC_SEL_MASK); 2116 2117 } else { 2118 2119 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2120 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2121 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2122 2123 /* put vclk into reset, use atomic updates */ 2124 SETPLL(sc, RADEON_P2PLL_CNTL, 2125 RADEON_P2PLL_RESET | 2126 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2127 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2128 2129 /* program reference divider */ 2130 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2131 ~RADEON_P2PLL_REF_DIV_MASK); 2132 2133 /* program feedback and post dividers */ 2134 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2135 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2136 RADEON_P2PLL_POST0_DIV_MASK); 2137 data |= pbit; 2138 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2139 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2140 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2141 2142 PRINTPLL(RADEON_P2PLL_REF_DIV); 2143 PRINTPLL(RADEON_P2PLL_DIV_0); 2144 2145 /* use the atomic update */ 2146 radeonfb_pllwriteupdate(sc, crtc); 2147 2148 /* and wait for it to complete */ 2149 radeonfb_pllwaitatomicread(sc, crtc); 2150 2151 /* program HTOTAL (why?) */ 2152 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2153 2154 /* drop reset */ 2155 CLRPLL(sc, RADEON_P2PLL_CNTL, 2156 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2157 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2158 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2159 2160 /* allow time for clock to lock */ 2161 delay(50000); 2162 2163 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2164 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2165 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2166 } 2167 PRINTREG(RADEON_CRTC_MORE_CNTL); 2168 } 2169 2170 void 2171 radeonfb_modeswitch(struct radeonfb_display *dp) 2172 { 2173 struct radeonfb_softc *sc = dp->rd_softc; 2174 int i; 2175 2176 /* blank the display while we switch modes */ 2177 radeonfb_blank(dp, 1); 2178 2179 #if 0 2180 SET32(sc, RADEON_CRTC_EXT_CNTL, 2181 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2182 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2183 #endif 2184 2185 /* these registers might get in the way... */ 2186 PUT32(sc, RADEON_OVR_CLR, 0); 2187 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2188 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2189 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2190 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2191 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2192 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2193 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2194 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2195 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2196 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2197 2198 for (i = 0; i < dp->rd_ncrtcs; i++) 2199 radeonfb_setcrtc(dp, i); 2200 2201 #if 0 2202 /* 2203 * DVO chip voodoo from xf86-video-radeon 2204 * apparently this is needed for some powerbooks with DVI outputs 2205 */ 2206 2207 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2208 int n = 0; 2209 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2210 for (i = 0; i < 5; i++) 2211 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2212 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2213 printf("n = %d\n", n); 2214 #endif 2215 2216 /* activate the display */ 2217 radeonfb_blank(dp, 0); 2218 } 2219 2220 void 2221 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2222 { 2223 int crtc, flags = 0; 2224 struct videomode *mode; 2225 struct radeonfb_softc *sc; 2226 struct radeonfb_crtc *cp; 2227 uint32_t v; 2228 uint32_t gencntl; 2229 uint32_t htotaldisp; 2230 uint32_t hsyncstrt; 2231 uint32_t vtotaldisp; 2232 uint32_t vsyncstrt; 2233 uint32_t fphsyncstrt; 2234 uint32_t fpvsyncstrt; 2235 uint32_t fphtotaldisp; 2236 uint32_t fpvtotaldisp; 2237 uint32_t pitch; 2238 2239 sc = dp->rd_softc; 2240 2241 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2242 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2243 flags |= NO_ODD_FBDIV; 2244 } 2245 2246 cp = &dp->rd_crtcs[index]; 2247 crtc = cp->rc_number; 2248 mode = &cp->rc_videomode; 2249 2250 #if 1 2251 pitch = dp->rd_stride / dp->rd_bpp; 2252 #else 2253 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2254 (sc->sc_maxbpp * 8)); 2255 #endif 2256 switch (crtc) { 2257 case 0: 2258 gencntl = RADEON_CRTC_GEN_CNTL; 2259 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2260 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2261 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2262 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2263 /* should probably leave those alone on non-LVDS */ 2264 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2265 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2266 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2267 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2268 break; 2269 case 1: 2270 gencntl = RADEON_CRTC2_GEN_CNTL; 2271 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2272 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2273 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2274 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2275 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2276 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2277 /* XXX these registers don't seem to exist */ 2278 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2279 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2280 break; 2281 default: 2282 panic("Bad CRTC!"); 2283 break; 2284 } 2285 2286 /* 2287 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2288 */ 2289 /* only bother with 32bpp and 8bpp */ 2290 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2291 2292 if (crtc == 1) { 2293 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2294 } else { 2295 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2296 } 2297 2298 if (mode->flags & VID_DBLSCAN) 2299 v |= RADEON_CRTC2_DBL_SCAN_EN; 2300 2301 if (mode->flags & VID_INTERLACE) 2302 v |= RADEON_CRTC2_INTERLACE_EN; 2303 2304 if (mode->flags & VID_CSYNC) { 2305 v |= RADEON_CRTC2_CSYNC_EN; 2306 if (crtc == 1) 2307 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2308 } 2309 2310 PUT32(sc, gencntl, v); 2311 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2312 2313 /* 2314 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2315 */ 2316 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2317 if (crtc == 0) { 2318 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2319 RADEON_CRTC_DISPLAY_DIS); 2320 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2321 if (mode->flags & VID_CSYNC) 2322 v |= RADEON_CRTC_VSYNC_TRISTAT; 2323 } 2324 /* unconditional turn on CRT, in case first CRTC is DFP */ 2325 v |= RADEON_CRTC_CRT_ON; 2326 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2327 PRINTREG(RADEON_CRTC_EXT_CNTL); 2328 2329 /* 2330 * H_TOTAL_DISP 2331 */ 2332 v = ((mode->hdisplay / 8) - 1) << 16; 2333 v |= (mode->htotal / 8) - 1; 2334 PUT32(sc, htotaldisp, v); 2335 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2336 if (fphtotaldisp) { 2337 PUT32(sc, fphtotaldisp, v); 2338 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2339 } 2340 /* 2341 * H_SYNC_STRT_WID 2342 */ 2343 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2344 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2345 if (mode->flags & VID_NHSYNC) 2346 v |= RADEON_CRTC_H_SYNC_POL; 2347 PUT32(sc, hsyncstrt, v); 2348 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2349 if (fphsyncstrt) { 2350 PUT32(sc, fphsyncstrt, v); 2351 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2352 } 2353 2354 /* 2355 * V_TOTAL_DISP 2356 */ 2357 v = ((mode->vdisplay - 1) << 16); 2358 v |= (mode->vtotal - 1); 2359 PUT32(sc, vtotaldisp, v); 2360 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2361 if (fpvtotaldisp) { 2362 PUT32(sc, fpvtotaldisp, v); 2363 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2364 } 2365 2366 /* 2367 * V_SYNC_STRT_WID 2368 */ 2369 v = ((mode->vsync_end - mode->vsync_start) << 16); 2370 v |= (mode->vsync_start - 1); 2371 if (mode->flags & VID_NVSYNC) 2372 v |= RADEON_CRTC_V_SYNC_POL; 2373 PUT32(sc, vsyncstrt, v); 2374 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2375 if (fpvsyncstrt) { 2376 PUT32(sc, fpvsyncstrt, v); 2377 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2378 } 2379 2380 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2381 2382 switch (crtc) { 2383 case 0: 2384 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2385 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2386 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2387 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2388 2389 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2390 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2391 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2392 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2393 PRINTREG(RADEON_CRTC_EXT_CNTL); 2394 PRINTREG(RADEON_CRTC_GEN_CNTL); 2395 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2396 break; 2397 2398 case 1: 2399 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2400 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2401 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2402 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2403 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2404 RADEON_CRTC2_VSYNC_DIS | 2405 RADEON_CRTC2_HSYNC_DIS | 2406 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2407 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2408 break; 2409 } 2410 } 2411 2412 int 2413 radeonfb_isblank(struct radeonfb_display *dp) 2414 { 2415 uint32_t reg, mask; 2416 2417 if(!dp->rd_softc->sc_mapped) 2418 return 1; 2419 2420 if (dp->rd_crtcs[0].rc_number) { 2421 reg = RADEON_CRTC2_GEN_CNTL; 2422 mask = RADEON_CRTC2_DISP_DIS; 2423 } else { 2424 reg = RADEON_CRTC_EXT_CNTL; 2425 mask = RADEON_CRTC_DISPLAY_DIS; 2426 } 2427 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2428 } 2429 2430 void 2431 radeonfb_blank(struct radeonfb_display *dp, int blank) 2432 { 2433 struct radeonfb_softc *sc = dp->rd_softc; 2434 uint32_t reg, mask; 2435 uint32_t fpreg, fpval; 2436 int i; 2437 2438 if (!sc->sc_mapped) 2439 return; 2440 2441 for (i = 0; i < dp->rd_ncrtcs; i++) { 2442 2443 if (dp->rd_crtcs[i].rc_number) { 2444 reg = RADEON_CRTC2_GEN_CNTL; 2445 mask = RADEON_CRTC2_DISP_DIS; 2446 fpreg = RADEON_FP2_GEN_CNTL; 2447 fpval = RADEON_FP2_ON; 2448 } else { 2449 reg = RADEON_CRTC_EXT_CNTL; 2450 mask = RADEON_CRTC_DISPLAY_DIS; 2451 fpreg = RADEON_FP_GEN_CNTL; 2452 fpval = RADEON_FP_FPON; 2453 } 2454 2455 if (blank) { 2456 SET32(sc, reg, mask); 2457 CLR32(sc, fpreg, fpval); 2458 } else { 2459 CLR32(sc, reg, mask); 2460 SET32(sc, fpreg, fpval); 2461 } 2462 } 2463 PRINTREG(RADEON_FP_GEN_CNTL); 2464 PRINTREG(RADEON_FP2_GEN_CNTL); 2465 } 2466 2467 void 2468 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2469 long *defattr) 2470 { 2471 struct radeonfb_display *dp = cookie; 2472 struct rasops_info *ri = &scr->scr_ri; 2473 2474 /* initialize font subsystem */ 2475 wsfont_init(); 2476 2477 scr->scr_flags |= VCONS_LOADFONT; 2478 2479 DPRINTF(("init screen called, existing %d\n", existing)); 2480 2481 ri->ri_depth = dp->rd_bpp; 2482 ri->ri_width = dp->rd_virtx; 2483 ri->ri_height = dp->rd_virty; 2484 ri->ri_stride = dp->rd_stride; 2485 ri->ri_flg = RI_CENTER; 2486 switch (ri->ri_depth) { 2487 case 8: 2488 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2489 break; 2490 case 32: 2491 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2492 /* we run radeons in RGB even on SPARC hardware */ 2493 ri->ri_rnum = 8; 2494 ri->ri_gnum = 8; 2495 ri->ri_bnum = 8; 2496 ri->ri_rpos = 16; 2497 ri->ri_gpos = 8; 2498 ri->ri_bpos = 0; 2499 break; 2500 } 2501 2502 ri->ri_bits = (void *)dp->rd_fbptr; 2503 2504 #ifdef VCONS_DRAW_INTR 2505 scr->scr_flags |= VCONS_DONT_READ; 2506 #endif 2507 2508 if (existing) { 2509 ri->ri_flg |= RI_CLEAR; 2510 2511 /* start a modeswitch now */ 2512 radeonfb_modeswitch(dp); 2513 } 2514 2515 /* 2516 * XXX: font selection should be based on properties, with some 2517 * normal/reasonable default. 2518 */ 2519 2520 /* initialize and look for an initial font */ 2521 rasops_init(ri, 0, 0); 2522 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2523 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2524 2525 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2526 dp->rd_virtx / ri->ri_font->fontwidth); 2527 2528 /* enable acceleration */ 2529 dp->rd_putchar = ri->ri_ops.putchar; 2530 ri->ri_ops.copyrows = radeonfb_copyrows; 2531 ri->ri_ops.copycols = radeonfb_copycols; 2532 ri->ri_ops.eraserows = radeonfb_eraserows; 2533 ri->ri_ops.erasecols = radeonfb_erasecols; 2534 /* pick a putchar method based on font and Radeon model */ 2535 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2536 /* got a bitmap font */ 2537 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2538 if (IS_R300(dp->rd_softc)) { 2539 /* 2540 * radeonfb_putchar() doesn't work right on some R3xx 2541 * so we use software drawing here, the wrapper just 2542 * makes sure the engine is idle before scribbling 2543 * into vram 2544 */ 2545 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2546 } else 2547 #endif 2548 ri->ri_ops.putchar = radeonfb_putchar; 2549 } else { 2550 /* got an alpha font */ 2551 switch(ri->ri_depth) { 2552 case 32: 2553 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2554 break; 2555 case 8: 2556 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2557 break; 2558 default: 2559 /* XXX this should never happen */ 2560 panic("%s: depth is not 8 or 32 but we got an" \ 2561 " alpha font?!", __func__); 2562 } 2563 } 2564 ri->ri_ops.cursor = radeonfb_cursor; 2565 } 2566 2567 void 2568 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2569 { 2570 uint32_t gen, ext, gen2 = 0; 2571 uint32_t agploc, aperbase, apersize, mcfbloc; 2572 2573 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2574 /* XXX */ 2575 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2576 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2577 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2578 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2579 2580 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2581 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2582 #if 0 2583 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2584 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2585 #endif 2586 2587 if (HAS_CRTC2(sc)) { 2588 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2589 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2590 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2591 } 2592 2593 delay(100000); 2594 2595 mcfbloc = (aperbase >> 16) | 2596 ((aperbase + (apersize - 1)) & 0xffff0000); 2597 2598 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2599 sc->sc_memsz = apersize; 2600 2601 if (((agploc & 0xffff) << 16) != 2602 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2603 agploc = mcfbloc & 0xffff0000U; 2604 agploc |= ((agploc + 0x10000) >> 16); 2605 } 2606 2607 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2608 2609 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2610 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2611 2612 DPRINTF(("aperbase = %u\n", aperbase)); 2613 PRINTREG(RADEON_MC_FB_LOCATION); 2614 PRINTREG(RADEON_MC_AGP_LOCATION); 2615 2616 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2617 2618 if (HAS_CRTC2(sc)) 2619 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2620 2621 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2622 2623 #if 0 2624 /* XXX: what is this AGP garbage? :-) */ 2625 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2626 #endif 2627 2628 delay(100000); 2629 2630 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2631 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2632 2633 if (HAS_CRTC2(sc)) 2634 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2635 } 2636 2637 void 2638 radeonfb_init_misc(struct radeonfb_softc *sc) 2639 { 2640 PUT32(sc, RADEON_BUS_CNTL, 2641 RADEON_BUS_MASTER_DIS | 2642 RADEON_BUS_PREFETCH_MODE_ACT | 2643 RADEON_BUS_PCI_READ_RETRY_EN | 2644 RADEON_BUS_PCI_WRT_RETRY_EN | 2645 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2646 RADEON_BUS_MSTR_RD_MULT | 2647 RADEON_BUS_MSTR_RD_LINE | 2648 RADEON_BUS_RD_DISCARD_EN | 2649 RADEON_BUS_MSTR_DISCONNECT_EN | 2650 RADEON_BUS_READ_BURST); 2651 2652 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2653 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2654 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2655 PUT32(sc, RADEON_RBBM_CNTL, 2656 (3 << RADEON_RB_SETTLE_SHIFT) | 2657 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2658 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2659 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2660 2661 /* XXX: figure out what these mean! */ 2662 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2663 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2664 #if 0 2665 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2666 #endif 2667 2668 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2669 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2670 } 2671 2672 static void 2673 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2674 { 2675 struct radeonfb_softc *sc = dp->rd_softc; 2676 int crtc, cc; 2677 uint32_t vclk; 2678 2679 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2680 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2681 2682 /* initialize the palette for every CRTC used by this display */ 2683 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2684 crtc = dp->rd_crtcs[cc].rc_number; 2685 2686 if (crtc) 2687 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2688 else 2689 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2690 2691 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2692 PUT32(sc, RADEON_PALETTE_30_DATA, 2693 (r << 22) | (g << 12) | (b << 2)); 2694 } 2695 2696 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2697 } 2698 2699 /* 2700 * This loads a linear color map for true color. 2701 */ 2702 void 2703 radeonfb_init_palette(struct radeonfb_display *dp) 2704 { 2705 int i; 2706 2707 #define DAC_WIDTH ((1 << 10) - 1) 2708 #define CLUT_WIDTH ((1 << 8) - 1) 2709 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2710 2711 if (dp->rd_bpp == 8) { 2712 2713 /* R3G3B2 palette */ 2714 uint32_t tmp, r, g, b; 2715 2716 for (i = 0; i <= CLUT_WIDTH; ++i) { 2717 tmp = i & 0xe0; 2718 2719 /* 2720 * replicate bits so 0xe0 maps to a red value of 0xff 2721 * in order to make white look actually white 2722 */ 2723 tmp |= (tmp >> 3) | (tmp >> 6); 2724 r = tmp; 2725 2726 tmp = (i & 0x1c) << 3; 2727 tmp |= (tmp >> 3) | (tmp >> 6); 2728 g = tmp; 2729 2730 tmp = (i & 0x03) << 6; 2731 tmp |= tmp >> 2; 2732 tmp |= tmp >> 4; 2733 b = tmp; 2734 2735 radeonfb_putpal(dp, i, r, g, b); 2736 } 2737 } else { 2738 /* linear ramp */ 2739 for (i = 0; i <= CLUT_WIDTH; ++i) { 2740 radeonfb_putpal(dp, i, i, i, i); 2741 } 2742 } 2743 } 2744 2745 static int 2746 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2747 { 2748 u_char *r, *g, *b; 2749 u_int index = cm->index; 2750 u_int count = cm->count; 2751 int i, error; 2752 u_char rbuf[256], gbuf[256], bbuf[256]; 2753 2754 #ifdef GENFB_DEBUG 2755 aprint_debug("putcmap: %d %d\n",index, count); 2756 #endif 2757 if (cm->index >= 256 || cm->count > 256 || 2758 (cm->index + cm->count) > 256) 2759 return EINVAL; 2760 error = copyin(cm->red, &rbuf[index], count); 2761 if (error) 2762 return error; 2763 error = copyin(cm->green, &gbuf[index], count); 2764 if (error) 2765 return error; 2766 error = copyin(cm->blue, &bbuf[index], count); 2767 if (error) 2768 return error; 2769 2770 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2771 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2772 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2773 2774 r = &dp->rd_cmap_red[index]; 2775 g = &dp->rd_cmap_green[index]; 2776 b = &dp->rd_cmap_blue[index]; 2777 2778 for (i = 0; i < count; i++) { 2779 radeonfb_putpal(dp, index, *r, *g, *b); 2780 index++; 2781 r++, g++, b++; 2782 } 2783 return 0; 2784 } 2785 2786 static int 2787 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2788 { 2789 u_int index = cm->index; 2790 u_int count = cm->count; 2791 int error; 2792 2793 if (index >= 255 || count > 256 || index + count > 256) 2794 return EINVAL; 2795 2796 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2797 if (error) 2798 return error; 2799 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2800 if (error) 2801 return error; 2802 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2803 if (error) 2804 return error; 2805 2806 return 0; 2807 } 2808 2809 /* 2810 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2811 */ 2812 void 2813 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2814 { 2815 uint32_t tmp, save; 2816 2817 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2818 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2819 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2820 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2821 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2822 } 2823 2824 /* 2825 * Acceleration entry points. 2826 */ 2827 2828 /* this one draws characters using bitmap fonts */ 2829 static void 2830 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2831 { 2832 struct rasops_info *ri = cookie; 2833 struct vcons_screen *scr = ri->ri_hw; 2834 struct radeonfb_display *dp = scr->scr_cookie; 2835 struct radeonfb_softc *sc = dp->rd_softc; 2836 struct wsdisplay_font *font = PICK_FONT(ri, c); 2837 uint32_t w, h; 2838 int xd, yd, offset, i; 2839 uint32_t bg, fg, gmc; 2840 uint32_t reg; 2841 uint8_t *data8; 2842 uint16_t *data16; 2843 void *data; 2844 2845 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2846 return; 2847 2848 if (!CHAR_IN_FONT(c, font)) 2849 return; 2850 2851 w = font->fontwidth; 2852 h = font->fontheight; 2853 2854 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2855 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2856 2857 xd = ri->ri_xorigin + col * w; 2858 yd = ri->ri_yorigin + row * h; 2859 2860 if (c == 0x20) { 2861 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2862 return; 2863 } 2864 data = WSFONT_GLYPH(c, font); 2865 2866 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2867 2868 radeonfb_wait_fifo(sc, 9); 2869 2870 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2871 RADEON_GMC_BRUSH_NONE | 2872 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2873 RADEON_GMC_DST_CLIPPING | 2874 RADEON_ROP3_S | 2875 RADEON_DP_SRC_SOURCE_HOST_DATA | 2876 RADEON_GMC_CLR_CMP_CNTL_DIS | 2877 RADEON_GMC_WR_MSK_DIS | 2878 gmc); 2879 2880 PUT32(sc, RADEON_SC_LEFT, xd); 2881 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2882 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2883 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2884 PUT32(sc, RADEON_DP_CNTL, 2885 RADEON_DST_X_LEFT_TO_RIGHT | 2886 RADEON_DST_Y_TOP_TO_BOTTOM); 2887 2888 PUT32(sc, RADEON_SRC_X_Y, 0); 2889 offset = 32 - (font->stride << 3); 2890 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2891 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2892 2893 radeonfb_wait_fifo(sc, h); 2894 switch (font->stride) { 2895 case 1: { 2896 data8 = data; 2897 for (i = 0; i < h; i++) { 2898 reg = *data8; 2899 #if BYTE_ORDER == LITTLE_ENDIAN 2900 reg = reg << 24; 2901 #endif 2902 bus_space_write_stream_4(sc->sc_regt, 2903 sc->sc_regh, RADEON_HOST_DATA0, reg); 2904 data8++; 2905 } 2906 break; 2907 } 2908 case 2: { 2909 data16 = data; 2910 for (i = 0; i < h; i++) { 2911 reg = *data16; 2912 #if BYTE_ORDER == LITTLE_ENDIAN 2913 reg = reg << 16; 2914 #endif 2915 bus_space_write_stream_4(sc->sc_regt, 2916 sc->sc_regh, RADEON_HOST_DATA0, reg); 2917 data16++; 2918 } 2919 break; 2920 } 2921 } 2922 if (attr & 1) 2923 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2924 } 2925 2926 /* ... while this one is for anti-aliased ones */ 2927 static void 2928 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2929 { 2930 struct rasops_info *ri = cookie; 2931 struct vcons_screen *scr = ri->ri_hw; 2932 struct radeonfb_display *dp = scr->scr_cookie; 2933 struct radeonfb_softc *sc = dp->rd_softc; 2934 struct wsdisplay_font *font = PICK_FONT(ri, c); 2935 uint32_t bg, fg, gmc; 2936 uint8_t *data; 2937 int w, h, xd, yd; 2938 int i, r, g, b, aval; 2939 int rf, gf, bf, rb, gb, bb; 2940 uint32_t pixel; 2941 int rv; 2942 2943 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2944 return; 2945 2946 if (!CHAR_IN_FONT(c, font)) 2947 return; 2948 2949 w = font->fontwidth; 2950 h = font->fontheight; 2951 2952 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2953 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2954 2955 xd = ri->ri_xorigin + col * w; 2956 yd = ri->ri_yorigin + row * h; 2957 2958 if (c == 0x20) { 2959 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2960 if (attr & 1) 2961 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2962 return; 2963 } 2964 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2965 if (rv == GC_OK) 2966 return; 2967 2968 data = WSFONT_GLYPH(c, font); 2969 2970 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2971 2972 radeonfb_wait_fifo(sc, 5); 2973 2974 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2975 RADEON_GMC_BRUSH_NONE | 2976 RADEON_GMC_SRC_DATATYPE_COLOR | 2977 RADEON_ROP3_S | 2978 RADEON_DP_SRC_SOURCE_HOST_DATA | 2979 RADEON_GMC_CLR_CMP_CNTL_DIS | 2980 RADEON_GMC_WR_MSK_DIS | 2981 gmc); 2982 2983 PUT32(sc, RADEON_DP_CNTL, 2984 RADEON_DST_X_LEFT_TO_RIGHT | 2985 RADEON_DST_Y_TOP_TO_BOTTOM); 2986 2987 PUT32(sc, RADEON_SRC_X_Y, 0); 2988 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2989 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2990 2991 rf = (fg >> 16) & 0xff; 2992 rb = (bg >> 16) & 0xff; 2993 gf = (fg >> 8) & 0xff; 2994 gb = (bg >> 8) & 0xff; 2995 bf = fg & 0xff; 2996 bb = bg & 0xff; 2997 2998 /* 2999 * I doubt we can upload data faster than even the slowest Radeon 3000 * could process them, especially when doing the alpha blending stuff 3001 * along the way, so just make sure there's some room in the FIFO and 3002 * then hammer away 3003 * As it turns out we can, so make periodic stops to let the FIFO 3004 * drain. 3005 */ 3006 radeonfb_wait_fifo(sc, 20); 3007 for (i = 0; i < ri->ri_fontscale; i++) { 3008 aval = *data; 3009 data++; 3010 if (aval == 0) { 3011 pixel = bg; 3012 } else if (aval == 255) { 3013 pixel = fg; 3014 } else { 3015 r = aval * rf + (255 - aval) * rb; 3016 g = aval * gf + (255 - aval) * gb; 3017 b = aval * bf + (255 - aval) * bb; 3018 pixel = (r & 0xff00) << 8 | 3019 (g & 0xff00) | 3020 (b & 0xff00) >> 8; 3021 } 3022 if (i & 16) 3023 radeonfb_wait_fifo(sc, 20); 3024 PUT32(sc, RADEON_HOST_DATA0, pixel); 3025 } 3026 if (rv == GC_ADD) { 3027 glyphcache_add(&dp->rd_gc, c, xd, yd); 3028 } else 3029 if (attr & 1) 3030 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3031 3032 } 3033 3034 static void 3035 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3036 { 3037 struct rasops_info *ri = cookie; 3038 struct vcons_screen *scr = ri->ri_hw; 3039 struct radeonfb_display *dp = scr->scr_cookie; 3040 struct radeonfb_softc *sc = dp->rd_softc; 3041 struct wsdisplay_font *font = PICK_FONT(ri, c); 3042 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3043 int i, x, y, wi, he, r, g, b, aval; 3044 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3045 uint8_t *data8; 3046 int rv, cnt; 3047 3048 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3049 return; 3050 3051 if (!CHAR_IN_FONT(c, font)) 3052 return; 3053 3054 wi = font->fontwidth; 3055 he = font->fontheight; 3056 3057 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3058 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3059 3060 x = ri->ri_xorigin + col * wi; 3061 y = ri->ri_yorigin + row * he; 3062 3063 if (c == 0x20) { 3064 radeonfb_rectfill(dp, x, y, wi, he, bg); 3065 if (attr & 1) 3066 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3067 return; 3068 } 3069 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3070 if (rv == GC_OK) 3071 return; 3072 3073 data8 = WSFONT_GLYPH(c, font); 3074 3075 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3076 3077 radeonfb_wait_fifo(sc, 5); 3078 3079 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3080 RADEON_GMC_BRUSH_NONE | 3081 RADEON_GMC_SRC_DATATYPE_COLOR | 3082 RADEON_ROP3_S | 3083 RADEON_DP_SRC_SOURCE_HOST_DATA | 3084 RADEON_GMC_CLR_CMP_CNTL_DIS | 3085 RADEON_GMC_WR_MSK_DIS | 3086 gmc); 3087 3088 PUT32(sc, RADEON_DP_CNTL, 3089 RADEON_DST_X_LEFT_TO_RIGHT | 3090 RADEON_DST_Y_TOP_TO_BOTTOM); 3091 3092 PUT32(sc, RADEON_SRC_X_Y, 0); 3093 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3094 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3095 3096 /* 3097 * we need the RGB colours here, so get offsets into rasops_cmap 3098 */ 3099 fgo = ((attr >> 24) & 0xf) * 3; 3100 bgo = ((attr >> 16) & 0xf) * 3; 3101 3102 r0 = rasops_cmap[bgo]; 3103 r1 = rasops_cmap[fgo]; 3104 g0 = rasops_cmap[bgo + 1]; 3105 g1 = rasops_cmap[fgo + 1]; 3106 b0 = rasops_cmap[bgo + 2]; 3107 b1 = rasops_cmap[fgo + 2]; 3108 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3109 bg8 = R3G3B2(r0, g0, b0); 3110 fg8 = R3G3B2(r1, g1, b1); 3111 3112 radeonfb_wait_fifo(sc, 20); 3113 cnt = 0; 3114 for (i = 0; i < ri->ri_fontscale; i++) { 3115 aval = *data8; 3116 if (aval == 0) { 3117 pixel = bg8; 3118 } else if (aval == 255) { 3119 pixel = fg8; 3120 } else { 3121 r = aval * r1 + (255 - aval) * r0; 3122 g = aval * g1 + (255 - aval) * g0; 3123 b = aval * b1 + (255 - aval) * b0; 3124 pixel = ((r & 0xe000) >> 8) | 3125 ((g & 0xe000) >> 11) | 3126 ((b & 0xc000) >> 14); 3127 } 3128 latch |= pixel << (8 * (i & 3)); 3129 /* write in 32bit chunks */ 3130 if ((i & 3) == 3) { 3131 PUT32(sc, RADEON_HOST_DATA0, latch); 3132 /* 3133 * not strictly necessary, old data should be shifted 3134 * out 3135 */ 3136 latch = 0; 3137 cnt++; 3138 if (cnt > 16) { 3139 cnt = 0; 3140 radeonfb_wait_fifo(sc, 20); 3141 } 3142 } 3143 data8++; 3144 } 3145 /* if we have pixels left in latch write them out */ 3146 if ((i & 3) != 0) { 3147 /* 3148 * radeon is weird - apparently leftover pixels are written 3149 * from the middle, not from the left as everything else 3150 */ 3151 PUT32(sc, RADEON_HOST_DATA0, latch); 3152 } 3153 3154 if (rv == GC_ADD) { 3155 glyphcache_add(&dp->rd_gc, c, x, y); 3156 } else 3157 if (attr & 1) 3158 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3159 3160 } 3161 3162 /* 3163 * wrapper for software character drawing 3164 * just sync the engine and call rasops*_putchar() 3165 */ 3166 3167 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3168 static void 3169 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3170 { 3171 struct rasops_info *ri = cookie; 3172 struct vcons_screen *scr = ri->ri_hw; 3173 struct radeonfb_display *dp = scr->scr_cookie; 3174 3175 radeonfb_engine_idle(dp->rd_softc); 3176 dp->rd_putchar(ri, row, col, c, attr); 3177 } 3178 #endif 3179 3180 static void 3181 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3182 { 3183 struct rasops_info *ri = cookie; 3184 struct vcons_screen *scr = ri->ri_hw; 3185 struct radeonfb_display *dp = scr->scr_cookie; 3186 uint32_t x, y, w, h, fg, bg, ul; 3187 3188 /* XXX: check for full emulation mode? */ 3189 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3190 x = ri->ri_xorigin; 3191 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3192 w = ri->ri_emuwidth; 3193 h = ri->ri_font->fontheight * nrows; 3194 3195 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3196 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3197 } 3198 } 3199 3200 static void 3201 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3202 { 3203 struct rasops_info *ri = cookie; 3204 struct vcons_screen *scr = ri->ri_hw; 3205 struct radeonfb_display *dp = scr->scr_cookie; 3206 uint32_t x, ys, yd, w, h; 3207 3208 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3209 x = ri->ri_xorigin; 3210 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3211 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3212 w = ri->ri_emuwidth; 3213 h = ri->ri_font->fontheight * nrows; 3214 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3215 RADEON_ROP3_S); 3216 } 3217 } 3218 3219 static void 3220 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3221 { 3222 struct rasops_info *ri = cookie; 3223 struct vcons_screen *scr = ri->ri_hw; 3224 struct radeonfb_display *dp = scr->scr_cookie; 3225 uint32_t xs, xd, y, w, h; 3226 3227 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3228 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3229 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3230 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3231 w = ri->ri_font->fontwidth * ncols; 3232 h = ri->ri_font->fontheight; 3233 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3234 RADEON_ROP3_S); 3235 } 3236 } 3237 3238 static void 3239 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3240 long fillattr) 3241 { 3242 struct rasops_info *ri = cookie; 3243 struct vcons_screen *scr = ri->ri_hw; 3244 struct radeonfb_display *dp = scr->scr_cookie; 3245 uint32_t x, y, w, h, fg, bg, ul; 3246 3247 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3248 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3249 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3250 w = ri->ri_font->fontwidth * ncols; 3251 h = ri->ri_font->fontheight; 3252 3253 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3254 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3255 } 3256 } 3257 3258 static void 3259 radeonfb_cursor(void *cookie, int on, int row, int col) 3260 { 3261 struct rasops_info *ri = cookie; 3262 struct vcons_screen *scr = ri->ri_hw; 3263 struct radeonfb_display *dp = scr->scr_cookie; 3264 int x, y, wi, he; 3265 3266 wi = ri->ri_font->fontwidth; 3267 he = ri->ri_font->fontheight; 3268 3269 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3270 x = ri->ri_ccol * wi + ri->ri_xorigin; 3271 y = ri->ri_crow * he + ri->ri_yorigin; 3272 /* first turn off the old cursor */ 3273 if (ri->ri_flg & RI_CURSOR) { 3274 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3275 RADEON_ROP3_Dn); 3276 ri->ri_flg &= ~RI_CURSOR; 3277 } 3278 ri->ri_crow = row; 3279 ri->ri_ccol = col; 3280 /* then (possibly) turn on the new one */ 3281 if (on) { 3282 x = ri->ri_ccol * wi + ri->ri_xorigin; 3283 y = ri->ri_crow * he + ri->ri_yorigin; 3284 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3285 RADEON_ROP3_Dn); 3286 ri->ri_flg |= RI_CURSOR; 3287 } 3288 } else { 3289 scr->scr_ri.ri_crow = row; 3290 scr->scr_ri.ri_ccol = col; 3291 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3292 } 3293 } 3294 3295 /* 3296 * Underlying acceleration support. 3297 */ 3298 3299 static void 3300 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3301 int width, int height, uint32_t color) 3302 { 3303 struct radeonfb_softc *sc = dp->rd_softc; 3304 uint32_t gmc; 3305 3306 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3307 3308 radeonfb_wait_fifo(sc, 6); 3309 3310 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3311 RADEON_GMC_BRUSH_SOLID_COLOR | 3312 RADEON_GMC_SRC_DATATYPE_COLOR | 3313 RADEON_GMC_CLR_CMP_CNTL_DIS | 3314 RADEON_ROP3_P | gmc); 3315 3316 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3317 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3318 PUT32(sc, RADEON_DP_CNTL, 3319 RADEON_DST_X_LEFT_TO_RIGHT | 3320 RADEON_DST_Y_TOP_TO_BOTTOM); 3321 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3322 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3323 3324 } 3325 3326 static void 3327 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3328 int width, int height, long attr) 3329 { 3330 struct radeonfb_display *dp = cookie; 3331 3332 radeonfb_rectfill(dp, dstx, dsty, width, height, 3333 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3334 } 3335 3336 static void 3337 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3338 int dstx, int dsty, int width, int height, int rop) 3339 { 3340 struct radeonfb_display *dp = cookie; 3341 struct radeonfb_softc *sc = dp->rd_softc; 3342 uint32_t gmc; 3343 uint32_t dir; 3344 3345 if (dsty < srcy) { 3346 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3347 } else { 3348 srcy += height - 1; 3349 dsty += height - 1; 3350 dir = 0; 3351 } 3352 if (dstx < srcx) { 3353 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3354 } else { 3355 srcx += width - 1; 3356 dstx += width - 1; 3357 } 3358 3359 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3360 3361 radeonfb_wait_fifo(sc, 6); 3362 3363 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3364 RADEON_GMC_BRUSH_SOLID_COLOR | 3365 RADEON_GMC_SRC_DATATYPE_COLOR | 3366 RADEON_GMC_CLR_CMP_CNTL_DIS | 3367 RADEON_DP_SRC_SOURCE_MEMORY | 3368 rop | gmc); 3369 3370 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3371 PUT32(sc, RADEON_DP_CNTL, dir); 3372 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3373 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3374 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3375 } 3376 3377 static void 3378 radeonfb_engine_idle(struct radeonfb_softc *sc) 3379 { 3380 3381 radeonfb_wait_fifo(sc, 64); 3382 while ((GET32(sc, RADEON_RBBM_STATUS) & 3383 RADEON_RBBM_ACTIVE) != 0); 3384 radeonfb_engine_flush(sc); 3385 } 3386 3387 static inline void 3388 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3389 { 3390 int i; 3391 3392 for (i = RADEON_TIMEOUT; i; i--) { 3393 if ((GET32(sc, RADEON_RBBM_STATUS) & 3394 RADEON_RBBM_FIFOCNT_MASK) >= n) 3395 return; 3396 } 3397 #ifdef DIAGNOSTIC 3398 if (!i) 3399 printf("%s: timed out waiting for fifo (%x)\n", 3400 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3401 #endif 3402 } 3403 3404 static void 3405 radeonfb_engine_flush(struct radeonfb_softc *sc) 3406 { 3407 int i = 0; 3408 3409 if (IS_R300(sc)) { 3410 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3411 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3412 i++; 3413 } 3414 } else { 3415 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3416 RADEON_RB2D_DC_FLUSH_ALL); 3417 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3418 RADEON_RB2D_DC_BUSY) { 3419 i++; 3420 } 3421 } 3422 #ifdef DIAGNOSTIC 3423 if (i > RADEON_TIMEOUT) 3424 printf("%s: engine flush timed out!\n", XNAME(sc)); 3425 #endif 3426 } 3427 3428 static inline void 3429 radeonfb_unclip(struct radeonfb_softc *sc) 3430 { 3431 3432 radeonfb_wait_fifo(sc, 2); 3433 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3434 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3435 } 3436 3437 static void 3438 radeonfb_engine_init(struct radeonfb_display *dp) 3439 { 3440 struct radeonfb_softc *sc = dp->rd_softc; 3441 uint32_t pitch; 3442 3443 /* no 3D */ 3444 PUT32(sc, RADEON_RB3D_CNTL, 0); 3445 3446 radeonfb_engine_reset(sc); 3447 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3448 3449 radeonfb_wait_fifo(sc, 1); 3450 if (!IS_R300(sc)) 3451 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3452 3453 radeonfb_wait_fifo(sc, 3); 3454 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3455 (pitch << 22) | (sc->sc_aperbase >> 10)); 3456 3457 3458 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3459 (pitch << 22) | (sc->sc_aperbase >> 10)); 3460 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3461 (pitch << 22) | (sc->sc_aperbase >> 10)); 3462 3463 (void)GET32(sc, RADEON_DP_DATATYPE); 3464 3465 /* default scissors -- no clipping */ 3466 radeonfb_wait_fifo(sc, 1); 3467 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3468 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3469 3470 radeonfb_wait_fifo(sc, 1); 3471 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3472 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3473 RADEON_GMC_CLR_CMP_CNTL_DIS | 3474 RADEON_GMC_BRUSH_SOLID_COLOR | 3475 RADEON_GMC_SRC_DATATYPE_COLOR); 3476 3477 radeonfb_wait_fifo(sc, 10); 3478 PUT32(sc, RADEON_DST_LINE_START, 0); 3479 PUT32(sc, RADEON_DST_LINE_END, 0); 3480 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3481 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3482 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3483 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3484 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3485 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3486 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3487 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3488 radeonfb_engine_idle(sc); 3489 } 3490 3491 static void 3492 radeonfb_engine_reset(struct radeonfb_softc *sc) 3493 { 3494 uint32_t hpc, rbbm, mclkcntl, clkindex; 3495 3496 radeonfb_engine_flush(sc); 3497 3498 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3499 if (HAS_R300CG(sc)) 3500 radeonfb_r300cg_workaround(sc); 3501 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3502 3503 /* 3504 * According to comments in XFree code, resetting the HDP via 3505 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3506 * So we use HOST_PATH_CNTL instead. 3507 */ 3508 3509 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3510 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3511 if (IS_R300(sc)) { 3512 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3513 RADEON_SOFT_RESET_CP | 3514 RADEON_SOFT_RESET_HI | 3515 RADEON_SOFT_RESET_E2); 3516 GET32(sc, RADEON_RBBM_SOFT_RESET); 3517 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3518 /* 3519 * XXX: this bit is not defined in any ATI docs I have, 3520 * nor in the XFree code, but XFree does it. Why? 3521 */ 3522 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3523 } else { 3524 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3525 RADEON_SOFT_RESET_CP | 3526 RADEON_SOFT_RESET_SE | 3527 RADEON_SOFT_RESET_RE | 3528 RADEON_SOFT_RESET_PP | 3529 RADEON_SOFT_RESET_E2 | 3530 RADEON_SOFT_RESET_RB); 3531 GET32(sc, RADEON_RBBM_SOFT_RESET); 3532 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3533 ~(RADEON_SOFT_RESET_CP | 3534 RADEON_SOFT_RESET_SE | 3535 RADEON_SOFT_RESET_RE | 3536 RADEON_SOFT_RESET_PP | 3537 RADEON_SOFT_RESET_E2 | 3538 RADEON_SOFT_RESET_RB)); 3539 GET32(sc, RADEON_RBBM_SOFT_RESET); 3540 } 3541 3542 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3543 GET32(sc, RADEON_HOST_PATH_CNTL); 3544 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3545 3546 if (IS_R300(sc)) 3547 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3548 3549 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3550 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3551 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3552 3553 if (HAS_R300CG(sc)) 3554 radeonfb_r300cg_workaround(sc); 3555 } 3556 3557 static int 3558 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3559 { 3560 int x, y; 3561 3562 x = pos->x; 3563 y = pos->y; 3564 3565 /* 3566 * This doesn't let a cursor move off the screen. I'm not 3567 * sure if this will have negative effects for e.g. Xinerama. 3568 * I'd guess Xinerama handles it by changing the cursor shape, 3569 * but that needs verification. 3570 */ 3571 if (x >= dp->rd_virtx) 3572 x = dp->rd_virtx - 1; 3573 if (x < 0) 3574 x = 0; 3575 if (y >= dp->rd_virty) 3576 y = dp->rd_virty - 1; 3577 if (y < 0) 3578 y = 0; 3579 3580 dp->rd_cursor.rc_pos.x = x; 3581 dp->rd_cursor.rc_pos.y = y; 3582 3583 radeonfb_cursor_position(dp); 3584 return 0; 3585 } 3586 3587 static int 3588 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3589 { 3590 unsigned flags; 3591 3592 uint8_t r[2], g[2], b[2]; 3593 unsigned index, count; 3594 int i, err; 3595 int pitch, size; 3596 struct radeonfb_cursor nc; 3597 3598 flags = wc->which; 3599 3600 /* copy old values */ 3601 nc = dp->rd_cursor; 3602 3603 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3604 index = wc->cmap.index; 3605 count = wc->cmap.count; 3606 3607 if (index >= 2 || (index + count) > 2) 3608 return EINVAL; 3609 3610 err = copyin(wc->cmap.red, &r[index], count); 3611 if (err) 3612 return err; 3613 err = copyin(wc->cmap.green, &g[index], count); 3614 if (err) 3615 return err; 3616 err = copyin(wc->cmap.blue, &b[index], count); 3617 if (err) 3618 return err; 3619 3620 for (i = index; i < index + count; i++) { 3621 nc.rc_cmap[i] = 3622 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3623 } 3624 } 3625 3626 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3627 if ((wc->size.x > RADEON_CURSORMAXX) || 3628 (wc->size.y > RADEON_CURSORMAXY)) 3629 return EINVAL; 3630 3631 /* figure bytes per line */ 3632 pitch = (wc->size.x + 7) / 8; 3633 size = pitch * wc->size.y; 3634 3635 /* clear the old cursor and mask */ 3636 memset(nc.rc_image, 0, 512); 3637 memset(nc.rc_mask, 0, 512); 3638 3639 nc.rc_size = wc->size; 3640 3641 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3642 return err; 3643 3644 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3645 return err; 3646 } 3647 3648 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3649 nc.rc_hot = wc->hot; 3650 if (nc.rc_hot.x >= nc.rc_size.x) 3651 nc.rc_hot.x = nc.rc_size.x - 1; 3652 if (nc.rc_hot.y >= nc.rc_size.y) 3653 nc.rc_hot.y = nc.rc_size.y - 1; 3654 } 3655 3656 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3657 nc.rc_pos = wc->pos; 3658 if (nc.rc_pos.x >= dp->rd_virtx) 3659 nc.rc_pos.x = dp->rd_virtx - 1; 3660 #if 0 3661 if (nc.rc_pos.x < 0) 3662 nc.rc_pos.x = 0; 3663 #endif 3664 if (nc.rc_pos.y >= dp->rd_virty) 3665 nc.rc_pos.y = dp->rd_virty - 1; 3666 #if 0 3667 if (nc.rc_pos.y < 0) 3668 nc.rc_pos.y = 0; 3669 #endif 3670 } 3671 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3672 nc.rc_visible = wc->enable; 3673 } 3674 3675 dp->rd_cursor = nc; 3676 radeonfb_cursor_update(dp, wc->which); 3677 3678 return 0; 3679 } 3680 3681 static uint8_t 3682 radeonfb_backwards(uint8_t d) 3683 { 3684 uint8_t l; 3685 3686 l = d << 7; 3687 l |= ((d & 0x02) << 5); 3688 l |= ((d & 0x04) << 3); 3689 l |= ((d & 0x08) << 1); 3690 l |= ((d & 0x10) >> 1); 3691 l |= ((d & 0x20) >> 3); 3692 l |= ((d & 0x40) >> 5); 3693 l |= ((d & 0x80) >> 7); 3694 return l; 3695 } 3696 3697 /* 3698 * Change the cursor shape. Call this with the cursor locked to avoid 3699 * flickering/tearing. 3700 */ 3701 static void 3702 radeonfb_cursor_shape(struct radeonfb_display *dp) 3703 { 3704 uint8_t and[512], xor[512]; 3705 int i, j, src, dst /* , pitch */; 3706 const uint8_t *msk = dp->rd_cursor.rc_mask; 3707 const uint8_t *img = dp->rd_cursor.rc_image; 3708 3709 /* 3710 * Radeon cursor data interleaves one line of AND data followed 3711 * by a line of XOR data. (Each line corresponds to a whole hardware 3712 * pitch - i.e. 64 pixels or 8 bytes.) 3713 * 3714 * The cursor is displayed using the following table: 3715 * 3716 * AND XOR Result 3717 * ---------------------- 3718 * 0 0 Cursor color 0 3719 * 0 1 Cursor color 1 3720 * 1 0 Transparent 3721 * 1 1 Complement of background 3722 * 3723 * Our masks are therefore different from what we were passed. 3724 * Passed in, I'm assuming the data represents either color 0 or 1, 3725 * and a mask, so the passed in table looks like: 3726 * 3727 * IMG Mask Result 3728 * ----------------------- 3729 * 0 0 Transparent 3730 * 0 1 Cursor color 0 3731 * 1 0 Transparent 3732 * 1 1 Cursor color 1 3733 * 3734 * IF mask bit == 1, AND = 0, XOR = color. 3735 * IF mask bit == 0, AND = 1, XOR = 0. 3736 * 3737 * hence: AND = ~(mask); XOR = color & ~(mask); 3738 */ 3739 3740 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3741 3742 /* start by assuming all bits are transparent */ 3743 memset(and, 0xff, 512); 3744 memset(xor, 0x00, 512); 3745 3746 src = 0; 3747 dst = 0; 3748 for (i = 0; i < 64; i++) { 3749 for (j = 0; j < 64; j += 8) { 3750 if ((i < dp->rd_cursor.rc_size.y) && 3751 (j < dp->rd_cursor.rc_size.x)) { 3752 3753 /* take care to leave odd bits alone */ 3754 and[dst] &= ~(msk[src]); 3755 xor[dst] = img[src] & msk[src]; 3756 src++; 3757 } 3758 dst++; 3759 } 3760 } 3761 3762 for (i = 0; i < 512; i++) { 3763 and[i] = radeonfb_backwards(and[i]); 3764 xor[i] = radeonfb_backwards(xor[i]); 3765 } 3766 3767 /* copy the image into place */ 3768 for (i = 0; i < 64; i++) { 3769 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3770 &and[i * 8], 8); 3771 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3772 &xor[i * 8], 8); 3773 } 3774 } 3775 3776 static void 3777 radeonfb_cursor_position(struct radeonfb_display *dp) 3778 { 3779 struct radeonfb_softc *sc = dp->rd_softc; 3780 uint32_t offset, hvoff, hvpos; /* registers */ 3781 uint32_t coff; /* cursor offset */ 3782 int i, x, y, xoff, yoff, crtcoff; 3783 3784 /* 3785 * XXX: this also needs to handle pan/scan 3786 */ 3787 for (i = 0; i < dp->rd_ncrtcs; i++) { 3788 3789 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3790 3791 if (rcp->rc_number) { 3792 offset = RADEON_CUR2_OFFSET; 3793 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3794 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3795 crtcoff = RADEON_CRTC2_OFFSET; 3796 } else { 3797 offset = RADEON_CUR_OFFSET; 3798 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3799 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3800 crtcoff = RADEON_CRTC_OFFSET; 3801 } 3802 3803 x = dp->rd_cursor.rc_pos.x; 3804 y = dp->rd_cursor.rc_pos.y; 3805 3806 while (y < rcp->rc_yoffset) { 3807 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3808 } 3809 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3810 rcp->rc_yoffset += RADEON_PANINCREMENT; 3811 } 3812 while (x < rcp->rc_xoffset) { 3813 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3814 } 3815 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3816 rcp->rc_xoffset += RADEON_PANINCREMENT; 3817 } 3818 3819 /* adjust for the cursor's hotspot */ 3820 x -= dp->rd_cursor.rc_hot.x; 3821 y -= dp->rd_cursor.rc_hot.y; 3822 xoff = yoff = 0; 3823 3824 if (x >= dp->rd_virtx) 3825 x = dp->rd_virtx - 1; 3826 if (y >= dp->rd_virty) 3827 y = dp->rd_virty - 1; 3828 3829 /* now adjust cursor so it is relative to viewport */ 3830 x -= rcp->rc_xoffset; 3831 y -= rcp->rc_yoffset; 3832 3833 /* 3834 * no need to check for fall off, because we should 3835 * never move off the screen entirely! 3836 */ 3837 coff = 0; 3838 if (x < 0) { 3839 xoff = -x; 3840 x = 0; 3841 } 3842 if (y < 0) { 3843 yoff = -y; 3844 y = 0; 3845 coff = (yoff * 2) * 8; 3846 } 3847 3848 /* pan the display */ 3849 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3850 rcp->rc_xoffset); 3851 3852 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3853 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3854 /* NB: this unlocks the cursor */ 3855 PUT32(sc, hvpos, (x << 16) | y); 3856 } 3857 } 3858 3859 static void 3860 radeonfb_cursor_visible(struct radeonfb_display *dp) 3861 { 3862 int i; 3863 uint32_t gencntl, bit; 3864 3865 for (i = 0; i < dp->rd_ncrtcs; i++) { 3866 if (dp->rd_crtcs[i].rc_number) { 3867 gencntl = RADEON_CRTC2_GEN_CNTL; 3868 bit = RADEON_CRTC2_CUR_EN; 3869 } else { 3870 gencntl = RADEON_CRTC_GEN_CNTL; 3871 bit = RADEON_CRTC_CUR_EN; 3872 } 3873 3874 if (dp->rd_cursor.rc_visible) 3875 SET32(dp->rd_softc, gencntl, bit); 3876 else 3877 CLR32(dp->rd_softc, gencntl, bit); 3878 } 3879 } 3880 3881 static void 3882 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3883 { 3884 int i; 3885 uint32_t c0reg, c1reg; 3886 struct radeonfb_softc *sc = dp->rd_softc; 3887 3888 for (i = 0; i < dp->rd_ncrtcs; i++) { 3889 if (dp->rd_crtcs[i].rc_number) { 3890 c0reg = RADEON_CUR2_CLR0; 3891 c1reg = RADEON_CUR2_CLR1; 3892 } else { 3893 c0reg = RADEON_CUR_CLR0; 3894 c1reg = RADEON_CUR_CLR1; 3895 } 3896 3897 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3898 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3899 } 3900 } 3901 3902 static void 3903 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3904 { 3905 struct radeonfb_softc *sc; 3906 int i; 3907 3908 sc = dp->rd_softc; 3909 for (i = 0; i < dp->rd_ncrtcs; i++) { 3910 if (dp->rd_crtcs[i].rc_number) { 3911 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3912 } else { 3913 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3914 } 3915 } 3916 3917 if (which & WSDISPLAY_CURSOR_DOCMAP) 3918 radeonfb_cursor_cmap(dp); 3919 3920 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3921 radeonfb_cursor_shape(dp); 3922 3923 if (which & WSDISPLAY_CURSOR_DOCUR) 3924 radeonfb_cursor_visible(dp); 3925 3926 /* this one is unconditional, because it updates other stuff */ 3927 radeonfb_cursor_position(dp); 3928 } 3929 3930 static struct videomode * 3931 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3932 { 3933 int r1, r2; 3934 3935 /* otherwise pick the higher refresh rate */ 3936 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3937 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3938 3939 return (r1 < r2 ? m2 : m1); 3940 } 3941 3942 static const struct videomode * 3943 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3944 int x, int y) 3945 { 3946 struct edid_info *ep = &rp->rp_edid; 3947 struct videomode *vmp = NULL; 3948 int i; 3949 3950 if (!rp->rp_edid_valid) { 3951 /* fallback to safe mode */ 3952 return radeonfb_modelookup(sc->sc_defaultmode); 3953 } 3954 3955 /* always choose the preferred mode first! */ 3956 if (ep->edid_preferred_mode) { 3957 3958 /* XXX: add auto-stretching support for native mode */ 3959 3960 /* this may want panning to occur, btw */ 3961 if ((ep->edid_preferred_mode->hdisplay <= x) && 3962 (ep->edid_preferred_mode->vdisplay <= y)) 3963 return ep->edid_preferred_mode; 3964 } 3965 3966 for (i = 0; i < ep->edid_nmodes; i++) { 3967 /* 3968 * We elect to pick a resolution that is too large for 3969 * the monitor than one that is too small. This means 3970 * that we will prefer to pan rather than to try to 3971 * center a smaller display on a larger screen. In 3972 * practice, this shouldn't matter because if a 3973 * monitor can support a larger resolution, it can 3974 * probably also support the smaller. A specific 3975 * exception is fixed format panels, but hopefully 3976 * they are properly dealt with by the "autostretch" 3977 * logic above. 3978 */ 3979 if ((ep->edid_modes[i].hdisplay > x) || 3980 (ep->edid_modes[i].vdisplay > y)) { 3981 continue; 3982 } 3983 3984 /* 3985 * at this point, the display mode is no larger than 3986 * what we've requested. 3987 */ 3988 if (vmp == NULL) 3989 vmp = &ep->edid_modes[i]; 3990 3991 /* eliminate smaller modes */ 3992 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3993 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3994 continue; 3995 3996 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3997 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 3998 vmp = &ep->edid_modes[i]; 3999 continue; 4000 } 4001 4002 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4003 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4004 4005 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4006 } 4007 4008 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4009 } 4010 4011 static int 4012 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4013 { 4014 int i; 4015 4016 for (i = 0; i < nlist; i++) { 4017 if ((x == list[i].hdisplay) && 4018 (y == list[i].vdisplay)) { 4019 return 1; 4020 } 4021 } 4022 return 0; 4023 } 4024 4025 static void 4026 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4027 int pan) 4028 { 4029 struct radeonfb_port *rp; 4030 struct edid_info *ep; 4031 int i, j; 4032 4033 *x = 0; 4034 *y = 0; 4035 4036 if (pan) { 4037 for (i = 0; i < dp->rd_ncrtcs; i++) { 4038 rp = dp->rd_crtcs[i].rc_port; 4039 ep = &rp->rp_edid; 4040 if (!rp->rp_edid_valid) { 4041 /* monitor not present */ 4042 continue; 4043 } 4044 4045 /* 4046 * For now we are ignoring "conflict" that 4047 * could occur when mixing some modes like 4048 * 1280x1024 and 1400x800. It isn't clear 4049 * which is better, so the first one wins. 4050 */ 4051 for (j = 0; j < ep->edid_nmodes; j++) { 4052 /* 4053 * ignore resolutions that are too big for 4054 * the radeon 4055 */ 4056 if (ep->edid_modes[j].hdisplay > 4057 dp->rd_softc->sc_maxx) 4058 continue; 4059 if (ep->edid_modes[j].vdisplay > 4060 dp->rd_softc->sc_maxy) 4061 continue; 4062 4063 /* 4064 * pick largest resolution, the 4065 * smaller monitor will pan 4066 */ 4067 if ((ep->edid_modes[j].hdisplay >= *x) && 4068 (ep->edid_modes[j].vdisplay >= *y)) { 4069 *x = ep->edid_modes[j].hdisplay; 4070 *y = ep->edid_modes[j].vdisplay; 4071 } 4072 } 4073 } 4074 4075 } else { 4076 struct videomode modes[64]; 4077 int nmodes = 0; 4078 int valid = 0; 4079 4080 for (i = 0; i < dp->rd_ncrtcs; i++) { 4081 /* 4082 * pick the largest resolution in common. 4083 */ 4084 rp = dp->rd_crtcs[i].rc_port; 4085 ep = &rp->rp_edid; 4086 4087 if (!rp->rp_edid_valid) 4088 continue; 4089 4090 if (!valid) { 4091 /* 4092 * Pick the preferred mode for this port 4093 * if available. 4094 */ 4095 if (ep->edid_preferred_mode) { 4096 struct videomode *vmp = 4097 ep->edid_preferred_mode; 4098 4099 if ((vmp->hdisplay <= 4100 dp->rd_softc->sc_maxx) && 4101 (vmp->vdisplay <= 4102 dp->rd_softc->sc_maxy)) 4103 modes[nmodes++] = *vmp; 4104 } else { 4105 4106 /* initialize starting list */ 4107 for (j = 0; j < ep->edid_nmodes; j++) { 4108 /* 4109 * ignore resolutions that are 4110 * too big for the radeon 4111 */ 4112 if (ep->edid_modes[j].hdisplay > 4113 dp->rd_softc->sc_maxx) 4114 continue; 4115 if (ep->edid_modes[j].vdisplay > 4116 dp->rd_softc->sc_maxy) 4117 continue; 4118 4119 modes[nmodes] = 4120 ep->edid_modes[j]; 4121 nmodes++; 4122 } 4123 } 4124 valid = 1; 4125 } else { 4126 /* merge into preexisting list */ 4127 for (j = 0; j < nmodes; j++) { 4128 if (!radeonfb_hasres(ep->edid_modes, 4129 ep->edid_nmodes, 4130 modes[j].hdisplay, 4131 modes[j].vdisplay)) { 4132 modes[j] = modes[nmodes]; 4133 j--; 4134 nmodes--; 4135 } 4136 } 4137 } 4138 } 4139 4140 /* now we have to pick from the merged list */ 4141 for (i = 0; i < nmodes; i++) { 4142 if ((modes[i].hdisplay >= *x) && 4143 (modes[i].vdisplay >= *y)) { 4144 *x = modes[i].hdisplay; 4145 *y = modes[i].vdisplay; 4146 } 4147 } 4148 } 4149 4150 if ((*x == 0) || (*y == 0)) { 4151 /* fallback to safe mode */ 4152 *x = 640; 4153 *y = 480; 4154 } 4155 } 4156 4157 /* 4158 * backlight levels are linear on: 4159 * - RV200, RV250, RV280, RV350 4160 * - but NOT on PowerBook4,3 6,3 6,5 4161 * according to Linux' radeonfb 4162 */ 4163 4164 /* Get the current backlight level for the display. */ 4165 4166 static int 4167 radeonfb_get_backlight(struct radeonfb_display *dp) 4168 { 4169 int s; 4170 uint32_t level; 4171 4172 s = spltty(); 4173 4174 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4175 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4176 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4177 4178 /* 4179 * On some chips, we should negate the backlight level. 4180 * XXX Find out on which chips. 4181 */ 4182 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4183 level = RADEONFB_BACKLIGHT_MAX - level; 4184 4185 splx(s); 4186 4187 return level; 4188 } 4189 4190 /* Set the backlight to the given level for the display. */ 4191 static void 4192 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4193 { 4194 if (dp->rd_bl_on == on) 4195 return; 4196 dp->rd_bl_on = on; 4197 radeonfb_set_backlight(dp, dp->rd_bl_level); 4198 } 4199 4200 static int 4201 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4202 { 4203 struct radeonfb_softc *sc = dp->rd_softc;; 4204 int rlevel, s; 4205 uint32_t lvds; 4206 4207 if(!sc->sc_mapped) 4208 return 0; 4209 4210 s = spltty(); 4211 4212 dp->rd_bl_level = level; 4213 if (dp->rd_bl_on == 0) 4214 level = 0; 4215 4216 if (level < 0) 4217 level = 0; 4218 else if (level >= RADEONFB_BACKLIGHT_MAX) 4219 level = RADEONFB_BACKLIGHT_MAX; 4220 4221 /* On some chips, we should negate the backlight level. */ 4222 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4223 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4224 } else 4225 rlevel = level; 4226 4227 callout_stop(&dp->rd_bl_lvds_co); 4228 radeonfb_engine_idle(sc); 4229 4230 /* 4231 * Turn off the display if the backlight is set to 0, since the 4232 * display is useless without backlight anyway. 4233 */ 4234 if (level == 0) 4235 radeonfb_blank(dp, 1); 4236 else if (radeonfb_get_backlight(dp) == 0) 4237 radeonfb_blank(dp, 0); 4238 4239 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4240 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4241 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4242 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4243 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4244 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4245 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4246 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4247 lvds |= RADEON_LVDS_ON; 4248 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4249 } else { 4250 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4251 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4252 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4253 } 4254 4255 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4256 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4257 /* XXX What is the correct delay? */ 4258 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4259 4260 splx(s); 4261 4262 return 0; 4263 } 4264 4265 /* 4266 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4267 * Set the delayed bits in the register, and clear the stored delayed 4268 * value. 4269 */ 4270 4271 static void radeonfb_lvds_callout(void *arg) 4272 { 4273 struct radeonfb_display *dp = arg; 4274 int s; 4275 4276 s = splhigh(); 4277 4278 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4279 dp->rd_bl_lvds_val); 4280 dp->rd_bl_lvds_val = 0; 4281 4282 splx(s); 4283 } 4284 4285 static void 4286 radeonfb_brightness_up(device_t dev) 4287 { 4288 struct radeonfb_softc *sc = device_private(dev); 4289 struct radeonfb_display *dp = &sc->sc_displays[0]; 4290 int level; 4291 4292 /* we assume the main display is the first one - need a better way */ 4293 if (sc->sc_ndisplays < 1) return; 4294 /* make sure pushing the hotkeys always has an effect */ 4295 dp->rd_bl_on = 1; 4296 level = dp->rd_bl_level; 4297 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4298 radeonfb_set_backlight(dp, level); 4299 } 4300 4301 static void 4302 radeonfb_brightness_down(device_t dev) 4303 { 4304 struct radeonfb_softc *sc = device_private(dev); 4305 struct radeonfb_display *dp = &sc->sc_displays[0]; 4306 int level; 4307 4308 /* we assume the main display is the first one - need a better way */ 4309 if (sc->sc_ndisplays < 1) return; 4310 /* make sure pushing the hotkeys always has an effect */ 4311 dp->rd_bl_on = 1; 4312 level = dp->rd_bl_level; 4313 level = max(0, level - 5); 4314 radeonfb_set_backlight(dp, level); 4315 } 4316
Indexes created Wed Sep 24 02:09:48 GMT 2025