radeonfb.c revision 1.93
1 /* $NetBSD: radeonfb.c,v 1.93 2017/10/11 17:08:32 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.93 2017/10/11 17:08:32 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 482 /* enable memory and IO access */ 483 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 484 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 485 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 486 487 /* 488 * Some flags are general to entire chip families, and rather 489 * than clutter up the table with them, we go ahead and set 490 * them here. 491 */ 492 switch (sc->sc_family) { 493 case RADEON_RS100: 494 case RADEON_RS200: 495 sc->sc_flags |= RFB_IGP | RFB_RV100; 496 break; 497 498 case RADEON_RV100: 499 case RADEON_RV200: 500 case RADEON_RV250: 501 case RADEON_RV280: 502 sc->sc_flags |= RFB_RV100; 503 break; 504 505 case RADEON_RS300: 506 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 507 break; 508 509 case RADEON_R300: 510 case RADEON_RV350: 511 case RADEON_R350: 512 case RADEON_RV380: 513 case RADEON_R420: 514 /* newer chips */ 515 sc->sc_flags |= RFB_R300; 516 break; 517 518 case RADEON_R100: 519 sc->sc_flags |= RFB_NCRTC2; 520 break; 521 } 522 523 if ((sc->sc_family == RADEON_RV200) || 524 (sc->sc_family == RADEON_RV250) || 525 (sc->sc_family == RADEON_RV280) || 526 (sc->sc_family == RADEON_RV350)) { 527 bool inverted = 0; 528 /* backlight level is linear */ 529 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 530 prop_dictionary_get_bool(device_properties(sc->sc_dev), 531 "backlight_level_reverted", &inverted); 532 if (inverted) { 533 DPRINTF(("nope, it's inverted\n")); 534 sc->sc_flags |= RFB_INV_BLIGHT; 535 } 536 } else 537 sc->sc_flags |= RFB_INV_BLIGHT; 538 539 /* 540 * XXX: to support true multihead, this must change. 541 */ 542 sc->sc_ndisplays = 1; 543 544 /* XXX: */ 545 if (!HAS_CRTC2(sc)) { 546 sc->sc_ndisplays = 1; 547 } 548 549 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 550 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 551 &sc->sc_regsz) != 0) { 552 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 553 goto error; 554 } 555 556 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 557 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 558 { 559 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 560 goto error; 561 } 562 sc->sc_romt = sc->sc_memt; 563 564 sc->sc_mapped = TRUE; 565 566 /* scratch register test... */ 567 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 568 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 569 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 570 goto error; 571 } 572 573 PRINTREG(RADEON_CRTC_EXT_CNTL); 574 PRINTREG(RADEON_CRTC_GEN_CNTL); 575 PRINTREG(RADEON_CRTC2_GEN_CNTL); 576 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 577 PRINTREG(RADEON_DAC_CNTL2); 578 PRINTREG(RADEON_BIOS_4_SCRATCH); 579 PRINTREG(RADEON_FP_GEN_CNTL); 580 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 581 PRINTREG(RADEON_FP2_GEN_CNTL); 582 PRINTREG(RADEON_TMDS_CNTL); 583 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 584 PRINTREG(RADEON_TMDS_PLL_CNTL); 585 PRINTREG(RADEON_LVDS_GEN_CNTL); 586 PRINTREG(RADEON_DISP_HW_DEBUG); 587 PRINTREG(RADEON_PIXCLKS_CNTL); 588 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 589 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 590 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 592 if (IS_RV100(sc)) 593 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 594 595 /* XXX 596 * according to xf86-video-radeon R3xx has this bit backwards 597 */ 598 if (IS_R300(sc)) { 599 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 600 0, 601 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 602 } else { 603 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 604 RADEON_TMDS_TRANSMITTER_PLLEN, 605 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 606 } 607 608 radeonfb_i2c_init(sc); 609 610 radeonfb_loadbios(sc, pa); 611 612 #ifdef RADEONFB_BIOS_INIT 613 if (radeonfb_bios_init(sc)) { 614 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 615 } 616 #endif 617 618 if (radeonfb_getclocks(sc)) { 619 aprint_error("%s: Unable to get reference clocks from BIOS\n", 620 XNAME(sc)); 621 goto error; 622 } 623 624 if (radeonfb_gettmds(sc)) { 625 aprint_error("%s: Unable to identify TMDS PLL settings\n", 626 XNAME(sc)); 627 goto error; 628 } 629 630 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 631 "minpll = %d, maxpll = %d\n", XNAME(sc), 632 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 633 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 634 635 radeonfb_getconnectors(sc); 636 637 radeonfb_set_fbloc(sc); 638 639 /* 64 MB should be enough -- more just wastes map entries */ 640 if (sc->sc_memsz > (64 << 20)) 641 sc->sc_memsz = (64 << 20); 642 643 for (i = 0; radeonfb_limits[i].size; i++) { 644 if (sc->sc_memsz >= radeonfb_limits[i].size) { 645 sc->sc_maxx = radeonfb_limits[i].maxx; 646 sc->sc_maxy = radeonfb_limits[i].maxy; 647 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 648 /* framebuffer offset, start at a 4K page */ 649 sc->sc_fboffset = sc->sc_memsz / 650 radeonfb_limits[i].maxdisp; 651 /* 652 * we use the fbsize to figure out where we can store 653 * things like cursor data. 654 */ 655 sc->sc_fbsize = 656 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 657 RADEON_STRIDEALIGN) * sc->sc_maxy, 658 4096); 659 break; 660 } 661 } 662 663 664 radeonfb_init_misc(sc); 665 666 /* program the DAC wirings */ 667 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 668 switch (sc->sc_ports[i].rp_dac_type) { 669 case RADEON_DAC_PRIMARY: 670 PATCH32(sc, RADEON_DAC_CNTL2, 671 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 672 ~RADEON_DAC2_DAC_CLK_SEL); 673 break; 674 case RADEON_DAC_TVDAC: 675 /* we always use the TVDAC to drive a secondary analog 676 * CRT for now. if we ever support TV-out this will 677 * have to change. 678 */ 679 SET32(sc, RADEON_DAC_CNTL2, 680 RADEON_DAC2_DAC2_CLK_SEL); 681 PATCH32(sc, RADEON_DISP_HW_DEBUG, 682 i ? 0 : RADEON_CRT2_DISP1_SEL, 683 ~RADEON_CRT2_DISP1_SEL); 684 /* we're using CRTC2 for the 2nd port */ 685 if (sc->sc_ports[i].rp_number == 1) { 686 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 687 RADEON_DISP_DAC2_SOURCE_CRTC2, 688 ~RADEON_DISP_DAC2_SOURCE_MASK); 689 } 690 691 break; 692 } 693 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 694 sc->sc_ports[i].rp_tmds_type)); 695 switch (sc->sc_ports[i].rp_tmds_type) { 696 case RADEON_TMDS_INT: 697 /* point FP0 at the CRTC this port uses */ 698 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 699 __func__, sc->sc_ports[i].rp_number)); 700 if (IS_R300(sc)) { 701 PATCH32(sc, RADEON_FP_GEN_CNTL, 702 sc->sc_ports[i].rp_number ? 703 R200_FP_SOURCE_SEL_CRTC2 : 704 R200_FP_SOURCE_SEL_CRTC1, 705 ~R200_FP_SOURCE_SEL_MASK); 706 } else { 707 PATCH32(sc, RADEON_FP_GEN_CNTL, 708 sc->sc_ports[i].rp_number ? 709 RADEON_FP_SEL_CRTC2 : 710 RADEON_FP_SEL_CRTC1, 711 ~RADEON_FP_SEL_MASK); 712 } 713 break; 714 case RADEON_TMDS_EXT: 715 /* point FP2 at the CRTC this port uses */ 716 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 717 __func__, sc->sc_ports[i].rp_number)); 718 if (IS_R300(sc)) { 719 PATCH32(sc, RADEON_FP2_GEN_CNTL, 720 sc->sc_ports[i].rp_number ? 721 R200_FP2_SOURCE_SEL_CRTC2 : 722 R200_FP2_SOURCE_SEL_CRTC1, 723 ~R200_FP2_SOURCE_SEL_CRTC2); 724 } else { 725 PATCH32(sc, RADEON_FP2_GEN_CNTL, 726 sc->sc_ports[i].rp_number ? 727 RADEON_FP2_SRC_SEL_CRTC2 : 728 RADEON_FP2_SRC_SEL_CRTC1, 729 ~RADEON_FP2_SRC_SEL_CRTC2); 730 } 731 break; 732 } 733 } 734 PRINTREG(RADEON_DAC_CNTL2); 735 PRINTREG(RADEON_DISP_HW_DEBUG); 736 737 PRINTREG(RADEON_DAC_CNTL); 738 /* other DAC programming */ 739 v = GET32(sc, RADEON_DAC_CNTL); 740 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 741 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 742 PUT32(sc, RADEON_DAC_CNTL, v); 743 PRINTREG(RADEON_DAC_CNTL); 744 745 /* XXX: this may need more investigation */ 746 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 747 PRINTREG(RADEON_TV_DAC_CNTL); 748 749 /* enable TMDS */ 750 SET32(sc, RADEON_FP_GEN_CNTL, 751 RADEON_FP_TMDS_EN | 752 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 753 RADEON_FP_CRTC_DONT_SHADOW_HEND); 754 /* 755 * XXX 756 * no idea why this is necessary - if I do not clear this bit on my 757 * iBook G4 the screen remains black, even though it's already clear. 758 * It needs to be set on my Sun XVR-100 for the DVI port to work 759 * TODO: 760 * see if this is still necessary now that CRTCs, DACs and outputs are 761 * getting wired up in a halfway sane way 762 */ 763 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 764 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 765 } else { 766 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 767 } 768 769 /* 770 * we use bus_space_map instead of pci_mapreg, because we don't 771 * need the full aperature space. no point in wasting virtual 772 * address space we don't intend to use, right? 773 */ 774 if ((sc->sc_memsz < (4096 * 1024)) || 775 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 776 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 777 (bsz < sc->sc_memsz)) { 778 sc->sc_memsz = 0; 779 aprint_error("%s: Bad frame buffer configuration\n", 780 XNAME(sc)); 781 goto error; 782 } 783 784 sc->sc_memt = pa->pa_memt; 785 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 786 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 787 sc->sc_memsz = 0; 788 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 789 goto error; 790 } 791 792 aprint_normal("%s: %d MB aperture at 0x%08x, " 793 "%d KB registers at 0x%08x\n", XNAME(sc), 794 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 795 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 796 797 /* setup default video mode from devprop (allows PROM override) */ 798 sc->sc_defaultmode = radeonfb_default_mode; 799 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 800 "videomode", &mptr)) { 801 802 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 803 sc->sc_defaultmode = sc->sc_modebuf; 804 } 805 806 /* initialize some basic display parameters */ 807 for (i = 0; i < sc->sc_ndisplays; i++) { 808 struct radeonfb_display *dp = &sc->sc_displays[i]; 809 struct rasops_info *ri; 810 long defattr; 811 struct wsemuldisplaydev_attach_args aa; 812 813 /* 814 * Figure out how many "displays" (desktops) we are going to 815 * support. If more than one, then each CRTC gets its own 816 * programming. 817 * 818 * XXX: this code needs to change to support mergedfb. 819 * XXX: would be nice to allow this to be overridden 820 */ 821 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 822 DPRINTF(("dual crtcs!\n")); 823 dp->rd_ncrtcs = 2; 824 dp->rd_crtcs[0].rc_port = 825 &sc->sc_ports[0]; 826 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 827 dp->rd_crtcs[1].rc_port = 828 &sc->sc_ports[1]; 829 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 830 } else { 831 dp->rd_ncrtcs = 1; 832 dp->rd_crtcs[0].rc_port = 833 &sc->sc_ports[i]; 834 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 835 } 836 837 dp->rd_softc = sc; 838 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 839 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 840 841 /* for text mode, we pick a resolution that won't 842 * require panning */ 843 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 844 845 aprint_normal("%s: display %d: " 846 "initial virtual resolution %dx%d at %d bpp\n", 847 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 848 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 849 sc->sc_fboffset >> 20); 850 /* now select the *video mode* that we will use */ 851 for (j = 0; j < dp->rd_ncrtcs; j++) { 852 const struct videomode *vmp; 853 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 854 dp->rd_virtx, dp->rd_virty); 855 856 /* 857 * virtual resolution should be at least as high as 858 * physical 859 */ 860 if (dp->rd_virtx < vmp->hdisplay || 861 dp->rd_virty < vmp->vdisplay) { 862 dp->rd_virtx = vmp->hdisplay; 863 dp->rd_virty = vmp->vdisplay; 864 } 865 866 dp->rd_crtcs[j].rc_videomode = *vmp; 867 printf("%s: port %d: physical %dx%d %dHz\n", 868 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 869 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 870 vmp->htotal), vmp->vtotal)); 871 } 872 873 /* N.B.: radeon wants 64-byte aligned stride */ 874 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 875 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 876 DPRINTF(("stride: %d\n", dp->rd_stride)); 877 878 dp->rd_offset = sc->sc_fboffset * i; 879 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 880 sc->sc_memh) + dp->rd_offset; 881 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 882 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 883 884 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 885 886 switch (dp->rd_bpp) { 887 case 8: 888 dp->rd_format = 2; 889 break; 890 case 32: 891 dp->rd_format = 6; 892 break; 893 default: 894 aprint_error("%s: bad depth %d\n", XNAME(sc), 895 dp->rd_bpp); 896 goto error; 897 } 898 899 DPRINTF(("init engine\n")); 900 /* XXX: this seems suspicious - per display engine 901 initialization? */ 902 radeonfb_engine_init(dp); 903 904 /* copy the template into place */ 905 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 906 dp->rd_wsscreens = dp->rd_wsscreens_storage; 907 908 /* and make up the list */ 909 dp->rd_wsscreenlist.nscreens = 1; 910 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 911 912 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 913 &radeonfb_accessops); 914 915 dp->rd_vd.init_screen = radeonfb_init_screen; 916 917 #ifdef RADEONFB_DEBUG 918 dp->rd_virty -= 200; 919 #endif 920 921 dp->rd_console = 0; 922 prop_dictionary_get_bool(device_properties(sc->sc_dev), 923 "is_console", &dp->rd_console); 924 925 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 926 927 928 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 929 dp->rd_console, &defattr); 930 931 ri = &dp->rd_vscreen.scr_ri; 932 933 /* clear the screen */ 934 rasops_unpack_attr(defattr, &fg, &bg, &ul); 935 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 936 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 937 dp->rd_bg); 938 939 dp->rd_wsscreens->textops = &ri->ri_ops; 940 dp->rd_wsscreens->capabilities = ri->ri_caps; 941 dp->rd_wsscreens->nrows = ri->ri_rows; 942 dp->rd_wsscreens->ncols = ri->ri_cols; 943 944 #ifdef SPLASHSCREEN 945 dp->rd_splash.si_depth = ri->ri_depth; 946 dp->rd_splash.si_bits = ri->ri_bits; 947 dp->rd_splash.si_hwbits = ri->ri_hwbits; 948 dp->rd_splash.si_width = ri->ri_width; 949 dp->rd_splash.si_height = ri->ri_height; 950 dp->rd_splash.si_stride = ri->ri_stride; 951 dp->rd_splash.si_fillrect = NULL; 952 #endif 953 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 954 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 955 dp->rd_gc.gc_rop = RADEON_ROP3_S; 956 dp->rd_gc.gc_blitcookie = dp; 957 /* 958 * use memory between framebuffer and cursor area as glyph 959 * cache, cap at 4096 lines 960 */ 961 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 962 min(4096, 963 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 964 dp->rd_virtx, 965 ri->ri_font->fontwidth, 966 ri->ri_font->fontheight, 967 defattr); 968 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 969 dp->rd_vd.show_screen_cb = glyphcache_adapt; 970 971 if (dp->rd_console) { 972 973 radeonfb_modeswitch(dp); 974 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 975 defattr); 976 #ifdef SPLASHSCREEN 977 if (splash_render(&dp->rd_splash, 978 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 979 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 980 else 981 #endif 982 vcons_replay_msgbuf(&dp->rd_vscreen); 983 } else { 984 985 /* 986 * since we're not the console we can postpone 987 * the rest until someone actually allocates a 988 * screen for us. but we do clear the screen 989 * at least. 990 */ 991 memset(ri->ri_bits, 0, 1024); 992 993 radeonfb_modeswitch(dp); 994 #ifdef SPLASHSCREEN 995 if (splash_render(&dp->rd_splash, 996 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 997 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 998 #endif 999 } 1000 1001 aa.console = dp->rd_console; 1002 aa.scrdata = &dp->rd_wsscreenlist; 1003 aa.accessops = &radeonfb_accessops; 1004 aa.accesscookie = &dp->rd_vd; 1005 1006 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1007 1008 radeonfb_blank(dp, 0); 1009 1010 /* Initialise delayed lvds operations for backlight. */ 1011 callout_init(&dp->rd_bl_lvds_co, 0); 1012 callout_setfunc(&dp->rd_bl_lvds_co, 1013 radeonfb_lvds_callout, dp); 1014 dp->rd_bl_on = 1; 1015 dp->rd_bl_level = radeonfb_get_backlight(dp); 1016 radeonfb_set_backlight(dp, dp->rd_bl_level); 1017 } 1018 1019 for (i = 0; i < RADEON_NDISPLAYS; i++) 1020 radeonfb_init_palette(&sc->sc_displays[i]); 1021 1022 if (HAS_CRTC2(sc)) { 1023 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1024 } 1025 1026 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1027 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1028 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1029 radeonfb_brightness_up, TRUE); 1030 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1031 radeonfb_brightness_down, TRUE); 1032 1033 /* 1034 * if we attach a DRM we need to unmap registers in 1035 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1036 * screen blanking we only do it if needed 1037 */ 1038 sc->sc_needs_unmap = 1039 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1040 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1041 1042 PRINTREG(RADEON_CRTC_EXT_CNTL); 1043 PRINTREG(RADEON_CRTC_GEN_CNTL); 1044 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1045 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1046 PRINTREG(RADEON_DAC_CNTL2); 1047 PRINTREG(RADEON_FP_GEN_CNTL); 1048 PRINTREG(RADEON_FP2_GEN_CNTL); 1049 PRINTREG(RADEON_TMDS_CNTL); 1050 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1051 PRINTREG(RADEON_TMDS_PLL_CNTL); 1052 PRINTREG(RADEON_PIXCLKS_CNTL); 1053 1054 return; 1055 1056 error: 1057 if (sc->sc_biossz) 1058 free(sc->sc_bios, M_DEVBUF); 1059 1060 if (sc->sc_regsz) 1061 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1062 1063 if (sc->sc_memsz) 1064 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1065 } 1066 1067 static void 1068 radeonfb_map(struct radeonfb_softc *sc) 1069 { 1070 if (!sc->sc_mapped) { 1071 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1072 &sc->sc_regh) != 0) { 1073 aprint_error_dev(sc->sc_dev, 1074 "unable to map registers!\n"); 1075 return; 1076 } 1077 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1078 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1079 sc->sc_memsz = 0; 1080 aprint_error_dev(sc->sc_dev, 1081 "Unable to map frame buffer\n"); 1082 return; 1083 } 1084 sc->sc_mapped = TRUE; 1085 } 1086 } 1087 1088 static void 1089 radeonfb_unmap(struct radeonfb_softc *sc) 1090 { 1091 if (!sc->sc_needs_unmap) 1092 return; 1093 1094 if (sc->sc_mapped) { 1095 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1096 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1097 sc->sc_mapped = FALSE; 1098 } 1099 } 1100 1101 static int 1102 radeonfb_drm_print(void *aux, const char *pnp) 1103 { 1104 if (pnp) 1105 aprint_normal("drm at %s", pnp); 1106 return (UNCONF); 1107 } 1108 1109 int 1110 radeonfb_ioctl(void *v, void *vs, 1111 unsigned long cmd, void *d, int flag, struct lwp *l) 1112 { 1113 struct vcons_data *vd; 1114 struct radeonfb_display *dp; 1115 struct radeonfb_softc *sc; 1116 struct wsdisplay_param *param; 1117 struct vcons_screen *ms; 1118 1119 vd = (struct vcons_data *)v; 1120 ms = vd->active; 1121 dp = (struct radeonfb_display *)vd->cookie; 1122 sc = dp->rd_softc; 1123 1124 /* can't do these without registers being mapped */ 1125 if (!sc->sc_mapped) { 1126 switch (cmd) { 1127 case WSDISPLAYIO_GVIDEO: 1128 case WSDISPLAYIO_SVIDEO: 1129 case WSDISPLAYIO_GETCMAP: 1130 case WSDISPLAYIO_PUTCMAP: 1131 case WSDISPLAYIO_SCURSOR: 1132 case WSDISPLAYIO_GCURPOS: 1133 case WSDISPLAYIO_SCURPOS: 1134 case WSDISPLAYIO_SETPARAM: 1135 return EINVAL; 1136 } 1137 } 1138 1139 switch (cmd) { 1140 case WSDISPLAYIO_GTYPE: 1141 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1142 return 0; 1143 1144 case WSDISPLAYIO_GINFO: 1145 if (vd->active != NULL) { 1146 struct wsdisplay_fbinfo *fb; 1147 fb = (struct wsdisplay_fbinfo *)d; 1148 fb->width = dp->rd_virtx; 1149 fb->height = dp->rd_virty; 1150 fb->depth = dp->rd_bpp; 1151 fb->cmsize = 256; 1152 return 0; 1153 } else 1154 return ENODEV; 1155 case WSDISPLAYIO_GVIDEO: 1156 if (radeonfb_isblank(dp)) 1157 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1158 else 1159 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1160 return 0; 1161 1162 case WSDISPLAYIO_SVIDEO: 1163 radeonfb_blank(dp, 1164 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1165 radeonfb_switch_backlight(dp, 1166 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1167 return 0; 1168 1169 case WSDISPLAYIO_GETCMAP: 1170 if (dp->rd_bpp == 8) 1171 return radeonfb_getcmap(dp, 1172 (struct wsdisplay_cmap *)d); 1173 return EINVAL; 1174 1175 case WSDISPLAYIO_PUTCMAP: 1176 if (dp->rd_bpp == 8) 1177 return radeonfb_putcmap(dp, 1178 (struct wsdisplay_cmap *)d); 1179 return EINVAL; 1180 1181 case WSDISPLAYIO_LINEBYTES: 1182 *(unsigned *)d = dp->rd_stride; 1183 return 0; 1184 1185 case WSDISPLAYIO_SMODE: 1186 if (*(int *)d != dp->rd_wsmode) { 1187 dp->rd_wsmode = *(int *)d; 1188 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1189 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1190 radeonfb_map(sc); 1191 1192 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1193 (dp->rd_vd.active)) { 1194 radeonfb_engine_init(dp); 1195 glyphcache_wipe(&dp->rd_gc); 1196 radeonfb_init_palette(dp); 1197 radeonfb_modeswitch(dp); 1198 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1199 dp->rd_virty, dp->rd_bg); 1200 vcons_redraw_screen(dp->rd_vd.active); 1201 } 1202 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1203 radeonfb_unmap(sc); 1204 } 1205 return 0; 1206 1207 case WSDISPLAYIO_GCURMAX: 1208 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1209 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1210 return 0; 1211 1212 case WSDISPLAYIO_SCURSOR: 1213 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1214 1215 case WSDISPLAYIO_GCURSOR: 1216 return EPASSTHROUGH; 1217 1218 case WSDISPLAYIO_GCURPOS: 1219 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1220 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1221 return 0; 1222 1223 case WSDISPLAYIO_SCURPOS: 1224 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1225 1226 case WSDISPLAYIO_SSPLASH: 1227 #if defined(SPLASHSCREEN) 1228 if (*(int *)d == 1) { 1229 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1230 splash_render(&dp->rd_splash, 1231 SPLASH_F_CENTER|SPLASH_F_FILL); 1232 } else 1233 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1234 return 0; 1235 #else 1236 return ENODEV; 1237 #endif 1238 case WSDISPLAYIO_GETPARAM: 1239 param = (struct wsdisplay_param *)d; 1240 switch (param->param) { 1241 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1242 param->min = 0; 1243 param->max = 255; 1244 param->curval = dp->rd_bl_level; 1245 return 0; 1246 case WSDISPLAYIO_PARAM_BACKLIGHT: 1247 param->min = 0; 1248 param->max = RADEONFB_BACKLIGHT_MAX; 1249 param->curval = dp->rd_bl_on; 1250 return 0; 1251 } 1252 return EPASSTHROUGH; 1253 1254 case WSDISPLAYIO_SETPARAM: 1255 param = (struct wsdisplay_param *)d; 1256 switch (param->param) { 1257 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1258 radeonfb_set_backlight(dp, param->curval); 1259 return 0; 1260 case WSDISPLAYIO_PARAM_BACKLIGHT: 1261 radeonfb_switch_backlight(dp, param->curval); 1262 return 0; 1263 } 1264 return EPASSTHROUGH; 1265 1266 /* PCI config read/write passthrough. */ 1267 case PCI_IOC_CFGREAD: 1268 case PCI_IOC_CFGWRITE: 1269 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1270 1271 case WSDISPLAYIO_GET_BUSID: 1272 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1273 sc->sc_pt, d); 1274 1275 case WSDISPLAYIO_GET_EDID: { 1276 struct wsdisplayio_edid_info *ei = d; 1277 return wsdisplayio_get_edid(sc->sc_dev, ei); 1278 } 1279 1280 case WSDISPLAYIO_GET_FBINFO: { 1281 struct wsdisplayio_fbinfo *fbi = d; 1282 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1283 } 1284 1285 default: 1286 return EPASSTHROUGH; 1287 } 1288 } 1289 1290 paddr_t 1291 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1292 { 1293 struct vcons_data *vd; 1294 struct radeonfb_display *dp; 1295 struct radeonfb_softc *sc; 1296 paddr_t pa; 1297 1298 vd = (struct vcons_data *)v; 1299 dp = (struct radeonfb_display *)vd->cookie; 1300 sc = dp->rd_softc; 1301 1302 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1303 pa = bus_space_mmap(sc->sc_memt, 1304 sc->sc_memaddr + dp->rd_offset + offset, 0, 1305 prot, BUS_SPACE_MAP_LINEAR); 1306 return pa; 1307 } 1308 1309 /* 1310 * restrict all other mappings to processes with superuser privileges 1311 * or the kernel itself 1312 */ 1313 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1314 NULL, NULL, NULL, NULL) != 0) { 1315 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1316 return -1; 1317 } 1318 1319 if ((offset >= sc->sc_regaddr) && 1320 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1321 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1322 BUS_SPACE_MAP_LINEAR); 1323 } 1324 1325 if ((offset >= sc->sc_memaddr) && 1326 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1327 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1328 BUS_SPACE_MAP_LINEAR); 1329 } 1330 1331 if ((offset >= sc->sc_romaddr) && 1332 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1333 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1334 BUS_SPACE_MAP_LINEAR); 1335 } 1336 1337 #ifdef PCI_MAGIC_IO_RANGE 1338 /* allow mapping of IO space */ 1339 if ((offset >= PCI_MAGIC_IO_RANGE) && 1340 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1341 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1342 0, prot, 0); 1343 return pa; 1344 } 1345 #endif /* PCI_MAGIC_IO_RANGE */ 1346 1347 return -1; 1348 } 1349 1350 static void 1351 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1352 { 1353 bus_space_tag_t romt; 1354 bus_space_handle_t romh, biosh; 1355 bus_size_t romsz; 1356 bus_addr_t ptr; 1357 1358 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1359 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1360 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1361 return; 1362 } 1363 1364 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1365 &sc->sc_biossz); 1366 if (sc->sc_biossz == 0) { 1367 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1368 return; 1369 } 1370 1371 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1372 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1373 1374 /* unmap the PCI expansion rom */ 1375 bus_space_unmap(romt, romh, romsz); 1376 1377 /* turn off rom decoder now */ 1378 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1379 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1380 ~PCI_MAPREG_ROM_ENABLE); 1381 1382 ptr = GETBIOS16(sc, 0x48); 1383 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1384 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1385 sc->sc_flags |= RFB_ATOM; 1386 } 1387 1388 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1389 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1390 } 1391 1392 1393 uint32_t 1394 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1395 { 1396 1397 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1398 } 1399 1400 void 1401 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1402 { 1403 1404 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1405 } 1406 1407 void 1408 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1409 { 1410 1411 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1412 } 1413 1414 void 1415 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1416 uint32_t andmask, uint32_t ormask) 1417 { 1418 int s; 1419 uint32_t val; 1420 1421 s = splhigh(); 1422 val = radeonfb_get32(sc, reg); 1423 val = (val & andmask) | ormask; 1424 radeonfb_put32(sc, reg, val); 1425 splx(s); 1426 } 1427 1428 uint32_t 1429 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1430 { 1431 int s; 1432 uint32_t val; 1433 1434 s = splhigh(); 1435 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1436 val = radeonfb_get32(sc, RADEON_MM_DATA); 1437 splx(s); 1438 1439 return (val); 1440 } 1441 1442 void 1443 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1444 { 1445 int s; 1446 1447 s = splhigh(); 1448 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1449 radeonfb_put32(sc, RADEON_MM_DATA, val); 1450 splx(s); 1451 } 1452 1453 void 1454 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1455 uint32_t andmask, uint32_t ormask) 1456 { 1457 int s; 1458 uint32_t val; 1459 1460 s = splhigh(); 1461 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1462 val = radeonfb_get32(sc, RADEON_MM_DATA); 1463 val = (val & andmask) | ormask; 1464 radeonfb_put32(sc, RADEON_MM_DATA, val); 1465 splx(s); 1466 } 1467 1468 uint32_t 1469 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1470 { 1471 int s; 1472 uint32_t val; 1473 1474 s = splhigh(); 1475 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1476 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1477 if (HAS_R300CG(sc)) 1478 radeonfb_r300cg_workaround(sc); 1479 splx(s); 1480 1481 return (val); 1482 } 1483 1484 void 1485 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1486 { 1487 int s; 1488 1489 s = splhigh(); 1490 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1491 RADEON_PLL_WR_EN); 1492 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1493 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1494 splx(s); 1495 } 1496 1497 void 1498 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1499 uint32_t andmask, uint32_t ormask) 1500 { 1501 int s; 1502 uint32_t val; 1503 1504 s = splhigh(); 1505 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1506 RADEON_PLL_WR_EN); 1507 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1508 val = (val & andmask) | ormask; 1509 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1510 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1511 splx(s); 1512 } 1513 1514 int 1515 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1516 { 1517 uint32_t saved; 1518 1519 saved = GET32(sc, reg); 1520 PUT32(sc, reg, v); 1521 if (GET32(sc, reg) != v) { 1522 return -1; 1523 } 1524 PUT32(sc, reg, saved); 1525 return 0; 1526 } 1527 1528 uintmax_t 1529 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1530 uintmax_t defval) 1531 { 1532 prop_number_t pn; 1533 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1534 if (pn == NULL) { 1535 return defval; 1536 } 1537 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1538 return (prop_number_integer_value(pn)); 1539 } 1540 1541 int 1542 radeonfb_getclocks(struct radeonfb_softc *sc) 1543 { 1544 bus_addr_t ptr; 1545 int refclk = 0; 1546 int refdiv = 0; 1547 int minpll = 0; 1548 int maxpll = 0; 1549 1550 /* load initial property values if port/board provides them */ 1551 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1552 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1553 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1554 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1555 1556 PRINTPLL(RADEON_PPLL_REF_DIV); 1557 PRINTPLL(RADEON_PPLL_DIV_0); 1558 PRINTPLL(RADEON_PPLL_DIV_1); 1559 PRINTPLL(RADEON_PPLL_DIV_2); 1560 PRINTPLL(RADEON_PPLL_DIV_3); 1561 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1562 PRINTPLL(RADEON_P2PLL_REF_DIV); 1563 PRINTPLL(RADEON_P2PLL_DIV_0); 1564 1565 if (refclk && refdiv && minpll && maxpll) 1566 goto dontprobe; 1567 1568 if (!sc->sc_biossz) { 1569 /* no BIOS */ 1570 aprint_verbose("%s: No video BIOS, using default clocks\n", 1571 XNAME(sc)); 1572 if (IS_IGP(sc)) 1573 refclk = refclk ? refclk : 1432; 1574 else 1575 refclk = refclk ? refclk : 2700; 1576 refdiv = refdiv ? refdiv : 12; 1577 minpll = minpll ? minpll : 12500; 1578 /* XXX 1579 * Need to check if the firmware or something programmed a 1580 * higher value than this, and if so, bump it. 1581 * The RV280 in my iBook is unhappy if the PLL input is less 1582 * than 360MHz 1583 */ 1584 maxpll = maxpll ? maxpll : 40000/*35000*/; 1585 } else if (IS_ATOM(sc)) { 1586 /* ATOM BIOS */ 1587 ptr = GETBIOS16(sc, 0x48); 1588 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1589 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1590 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1591 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1592 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1593 /* 1594 * ATOM BIOS doesn't supply a reference divider, so we 1595 * have to probe for it. 1596 */ 1597 if (refdiv < 2) 1598 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1599 RADEON_PPLL_REF_DIV_MASK; 1600 /* 1601 * if probe is zero, just assume one that should work 1602 * for most parts 1603 */ 1604 if (refdiv < 2) 1605 refdiv = 12; 1606 1607 } else { 1608 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1609 /* Legacy BIOS */ 1610 ptr = GETBIOS16(sc, 0x48); 1611 ptr = GETBIOS16(sc, ptr + 0x30); 1612 if (IS_R300(sc)) { 1613 refdiv = refdiv ? refdiv : 1614 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1615 R300_PPLL_REF_DIV_ACC_SHIFT; 1616 } else { 1617 refdiv = refdiv ? refdiv : 1618 tmp & RADEON_PPLL_REF_DIV_MASK; 1619 } 1620 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1621 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1622 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1623 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1624 } 1625 1626 1627 dontprobe: 1628 sc->sc_refclk = refclk * 10; 1629 sc->sc_refdiv = refdiv; 1630 sc->sc_minpll = minpll * 10; 1631 sc->sc_maxpll = maxpll * 10; 1632 return 0; 1633 } 1634 1635 int 1636 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1637 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1638 { 1639 int i; 1640 uint32_t outfreq; 1641 int div; 1642 1643 DPRINTF(("dot clock: %u\n", dotclock)); 1644 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1645 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) continue; 1646 outfreq = div * dotclock; 1647 if ((outfreq >= sc->sc_minpll) && 1648 (outfreq <= sc->sc_maxpll)) { 1649 DPRINTF(("outfreq: %u\n", outfreq)); 1650 *postdivbit = 1651 ((uint32_t)radeonfb_dividers[i].mask << 16); 1652 DPRINTF(("post divider: %d (mask %x)\n", div, 1653 *postdivbit)); 1654 break; 1655 } 1656 } 1657 1658 if (div == 0) 1659 return 1; 1660 1661 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1662 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1663 return 0; 1664 } 1665 1666 #if 0 1667 #ifdef RADEONFB_DEBUG 1668 static void 1669 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1670 { 1671 char asc[17]; 1672 unsigned ptr = (unsigned)buffer; 1673 char *start = (char *)(ptr & ~0xf); 1674 char *end = (char *)(ptr + size); 1675 1676 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1677 1678 if (pfx == NULL) { 1679 pfx = ""; 1680 } 1681 1682 while (start < end) { 1683 unsigned offset = (unsigned)start & 0xf; 1684 if (offset == 0) { 1685 printf("%s%x: ", pfx, (unsigned)start); 1686 } 1687 if (((unsigned)start < ptr) || 1688 ((unsigned)start >= (ptr + size))) { 1689 printf(" "); 1690 asc[offset] = ' '; 1691 } else { 1692 printf("%02x", *(unsigned char *)start); 1693 if ((*start >= ' ') && (*start <= '~')) { 1694 asc[offset] = *start; 1695 } else { 1696 asc[offset] = '.'; 1697 } 1698 } 1699 asc[offset + 1] = 0; 1700 if (offset % 2) { 1701 printf(" "); 1702 } 1703 if (offset == 15) { 1704 printf(" %s\n", asc); 1705 } 1706 start++; 1707 } 1708 } 1709 #endif 1710 #endif 1711 1712 int 1713 radeonfb_getconnectors(struct radeonfb_softc *sc) 1714 { 1715 int i; 1716 int found = 0; 1717 1718 for (i = 0; i < 2; i++) { 1719 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1720 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1721 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1722 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1723 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1724 } 1725 1726 /* 1727 * This logic is borrowed from Xorg's radeon driver. 1728 */ 1729 if (!sc->sc_biossz) 1730 goto nobios; 1731 1732 if (IS_ATOM(sc)) { 1733 /* not done yet */ 1734 } else { 1735 uint16_t ptr; 1736 int port = 0; 1737 1738 ptr = GETBIOS16(sc, 0x48); 1739 ptr = GETBIOS16(sc, ptr + 0x50); 1740 for (i = 1; i < 4; i++) { 1741 uint16_t entry; 1742 uint8_t conn, ddc, dac, tmds; 1743 1744 /* 1745 * Parse the connector table. From reading the code, 1746 * it appears to made up of 16-bit entries for each 1747 * connector. The 16-bits are defined as: 1748 * 1749 * bits 12-15 - connector type (0 == end of table) 1750 * bits 8-11 - DDC type 1751 * bits 5-7 - ??? 1752 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1753 * bits 1-3 - ??? 1754 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1755 */ 1756 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1757 break; 1758 entry = GETBIOS16(sc, ptr + i * 2); 1759 1760 conn = (entry >> 12) & 0xf; 1761 ddc = (entry >> 8) & 0xf; 1762 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1763 RADEON_DAC_PRIMARY; 1764 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1765 RADEON_TMDS_INT; 1766 1767 if (conn == RADEON_CONN_NONE) 1768 continue; /* no connector */ 1769 1770 1771 1772 /* 1773 * XXX 1774 * both Mac Mini variants have both outputs wired to 1775 * the same connector and share the DDC lines 1776 */ 1777 if ((found > 0) && 1778 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1779 /* duplicate entry for same connector */ 1780 continue; 1781 } 1782 1783 /* internal DDC_DVI port gets priority */ 1784 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1785 port = 0; 1786 else 1787 port = 1; 1788 1789 sc->sc_ports[port].rp_ddc_type = 1790 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1791 sc->sc_ports[port].rp_dac_type = dac; 1792 sc->sc_ports[port].rp_conn_type = 1793 min(conn, RADEON_CONN_UNSUPPORTED) ; 1794 1795 sc->sc_ports[port].rp_tmds_type = tmds; 1796 1797 if ((conn != RADEON_CONN_DVI_I) && 1798 (conn != RADEON_CONN_DVI_D) && 1799 (tmds == RADEON_TMDS_INT)) 1800 sc->sc_ports[port].rp_tmds_type = 1801 RADEON_TMDS_UNKNOWN; 1802 sc->sc_ports[port].rp_number = i - 1; 1803 1804 found += (port + 1); 1805 } 1806 } 1807 1808 nobios: 1809 if (!found) { 1810 bool dvi_ext = FALSE, dvi_int = FALSE; 1811 DPRINTF(("No connector info in BIOS!\n")); 1812 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1813 "dvi-internal", &dvi_int); 1814 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1815 "dvi-external", &dvi_ext); 1816 if (dvi_ext) { 1817 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1818 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1819 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1820 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1821 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1822 sc->sc_ports[0].rp_number = 0; 1823 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1824 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1825 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1826 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1827 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1828 sc->sc_ports[1].rp_number = 1; 1829 } else if (dvi_int) { 1830 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1831 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1832 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1833 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1834 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1835 sc->sc_ports[0].rp_number = 0; 1836 } else if IS_MOBILITY(sc) { 1837 /* default, port 0 = internal TMDS, port 1 = CRT */ 1838 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1839 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1840 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1841 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1842 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1843 sc->sc_ports[0].rp_number = 0; 1844 1845 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1846 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1847 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1848 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1849 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1850 sc->sc_ports[1].rp_number = 1; 1851 } else { 1852 /* default, port 0 = DVI, port 1 = CRT */ 1853 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1854 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1855 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1856 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1857 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1858 sc->sc_ports[0].rp_number = 1; 1859 1860 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1861 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1862 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1863 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1864 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1865 sc->sc_ports[1].rp_number = 0; 1866 } 1867 } 1868 1869 /* 1870 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1871 * these chips should use TVDAC for the VGA port. 1872 */ 1873 if (HAS_SDAC(sc)) { 1874 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1875 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1876 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1877 } else { 1878 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1879 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1880 } 1881 } else if (!HAS_CRTC2(sc)) { 1882 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1883 } 1884 1885 for (i = 0; i < 2; i++) { 1886 char edid[128]; 1887 uint8_t ddc; 1888 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1889 prop_data_t edid_data; 1890 1891 DPRINTF(("Port #%d:\n", i)); 1892 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1893 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1894 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1895 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1896 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1897 1898 sc->sc_ports[i].rp_edid_valid = 0; 1899 /* first look for static EDID data */ 1900 if ((edid_data = prop_dictionary_get(device_properties( 1901 sc->sc_dev), "EDID")) != NULL) { 1902 1903 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1904 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1905 if (edid_parse(edid, eip) == 0) { 1906 1907 sc->sc_ports[i].rp_edid_valid = 1; 1908 } 1909 } 1910 /* if we didn't find any we'll try to talk to the monitor */ 1911 if (sc->sc_ports[i].rp_edid_valid != 1) { 1912 1913 ddc = sc->sc_ports[i].rp_ddc_type; 1914 if (ddc != RADEON_DDC_NONE) { 1915 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1916 == 0) && (edid_parse(edid, eip) == 0)) { 1917 1918 sc->sc_ports[i].rp_edid_valid = 1; 1919 #ifdef RADEONFB_DEBUG 1920 edid_print(eip); 1921 #endif 1922 } 1923 } 1924 } 1925 } 1926 1927 return found; 1928 } 1929 1930 int 1931 radeonfb_gettmds(struct radeonfb_softc *sc) 1932 { 1933 int i; 1934 1935 if (!sc->sc_biossz) { 1936 goto nobios; 1937 } 1938 1939 if (IS_ATOM(sc)) { 1940 /* XXX: not done yet */ 1941 } else { 1942 uint16_t ptr; 1943 int n; 1944 1945 ptr = GETBIOS16(sc, 0x48); 1946 ptr = GETBIOS16(sc, ptr + 0x34); 1947 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1948 if (GETBIOS8(sc, ptr) == 3) { 1949 /* revision three table */ 1950 n = GETBIOS8(sc, ptr + 5) + 1; 1951 n = min(n, 4); 1952 1953 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1954 for (i = 0; i < n; i++) { 1955 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1956 ptr + i * 10 + 8); 1957 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1958 ptr + i * 10 + 0x10); 1959 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1960 sc->sc_tmds_pll[i].rtp_freq, 1961 sc->sc_tmds_pll[i].rtp_pll)); 1962 } 1963 return 0; 1964 } 1965 } 1966 1967 nobios: 1968 DPRINTF(("no suitable DFP table present\n")); 1969 for (i = 0; 1970 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1971 i++) { 1972 int j; 1973 1974 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1975 continue; 1976 1977 for (j = 0; j < 4; j++) { 1978 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1979 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1980 sc->sc_tmds_pll[j].rtp_freq, 1981 sc->sc_tmds_pll[j].rtp_pll)); 1982 } 1983 return 0; 1984 } 1985 1986 return -1; 1987 } 1988 1989 const struct videomode * 1990 radeonfb_modelookup(const char *name) 1991 { 1992 int i; 1993 1994 for (i = 0; i < videomode_count; i++) 1995 if (!strcmp(name, videomode_list[i].name)) 1996 return &videomode_list[i]; 1997 1998 return NULL; 1999 } 2000 2001 void 2002 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2003 { 2004 if (crtc) { 2005 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2006 RADEON_P2PLL_ATOMIC_UPDATE_R); 2007 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2008 } else { 2009 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2010 RADEON_PPLL_ATOMIC_UPDATE_R); 2011 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2012 } 2013 } 2014 2015 void 2016 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2017 { 2018 int i; 2019 2020 for (i = 10000; i; i--) { 2021 if (crtc) { 2022 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2023 RADEON_P2PLL_ATOMIC_UPDATE_R) 2024 break; 2025 } else { 2026 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2027 RADEON_PPLL_ATOMIC_UPDATE_R) 2028 break; 2029 } 2030 } 2031 } 2032 2033 void 2034 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2035 { 2036 uint32_t pbit = 0; 2037 uint32_t feed = 0; 2038 uint32_t data, refdiv, div0; 2039 2040 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2041 2042 if (crtc == 0) { 2043 2044 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2045 if (IS_R300(sc)) { 2046 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2047 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2048 } else { 2049 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2050 sc->sc_refdiv; 2051 } 2052 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2053 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2054 RADEON_PPLL_POST3_DIV_MASK); 2055 div0 |= pbit; 2056 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2057 2058 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2059 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2060 /* 2061 * nothing to do here, the PLL is already where we 2062 * want it 2063 */ 2064 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2065 ~RADEON_PLL_DIV_SEL); 2066 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2067 return; 2068 } 2069 2070 /* alright, we do need to reprogram stuff */ 2071 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2072 RADEON_VCLK_SRC_SEL_CPUCLK, 2073 ~RADEON_VCLK_SRC_SEL_MASK); 2074 2075 /* put vclk into reset, use atomic updates */ 2076 SETPLL(sc, RADEON_PPLL_CNTL, 2077 RADEON_PPLL_REFCLK_SEL | 2078 RADEON_PPLL_FBCLK_SEL | 2079 RADEON_PPLL_RESET | 2080 RADEON_PPLL_ATOMIC_UPDATE_EN | 2081 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2082 2083 /* select clock 0 */ 2084 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2085 ~RADEON_PLL_DIV_SEL); 2086 2087 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2088 2089 /* xf86-video-radeon does this, not sure why */ 2090 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2091 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2092 2093 /* use the atomic update */ 2094 radeonfb_pllwriteupdate(sc, crtc); 2095 2096 /* and wait for it to complete */ 2097 radeonfb_pllwaitatomicread(sc, crtc); 2098 2099 /* program HTOTAL (why?) */ 2100 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2101 2102 /* drop reset */ 2103 CLRPLL(sc, RADEON_PPLL_CNTL, 2104 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2105 RADEON_PPLL_ATOMIC_UPDATE_EN | 2106 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2107 2108 PRINTPLL(RADEON_PPLL_CNTL); 2109 PRINTPLL(RADEON_PPLL_REF_DIV); 2110 PRINTPLL(RADEON_PPLL_DIV_3); 2111 2112 /* give clock time to lock */ 2113 delay(50000); 2114 2115 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2116 RADEON_VCLK_SRC_SEL_PPLLCLK, 2117 ~RADEON_VCLK_SRC_SEL_MASK); 2118 2119 } else { 2120 2121 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2122 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2123 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2124 2125 /* put vclk into reset, use atomic updates */ 2126 SETPLL(sc, RADEON_P2PLL_CNTL, 2127 RADEON_P2PLL_RESET | 2128 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2129 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2130 2131 /* program reference divider */ 2132 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2133 ~RADEON_P2PLL_REF_DIV_MASK); 2134 2135 /* program feedback and post dividers */ 2136 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2137 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2138 RADEON_P2PLL_POST0_DIV_MASK); 2139 data |= pbit; 2140 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2141 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2142 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2143 2144 PRINTPLL(RADEON_P2PLL_REF_DIV); 2145 PRINTPLL(RADEON_P2PLL_DIV_0); 2146 2147 /* use the atomic update */ 2148 radeonfb_pllwriteupdate(sc, crtc); 2149 2150 /* and wait for it to complete */ 2151 radeonfb_pllwaitatomicread(sc, crtc); 2152 2153 /* program HTOTAL (why?) */ 2154 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2155 2156 /* drop reset */ 2157 CLRPLL(sc, RADEON_P2PLL_CNTL, 2158 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2159 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2160 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2161 2162 /* allow time for clock to lock */ 2163 delay(50000); 2164 2165 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2166 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2167 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2168 } 2169 PRINTREG(RADEON_CRTC_MORE_CNTL); 2170 } 2171 2172 void 2173 radeonfb_modeswitch(struct radeonfb_display *dp) 2174 { 2175 struct radeonfb_softc *sc = dp->rd_softc; 2176 int i; 2177 2178 /* blank the display while we switch modes */ 2179 radeonfb_blank(dp, 1); 2180 2181 #if 0 2182 SET32(sc, RADEON_CRTC_EXT_CNTL, 2183 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2184 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2185 #endif 2186 2187 /* these registers might get in the way... */ 2188 PUT32(sc, RADEON_OVR_CLR, 0); 2189 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2190 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2191 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2192 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2193 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2194 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2195 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2196 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2197 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2198 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2199 2200 for (i = 0; i < dp->rd_ncrtcs; i++) 2201 radeonfb_setcrtc(dp, i); 2202 2203 #if 0 2204 /* 2205 * DVO chip voodoo from xf86-video-radeon 2206 * apparently this is needed for some powerbooks with DVI outputs 2207 */ 2208 2209 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2210 int n = 0; 2211 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2212 for (i = 0; i < 5; i++) 2213 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2214 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2215 printf("n = %d\n", n); 2216 #endif 2217 2218 /* activate the display */ 2219 radeonfb_blank(dp, 0); 2220 } 2221 2222 void 2223 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2224 { 2225 int crtc, flags = 0; 2226 struct videomode *mode; 2227 struct radeonfb_softc *sc; 2228 struct radeonfb_crtc *cp; 2229 uint32_t v; 2230 uint32_t gencntl; 2231 uint32_t htotaldisp; 2232 uint32_t hsyncstrt; 2233 uint32_t vtotaldisp; 2234 uint32_t vsyncstrt; 2235 uint32_t fphsyncstrt; 2236 uint32_t fpvsyncstrt; 2237 uint32_t fphtotaldisp; 2238 uint32_t fpvtotaldisp; 2239 uint32_t pitch; 2240 2241 sc = dp->rd_softc; 2242 2243 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2244 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2245 flags |= NO_ODD_FBDIV; 2246 } 2247 2248 cp = &dp->rd_crtcs[index]; 2249 crtc = cp->rc_number; 2250 mode = &cp->rc_videomode; 2251 2252 #if 1 2253 pitch = dp->rd_stride / dp->rd_bpp; 2254 #else 2255 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2256 (sc->sc_maxbpp * 8)); 2257 #endif 2258 switch (crtc) { 2259 case 0: 2260 gencntl = RADEON_CRTC_GEN_CNTL; 2261 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2262 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2263 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2264 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2265 /* should probably leave those alone on non-LVDS */ 2266 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2267 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2268 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2269 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2270 break; 2271 case 1: 2272 gencntl = RADEON_CRTC2_GEN_CNTL; 2273 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2274 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2275 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2276 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2277 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2278 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2279 /* XXX these registers don't seem to exist */ 2280 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2281 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2282 break; 2283 default: 2284 panic("Bad CRTC!"); 2285 break; 2286 } 2287 2288 /* 2289 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2290 */ 2291 /* only bother with 32bpp and 8bpp */ 2292 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2293 2294 if (crtc == 1) { 2295 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2296 } else { 2297 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2298 } 2299 2300 if (mode->flags & VID_DBLSCAN) 2301 v |= RADEON_CRTC2_DBL_SCAN_EN; 2302 2303 if (mode->flags & VID_INTERLACE) 2304 v |= RADEON_CRTC2_INTERLACE_EN; 2305 2306 if (mode->flags & VID_CSYNC) { 2307 v |= RADEON_CRTC2_CSYNC_EN; 2308 if (crtc == 1) 2309 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2310 } 2311 2312 PUT32(sc, gencntl, v); 2313 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2314 2315 /* 2316 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2317 */ 2318 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2319 if (crtc == 0) { 2320 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2321 RADEON_CRTC_DISPLAY_DIS); 2322 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2323 if (mode->flags & VID_CSYNC) 2324 v |= RADEON_CRTC_VSYNC_TRISTAT; 2325 } 2326 /* unconditional turn on CRT, in case first CRTC is DFP */ 2327 v |= RADEON_CRTC_CRT_ON; 2328 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2329 PRINTREG(RADEON_CRTC_EXT_CNTL); 2330 2331 /* 2332 * H_TOTAL_DISP 2333 */ 2334 v = ((mode->hdisplay / 8) - 1) << 16; 2335 v |= (mode->htotal / 8) - 1; 2336 PUT32(sc, htotaldisp, v); 2337 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2338 if (fphtotaldisp) { 2339 PUT32(sc, fphtotaldisp, v); 2340 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2341 } 2342 /* 2343 * H_SYNC_STRT_WID 2344 */ 2345 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2346 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2347 if (mode->flags & VID_NHSYNC) 2348 v |= RADEON_CRTC_H_SYNC_POL; 2349 PUT32(sc, hsyncstrt, v); 2350 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2351 if (fphsyncstrt) { 2352 PUT32(sc, fphsyncstrt, v); 2353 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2354 } 2355 2356 /* 2357 * V_TOTAL_DISP 2358 */ 2359 v = ((mode->vdisplay - 1) << 16); 2360 v |= (mode->vtotal - 1); 2361 PUT32(sc, vtotaldisp, v); 2362 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2363 if (fpvtotaldisp) { 2364 PUT32(sc, fpvtotaldisp, v); 2365 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2366 } 2367 2368 /* 2369 * V_SYNC_STRT_WID 2370 */ 2371 v = ((mode->vsync_end - mode->vsync_start) << 16); 2372 v |= (mode->vsync_start - 1); 2373 if (mode->flags & VID_NVSYNC) 2374 v |= RADEON_CRTC_V_SYNC_POL; 2375 PUT32(sc, vsyncstrt, v); 2376 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2377 if (fpvsyncstrt) { 2378 PUT32(sc, fpvsyncstrt, v); 2379 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2380 } 2381 2382 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2383 2384 switch (crtc) { 2385 case 0: 2386 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2387 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2388 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2389 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2390 2391 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2392 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2393 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2394 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2395 PRINTREG(RADEON_CRTC_EXT_CNTL); 2396 PRINTREG(RADEON_CRTC_GEN_CNTL); 2397 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2398 break; 2399 2400 case 1: 2401 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2402 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2403 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2404 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2405 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2406 RADEON_CRTC2_VSYNC_DIS | 2407 RADEON_CRTC2_HSYNC_DIS | 2408 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2409 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2410 break; 2411 } 2412 } 2413 2414 int 2415 radeonfb_isblank(struct radeonfb_display *dp) 2416 { 2417 uint32_t reg, mask; 2418 2419 if(!dp->rd_softc->sc_mapped) 2420 return 1; 2421 2422 if (dp->rd_crtcs[0].rc_number) { 2423 reg = RADEON_CRTC2_GEN_CNTL; 2424 mask = RADEON_CRTC2_DISP_DIS; 2425 } else { 2426 reg = RADEON_CRTC_EXT_CNTL; 2427 mask = RADEON_CRTC_DISPLAY_DIS; 2428 } 2429 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2430 } 2431 2432 void 2433 radeonfb_blank(struct radeonfb_display *dp, int blank) 2434 { 2435 struct radeonfb_softc *sc = dp->rd_softc; 2436 uint32_t reg, mask; 2437 uint32_t fpreg, fpval; 2438 int i; 2439 2440 if (!sc->sc_mapped) 2441 return; 2442 2443 for (i = 0; i < dp->rd_ncrtcs; i++) { 2444 2445 if (dp->rd_crtcs[i].rc_number) { 2446 reg = RADEON_CRTC2_GEN_CNTL; 2447 mask = RADEON_CRTC2_DISP_DIS; 2448 fpreg = RADEON_FP2_GEN_CNTL; 2449 fpval = RADEON_FP2_ON; 2450 } else { 2451 reg = RADEON_CRTC_EXT_CNTL; 2452 mask = RADEON_CRTC_DISPLAY_DIS; 2453 fpreg = RADEON_FP_GEN_CNTL; 2454 fpval = RADEON_FP_FPON; 2455 } 2456 2457 if (blank) { 2458 SET32(sc, reg, mask); 2459 CLR32(sc, fpreg, fpval); 2460 } else { 2461 CLR32(sc, reg, mask); 2462 SET32(sc, fpreg, fpval); 2463 } 2464 } 2465 PRINTREG(RADEON_FP_GEN_CNTL); 2466 PRINTREG(RADEON_FP2_GEN_CNTL); 2467 } 2468 2469 void 2470 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2471 long *defattr) 2472 { 2473 struct radeonfb_display *dp = cookie; 2474 struct rasops_info *ri = &scr->scr_ri; 2475 2476 /* initialize font subsystem */ 2477 wsfont_init(); 2478 2479 scr->scr_flags |= VCONS_LOADFONT; 2480 2481 DPRINTF(("init screen called, existing %d\n", existing)); 2482 2483 ri->ri_depth = dp->rd_bpp; 2484 ri->ri_width = dp->rd_virtx; 2485 ri->ri_height = dp->rd_virty; 2486 ri->ri_stride = dp->rd_stride; 2487 ri->ri_flg = RI_CENTER; 2488 switch (ri->ri_depth) { 2489 case 8: 2490 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2491 break; 2492 case 32: 2493 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2494 /* we run radeons in RGB even on SPARC hardware */ 2495 ri->ri_rnum = 8; 2496 ri->ri_gnum = 8; 2497 ri->ri_bnum = 8; 2498 ri->ri_rpos = 16; 2499 ri->ri_gpos = 8; 2500 ri->ri_bpos = 0; 2501 break; 2502 } 2503 2504 ri->ri_bits = (void *)dp->rd_fbptr; 2505 2506 #ifdef VCONS_DRAW_INTR 2507 scr->scr_flags |= VCONS_DONT_READ; 2508 #endif 2509 2510 if (existing) { 2511 ri->ri_flg |= RI_CLEAR; 2512 2513 /* start a modeswitch now */ 2514 radeonfb_modeswitch(dp); 2515 } 2516 2517 /* 2518 * XXX: font selection should be based on properties, with some 2519 * normal/reasonable default. 2520 */ 2521 2522 /* initialize and look for an initial font */ 2523 rasops_init(ri, 0, 0); 2524 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2525 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2526 2527 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2528 dp->rd_virtx / ri->ri_font->fontwidth); 2529 2530 /* enable acceleration */ 2531 dp->rd_putchar = ri->ri_ops.putchar; 2532 ri->ri_ops.copyrows = radeonfb_copyrows; 2533 ri->ri_ops.copycols = radeonfb_copycols; 2534 ri->ri_ops.eraserows = radeonfb_eraserows; 2535 ri->ri_ops.erasecols = radeonfb_erasecols; 2536 /* pick a putchar method based on font and Radeon model */ 2537 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2538 /* got a bitmap font */ 2539 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2540 if (IS_R300(dp->rd_softc)) { 2541 /* 2542 * radeonfb_putchar() doesn't work right on some R3xx 2543 * so we use software drawing here, the wrapper just 2544 * makes sure the engine is idle before scribbling 2545 * into vram 2546 */ 2547 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2548 } else 2549 #endif 2550 ri->ri_ops.putchar = radeonfb_putchar; 2551 } else { 2552 /* got an alpha font */ 2553 switch(ri->ri_depth) { 2554 case 32: 2555 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2556 break; 2557 case 8: 2558 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2559 break; 2560 default: 2561 /* XXX this should never happen */ 2562 panic("%s: depth is not 8 or 32 but we got an" \ 2563 " alpha font?!", __func__); 2564 } 2565 } 2566 ri->ri_ops.cursor = radeonfb_cursor; 2567 } 2568 2569 void 2570 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2571 { 2572 uint32_t gen, ext, gen2 = 0; 2573 uint32_t agploc, aperbase, apersize, mcfbloc; 2574 2575 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2576 /* XXX */ 2577 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2578 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2579 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2580 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2581 2582 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2583 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2584 #if 0 2585 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2586 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2587 #endif 2588 2589 if (HAS_CRTC2(sc)) { 2590 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2591 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2592 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2593 } 2594 2595 delay(100000); 2596 2597 mcfbloc = (aperbase >> 16) | 2598 ((aperbase + (apersize - 1)) & 0xffff0000); 2599 2600 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2601 sc->sc_memsz = apersize; 2602 2603 if (((agploc & 0xffff) << 16) != 2604 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2605 agploc = mcfbloc & 0xffff0000U; 2606 agploc |= ((agploc + 0x10000) >> 16); 2607 } 2608 2609 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2610 2611 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2612 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2613 2614 DPRINTF(("aperbase = %u\n", aperbase)); 2615 PRINTREG(RADEON_MC_FB_LOCATION); 2616 PRINTREG(RADEON_MC_AGP_LOCATION); 2617 2618 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2619 2620 if (HAS_CRTC2(sc)) 2621 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2622 2623 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2624 2625 #if 0 2626 /* XXX: what is this AGP garbage? :-) */ 2627 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2628 #endif 2629 2630 delay(100000); 2631 2632 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2633 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2634 2635 if (HAS_CRTC2(sc)) 2636 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2637 } 2638 2639 void 2640 radeonfb_init_misc(struct radeonfb_softc *sc) 2641 { 2642 PUT32(sc, RADEON_BUS_CNTL, 2643 RADEON_BUS_MASTER_DIS | 2644 RADEON_BUS_PREFETCH_MODE_ACT | 2645 RADEON_BUS_PCI_READ_RETRY_EN | 2646 RADEON_BUS_PCI_WRT_RETRY_EN | 2647 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2648 RADEON_BUS_MSTR_RD_MULT | 2649 RADEON_BUS_MSTR_RD_LINE | 2650 RADEON_BUS_RD_DISCARD_EN | 2651 RADEON_BUS_MSTR_DISCONNECT_EN | 2652 RADEON_BUS_READ_BURST); 2653 2654 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2655 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2656 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2657 PUT32(sc, RADEON_RBBM_CNTL, 2658 (3 << RADEON_RB_SETTLE_SHIFT) | 2659 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2660 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2661 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2662 2663 /* XXX: figure out what these mean! */ 2664 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2665 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2666 #if 0 2667 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2668 #endif 2669 2670 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2671 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2672 } 2673 2674 static void 2675 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2676 { 2677 struct radeonfb_softc *sc = dp->rd_softc; 2678 int crtc, cc; 2679 uint32_t vclk; 2680 2681 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2682 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2683 2684 /* initialize the palette for every CRTC used by this display */ 2685 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2686 crtc = dp->rd_crtcs[cc].rc_number; 2687 2688 if (crtc) 2689 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2690 else 2691 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2692 2693 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2694 PUT32(sc, RADEON_PALETTE_30_DATA, 2695 (r << 22) | (g << 12) | (b << 2)); 2696 } 2697 2698 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2699 } 2700 2701 /* 2702 * This loads a linear color map for true color. 2703 */ 2704 void 2705 radeonfb_init_palette(struct radeonfb_display *dp) 2706 { 2707 int i; 2708 2709 #define DAC_WIDTH ((1 << 10) - 1) 2710 #define CLUT_WIDTH ((1 << 8) - 1) 2711 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2712 2713 if (dp->rd_bpp == 8) { 2714 2715 /* R3G3B2 palette */ 2716 uint32_t tmp, r, g, b; 2717 2718 for (i = 0; i <= CLUT_WIDTH; ++i) { 2719 tmp = i & 0xe0; 2720 2721 /* 2722 * replicate bits so 0xe0 maps to a red value of 0xff 2723 * in order to make white look actually white 2724 */ 2725 tmp |= (tmp >> 3) | (tmp >> 6); 2726 r = tmp; 2727 2728 tmp = (i & 0x1c) << 3; 2729 tmp |= (tmp >> 3) | (tmp >> 6); 2730 g = tmp; 2731 2732 tmp = (i & 0x03) << 6; 2733 tmp |= tmp >> 2; 2734 tmp |= tmp >> 4; 2735 b = tmp; 2736 2737 radeonfb_putpal(dp, i, r, g, b); 2738 } 2739 } else { 2740 /* linear ramp */ 2741 for (i = 0; i <= CLUT_WIDTH; ++i) { 2742 radeonfb_putpal(dp, i, i, i, i); 2743 } 2744 } 2745 } 2746 2747 static int 2748 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2749 { 2750 u_char *r, *g, *b; 2751 u_int index = cm->index; 2752 u_int count = cm->count; 2753 int i, error; 2754 u_char rbuf[256], gbuf[256], bbuf[256]; 2755 2756 #ifdef GENFB_DEBUG 2757 aprint_debug("putcmap: %d %d\n",index, count); 2758 #endif 2759 if (cm->index >= 256 || cm->count > 256 || 2760 (cm->index + cm->count) > 256) 2761 return EINVAL; 2762 error = copyin(cm->red, &rbuf[index], count); 2763 if (error) 2764 return error; 2765 error = copyin(cm->green, &gbuf[index], count); 2766 if (error) 2767 return error; 2768 error = copyin(cm->blue, &bbuf[index], count); 2769 if (error) 2770 return error; 2771 2772 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2773 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2774 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2775 2776 r = &dp->rd_cmap_red[index]; 2777 g = &dp->rd_cmap_green[index]; 2778 b = &dp->rd_cmap_blue[index]; 2779 2780 for (i = 0; i < count; i++) { 2781 radeonfb_putpal(dp, index, *r, *g, *b); 2782 index++; 2783 r++, g++, b++; 2784 } 2785 return 0; 2786 } 2787 2788 static int 2789 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2790 { 2791 u_int index = cm->index; 2792 u_int count = cm->count; 2793 int error; 2794 2795 if (index >= 255 || count > 256 || index + count > 256) 2796 return EINVAL; 2797 2798 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2799 if (error) 2800 return error; 2801 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2802 if (error) 2803 return error; 2804 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2805 if (error) 2806 return error; 2807 2808 return 0; 2809 } 2810 2811 /* 2812 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2813 */ 2814 void 2815 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2816 { 2817 uint32_t tmp, save; 2818 2819 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2820 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2821 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2822 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2823 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2824 } 2825 2826 /* 2827 * Acceleration entry points. 2828 */ 2829 2830 /* this one draws characters using bitmap fonts */ 2831 static void 2832 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2833 { 2834 struct rasops_info *ri = cookie; 2835 struct vcons_screen *scr = ri->ri_hw; 2836 struct radeonfb_display *dp = scr->scr_cookie; 2837 struct radeonfb_softc *sc = dp->rd_softc; 2838 struct wsdisplay_font *font = PICK_FONT(ri, c); 2839 uint32_t w, h; 2840 int xd, yd, offset, i; 2841 uint32_t bg, fg, gmc; 2842 uint32_t reg; 2843 uint8_t *data8; 2844 uint16_t *data16; 2845 void *data; 2846 2847 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2848 return; 2849 2850 if (!CHAR_IN_FONT(c, font)) 2851 return; 2852 2853 w = font->fontwidth; 2854 h = font->fontheight; 2855 2856 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2857 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2858 2859 xd = ri->ri_xorigin + col * w; 2860 yd = ri->ri_yorigin + row * h; 2861 2862 if (c == 0x20) { 2863 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2864 return; 2865 } 2866 data = WSFONT_GLYPH(c, font); 2867 2868 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2869 2870 radeonfb_wait_fifo(sc, 9); 2871 2872 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2873 RADEON_GMC_BRUSH_NONE | 2874 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2875 RADEON_GMC_DST_CLIPPING | 2876 RADEON_ROP3_S | 2877 RADEON_DP_SRC_SOURCE_HOST_DATA | 2878 RADEON_GMC_CLR_CMP_CNTL_DIS | 2879 RADEON_GMC_WR_MSK_DIS | 2880 gmc); 2881 2882 PUT32(sc, RADEON_SC_LEFT, xd); 2883 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2884 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2885 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2886 PUT32(sc, RADEON_DP_CNTL, 2887 RADEON_DST_X_LEFT_TO_RIGHT | 2888 RADEON_DST_Y_TOP_TO_BOTTOM); 2889 2890 PUT32(sc, RADEON_SRC_X_Y, 0); 2891 offset = 32 - (font->stride << 3); 2892 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2893 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2894 2895 radeonfb_wait_fifo(sc, h); 2896 switch (font->stride) { 2897 case 1: { 2898 data8 = data; 2899 for (i = 0; i < h; i++) { 2900 reg = *data8; 2901 #if BYTE_ORDER == LITTLE_ENDIAN 2902 reg = reg << 24; 2903 #endif 2904 bus_space_write_stream_4(sc->sc_regt, 2905 sc->sc_regh, RADEON_HOST_DATA0, reg); 2906 data8++; 2907 } 2908 break; 2909 } 2910 case 2: { 2911 data16 = data; 2912 for (i = 0; i < h; i++) { 2913 reg = *data16; 2914 #if BYTE_ORDER == LITTLE_ENDIAN 2915 reg = reg << 16; 2916 #endif 2917 bus_space_write_stream_4(sc->sc_regt, 2918 sc->sc_regh, RADEON_HOST_DATA0, reg); 2919 data16++; 2920 } 2921 break; 2922 } 2923 } 2924 if (attr & 1) 2925 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2926 } 2927 2928 /* ... while this one is for anti-aliased ones */ 2929 static void 2930 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2931 { 2932 struct rasops_info *ri = cookie; 2933 struct vcons_screen *scr = ri->ri_hw; 2934 struct radeonfb_display *dp = scr->scr_cookie; 2935 struct radeonfb_softc *sc = dp->rd_softc; 2936 struct wsdisplay_font *font = PICK_FONT(ri, c); 2937 uint32_t bg, fg, gmc; 2938 uint8_t *data; 2939 int w, h, xd, yd; 2940 int i, r, g, b, aval; 2941 int rf, gf, bf, rb, gb, bb; 2942 uint32_t pixel; 2943 int rv; 2944 2945 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2946 return; 2947 2948 if (!CHAR_IN_FONT(c, font)) 2949 return; 2950 2951 w = font->fontwidth; 2952 h = font->fontheight; 2953 2954 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2955 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2956 2957 xd = ri->ri_xorigin + col * w; 2958 yd = ri->ri_yorigin + row * h; 2959 2960 if (c == 0x20) { 2961 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2962 if (attr & 1) 2963 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2964 return; 2965 } 2966 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2967 if (rv == GC_OK) 2968 return; 2969 2970 data = WSFONT_GLYPH(c, font); 2971 2972 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2973 2974 radeonfb_wait_fifo(sc, 5); 2975 2976 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2977 RADEON_GMC_BRUSH_NONE | 2978 RADEON_GMC_SRC_DATATYPE_COLOR | 2979 RADEON_ROP3_S | 2980 RADEON_DP_SRC_SOURCE_HOST_DATA | 2981 RADEON_GMC_CLR_CMP_CNTL_DIS | 2982 RADEON_GMC_WR_MSK_DIS | 2983 gmc); 2984 2985 PUT32(sc, RADEON_DP_CNTL, 2986 RADEON_DST_X_LEFT_TO_RIGHT | 2987 RADEON_DST_Y_TOP_TO_BOTTOM); 2988 2989 PUT32(sc, RADEON_SRC_X_Y, 0); 2990 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 2991 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 2992 2993 rf = (fg >> 16) & 0xff; 2994 rb = (bg >> 16) & 0xff; 2995 gf = (fg >> 8) & 0xff; 2996 gb = (bg >> 8) & 0xff; 2997 bf = fg & 0xff; 2998 bb = bg & 0xff; 2999 3000 /* 3001 * I doubt we can upload data faster than even the slowest Radeon 3002 * could process them, especially when doing the alpha blending stuff 3003 * along the way, so just make sure there's some room in the FIFO and 3004 * then hammer away 3005 * As it turns out we can, so make periodic stops to let the FIFO 3006 * drain. 3007 */ 3008 radeonfb_wait_fifo(sc, 20); 3009 for (i = 0; i < ri->ri_fontscale; i++) { 3010 aval = *data; 3011 data++; 3012 if (aval == 0) { 3013 pixel = bg; 3014 } else if (aval == 255) { 3015 pixel = fg; 3016 } else { 3017 r = aval * rf + (255 - aval) * rb; 3018 g = aval * gf + (255 - aval) * gb; 3019 b = aval * bf + (255 - aval) * bb; 3020 pixel = (r & 0xff00) << 8 | 3021 (g & 0xff00) | 3022 (b & 0xff00) >> 8; 3023 } 3024 if (i & 16) 3025 radeonfb_wait_fifo(sc, 20); 3026 PUT32(sc, RADEON_HOST_DATA0, pixel); 3027 } 3028 if (rv == GC_ADD) { 3029 glyphcache_add(&dp->rd_gc, c, xd, yd); 3030 } else 3031 if (attr & 1) 3032 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3033 3034 } 3035 3036 static void 3037 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3038 { 3039 struct rasops_info *ri = cookie; 3040 struct vcons_screen *scr = ri->ri_hw; 3041 struct radeonfb_display *dp = scr->scr_cookie; 3042 struct radeonfb_softc *sc = dp->rd_softc; 3043 struct wsdisplay_font *font = PICK_FONT(ri, c); 3044 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3045 int i, x, y, wi, he, r, g, b, aval; 3046 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3047 uint8_t *data8; 3048 int rv, cnt; 3049 3050 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3051 return; 3052 3053 if (!CHAR_IN_FONT(c, font)) 3054 return; 3055 3056 wi = font->fontwidth; 3057 he = font->fontheight; 3058 3059 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3060 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3061 3062 x = ri->ri_xorigin + col * wi; 3063 y = ri->ri_yorigin + row * he; 3064 3065 if (c == 0x20) { 3066 radeonfb_rectfill(dp, x, y, wi, he, bg); 3067 if (attr & 1) 3068 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3069 return; 3070 } 3071 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3072 if (rv == GC_OK) 3073 return; 3074 3075 data8 = WSFONT_GLYPH(c, font); 3076 3077 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3078 3079 radeonfb_wait_fifo(sc, 5); 3080 3081 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3082 RADEON_GMC_BRUSH_NONE | 3083 RADEON_GMC_SRC_DATATYPE_COLOR | 3084 RADEON_ROP3_S | 3085 RADEON_DP_SRC_SOURCE_HOST_DATA | 3086 RADEON_GMC_CLR_CMP_CNTL_DIS | 3087 RADEON_GMC_WR_MSK_DIS | 3088 gmc); 3089 3090 PUT32(sc, RADEON_DP_CNTL, 3091 RADEON_DST_X_LEFT_TO_RIGHT | 3092 RADEON_DST_Y_TOP_TO_BOTTOM); 3093 3094 PUT32(sc, RADEON_SRC_X_Y, 0); 3095 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3096 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3097 3098 /* 3099 * we need the RGB colours here, so get offsets into rasops_cmap 3100 */ 3101 fgo = ((attr >> 24) & 0xf) * 3; 3102 bgo = ((attr >> 16) & 0xf) * 3; 3103 3104 r0 = rasops_cmap[bgo]; 3105 r1 = rasops_cmap[fgo]; 3106 g0 = rasops_cmap[bgo + 1]; 3107 g1 = rasops_cmap[fgo + 1]; 3108 b0 = rasops_cmap[bgo + 2]; 3109 b1 = rasops_cmap[fgo + 2]; 3110 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3111 bg8 = R3G3B2(r0, g0, b0); 3112 fg8 = R3G3B2(r1, g1, b1); 3113 3114 radeonfb_wait_fifo(sc, 20); 3115 cnt = 0; 3116 for (i = 0; i < ri->ri_fontscale; i++) { 3117 aval = *data8; 3118 if (aval == 0) { 3119 pixel = bg8; 3120 } else if (aval == 255) { 3121 pixel = fg8; 3122 } else { 3123 r = aval * r1 + (255 - aval) * r0; 3124 g = aval * g1 + (255 - aval) * g0; 3125 b = aval * b1 + (255 - aval) * b0; 3126 pixel = ((r & 0xe000) >> 8) | 3127 ((g & 0xe000) >> 11) | 3128 ((b & 0xc000) >> 14); 3129 } 3130 latch |= pixel << (8 * (i & 3)); 3131 /* write in 32bit chunks */ 3132 if ((i & 3) == 3) { 3133 PUT32(sc, RADEON_HOST_DATA0, latch); 3134 /* 3135 * not strictly necessary, old data should be shifted 3136 * out 3137 */ 3138 latch = 0; 3139 cnt++; 3140 if (cnt > 16) { 3141 cnt = 0; 3142 radeonfb_wait_fifo(sc, 20); 3143 } 3144 } 3145 data8++; 3146 } 3147 /* if we have pixels left in latch write them out */ 3148 if ((i & 3) != 0) { 3149 /* 3150 * radeon is weird - apparently leftover pixels are written 3151 * from the middle, not from the left as everything else 3152 */ 3153 PUT32(sc, RADEON_HOST_DATA0, latch); 3154 } 3155 3156 if (rv == GC_ADD) { 3157 glyphcache_add(&dp->rd_gc, c, x, y); 3158 } else 3159 if (attr & 1) 3160 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3161 3162 } 3163 3164 /* 3165 * wrapper for software character drawing 3166 * just sync the engine and call rasops*_putchar() 3167 */ 3168 3169 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3170 static void 3171 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3172 { 3173 struct rasops_info *ri = cookie; 3174 struct vcons_screen *scr = ri->ri_hw; 3175 struct radeonfb_display *dp = scr->scr_cookie; 3176 3177 radeonfb_engine_idle(dp->rd_softc); 3178 dp->rd_putchar(ri, row, col, c, attr); 3179 } 3180 #endif 3181 3182 static void 3183 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3184 { 3185 struct rasops_info *ri = cookie; 3186 struct vcons_screen *scr = ri->ri_hw; 3187 struct radeonfb_display *dp = scr->scr_cookie; 3188 uint32_t x, y, w, h, fg, bg, ul; 3189 3190 /* XXX: check for full emulation mode? */ 3191 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3192 x = ri->ri_xorigin; 3193 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3194 w = ri->ri_emuwidth; 3195 h = ri->ri_font->fontheight * nrows; 3196 3197 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3198 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3199 } 3200 } 3201 3202 static void 3203 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3204 { 3205 struct rasops_info *ri = cookie; 3206 struct vcons_screen *scr = ri->ri_hw; 3207 struct radeonfb_display *dp = scr->scr_cookie; 3208 uint32_t x, ys, yd, w, h; 3209 3210 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3211 x = ri->ri_xorigin; 3212 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3213 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3214 w = ri->ri_emuwidth; 3215 h = ri->ri_font->fontheight * nrows; 3216 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3217 RADEON_ROP3_S); 3218 } 3219 } 3220 3221 static void 3222 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3223 { 3224 struct rasops_info *ri = cookie; 3225 struct vcons_screen *scr = ri->ri_hw; 3226 struct radeonfb_display *dp = scr->scr_cookie; 3227 uint32_t xs, xd, y, w, h; 3228 3229 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3230 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3231 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3232 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3233 w = ri->ri_font->fontwidth * ncols; 3234 h = ri->ri_font->fontheight; 3235 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3236 RADEON_ROP3_S); 3237 } 3238 } 3239 3240 static void 3241 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3242 long fillattr) 3243 { 3244 struct rasops_info *ri = cookie; 3245 struct vcons_screen *scr = ri->ri_hw; 3246 struct radeonfb_display *dp = scr->scr_cookie; 3247 uint32_t x, y, w, h, fg, bg, ul; 3248 3249 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3250 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3251 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3252 w = ri->ri_font->fontwidth * ncols; 3253 h = ri->ri_font->fontheight; 3254 3255 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3256 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3257 } 3258 } 3259 3260 static void 3261 radeonfb_cursor(void *cookie, int on, int row, int col) 3262 { 3263 struct rasops_info *ri = cookie; 3264 struct vcons_screen *scr = ri->ri_hw; 3265 struct radeonfb_display *dp = scr->scr_cookie; 3266 int x, y, wi, he; 3267 3268 wi = ri->ri_font->fontwidth; 3269 he = ri->ri_font->fontheight; 3270 3271 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3272 x = ri->ri_ccol * wi + ri->ri_xorigin; 3273 y = ri->ri_crow * he + ri->ri_yorigin; 3274 /* first turn off the old cursor */ 3275 if (ri->ri_flg & RI_CURSOR) { 3276 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3277 RADEON_ROP3_Dn); 3278 ri->ri_flg &= ~RI_CURSOR; 3279 } 3280 ri->ri_crow = row; 3281 ri->ri_ccol = col; 3282 /* then (possibly) turn on the new one */ 3283 if (on) { 3284 x = ri->ri_ccol * wi + ri->ri_xorigin; 3285 y = ri->ri_crow * he + ri->ri_yorigin; 3286 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3287 RADEON_ROP3_Dn); 3288 ri->ri_flg |= RI_CURSOR; 3289 } 3290 } else { 3291 scr->scr_ri.ri_crow = row; 3292 scr->scr_ri.ri_ccol = col; 3293 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3294 } 3295 } 3296 3297 /* 3298 * Underlying acceleration support. 3299 */ 3300 3301 static void 3302 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3303 int width, int height, uint32_t color) 3304 { 3305 struct radeonfb_softc *sc = dp->rd_softc; 3306 uint32_t gmc; 3307 3308 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3309 3310 radeonfb_wait_fifo(sc, 6); 3311 3312 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3313 RADEON_GMC_BRUSH_SOLID_COLOR | 3314 RADEON_GMC_SRC_DATATYPE_COLOR | 3315 RADEON_GMC_CLR_CMP_CNTL_DIS | 3316 RADEON_ROP3_P | gmc); 3317 3318 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3319 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3320 PUT32(sc, RADEON_DP_CNTL, 3321 RADEON_DST_X_LEFT_TO_RIGHT | 3322 RADEON_DST_Y_TOP_TO_BOTTOM); 3323 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3324 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3325 3326 } 3327 3328 static void 3329 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3330 int width, int height, long attr) 3331 { 3332 struct radeonfb_display *dp = cookie; 3333 3334 radeonfb_rectfill(dp, dstx, dsty, width, height, 3335 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3336 } 3337 3338 static void 3339 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3340 int dstx, int dsty, int width, int height, int rop) 3341 { 3342 struct radeonfb_display *dp = cookie; 3343 struct radeonfb_softc *sc = dp->rd_softc; 3344 uint32_t gmc; 3345 uint32_t dir; 3346 3347 if (dsty < srcy) { 3348 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3349 } else { 3350 srcy += height - 1; 3351 dsty += height - 1; 3352 dir = 0; 3353 } 3354 if (dstx < srcx) { 3355 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3356 } else { 3357 srcx += width - 1; 3358 dstx += width - 1; 3359 } 3360 3361 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3362 3363 radeonfb_wait_fifo(sc, 6); 3364 3365 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3366 RADEON_GMC_BRUSH_SOLID_COLOR | 3367 RADEON_GMC_SRC_DATATYPE_COLOR | 3368 RADEON_GMC_CLR_CMP_CNTL_DIS | 3369 RADEON_DP_SRC_SOURCE_MEMORY | 3370 rop | gmc); 3371 3372 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3373 PUT32(sc, RADEON_DP_CNTL, dir); 3374 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3375 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3376 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3377 } 3378 3379 static void 3380 radeonfb_engine_idle(struct radeonfb_softc *sc) 3381 { 3382 3383 radeonfb_wait_fifo(sc, 64); 3384 while ((GET32(sc, RADEON_RBBM_STATUS) & 3385 RADEON_RBBM_ACTIVE) != 0); 3386 radeonfb_engine_flush(sc); 3387 } 3388 3389 static inline void 3390 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3391 { 3392 int i; 3393 3394 for (i = RADEON_TIMEOUT; i; i--) { 3395 if ((GET32(sc, RADEON_RBBM_STATUS) & 3396 RADEON_RBBM_FIFOCNT_MASK) >= n) 3397 return; 3398 } 3399 #ifdef DIAGNOSTIC 3400 if (!i) 3401 printf("%s: timed out waiting for fifo (%x)\n", 3402 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3403 #endif 3404 } 3405 3406 static void 3407 radeonfb_engine_flush(struct radeonfb_softc *sc) 3408 { 3409 int i = 0; 3410 3411 if (IS_R300(sc)) { 3412 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3413 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3414 i++; 3415 } 3416 } else { 3417 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3418 RADEON_RB2D_DC_FLUSH_ALL); 3419 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3420 RADEON_RB2D_DC_BUSY) { 3421 i++; 3422 } 3423 } 3424 #ifdef DIAGNOSTIC 3425 if (i > RADEON_TIMEOUT) 3426 printf("%s: engine flush timed out!\n", XNAME(sc)); 3427 #endif 3428 } 3429 3430 static inline void 3431 radeonfb_unclip(struct radeonfb_softc *sc) 3432 { 3433 3434 radeonfb_wait_fifo(sc, 2); 3435 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3436 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3437 } 3438 3439 static void 3440 radeonfb_engine_init(struct radeonfb_display *dp) 3441 { 3442 struct radeonfb_softc *sc = dp->rd_softc; 3443 uint32_t pitch; 3444 3445 /* no 3D */ 3446 PUT32(sc, RADEON_RB3D_CNTL, 0); 3447 3448 radeonfb_engine_reset(sc); 3449 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3450 3451 radeonfb_wait_fifo(sc, 1); 3452 if (!IS_R300(sc)) 3453 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3454 3455 radeonfb_wait_fifo(sc, 3); 3456 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3457 (pitch << 22) | (sc->sc_aperbase >> 10)); 3458 3459 3460 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3461 (pitch << 22) | (sc->sc_aperbase >> 10)); 3462 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3463 (pitch << 22) | (sc->sc_aperbase >> 10)); 3464 3465 (void)GET32(sc, RADEON_DP_DATATYPE); 3466 3467 /* default scissors -- no clipping */ 3468 radeonfb_wait_fifo(sc, 1); 3469 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3470 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3471 3472 radeonfb_wait_fifo(sc, 1); 3473 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3474 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3475 RADEON_GMC_CLR_CMP_CNTL_DIS | 3476 RADEON_GMC_BRUSH_SOLID_COLOR | 3477 RADEON_GMC_SRC_DATATYPE_COLOR); 3478 3479 radeonfb_wait_fifo(sc, 10); 3480 PUT32(sc, RADEON_DST_LINE_START, 0); 3481 PUT32(sc, RADEON_DST_LINE_END, 0); 3482 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3483 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3484 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3485 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3486 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3487 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3488 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3489 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3490 radeonfb_engine_idle(sc); 3491 } 3492 3493 static void 3494 radeonfb_engine_reset(struct radeonfb_softc *sc) 3495 { 3496 uint32_t hpc, rbbm, mclkcntl, clkindex; 3497 3498 radeonfb_engine_flush(sc); 3499 3500 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3501 if (HAS_R300CG(sc)) 3502 radeonfb_r300cg_workaround(sc); 3503 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3504 3505 /* 3506 * According to comments in XFree code, resetting the HDP via 3507 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3508 * So we use HOST_PATH_CNTL instead. 3509 */ 3510 3511 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3512 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3513 if (IS_R300(sc)) { 3514 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3515 RADEON_SOFT_RESET_CP | 3516 RADEON_SOFT_RESET_HI | 3517 RADEON_SOFT_RESET_E2); 3518 GET32(sc, RADEON_RBBM_SOFT_RESET); 3519 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3520 /* 3521 * XXX: this bit is not defined in any ATI docs I have, 3522 * nor in the XFree code, but XFree does it. Why? 3523 */ 3524 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3525 } else { 3526 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3527 RADEON_SOFT_RESET_CP | 3528 RADEON_SOFT_RESET_SE | 3529 RADEON_SOFT_RESET_RE | 3530 RADEON_SOFT_RESET_PP | 3531 RADEON_SOFT_RESET_E2 | 3532 RADEON_SOFT_RESET_RB); 3533 GET32(sc, RADEON_RBBM_SOFT_RESET); 3534 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3535 ~(RADEON_SOFT_RESET_CP | 3536 RADEON_SOFT_RESET_SE | 3537 RADEON_SOFT_RESET_RE | 3538 RADEON_SOFT_RESET_PP | 3539 RADEON_SOFT_RESET_E2 | 3540 RADEON_SOFT_RESET_RB)); 3541 GET32(sc, RADEON_RBBM_SOFT_RESET); 3542 } 3543 3544 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3545 GET32(sc, RADEON_HOST_PATH_CNTL); 3546 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3547 3548 if (IS_R300(sc)) 3549 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3550 3551 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3552 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3553 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3554 3555 if (HAS_R300CG(sc)) 3556 radeonfb_r300cg_workaround(sc); 3557 } 3558 3559 static int 3560 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3561 { 3562 int x, y; 3563 3564 x = pos->x; 3565 y = pos->y; 3566 3567 /* 3568 * This doesn't let a cursor move off the screen. I'm not 3569 * sure if this will have negative effects for e.g. Xinerama. 3570 * I'd guess Xinerama handles it by changing the cursor shape, 3571 * but that needs verification. 3572 */ 3573 if (x >= dp->rd_virtx) 3574 x = dp->rd_virtx - 1; 3575 if (x < 0) 3576 x = 0; 3577 if (y >= dp->rd_virty) 3578 y = dp->rd_virty - 1; 3579 if (y < 0) 3580 y = 0; 3581 3582 dp->rd_cursor.rc_pos.x = x; 3583 dp->rd_cursor.rc_pos.y = y; 3584 3585 radeonfb_cursor_position(dp); 3586 return 0; 3587 } 3588 3589 static int 3590 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3591 { 3592 unsigned flags; 3593 3594 uint8_t r[2], g[2], b[2]; 3595 unsigned index, count; 3596 int i, err; 3597 int pitch, size; 3598 struct radeonfb_cursor nc; 3599 3600 flags = wc->which; 3601 3602 /* copy old values */ 3603 nc = dp->rd_cursor; 3604 3605 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3606 index = wc->cmap.index; 3607 count = wc->cmap.count; 3608 3609 if (index >= 2 || (index + count) > 2) 3610 return EINVAL; 3611 3612 err = copyin(wc->cmap.red, &r[index], count); 3613 if (err) 3614 return err; 3615 err = copyin(wc->cmap.green, &g[index], count); 3616 if (err) 3617 return err; 3618 err = copyin(wc->cmap.blue, &b[index], count); 3619 if (err) 3620 return err; 3621 3622 for (i = index; i < index + count; i++) { 3623 nc.rc_cmap[i] = 3624 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3625 } 3626 } 3627 3628 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3629 if ((wc->size.x > RADEON_CURSORMAXX) || 3630 (wc->size.y > RADEON_CURSORMAXY)) 3631 return EINVAL; 3632 3633 /* figure bytes per line */ 3634 pitch = (wc->size.x + 7) / 8; 3635 size = pitch * wc->size.y; 3636 3637 /* clear the old cursor and mask */ 3638 memset(nc.rc_image, 0, 512); 3639 memset(nc.rc_mask, 0, 512); 3640 3641 nc.rc_size = wc->size; 3642 3643 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3644 return err; 3645 3646 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3647 return err; 3648 } 3649 3650 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3651 nc.rc_hot = wc->hot; 3652 if (nc.rc_hot.x >= nc.rc_size.x) 3653 nc.rc_hot.x = nc.rc_size.x - 1; 3654 if (nc.rc_hot.y >= nc.rc_size.y) 3655 nc.rc_hot.y = nc.rc_size.y - 1; 3656 } 3657 3658 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3659 nc.rc_pos = wc->pos; 3660 if (nc.rc_pos.x >= dp->rd_virtx) 3661 nc.rc_pos.x = dp->rd_virtx - 1; 3662 #if 0 3663 if (nc.rc_pos.x < 0) 3664 nc.rc_pos.x = 0; 3665 #endif 3666 if (nc.rc_pos.y >= dp->rd_virty) 3667 nc.rc_pos.y = dp->rd_virty - 1; 3668 #if 0 3669 if (nc.rc_pos.y < 0) 3670 nc.rc_pos.y = 0; 3671 #endif 3672 } 3673 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3674 nc.rc_visible = wc->enable; 3675 } 3676 3677 dp->rd_cursor = nc; 3678 radeonfb_cursor_update(dp, wc->which); 3679 3680 return 0; 3681 } 3682 3683 static uint8_t 3684 radeonfb_backwards(uint8_t d) 3685 { 3686 uint8_t l; 3687 3688 l = d << 7; 3689 l |= ((d & 0x02) << 5); 3690 l |= ((d & 0x04) << 3); 3691 l |= ((d & 0x08) << 1); 3692 l |= ((d & 0x10) >> 1); 3693 l |= ((d & 0x20) >> 3); 3694 l |= ((d & 0x40) >> 5); 3695 l |= ((d & 0x80) >> 7); 3696 return l; 3697 } 3698 3699 /* 3700 * Change the cursor shape. Call this with the cursor locked to avoid 3701 * flickering/tearing. 3702 */ 3703 static void 3704 radeonfb_cursor_shape(struct radeonfb_display *dp) 3705 { 3706 uint8_t and[512], xor[512]; 3707 int i, j, src, dst /* , pitch */; 3708 const uint8_t *msk = dp->rd_cursor.rc_mask; 3709 const uint8_t *img = dp->rd_cursor.rc_image; 3710 3711 /* 3712 * Radeon cursor data interleaves one line of AND data followed 3713 * by a line of XOR data. (Each line corresponds to a whole hardware 3714 * pitch - i.e. 64 pixels or 8 bytes.) 3715 * 3716 * The cursor is displayed using the following table: 3717 * 3718 * AND XOR Result 3719 * ---------------------- 3720 * 0 0 Cursor color 0 3721 * 0 1 Cursor color 1 3722 * 1 0 Transparent 3723 * 1 1 Complement of background 3724 * 3725 * Our masks are therefore different from what we were passed. 3726 * Passed in, I'm assuming the data represents either color 0 or 1, 3727 * and a mask, so the passed in table looks like: 3728 * 3729 * IMG Mask Result 3730 * ----------------------- 3731 * 0 0 Transparent 3732 * 0 1 Cursor color 0 3733 * 1 0 Transparent 3734 * 1 1 Cursor color 1 3735 * 3736 * IF mask bit == 1, AND = 0, XOR = color. 3737 * IF mask bit == 0, AND = 1, XOR = 0. 3738 * 3739 * hence: AND = ~(mask); XOR = color & ~(mask); 3740 */ 3741 3742 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3743 3744 /* start by assuming all bits are transparent */ 3745 memset(and, 0xff, 512); 3746 memset(xor, 0x00, 512); 3747 3748 src = 0; 3749 dst = 0; 3750 for (i = 0; i < 64; i++) { 3751 for (j = 0; j < 64; j += 8) { 3752 if ((i < dp->rd_cursor.rc_size.y) && 3753 (j < dp->rd_cursor.rc_size.x)) { 3754 3755 /* take care to leave odd bits alone */ 3756 and[dst] &= ~(msk[src]); 3757 xor[dst] = img[src] & msk[src]; 3758 src++; 3759 } 3760 dst++; 3761 } 3762 } 3763 3764 for (i = 0; i < 512; i++) { 3765 and[i] = radeonfb_backwards(and[i]); 3766 xor[i] = radeonfb_backwards(xor[i]); 3767 } 3768 3769 /* copy the image into place */ 3770 for (i = 0; i < 64; i++) { 3771 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3772 &and[i * 8], 8); 3773 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3774 &xor[i * 8], 8); 3775 } 3776 } 3777 3778 static void 3779 radeonfb_cursor_position(struct radeonfb_display *dp) 3780 { 3781 struct radeonfb_softc *sc = dp->rd_softc; 3782 uint32_t offset, hvoff, hvpos; /* registers */ 3783 uint32_t coff; /* cursor offset */ 3784 int i, x, y, xoff, yoff, crtcoff; 3785 3786 /* 3787 * XXX: this also needs to handle pan/scan 3788 */ 3789 for (i = 0; i < dp->rd_ncrtcs; i++) { 3790 3791 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3792 3793 if (rcp->rc_number) { 3794 offset = RADEON_CUR2_OFFSET; 3795 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3796 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3797 crtcoff = RADEON_CRTC2_OFFSET; 3798 } else { 3799 offset = RADEON_CUR_OFFSET; 3800 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3801 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3802 crtcoff = RADEON_CRTC_OFFSET; 3803 } 3804 3805 x = dp->rd_cursor.rc_pos.x; 3806 y = dp->rd_cursor.rc_pos.y; 3807 3808 while (y < rcp->rc_yoffset) { 3809 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3810 } 3811 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3812 rcp->rc_yoffset += RADEON_PANINCREMENT; 3813 } 3814 while (x < rcp->rc_xoffset) { 3815 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3816 } 3817 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3818 rcp->rc_xoffset += RADEON_PANINCREMENT; 3819 } 3820 3821 /* adjust for the cursor's hotspot */ 3822 x -= dp->rd_cursor.rc_hot.x; 3823 y -= dp->rd_cursor.rc_hot.y; 3824 xoff = yoff = 0; 3825 3826 if (x >= dp->rd_virtx) 3827 x = dp->rd_virtx - 1; 3828 if (y >= dp->rd_virty) 3829 y = dp->rd_virty - 1; 3830 3831 /* now adjust cursor so it is relative to viewport */ 3832 x -= rcp->rc_xoffset; 3833 y -= rcp->rc_yoffset; 3834 3835 /* 3836 * no need to check for fall off, because we should 3837 * never move off the screen entirely! 3838 */ 3839 coff = 0; 3840 if (x < 0) { 3841 xoff = -x; 3842 x = 0; 3843 } 3844 if (y < 0) { 3845 yoff = -y; 3846 y = 0; 3847 coff = (yoff * 2) * 8; 3848 } 3849 3850 /* pan the display */ 3851 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3852 rcp->rc_xoffset); 3853 3854 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3855 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3856 /* NB: this unlocks the cursor */ 3857 PUT32(sc, hvpos, (x << 16) | y); 3858 } 3859 } 3860 3861 static void 3862 radeonfb_cursor_visible(struct radeonfb_display *dp) 3863 { 3864 int i; 3865 uint32_t gencntl, bit; 3866 3867 for (i = 0; i < dp->rd_ncrtcs; i++) { 3868 if (dp->rd_crtcs[i].rc_number) { 3869 gencntl = RADEON_CRTC2_GEN_CNTL; 3870 bit = RADEON_CRTC2_CUR_EN; 3871 } else { 3872 gencntl = RADEON_CRTC_GEN_CNTL; 3873 bit = RADEON_CRTC_CUR_EN; 3874 } 3875 3876 if (dp->rd_cursor.rc_visible) 3877 SET32(dp->rd_softc, gencntl, bit); 3878 else 3879 CLR32(dp->rd_softc, gencntl, bit); 3880 } 3881 } 3882 3883 static void 3884 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3885 { 3886 int i; 3887 uint32_t c0reg, c1reg; 3888 struct radeonfb_softc *sc = dp->rd_softc; 3889 3890 for (i = 0; i < dp->rd_ncrtcs; i++) { 3891 if (dp->rd_crtcs[i].rc_number) { 3892 c0reg = RADEON_CUR2_CLR0; 3893 c1reg = RADEON_CUR2_CLR1; 3894 } else { 3895 c0reg = RADEON_CUR_CLR0; 3896 c1reg = RADEON_CUR_CLR1; 3897 } 3898 3899 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3900 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3901 } 3902 } 3903 3904 static void 3905 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3906 { 3907 struct radeonfb_softc *sc; 3908 int i; 3909 3910 sc = dp->rd_softc; 3911 for (i = 0; i < dp->rd_ncrtcs; i++) { 3912 if (dp->rd_crtcs[i].rc_number) { 3913 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3914 } else { 3915 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3916 } 3917 } 3918 3919 if (which & WSDISPLAY_CURSOR_DOCMAP) 3920 radeonfb_cursor_cmap(dp); 3921 3922 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3923 radeonfb_cursor_shape(dp); 3924 3925 if (which & WSDISPLAY_CURSOR_DOCUR) 3926 radeonfb_cursor_visible(dp); 3927 3928 /* this one is unconditional, because it updates other stuff */ 3929 radeonfb_cursor_position(dp); 3930 } 3931 3932 static struct videomode * 3933 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3934 { 3935 int r1, r2; 3936 3937 /* otherwise pick the higher refresh rate */ 3938 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3939 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3940 3941 return (r1 < r2 ? m2 : m1); 3942 } 3943 3944 static const struct videomode * 3945 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3946 int x, int y) 3947 { 3948 struct edid_info *ep = &rp->rp_edid; 3949 struct videomode *vmp = NULL; 3950 int i; 3951 3952 if (!rp->rp_edid_valid) { 3953 /* fallback to safe mode */ 3954 return radeonfb_modelookup(sc->sc_defaultmode); 3955 } 3956 3957 /* always choose the preferred mode first! */ 3958 if (ep->edid_preferred_mode) { 3959 3960 /* XXX: add auto-stretching support for native mode */ 3961 3962 /* this may want panning to occur, btw */ 3963 if ((ep->edid_preferred_mode->hdisplay <= x) && 3964 (ep->edid_preferred_mode->vdisplay <= y)) 3965 return ep->edid_preferred_mode; 3966 } 3967 3968 for (i = 0; i < ep->edid_nmodes; i++) { 3969 /* 3970 * We elect to pick a resolution that is too large for 3971 * the monitor than one that is too small. This means 3972 * that we will prefer to pan rather than to try to 3973 * center a smaller display on a larger screen. In 3974 * practice, this shouldn't matter because if a 3975 * monitor can support a larger resolution, it can 3976 * probably also support the smaller. A specific 3977 * exception is fixed format panels, but hopefully 3978 * they are properly dealt with by the "autostretch" 3979 * logic above. 3980 */ 3981 if ((ep->edid_modes[i].hdisplay > x) || 3982 (ep->edid_modes[i].vdisplay > y)) { 3983 continue; 3984 } 3985 3986 /* 3987 * at this point, the display mode is no larger than 3988 * what we've requested. 3989 */ 3990 if (vmp == NULL) 3991 vmp = &ep->edid_modes[i]; 3992 3993 /* eliminate smaller modes */ 3994 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 3995 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 3996 continue; 3997 3998 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 3999 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4000 vmp = &ep->edid_modes[i]; 4001 continue; 4002 } 4003 4004 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4005 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4006 4007 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4008 } 4009 4010 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4011 } 4012 4013 static int 4014 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4015 { 4016 int i; 4017 4018 for (i = 0; i < nlist; i++) { 4019 if ((x == list[i].hdisplay) && 4020 (y == list[i].vdisplay)) { 4021 return 1; 4022 } 4023 } 4024 return 0; 4025 } 4026 4027 static void 4028 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4029 int pan) 4030 { 4031 struct radeonfb_port *rp; 4032 struct edid_info *ep; 4033 int i, j; 4034 4035 *x = 0; 4036 *y = 0; 4037 4038 if (pan) { 4039 for (i = 0; i < dp->rd_ncrtcs; i++) { 4040 rp = dp->rd_crtcs[i].rc_port; 4041 ep = &rp->rp_edid; 4042 if (!rp->rp_edid_valid) { 4043 /* monitor not present */ 4044 continue; 4045 } 4046 4047 /* 4048 * For now we are ignoring "conflict" that 4049 * could occur when mixing some modes like 4050 * 1280x1024 and 1400x800. It isn't clear 4051 * which is better, so the first one wins. 4052 */ 4053 for (j = 0; j < ep->edid_nmodes; j++) { 4054 /* 4055 * ignore resolutions that are too big for 4056 * the radeon 4057 */ 4058 if (ep->edid_modes[j].hdisplay > 4059 dp->rd_softc->sc_maxx) 4060 continue; 4061 if (ep->edid_modes[j].vdisplay > 4062 dp->rd_softc->sc_maxy) 4063 continue; 4064 4065 /* 4066 * pick largest resolution, the 4067 * smaller monitor will pan 4068 */ 4069 if ((ep->edid_modes[j].hdisplay >= *x) && 4070 (ep->edid_modes[j].vdisplay >= *y)) { 4071 *x = ep->edid_modes[j].hdisplay; 4072 *y = ep->edid_modes[j].vdisplay; 4073 } 4074 } 4075 } 4076 4077 } else { 4078 struct videomode modes[64]; 4079 int nmodes = 0; 4080 int valid = 0; 4081 4082 for (i = 0; i < dp->rd_ncrtcs; i++) { 4083 /* 4084 * pick the largest resolution in common. 4085 */ 4086 rp = dp->rd_crtcs[i].rc_port; 4087 ep = &rp->rp_edid; 4088 4089 if (!rp->rp_edid_valid) 4090 continue; 4091 4092 if (!valid) { 4093 /* 4094 * Pick the preferred mode for this port 4095 * if available. 4096 */ 4097 if (ep->edid_preferred_mode) { 4098 struct videomode *vmp = 4099 ep->edid_preferred_mode; 4100 4101 if ((vmp->hdisplay <= 4102 dp->rd_softc->sc_maxx) && 4103 (vmp->vdisplay <= 4104 dp->rd_softc->sc_maxy)) 4105 modes[nmodes++] = *vmp; 4106 } else { 4107 4108 /* initialize starting list */ 4109 for (j = 0; j < ep->edid_nmodes; j++) { 4110 /* 4111 * ignore resolutions that are 4112 * too big for the radeon 4113 */ 4114 if (ep->edid_modes[j].hdisplay > 4115 dp->rd_softc->sc_maxx) 4116 continue; 4117 if (ep->edid_modes[j].vdisplay > 4118 dp->rd_softc->sc_maxy) 4119 continue; 4120 4121 modes[nmodes] = 4122 ep->edid_modes[j]; 4123 nmodes++; 4124 } 4125 } 4126 valid = 1; 4127 } else { 4128 /* merge into preexisting list */ 4129 for (j = 0; j < nmodes; j++) { 4130 if (!radeonfb_hasres(ep->edid_modes, 4131 ep->edid_nmodes, 4132 modes[j].hdisplay, 4133 modes[j].vdisplay)) { 4134 modes[j] = modes[nmodes]; 4135 j--; 4136 nmodes--; 4137 } 4138 } 4139 } 4140 } 4141 4142 /* now we have to pick from the merged list */ 4143 for (i = 0; i < nmodes; i++) { 4144 if ((modes[i].hdisplay >= *x) && 4145 (modes[i].vdisplay >= *y)) { 4146 *x = modes[i].hdisplay; 4147 *y = modes[i].vdisplay; 4148 } 4149 } 4150 } 4151 4152 if ((*x == 0) || (*y == 0)) { 4153 /* fallback to safe mode */ 4154 *x = 640; 4155 *y = 480; 4156 } 4157 } 4158 4159 /* 4160 * backlight levels are linear on: 4161 * - RV200, RV250, RV280, RV350 4162 * - but NOT on PowerBook4,3 6,3 6,5 4163 * according to Linux' radeonfb 4164 */ 4165 4166 /* Get the current backlight level for the display. */ 4167 4168 static int 4169 radeonfb_get_backlight(struct radeonfb_display *dp) 4170 { 4171 int s; 4172 uint32_t level; 4173 4174 s = spltty(); 4175 4176 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4177 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4178 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4179 4180 /* 4181 * On some chips, we should negate the backlight level. 4182 * XXX Find out on which chips. 4183 */ 4184 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4185 level = RADEONFB_BACKLIGHT_MAX - level; 4186 4187 splx(s); 4188 4189 return level; 4190 } 4191 4192 /* Set the backlight to the given level for the display. */ 4193 static void 4194 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4195 { 4196 if (dp->rd_bl_on == on) 4197 return; 4198 dp->rd_bl_on = on; 4199 radeonfb_set_backlight(dp, dp->rd_bl_level); 4200 } 4201 4202 static int 4203 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4204 { 4205 struct radeonfb_softc *sc = dp->rd_softc;; 4206 int rlevel, s; 4207 uint32_t lvds; 4208 4209 if(!sc->sc_mapped) 4210 return 0; 4211 4212 s = spltty(); 4213 4214 dp->rd_bl_level = level; 4215 if (dp->rd_bl_on == 0) 4216 level = 0; 4217 4218 if (level < 0) 4219 level = 0; 4220 else if (level >= RADEONFB_BACKLIGHT_MAX) 4221 level = RADEONFB_BACKLIGHT_MAX; 4222 4223 /* On some chips, we should negate the backlight level. */ 4224 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4225 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4226 } else 4227 rlevel = level; 4228 4229 callout_stop(&dp->rd_bl_lvds_co); 4230 radeonfb_engine_idle(sc); 4231 4232 /* 4233 * Turn off the display if the backlight is set to 0, since the 4234 * display is useless without backlight anyway. 4235 */ 4236 if (level == 0) 4237 radeonfb_blank(dp, 1); 4238 else if (radeonfb_get_backlight(dp) == 0) 4239 radeonfb_blank(dp, 0); 4240 4241 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4242 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4243 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4244 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4245 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4246 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4247 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4248 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4249 lvds |= RADEON_LVDS_ON; 4250 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4251 } else { 4252 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4253 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4254 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4255 } 4256 4257 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4258 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4259 /* XXX What is the correct delay? */ 4260 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4261 4262 splx(s); 4263 4264 return 0; 4265 } 4266 4267 /* 4268 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4269 * Set the delayed bits in the register, and clear the stored delayed 4270 * value. 4271 */ 4272 4273 static void radeonfb_lvds_callout(void *arg) 4274 { 4275 struct radeonfb_display *dp = arg; 4276 int s; 4277 4278 s = splhigh(); 4279 4280 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4281 dp->rd_bl_lvds_val); 4282 dp->rd_bl_lvds_val = 0; 4283 4284 splx(s); 4285 } 4286 4287 static void 4288 radeonfb_brightness_up(device_t dev) 4289 { 4290 struct radeonfb_softc *sc = device_private(dev); 4291 struct radeonfb_display *dp = &sc->sc_displays[0]; 4292 int level; 4293 4294 /* we assume the main display is the first one - need a better way */ 4295 if (sc->sc_ndisplays < 1) return; 4296 /* make sure pushing the hotkeys always has an effect */ 4297 dp->rd_bl_on = 1; 4298 level = dp->rd_bl_level; 4299 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4300 radeonfb_set_backlight(dp, level); 4301 } 4302 4303 static void 4304 radeonfb_brightness_down(device_t dev) 4305 { 4306 struct radeonfb_softc *sc = device_private(dev); 4307 struct radeonfb_display *dp = &sc->sc_displays[0]; 4308 int level; 4309 4310 /* we assume the main display is the first one - need a better way */ 4311 if (sc->sc_ndisplays < 1) return; 4312 /* make sure pushing the hotkeys always has an effect */ 4313 dp->rd_bl_on = 1; 4314 level = dp->rd_bl_level; 4315 level = max(0, level - 5); 4316 radeonfb_set_backlight(dp, level); 4317 } 4318
Indexes created Mon Sep 22 21:09:42 GMT 2025