radeonfb.c revision 1.96
1 /* $NetBSD: radeonfb.c,v 1.96 2018/06/14 17:41:27 macallan Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.96 2018/06/14 17:41:27 macallan Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 482 /* enable memory and IO access */ 483 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 484 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 485 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 486 487 /* 488 * Some flags are general to entire chip families, and rather 489 * than clutter up the table with them, we go ahead and set 490 * them here. 491 */ 492 switch (sc->sc_family) { 493 case RADEON_RS100: 494 case RADEON_RS200: 495 sc->sc_flags |= RFB_IGP | RFB_RV100; 496 break; 497 498 case RADEON_RV100: 499 case RADEON_RV200: 500 case RADEON_RV250: 501 case RADEON_RV280: 502 sc->sc_flags |= RFB_RV100; 503 break; 504 505 case RADEON_RS300: 506 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 507 break; 508 509 case RADEON_R300: 510 case RADEON_RV350: 511 case RADEON_R350: 512 case RADEON_RV380: 513 case RADEON_R420: 514 /* newer chips */ 515 sc->sc_flags |= RFB_R300; 516 break; 517 518 case RADEON_R100: 519 sc->sc_flags |= RFB_NCRTC2; 520 break; 521 } 522 523 if ((sc->sc_family == RADEON_RV200) || 524 (sc->sc_family == RADEON_RV250) || 525 (sc->sc_family == RADEON_RV280) || 526 (sc->sc_family == RADEON_RV350)) { 527 bool inverted = 0; 528 /* backlight level is linear */ 529 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 530 prop_dictionary_get_bool(device_properties(sc->sc_dev), 531 "backlight_level_reverted", &inverted); 532 if (inverted) { 533 DPRINTF(("nope, it's inverted\n")); 534 sc->sc_flags |= RFB_INV_BLIGHT; 535 } 536 } else 537 sc->sc_flags |= RFB_INV_BLIGHT; 538 539 /* 540 * XXX: to support true multihead, this must change. 541 */ 542 sc->sc_ndisplays = 1; 543 544 /* XXX: */ 545 if (!HAS_CRTC2(sc)) { 546 sc->sc_ndisplays = 1; 547 } 548 549 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 550 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 551 &sc->sc_regsz) != 0) { 552 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 553 goto error; 554 } 555 556 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 557 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 558 { 559 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 560 goto error; 561 } 562 sc->sc_romt = sc->sc_memt; 563 564 sc->sc_mapped = TRUE; 565 566 /* scratch register test... */ 567 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 568 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 569 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 570 goto error; 571 } 572 573 PRINTREG(RADEON_CRTC_EXT_CNTL); 574 PRINTREG(RADEON_CRTC_GEN_CNTL); 575 PRINTREG(RADEON_CRTC2_GEN_CNTL); 576 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 577 PRINTREG(RADEON_DAC_CNTL2); 578 PRINTREG(RADEON_BIOS_4_SCRATCH); 579 PRINTREG(RADEON_FP_GEN_CNTL); 580 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 581 PRINTREG(RADEON_FP2_GEN_CNTL); 582 PRINTREG(RADEON_TMDS_CNTL); 583 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 584 PRINTREG(RADEON_TMDS_PLL_CNTL); 585 PRINTREG(RADEON_LVDS_GEN_CNTL); 586 PRINTREG(RADEON_DISP_HW_DEBUG); 587 PRINTREG(RADEON_PIXCLKS_CNTL); 588 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 589 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 590 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 592 if (IS_RV100(sc)) 593 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 594 595 /* XXX 596 * according to xf86-video-radeon R3xx has this bit backwards 597 */ 598 if (IS_R300(sc)) { 599 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 600 0, 601 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 602 } else { 603 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 604 RADEON_TMDS_TRANSMITTER_PLLEN, 605 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 606 } 607 608 radeonfb_i2c_init(sc); 609 610 radeonfb_loadbios(sc, pa); 611 612 #ifdef RADEONFB_BIOS_INIT 613 if (radeonfb_bios_init(sc)) { 614 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 615 } 616 #endif 617 618 if (radeonfb_getclocks(sc)) { 619 aprint_error("%s: Unable to get reference clocks from BIOS\n", 620 XNAME(sc)); 621 goto error; 622 } 623 624 if (radeonfb_gettmds(sc)) { 625 aprint_error("%s: Unable to identify TMDS PLL settings\n", 626 XNAME(sc)); 627 goto error; 628 } 629 630 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 631 "minpll = %d, maxpll = %d\n", XNAME(sc), 632 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 633 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 634 635 radeonfb_getconnectors(sc); 636 637 radeonfb_set_fbloc(sc); 638 639 /* 64 MB should be enough -- more just wastes map entries */ 640 if (sc->sc_memsz > (64 << 20)) 641 sc->sc_memsz = (64 << 20); 642 643 for (i = 0; radeonfb_limits[i].size; i++) { 644 if (sc->sc_memsz >= radeonfb_limits[i].size) { 645 sc->sc_maxx = radeonfb_limits[i].maxx; 646 sc->sc_maxy = radeonfb_limits[i].maxy; 647 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 648 /* framebuffer offset, start at a 4K page */ 649 sc->sc_fboffset = sc->sc_memsz / 650 radeonfb_limits[i].maxdisp; 651 /* 652 * we use the fbsize to figure out where we can store 653 * things like cursor data. 654 */ 655 sc->sc_fbsize = 656 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 657 RADEON_STRIDEALIGN) * sc->sc_maxy, 658 4096); 659 break; 660 } 661 } 662 663 664 radeonfb_init_misc(sc); 665 666 /* program the DAC wirings */ 667 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 668 switch (sc->sc_ports[i].rp_dac_type) { 669 case RADEON_DAC_PRIMARY: 670 PATCH32(sc, RADEON_DAC_CNTL2, 671 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 672 ~RADEON_DAC2_DAC_CLK_SEL); 673 break; 674 case RADEON_DAC_TVDAC: 675 /* we always use the TVDAC to drive a secondary analog 676 * CRT for now. if we ever support TV-out this will 677 * have to change. 678 */ 679 SET32(sc, RADEON_DAC_CNTL2, 680 RADEON_DAC2_DAC2_CLK_SEL); 681 PATCH32(sc, RADEON_DISP_HW_DEBUG, 682 i ? 0 : RADEON_CRT2_DISP1_SEL, 683 ~RADEON_CRT2_DISP1_SEL); 684 /* we're using CRTC2 for the 2nd port */ 685 if (sc->sc_ports[i].rp_number == 1) { 686 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 687 RADEON_DISP_DAC2_SOURCE_CRTC2, 688 ~RADEON_DISP_DAC2_SOURCE_MASK); 689 } 690 691 break; 692 } 693 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 694 sc->sc_ports[i].rp_tmds_type)); 695 switch (sc->sc_ports[i].rp_tmds_type) { 696 case RADEON_TMDS_INT: 697 /* point FP0 at the CRTC this port uses */ 698 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 699 __func__, sc->sc_ports[i].rp_number)); 700 if (IS_R300(sc)) { 701 PATCH32(sc, RADEON_FP_GEN_CNTL, 702 sc->sc_ports[i].rp_number ? 703 R200_FP_SOURCE_SEL_CRTC2 : 704 R200_FP_SOURCE_SEL_CRTC1, 705 ~R200_FP_SOURCE_SEL_MASK); 706 } else { 707 PATCH32(sc, RADEON_FP_GEN_CNTL, 708 sc->sc_ports[i].rp_number ? 709 RADEON_FP_SEL_CRTC2 : 710 RADEON_FP_SEL_CRTC1, 711 ~RADEON_FP_SEL_MASK); 712 } 713 break; 714 case RADEON_TMDS_EXT: 715 /* point FP2 at the CRTC this port uses */ 716 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 717 __func__, sc->sc_ports[i].rp_number)); 718 if (IS_R300(sc)) { 719 PATCH32(sc, RADEON_FP2_GEN_CNTL, 720 sc->sc_ports[i].rp_number ? 721 R200_FP2_SOURCE_SEL_CRTC2 : 722 R200_FP2_SOURCE_SEL_CRTC1, 723 ~R200_FP2_SOURCE_SEL_CRTC2); 724 } else { 725 PATCH32(sc, RADEON_FP2_GEN_CNTL, 726 sc->sc_ports[i].rp_number ? 727 RADEON_FP2_SRC_SEL_CRTC2 : 728 RADEON_FP2_SRC_SEL_CRTC1, 729 ~RADEON_FP2_SRC_SEL_CRTC2); 730 } 731 break; 732 } 733 } 734 PRINTREG(RADEON_DAC_CNTL2); 735 PRINTREG(RADEON_DISP_HW_DEBUG); 736 737 PRINTREG(RADEON_DAC_CNTL); 738 /* other DAC programming */ 739 v = GET32(sc, RADEON_DAC_CNTL); 740 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 741 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 742 PUT32(sc, RADEON_DAC_CNTL, v); 743 PRINTREG(RADEON_DAC_CNTL); 744 745 /* XXX: this may need more investigation */ 746 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 747 PRINTREG(RADEON_TV_DAC_CNTL); 748 749 /* enable TMDS */ 750 SET32(sc, RADEON_FP_GEN_CNTL, 751 RADEON_FP_TMDS_EN | 752 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 753 RADEON_FP_CRTC_DONT_SHADOW_HEND); 754 /* 755 * XXX 756 * no idea why this is necessary - if I do not clear this bit on my 757 * iBook G4 the screen remains black, even though it's already clear. 758 * It needs to be set on my Sun XVR-100 for the DVI port to work 759 * TODO: 760 * see if this is still necessary now that CRTCs, DACs and outputs are 761 * getting wired up in a halfway sane way 762 */ 763 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 764 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 765 } else { 766 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 767 } 768 769 /* 770 * we use bus_space_map instead of pci_mapreg, because we don't 771 * need the full aperature space. no point in wasting virtual 772 * address space we don't intend to use, right? 773 */ 774 if ((sc->sc_memsz < (4096 * 1024)) || 775 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 776 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 777 (bsz < sc->sc_memsz)) { 778 sc->sc_memsz = 0; 779 aprint_error("%s: Bad frame buffer configuration\n", 780 XNAME(sc)); 781 goto error; 782 } 783 784 sc->sc_memt = pa->pa_memt; 785 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 786 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 787 sc->sc_memsz = 0; 788 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 789 goto error; 790 } 791 792 aprint_normal("%s: %d MB aperture at 0x%08x, " 793 "%d KB registers at 0x%08x\n", XNAME(sc), 794 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 795 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 796 797 /* setup default video mode from devprop (allows PROM override) */ 798 sc->sc_defaultmode = radeonfb_default_mode; 799 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 800 "videomode", &mptr)) { 801 802 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 803 sc->sc_defaultmode = sc->sc_modebuf; 804 } 805 806 /* initialize some basic display parameters */ 807 for (i = 0; i < sc->sc_ndisplays; i++) { 808 struct radeonfb_display *dp = &sc->sc_displays[i]; 809 struct rasops_info *ri; 810 long defattr; 811 struct wsemuldisplaydev_attach_args aa; 812 813 /* 814 * Figure out how many "displays" (desktops) we are going to 815 * support. If more than one, then each CRTC gets its own 816 * programming. 817 * 818 * XXX: this code needs to change to support mergedfb. 819 * XXX: would be nice to allow this to be overridden 820 */ 821 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 822 DPRINTF(("dual crtcs!\n")); 823 dp->rd_ncrtcs = 2; 824 dp->rd_crtcs[0].rc_port = 825 &sc->sc_ports[0]; 826 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 827 dp->rd_crtcs[1].rc_port = 828 &sc->sc_ports[1]; 829 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 830 } else { 831 dp->rd_ncrtcs = 1; 832 dp->rd_crtcs[0].rc_port = 833 &sc->sc_ports[i]; 834 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 835 } 836 837 dp->rd_softc = sc; 838 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 839 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 840 841 /* for text mode, we pick a resolution that won't 842 * require panning */ 843 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 844 845 aprint_normal("%s: display %d: " 846 "initial virtual resolution %dx%d at %d bpp\n", 847 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 848 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 849 sc->sc_fboffset >> 20); 850 /* now select the *video mode* that we will use */ 851 for (j = 0; j < dp->rd_ncrtcs; j++) { 852 const struct videomode *vmp; 853 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 854 dp->rd_virtx, dp->rd_virty); 855 856 /* 857 * virtual resolution should be at least as high as 858 * physical 859 */ 860 if (dp->rd_virtx < vmp->hdisplay || 861 dp->rd_virty < vmp->vdisplay) { 862 dp->rd_virtx = vmp->hdisplay; 863 dp->rd_virty = vmp->vdisplay; 864 } 865 866 dp->rd_crtcs[j].rc_videomode = *vmp; 867 printf("%s: port %d: physical %dx%d %dHz\n", 868 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 869 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 870 vmp->htotal), vmp->vtotal)); 871 } 872 873 /* N.B.: radeon wants 64-byte aligned stride */ 874 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 875 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 876 DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx)); 877 878 dp->rd_offset = sc->sc_fboffset * i; 879 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 880 sc->sc_memh) + dp->rd_offset; 881 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 882 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 883 884 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 885 886 switch (dp->rd_bpp) { 887 case 8: 888 dp->rd_format = 2; 889 break; 890 case 32: 891 dp->rd_format = 6; 892 break; 893 default: 894 aprint_error("%s: bad depth %d\n", XNAME(sc), 895 dp->rd_bpp); 896 goto error; 897 } 898 899 DPRINTF(("init engine\n")); 900 /* XXX: this seems suspicious - per display engine 901 initialization? */ 902 radeonfb_engine_init(dp); 903 904 /* copy the template into place */ 905 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 906 dp->rd_wsscreens = dp->rd_wsscreens_storage; 907 908 /* and make up the list */ 909 dp->rd_wsscreenlist.nscreens = 1; 910 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 911 912 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 913 &radeonfb_accessops); 914 915 dp->rd_vd.init_screen = radeonfb_init_screen; 916 917 #ifdef RADEONFB_DEBUG 918 dp->rd_virty -= 200; 919 #endif 920 921 dp->rd_console = 0; 922 prop_dictionary_get_bool(device_properties(sc->sc_dev), 923 "is_console", &dp->rd_console); 924 925 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 926 927 928 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 929 dp->rd_console, &defattr); 930 931 ri = &dp->rd_vscreen.scr_ri; 932 933 /* clear the screen */ 934 rasops_unpack_attr(defattr, &fg, &bg, &ul); 935 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 936 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 937 dp->rd_bg); 938 939 dp->rd_wsscreens->textops = &ri->ri_ops; 940 dp->rd_wsscreens->capabilities = ri->ri_caps; 941 dp->rd_wsscreens->nrows = ri->ri_rows; 942 dp->rd_wsscreens->ncols = ri->ri_cols; 943 944 #ifdef SPLASHSCREEN 945 dp->rd_splash.si_depth = ri->ri_depth; 946 dp->rd_splash.si_bits = ri->ri_bits; 947 dp->rd_splash.si_hwbits = ri->ri_hwbits; 948 dp->rd_splash.si_width = ri->ri_width; 949 dp->rd_splash.si_height = ri->ri_height; 950 dp->rd_splash.si_stride = ri->ri_stride; 951 dp->rd_splash.si_fillrect = NULL; 952 #endif 953 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 954 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 955 dp->rd_gc.gc_rop = RADEON_ROP3_S; 956 dp->rd_gc.gc_blitcookie = dp; 957 /* 958 * use memory between framebuffer and cursor area as glyph 959 * cache, cap at 4096 lines 960 */ 961 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 962 min(4096, 963 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 964 dp->rd_virtx, 965 ri->ri_font->fontwidth, 966 ri->ri_font->fontheight, 967 defattr); 968 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 969 dp->rd_vd.show_screen_cb = glyphcache_adapt; 970 971 if (dp->rd_console) { 972 973 radeonfb_modeswitch(dp); 974 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 975 defattr); 976 #ifdef SPLASHSCREEN 977 if (splash_render(&dp->rd_splash, 978 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 979 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 980 else 981 #endif 982 vcons_replay_msgbuf(&dp->rd_vscreen); 983 } else { 984 985 /* 986 * since we're not the console we can postpone 987 * the rest until someone actually allocates a 988 * screen for us. but we do clear the screen 989 * at least. 990 */ 991 memset(ri->ri_bits, 0, 1024); 992 993 radeonfb_modeswitch(dp); 994 #ifdef SPLASHSCREEN 995 if (splash_render(&dp->rd_splash, 996 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 997 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 998 #endif 999 } 1000 1001 aa.console = dp->rd_console; 1002 aa.scrdata = &dp->rd_wsscreenlist; 1003 aa.accessops = &radeonfb_accessops; 1004 aa.accesscookie = &dp->rd_vd; 1005 1006 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1007 1008 radeonfb_blank(dp, 0); 1009 1010 /* Initialise delayed lvds operations for backlight. */ 1011 callout_init(&dp->rd_bl_lvds_co, 0); 1012 callout_setfunc(&dp->rd_bl_lvds_co, 1013 radeonfb_lvds_callout, dp); 1014 dp->rd_bl_on = 1; 1015 dp->rd_bl_level = radeonfb_get_backlight(dp); 1016 radeonfb_set_backlight(dp, dp->rd_bl_level); 1017 } 1018 1019 for (i = 0; i < RADEON_NDISPLAYS; i++) 1020 radeonfb_init_palette(&sc->sc_displays[i]); 1021 1022 if (HAS_CRTC2(sc)) { 1023 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1024 } 1025 1026 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1027 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1028 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1029 radeonfb_brightness_up, TRUE); 1030 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1031 radeonfb_brightness_down, TRUE); 1032 1033 /* 1034 * if we attach a DRM we need to unmap registers in 1035 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1036 * screen blanking we only do it if needed 1037 */ 1038 sc->sc_needs_unmap = 1039 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1040 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1041 1042 PRINTREG(RADEON_CRTC_EXT_CNTL); 1043 PRINTREG(RADEON_CRTC_GEN_CNTL); 1044 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1045 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1046 PRINTREG(RADEON_DAC_CNTL2); 1047 PRINTREG(RADEON_FP_GEN_CNTL); 1048 PRINTREG(RADEON_FP2_GEN_CNTL); 1049 PRINTREG(RADEON_TMDS_CNTL); 1050 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1051 PRINTREG(RADEON_TMDS_PLL_CNTL); 1052 PRINTREG(RADEON_PIXCLKS_CNTL); 1053 1054 return; 1055 1056 error: 1057 if (sc->sc_biossz) 1058 free(sc->sc_bios, M_DEVBUF); 1059 1060 if (sc->sc_regsz) 1061 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1062 1063 if (sc->sc_memsz) 1064 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1065 } 1066 1067 static void 1068 radeonfb_map(struct radeonfb_softc *sc) 1069 { 1070 if (!sc->sc_mapped) { 1071 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1072 &sc->sc_regh) != 0) { 1073 aprint_error_dev(sc->sc_dev, 1074 "unable to map registers!\n"); 1075 return; 1076 } 1077 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1078 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1079 sc->sc_memsz = 0; 1080 aprint_error_dev(sc->sc_dev, 1081 "Unable to map frame buffer\n"); 1082 return; 1083 } 1084 sc->sc_mapped = TRUE; 1085 } 1086 } 1087 1088 static void 1089 radeonfb_unmap(struct radeonfb_softc *sc) 1090 { 1091 if (!sc->sc_needs_unmap) 1092 return; 1093 1094 if (sc->sc_mapped) { 1095 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1096 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1097 sc->sc_mapped = FALSE; 1098 } 1099 } 1100 1101 static int 1102 radeonfb_drm_print(void *aux, const char *pnp) 1103 { 1104 if (pnp) 1105 aprint_normal("drm at %s", pnp); 1106 return (UNCONF); 1107 } 1108 1109 int 1110 radeonfb_ioctl(void *v, void *vs, 1111 unsigned long cmd, void *d, int flag, struct lwp *l) 1112 { 1113 struct vcons_data *vd; 1114 struct radeonfb_display *dp; 1115 struct radeonfb_softc *sc; 1116 struct wsdisplay_param *param; 1117 struct vcons_screen *ms; 1118 1119 vd = (struct vcons_data *)v; 1120 ms = vd->active; 1121 dp = (struct radeonfb_display *)vd->cookie; 1122 sc = dp->rd_softc; 1123 1124 /* can't do these without registers being mapped */ 1125 if (!sc->sc_mapped) { 1126 switch (cmd) { 1127 case WSDISPLAYIO_GVIDEO: 1128 case WSDISPLAYIO_SVIDEO: 1129 case WSDISPLAYIO_GETCMAP: 1130 case WSDISPLAYIO_PUTCMAP: 1131 case WSDISPLAYIO_SCURSOR: 1132 case WSDISPLAYIO_GCURPOS: 1133 case WSDISPLAYIO_SCURPOS: 1134 case WSDISPLAYIO_SETPARAM: 1135 return EINVAL; 1136 } 1137 } 1138 1139 switch (cmd) { 1140 case WSDISPLAYIO_GTYPE: 1141 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1142 return 0; 1143 1144 case WSDISPLAYIO_GINFO: 1145 if (vd->active != NULL) { 1146 struct wsdisplay_fbinfo *fb; 1147 fb = (struct wsdisplay_fbinfo *)d; 1148 fb->width = dp->rd_virtx; 1149 fb->height = dp->rd_virty; 1150 fb->depth = dp->rd_bpp; 1151 fb->cmsize = 256; 1152 return 0; 1153 } else 1154 return ENODEV; 1155 case WSDISPLAYIO_GVIDEO: 1156 if (radeonfb_isblank(dp)) 1157 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1158 else 1159 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1160 return 0; 1161 1162 case WSDISPLAYIO_SVIDEO: 1163 radeonfb_blank(dp, 1164 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1165 radeonfb_switch_backlight(dp, 1166 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1167 return 0; 1168 1169 case WSDISPLAYIO_GETCMAP: 1170 if (dp->rd_bpp == 8) 1171 return radeonfb_getcmap(dp, 1172 (struct wsdisplay_cmap *)d); 1173 return EINVAL; 1174 1175 case WSDISPLAYIO_PUTCMAP: 1176 if (dp->rd_bpp == 8) 1177 return radeonfb_putcmap(dp, 1178 (struct wsdisplay_cmap *)d); 1179 return EINVAL; 1180 1181 case WSDISPLAYIO_LINEBYTES: 1182 *(unsigned *)d = dp->rd_stride; 1183 return 0; 1184 1185 case WSDISPLAYIO_SMODE: 1186 if (*(int *)d != dp->rd_wsmode) { 1187 dp->rd_wsmode = *(int *)d; 1188 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1189 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1190 radeonfb_map(sc); 1191 1192 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1193 (dp->rd_vd.active)) { 1194 radeonfb_engine_init(dp); 1195 glyphcache_wipe(&dp->rd_gc); 1196 radeonfb_init_palette(dp); 1197 radeonfb_modeswitch(dp); 1198 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1199 dp->rd_virty, dp->rd_bg); 1200 vcons_redraw_screen(dp->rd_vd.active); 1201 } 1202 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1203 radeonfb_unmap(sc); 1204 } 1205 return 0; 1206 1207 case WSDISPLAYIO_GCURMAX: 1208 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1209 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1210 return 0; 1211 1212 case WSDISPLAYIO_SCURSOR: 1213 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1214 1215 case WSDISPLAYIO_GCURSOR: 1216 return EPASSTHROUGH; 1217 1218 case WSDISPLAYIO_GCURPOS: 1219 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1220 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1221 return 0; 1222 1223 case WSDISPLAYIO_SCURPOS: 1224 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1225 1226 case WSDISPLAYIO_SSPLASH: 1227 #if defined(SPLASHSCREEN) 1228 if (*(int *)d == 1) { 1229 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1230 splash_render(&dp->rd_splash, 1231 SPLASH_F_CENTER|SPLASH_F_FILL); 1232 } else 1233 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1234 return 0; 1235 #else 1236 return ENODEV; 1237 #endif 1238 case WSDISPLAYIO_GETPARAM: 1239 param = (struct wsdisplay_param *)d; 1240 switch (param->param) { 1241 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1242 param->min = 0; 1243 param->max = 255; 1244 param->curval = dp->rd_bl_level; 1245 return 0; 1246 case WSDISPLAYIO_PARAM_BACKLIGHT: 1247 param->min = 0; 1248 param->max = RADEONFB_BACKLIGHT_MAX; 1249 param->curval = dp->rd_bl_on; 1250 return 0; 1251 } 1252 return EPASSTHROUGH; 1253 1254 case WSDISPLAYIO_SETPARAM: 1255 param = (struct wsdisplay_param *)d; 1256 switch (param->param) { 1257 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1258 radeonfb_set_backlight(dp, param->curval); 1259 return 0; 1260 case WSDISPLAYIO_PARAM_BACKLIGHT: 1261 radeonfb_switch_backlight(dp, param->curval); 1262 return 0; 1263 } 1264 return EPASSTHROUGH; 1265 1266 /* PCI config read/write passthrough. */ 1267 case PCI_IOC_CFGREAD: 1268 case PCI_IOC_CFGWRITE: 1269 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1270 1271 case WSDISPLAYIO_GET_BUSID: 1272 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1273 sc->sc_pt, d); 1274 1275 case WSDISPLAYIO_GET_EDID: { 1276 struct wsdisplayio_edid_info *ei = d; 1277 return wsdisplayio_get_edid(sc->sc_dev, ei); 1278 } 1279 1280 case WSDISPLAYIO_GET_FBINFO: { 1281 struct wsdisplayio_fbinfo *fbi = d; 1282 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1283 } 1284 1285 default: 1286 return EPASSTHROUGH; 1287 } 1288 } 1289 1290 paddr_t 1291 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1292 { 1293 struct vcons_data *vd; 1294 struct radeonfb_display *dp; 1295 struct radeonfb_softc *sc; 1296 paddr_t pa; 1297 1298 vd = (struct vcons_data *)v; 1299 dp = (struct radeonfb_display *)vd->cookie; 1300 sc = dp->rd_softc; 1301 1302 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1303 pa = bus_space_mmap(sc->sc_memt, 1304 sc->sc_memaddr + dp->rd_offset + offset, 0, 1305 prot, BUS_SPACE_MAP_LINEAR); 1306 return pa; 1307 } 1308 1309 /* 1310 * restrict all other mappings to processes with superuser privileges 1311 * or the kernel itself 1312 */ 1313 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1314 NULL, NULL, NULL, NULL) != 0) { 1315 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1316 return -1; 1317 } 1318 1319 if ((offset >= sc->sc_regaddr) && 1320 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1321 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1322 BUS_SPACE_MAP_LINEAR); 1323 } 1324 1325 if ((offset >= sc->sc_memaddr) && 1326 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1327 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1328 BUS_SPACE_MAP_LINEAR); 1329 } 1330 1331 if ((offset >= sc->sc_romaddr) && 1332 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1333 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1334 BUS_SPACE_MAP_LINEAR); 1335 } 1336 1337 #ifdef PCI_MAGIC_IO_RANGE 1338 /* allow mapping of IO space */ 1339 if ((offset >= PCI_MAGIC_IO_RANGE) && 1340 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1341 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1342 0, prot, 0); 1343 return pa; 1344 } 1345 #endif /* PCI_MAGIC_IO_RANGE */ 1346 1347 return -1; 1348 } 1349 1350 static void 1351 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1352 { 1353 bus_space_tag_t romt; 1354 bus_space_handle_t romh, biosh; 1355 bus_size_t romsz; 1356 bus_addr_t ptr; 1357 1358 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1359 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1360 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1361 return; 1362 } 1363 1364 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1365 &sc->sc_biossz); 1366 if (sc->sc_biossz == 0) { 1367 aprint_verbose("%s: Video BIOS not present\n", XNAME(sc)); 1368 return; 1369 } 1370 1371 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1372 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, sc->sc_biossz); 1373 1374 /* unmap the PCI expansion rom */ 1375 bus_space_unmap(romt, romh, romsz); 1376 1377 /* turn off rom decoder now */ 1378 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1379 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1380 ~PCI_MAPREG_ROM_ENABLE); 1381 1382 ptr = GETBIOS16(sc, 0x48); 1383 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1384 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1385 sc->sc_flags |= RFB_ATOM; 1386 } 1387 1388 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1389 (unsigned)sc->sc_biossz >> 10, IS_ATOM(sc) ? "ATOM" : "Legacy"); 1390 } 1391 1392 1393 uint32_t 1394 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1395 { 1396 1397 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1398 } 1399 1400 void 1401 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1402 { 1403 1404 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1405 } 1406 1407 void 1408 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1409 { 1410 1411 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1412 } 1413 1414 void 1415 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1416 uint32_t andmask, uint32_t ormask) 1417 { 1418 int s; 1419 uint32_t val; 1420 1421 s = splhigh(); 1422 val = radeonfb_get32(sc, reg); 1423 val = (val & andmask) | ormask; 1424 radeonfb_put32(sc, reg, val); 1425 splx(s); 1426 } 1427 1428 uint32_t 1429 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1430 { 1431 int s; 1432 uint32_t val; 1433 1434 s = splhigh(); 1435 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1436 val = radeonfb_get32(sc, RADEON_MM_DATA); 1437 splx(s); 1438 1439 return (val); 1440 } 1441 1442 void 1443 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1444 { 1445 int s; 1446 1447 s = splhigh(); 1448 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1449 radeonfb_put32(sc, RADEON_MM_DATA, val); 1450 splx(s); 1451 } 1452 1453 void 1454 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1455 uint32_t andmask, uint32_t ormask) 1456 { 1457 int s; 1458 uint32_t val; 1459 1460 s = splhigh(); 1461 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1462 val = radeonfb_get32(sc, RADEON_MM_DATA); 1463 val = (val & andmask) | ormask; 1464 radeonfb_put32(sc, RADEON_MM_DATA, val); 1465 splx(s); 1466 } 1467 1468 uint32_t 1469 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1470 { 1471 int s; 1472 uint32_t val; 1473 1474 s = splhigh(); 1475 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1476 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1477 if (HAS_R300CG(sc)) 1478 radeonfb_r300cg_workaround(sc); 1479 splx(s); 1480 1481 return (val); 1482 } 1483 1484 void 1485 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1486 { 1487 int s; 1488 1489 s = splhigh(); 1490 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1491 RADEON_PLL_WR_EN); 1492 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1493 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1494 splx(s); 1495 } 1496 1497 void 1498 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1499 uint32_t andmask, uint32_t ormask) 1500 { 1501 int s; 1502 uint32_t val; 1503 1504 s = splhigh(); 1505 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1506 RADEON_PLL_WR_EN); 1507 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1508 val = (val & andmask) | ormask; 1509 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1510 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1511 splx(s); 1512 } 1513 1514 int 1515 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1516 { 1517 uint32_t saved; 1518 1519 saved = GET32(sc, reg); 1520 PUT32(sc, reg, v); 1521 if (GET32(sc, reg) != v) { 1522 return -1; 1523 } 1524 PUT32(sc, reg, saved); 1525 return 0; 1526 } 1527 1528 uintmax_t 1529 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1530 uintmax_t defval) 1531 { 1532 prop_number_t pn; 1533 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1534 if (pn == NULL) { 1535 return defval; 1536 } 1537 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1538 return (prop_number_integer_value(pn)); 1539 } 1540 1541 int 1542 radeonfb_getclocks(struct radeonfb_softc *sc) 1543 { 1544 bus_addr_t ptr; 1545 int refclk = 0; 1546 int refdiv = 0; 1547 int minpll = 0; 1548 int maxpll = 0; 1549 1550 /* load initial property values if port/board provides them */ 1551 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1552 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1553 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1554 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1555 1556 PRINTPLL(RADEON_PPLL_REF_DIV); 1557 PRINTPLL(RADEON_PPLL_DIV_0); 1558 PRINTPLL(RADEON_PPLL_DIV_1); 1559 PRINTPLL(RADEON_PPLL_DIV_2); 1560 PRINTPLL(RADEON_PPLL_DIV_3); 1561 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1562 PRINTPLL(RADEON_P2PLL_REF_DIV); 1563 PRINTPLL(RADEON_P2PLL_DIV_0); 1564 1565 if (refclk && refdiv && minpll && maxpll) 1566 goto dontprobe; 1567 1568 if (!sc->sc_biossz) { 1569 /* no BIOS */ 1570 aprint_verbose("%s: No video BIOS, using default clocks\n", 1571 XNAME(sc)); 1572 if (IS_IGP(sc)) 1573 refclk = refclk ? refclk : 1432; 1574 else 1575 refclk = refclk ? refclk : 2700; 1576 refdiv = refdiv ? refdiv : 12; 1577 minpll = minpll ? minpll : 12500; 1578 /* XXX 1579 * Need to check if the firmware or something programmed a 1580 * higher value than this, and if so, bump it. 1581 * The RV280 in my iBook is unhappy if the PLL input is less 1582 * than 360MHz 1583 */ 1584 maxpll = maxpll ? maxpll : 40000/*35000*/; 1585 } else if (IS_ATOM(sc)) { 1586 /* ATOM BIOS */ 1587 ptr = GETBIOS16(sc, 0x48); 1588 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1589 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1590 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1591 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1592 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1593 /* 1594 * ATOM BIOS doesn't supply a reference divider, so we 1595 * have to probe for it. 1596 */ 1597 if (refdiv < 2) 1598 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1599 RADEON_PPLL_REF_DIV_MASK; 1600 /* 1601 * if probe is zero, just assume one that should work 1602 * for most parts 1603 */ 1604 if (refdiv < 2) 1605 refdiv = 12; 1606 1607 } else { 1608 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1609 /* Legacy BIOS */ 1610 ptr = GETBIOS16(sc, 0x48); 1611 ptr = GETBIOS16(sc, ptr + 0x30); 1612 if (IS_R300(sc)) { 1613 refdiv = refdiv ? refdiv : 1614 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1615 R300_PPLL_REF_DIV_ACC_SHIFT; 1616 } else { 1617 refdiv = refdiv ? refdiv : 1618 tmp & RADEON_PPLL_REF_DIV_MASK; 1619 } 1620 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1621 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1622 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1623 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1624 } 1625 1626 1627 dontprobe: 1628 sc->sc_refclk = refclk * 10; 1629 sc->sc_refdiv = refdiv; 1630 sc->sc_minpll = minpll * 10; 1631 sc->sc_maxpll = maxpll * 10; 1632 return 0; 1633 } 1634 1635 int 1636 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1637 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1638 { 1639 int i; 1640 uint32_t outfreq; 1641 int div; 1642 1643 DPRINTF(("dot clock: %u\n", dotclock)); 1644 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1645 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) continue; 1646 /* 1647 * XXX 1648 * the rv350 in my last generation 14" iBook G4 produces 1649 * garbage with dividers > 4. No idea if this is a hardware 1650 * limitation or an error in the divider table. 1651 */ 1652 if ((sc->sc_family == RADEON_RV350) && (div > 4)) continue; 1653 outfreq = div * dotclock; 1654 if ((outfreq >= sc->sc_minpll) && 1655 (outfreq <= sc->sc_maxpll)) { 1656 DPRINTF(("outfreq: %u\n", outfreq)); 1657 *postdivbit = 1658 ((uint32_t)radeonfb_dividers[i].mask << 16); 1659 DPRINTF(("post divider: %d (mask %x)\n", div, 1660 *postdivbit)); 1661 break; 1662 } 1663 } 1664 1665 if (div == 0) 1666 return 1; 1667 1668 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1669 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1670 return 0; 1671 } 1672 1673 #if 0 1674 #ifdef RADEONFB_DEBUG 1675 static void 1676 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1677 { 1678 char asc[17]; 1679 unsigned ptr = (unsigned)buffer; 1680 char *start = (char *)(ptr & ~0xf); 1681 char *end = (char *)(ptr + size); 1682 1683 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1684 1685 if (pfx == NULL) { 1686 pfx = ""; 1687 } 1688 1689 while (start < end) { 1690 unsigned offset = (unsigned)start & 0xf; 1691 if (offset == 0) { 1692 printf("%s%x: ", pfx, (unsigned)start); 1693 } 1694 if (((unsigned)start < ptr) || 1695 ((unsigned)start >= (ptr + size))) { 1696 printf(" "); 1697 asc[offset] = ' '; 1698 } else { 1699 printf("%02x", *(unsigned char *)start); 1700 if ((*start >= ' ') && (*start <= '~')) { 1701 asc[offset] = *start; 1702 } else { 1703 asc[offset] = '.'; 1704 } 1705 } 1706 asc[offset + 1] = 0; 1707 if (offset % 2) { 1708 printf(" "); 1709 } 1710 if (offset == 15) { 1711 printf(" %s\n", asc); 1712 } 1713 start++; 1714 } 1715 } 1716 #endif 1717 #endif 1718 1719 int 1720 radeonfb_getconnectors(struct radeonfb_softc *sc) 1721 { 1722 int i; 1723 int found = 0; 1724 1725 for (i = 0; i < 2; i++) { 1726 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1727 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1728 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1729 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1730 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1731 } 1732 1733 /* 1734 * This logic is borrowed from Xorg's radeon driver. 1735 */ 1736 if (!sc->sc_biossz) 1737 goto nobios; 1738 1739 if (IS_ATOM(sc)) { 1740 /* not done yet */ 1741 } else { 1742 uint16_t ptr; 1743 int port = 0; 1744 1745 ptr = GETBIOS16(sc, 0x48); 1746 ptr = GETBIOS16(sc, ptr + 0x50); 1747 for (i = 1; i < 4; i++) { 1748 uint16_t entry; 1749 uint8_t conn, ddc, dac, tmds; 1750 1751 /* 1752 * Parse the connector table. From reading the code, 1753 * it appears to made up of 16-bit entries for each 1754 * connector. The 16-bits are defined as: 1755 * 1756 * bits 12-15 - connector type (0 == end of table) 1757 * bits 8-11 - DDC type 1758 * bits 5-7 - ??? 1759 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1760 * bits 1-3 - ??? 1761 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1762 */ 1763 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1764 break; 1765 entry = GETBIOS16(sc, ptr + i * 2); 1766 1767 conn = (entry >> 12) & 0xf; 1768 ddc = (entry >> 8) & 0xf; 1769 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1770 RADEON_DAC_PRIMARY; 1771 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1772 RADEON_TMDS_INT; 1773 1774 if (conn == RADEON_CONN_NONE) 1775 continue; /* no connector */ 1776 1777 1778 1779 /* 1780 * XXX 1781 * both Mac Mini variants have both outputs wired to 1782 * the same connector and share the DDC lines 1783 */ 1784 if ((found > 0) && 1785 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1786 /* duplicate entry for same connector */ 1787 continue; 1788 } 1789 1790 /* internal DDC_DVI port gets priority */ 1791 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1792 port = 0; 1793 else 1794 port = 1; 1795 1796 sc->sc_ports[port].rp_ddc_type = 1797 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1798 sc->sc_ports[port].rp_dac_type = dac; 1799 sc->sc_ports[port].rp_conn_type = 1800 min(conn, RADEON_CONN_UNSUPPORTED) ; 1801 1802 sc->sc_ports[port].rp_tmds_type = tmds; 1803 1804 if ((conn != RADEON_CONN_DVI_I) && 1805 (conn != RADEON_CONN_DVI_D) && 1806 (tmds == RADEON_TMDS_INT)) 1807 sc->sc_ports[port].rp_tmds_type = 1808 RADEON_TMDS_UNKNOWN; 1809 sc->sc_ports[port].rp_number = i - 1; 1810 1811 found += (port + 1); 1812 } 1813 } 1814 1815 nobios: 1816 if (!found) { 1817 bool dvi_ext = FALSE, dvi_int = FALSE; 1818 DPRINTF(("No connector info in BIOS!\n")); 1819 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1820 "dvi-internal", &dvi_int); 1821 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1822 "dvi-external", &dvi_ext); 1823 if (dvi_ext) { 1824 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1825 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1826 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1827 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1828 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1829 sc->sc_ports[0].rp_number = 0; 1830 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1831 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1832 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1833 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1834 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1835 sc->sc_ports[1].rp_number = 1; 1836 } else if (dvi_int) { 1837 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1838 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1839 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1840 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1841 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1842 sc->sc_ports[0].rp_number = 0; 1843 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1844 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1845 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1846 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1847 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1848 sc->sc_ports[1].rp_number = 1; 1849 } else if IS_MOBILITY(sc) { 1850 /* default, port 0 = internal TMDS, port 1 = CRT */ 1851 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1852 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1853 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1854 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1855 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1856 sc->sc_ports[0].rp_number = 0; 1857 1858 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1859 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1860 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1861 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1862 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1863 sc->sc_ports[1].rp_number = 1; 1864 } else { 1865 /* default, port 0 = DVI, port 1 = CRT */ 1866 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1867 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1868 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1869 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1870 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1871 sc->sc_ports[0].rp_number = 1; 1872 1873 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1874 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1875 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1876 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1877 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1878 sc->sc_ports[1].rp_number = 0; 1879 } 1880 } 1881 1882 /* 1883 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1884 * these chips should use TVDAC for the VGA port. 1885 */ 1886 if (HAS_SDAC(sc)) { 1887 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1888 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1889 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1890 } else { 1891 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1892 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1893 } 1894 } else if (!HAS_CRTC2(sc)) { 1895 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1896 } 1897 1898 for (i = 0; i < 2; i++) { 1899 char edid[128]; 1900 uint8_t ddc; 1901 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1902 prop_data_t edid_data; 1903 1904 DPRINTF(("Port #%d:\n", i)); 1905 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1906 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1907 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1908 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1909 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1910 1911 sc->sc_ports[i].rp_edid_valid = 0; 1912 /* first look for static EDID data */ 1913 if ((edid_data = prop_dictionary_get(device_properties( 1914 sc->sc_dev), "EDID")) != NULL) { 1915 1916 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1917 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1918 if (edid_parse(edid, eip) == 0) { 1919 1920 sc->sc_ports[i].rp_edid_valid = 1; 1921 } 1922 } 1923 /* if we didn't find any we'll try to talk to the monitor */ 1924 if (sc->sc_ports[i].rp_edid_valid != 1) { 1925 1926 ddc = sc->sc_ports[i].rp_ddc_type; 1927 if (ddc != RADEON_DDC_NONE) { 1928 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1929 == 0) && (edid_parse(edid, eip) == 0)) { 1930 1931 sc->sc_ports[i].rp_edid_valid = 1; 1932 #ifdef RADEONFB_DEBUG 1933 edid_print(eip); 1934 #endif 1935 } 1936 } 1937 } 1938 } 1939 1940 return found; 1941 } 1942 1943 int 1944 radeonfb_gettmds(struct radeonfb_softc *sc) 1945 { 1946 int i; 1947 1948 if (!sc->sc_biossz) { 1949 goto nobios; 1950 } 1951 1952 if (IS_ATOM(sc)) { 1953 /* XXX: not done yet */ 1954 } else { 1955 uint16_t ptr; 1956 int n; 1957 1958 ptr = GETBIOS16(sc, 0x48); 1959 ptr = GETBIOS16(sc, ptr + 0x34); 1960 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 1961 if (GETBIOS8(sc, ptr) == 3) { 1962 /* revision three table */ 1963 n = GETBIOS8(sc, ptr + 5) + 1; 1964 n = min(n, 4); 1965 1966 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 1967 for (i = 0; i < n; i++) { 1968 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 1969 ptr + i * 10 + 8); 1970 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 1971 ptr + i * 10 + 0x10); 1972 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1973 sc->sc_tmds_pll[i].rtp_freq, 1974 sc->sc_tmds_pll[i].rtp_pll)); 1975 } 1976 return 0; 1977 } 1978 } 1979 1980 nobios: 1981 DPRINTF(("no suitable DFP table present\n")); 1982 for (i = 0; 1983 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 1984 i++) { 1985 int j; 1986 1987 if (radeonfb_tmds_pll[i].family != sc->sc_family) 1988 continue; 1989 1990 for (j = 0; j < 4; j++) { 1991 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 1992 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 1993 sc->sc_tmds_pll[j].rtp_freq, 1994 sc->sc_tmds_pll[j].rtp_pll)); 1995 } 1996 return 0; 1997 } 1998 1999 return -1; 2000 } 2001 2002 const struct videomode * 2003 radeonfb_modelookup(const char *name) 2004 { 2005 int i; 2006 2007 for (i = 0; i < videomode_count; i++) 2008 if (!strcmp(name, videomode_list[i].name)) 2009 return &videomode_list[i]; 2010 2011 return NULL; 2012 } 2013 2014 void 2015 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2016 { 2017 if (crtc) { 2018 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2019 RADEON_P2PLL_ATOMIC_UPDATE_R); 2020 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2021 } else { 2022 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2023 RADEON_PPLL_ATOMIC_UPDATE_R); 2024 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2025 } 2026 } 2027 2028 void 2029 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2030 { 2031 int i; 2032 2033 for (i = 10000; i; i--) { 2034 if (crtc) { 2035 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2036 RADEON_P2PLL_ATOMIC_UPDATE_R) 2037 break; 2038 } else { 2039 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2040 RADEON_PPLL_ATOMIC_UPDATE_R) 2041 break; 2042 } 2043 } 2044 } 2045 2046 void 2047 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2048 { 2049 uint32_t pbit = 0; 2050 uint32_t feed = 0; 2051 uint32_t data, refdiv, div0, r2xxref; 2052 2053 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2054 2055 if (crtc == 0) { 2056 2057 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2058 2059 /* 2060 * XXX 2061 * the RV350 in my last generation iBook G4 behaves like an 2062 * r2xx here - try to detect that and not screw up the reference 2063 * divider. 2064 * xf86-video-radeon just skips PLL programming altogether 2065 * on iBooks, probably for this reason. 2066 */ 2067 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2068 if (IS_R300(sc) && (r2xxref != refdiv)) { 2069 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2070 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2071 } else { 2072 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2073 sc->sc_refdiv; 2074 } 2075 DPRINTF(("refdiv %08x\n", refdiv)); 2076 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2077 DPRINTF(("div0 %08x\n", div0)); 2078 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2079 RADEON_PPLL_POST3_DIV_MASK); 2080 div0 |= pbit; 2081 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2082 DPRINTF(("div0 %08x\n", div0)); 2083 2084 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2085 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2086 /* 2087 * nothing to do here, the PLL is already where we 2088 * want it 2089 */ 2090 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2091 ~RADEON_PLL_DIV_SEL); 2092 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2093 return; 2094 } 2095 2096 /* alright, we do need to reprogram stuff */ 2097 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2098 RADEON_VCLK_SRC_SEL_CPUCLK, 2099 ~RADEON_VCLK_SRC_SEL_MASK); 2100 2101 /* put vclk into reset, use atomic updates */ 2102 SETPLL(sc, RADEON_PPLL_CNTL, 2103 RADEON_PPLL_REFCLK_SEL | 2104 RADEON_PPLL_FBCLK_SEL | 2105 RADEON_PPLL_RESET | 2106 RADEON_PPLL_ATOMIC_UPDATE_EN | 2107 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2108 2109 /* select clock 0 */ 2110 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2111 ~RADEON_PLL_DIV_SEL); 2112 2113 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2114 2115 /* xf86-video-radeon does this, not sure why */ 2116 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2117 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2118 2119 /* use the atomic update */ 2120 radeonfb_pllwriteupdate(sc, crtc); 2121 2122 /* and wait for it to complete */ 2123 radeonfb_pllwaitatomicread(sc, crtc); 2124 2125 /* program HTOTAL (why?) */ 2126 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2127 2128 /* drop reset */ 2129 CLRPLL(sc, RADEON_PPLL_CNTL, 2130 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2131 RADEON_PPLL_ATOMIC_UPDATE_EN | 2132 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2133 2134 PRINTPLL(RADEON_PPLL_CNTL); 2135 PRINTPLL(RADEON_PPLL_REF_DIV); 2136 PRINTPLL(RADEON_PPLL_DIV_3); 2137 2138 /* give clock time to lock */ 2139 delay(50000); 2140 2141 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2142 RADEON_VCLK_SRC_SEL_PPLLCLK, 2143 ~RADEON_VCLK_SRC_SEL_MASK); 2144 2145 } else { 2146 2147 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2148 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2149 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2150 2151 /* put vclk into reset, use atomic updates */ 2152 SETPLL(sc, RADEON_P2PLL_CNTL, 2153 RADEON_P2PLL_RESET | 2154 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2155 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2156 2157 /* program reference divider */ 2158 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2159 ~RADEON_P2PLL_REF_DIV_MASK); 2160 2161 /* program feedback and post dividers */ 2162 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2163 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2164 RADEON_P2PLL_POST0_DIV_MASK); 2165 data |= pbit; 2166 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2167 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2168 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2169 2170 PRINTPLL(RADEON_P2PLL_REF_DIV); 2171 PRINTPLL(RADEON_P2PLL_DIV_0); 2172 2173 /* use the atomic update */ 2174 radeonfb_pllwriteupdate(sc, crtc); 2175 2176 /* and wait for it to complete */ 2177 radeonfb_pllwaitatomicread(sc, crtc); 2178 2179 /* program HTOTAL (why?) */ 2180 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2181 2182 /* drop reset */ 2183 CLRPLL(sc, RADEON_P2PLL_CNTL, 2184 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2185 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2186 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2187 2188 /* allow time for clock to lock */ 2189 delay(50000); 2190 2191 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2192 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2193 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2194 } 2195 PRINTREG(RADEON_CRTC_MORE_CNTL); 2196 } 2197 2198 void 2199 radeonfb_modeswitch(struct radeonfb_display *dp) 2200 { 2201 struct radeonfb_softc *sc = dp->rd_softc; 2202 int i; 2203 2204 /* blank the display while we switch modes */ 2205 radeonfb_blank(dp, 1); 2206 2207 #if 0 2208 SET32(sc, RADEON_CRTC_EXT_CNTL, 2209 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2210 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2211 #endif 2212 2213 /* these registers might get in the way... */ 2214 PUT32(sc, RADEON_OVR_CLR, 0); 2215 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2216 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2217 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2218 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2219 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2220 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2221 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2222 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2223 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2224 PUT32(sc, RADEON_SURFACE_CNTL, 0); 2225 2226 for (i = 0; i < dp->rd_ncrtcs; i++) 2227 radeonfb_setcrtc(dp, i); 2228 2229 #if 0 2230 /* 2231 * DVO chip voodoo from xf86-video-radeon 2232 * apparently this is needed for some powerbooks with DVI outputs 2233 */ 2234 2235 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2236 int n = 0; 2237 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2238 for (i = 0; i < 5; i++) 2239 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2240 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2241 printf("n = %d\n", n); 2242 #endif 2243 2244 /* activate the display */ 2245 radeonfb_blank(dp, 0); 2246 } 2247 2248 void 2249 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2250 { 2251 int crtc, flags = 0; 2252 struct videomode *mode; 2253 struct radeonfb_softc *sc; 2254 struct radeonfb_crtc *cp; 2255 uint32_t v; 2256 uint32_t gencntl; 2257 uint32_t htotaldisp; 2258 uint32_t hsyncstrt; 2259 uint32_t vtotaldisp; 2260 uint32_t vsyncstrt; 2261 uint32_t fphsyncstrt; 2262 uint32_t fpvsyncstrt; 2263 uint32_t fphtotaldisp; 2264 uint32_t fpvtotaldisp; 2265 uint32_t pitch; 2266 2267 sc = dp->rd_softc; 2268 2269 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2270 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2271 flags |= NO_ODD_FBDIV; 2272 } 2273 2274 cp = &dp->rd_crtcs[index]; 2275 crtc = cp->rc_number; 2276 mode = &cp->rc_videomode; 2277 2278 #if 1 2279 pitch = dp->rd_stride / dp->rd_bpp; 2280 #else 2281 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2282 (sc->sc_maxbpp * 8)); 2283 #endif 2284 switch (crtc) { 2285 case 0: 2286 gencntl = RADEON_CRTC_GEN_CNTL; 2287 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2288 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2289 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2290 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2291 /* should probably leave those alone on non-LVDS */ 2292 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2293 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2294 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2295 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2296 break; 2297 case 1: 2298 gencntl = RADEON_CRTC2_GEN_CNTL; 2299 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2300 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2301 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2302 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2303 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2304 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2305 /* XXX these registers don't seem to exist */ 2306 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2307 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2308 break; 2309 default: 2310 panic("Bad CRTC!"); 2311 break; 2312 } 2313 2314 /* 2315 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2316 */ 2317 /* only bother with 32bpp and 8bpp */ 2318 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2319 2320 if (crtc == 1) { 2321 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2322 } else { 2323 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2324 } 2325 2326 if (mode->flags & VID_DBLSCAN) 2327 v |= RADEON_CRTC2_DBL_SCAN_EN; 2328 2329 if (mode->flags & VID_INTERLACE) 2330 v |= RADEON_CRTC2_INTERLACE_EN; 2331 2332 if (mode->flags & VID_CSYNC) { 2333 v |= RADEON_CRTC2_CSYNC_EN; 2334 if (crtc == 1) 2335 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2336 } 2337 2338 PUT32(sc, gencntl, v); 2339 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2340 2341 /* 2342 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2343 */ 2344 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2345 if (crtc == 0) { 2346 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2347 RADEON_CRTC_DISPLAY_DIS); 2348 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2349 if (mode->flags & VID_CSYNC) 2350 v |= RADEON_CRTC_VSYNC_TRISTAT; 2351 } 2352 /* unconditional turn on CRT, in case first CRTC is DFP */ 2353 v |= RADEON_CRTC_CRT_ON; 2354 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2355 PRINTREG(RADEON_CRTC_EXT_CNTL); 2356 2357 /* 2358 * H_TOTAL_DISP 2359 */ 2360 v = ((mode->hdisplay / 8) - 1) << 16; 2361 v |= (mode->htotal / 8) - 1; 2362 PUT32(sc, htotaldisp, v); 2363 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2364 if (fphtotaldisp) { 2365 PUT32(sc, fphtotaldisp, v); 2366 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2367 } 2368 /* 2369 * H_SYNC_STRT_WID 2370 */ 2371 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2372 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2373 if (mode->flags & VID_NHSYNC) 2374 v |= RADEON_CRTC_H_SYNC_POL; 2375 PUT32(sc, hsyncstrt, v); 2376 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2377 if (fphsyncstrt) { 2378 PUT32(sc, fphsyncstrt, v); 2379 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2380 } 2381 2382 /* 2383 * V_TOTAL_DISP 2384 */ 2385 v = ((mode->vdisplay - 1) << 16); 2386 v |= (mode->vtotal - 1); 2387 PUT32(sc, vtotaldisp, v); 2388 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2389 if (fpvtotaldisp) { 2390 PUT32(sc, fpvtotaldisp, v); 2391 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2392 } 2393 2394 /* 2395 * V_SYNC_STRT_WID 2396 */ 2397 v = ((mode->vsync_end - mode->vsync_start) << 16); 2398 v |= (mode->vsync_start - 1); 2399 if (mode->flags & VID_NVSYNC) 2400 v |= RADEON_CRTC_V_SYNC_POL; 2401 PUT32(sc, vsyncstrt, v); 2402 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2403 if (fpvsyncstrt) { 2404 PUT32(sc, fpvsyncstrt, v); 2405 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2406 } 2407 2408 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2409 2410 switch (crtc) { 2411 case 0: 2412 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2413 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2414 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2415 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2416 2417 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2418 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2419 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2420 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2421 PRINTREG(RADEON_CRTC_EXT_CNTL); 2422 PRINTREG(RADEON_CRTC_GEN_CNTL); 2423 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2424 break; 2425 2426 case 1: 2427 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2428 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2429 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2430 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2431 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2432 RADEON_CRTC2_VSYNC_DIS | 2433 RADEON_CRTC2_HSYNC_DIS | 2434 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2435 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2436 break; 2437 } 2438 } 2439 2440 int 2441 radeonfb_isblank(struct radeonfb_display *dp) 2442 { 2443 uint32_t reg, mask; 2444 2445 if(!dp->rd_softc->sc_mapped) 2446 return 1; 2447 2448 if (dp->rd_crtcs[0].rc_number) { 2449 reg = RADEON_CRTC2_GEN_CNTL; 2450 mask = RADEON_CRTC2_DISP_DIS; 2451 } else { 2452 reg = RADEON_CRTC_EXT_CNTL; 2453 mask = RADEON_CRTC_DISPLAY_DIS; 2454 } 2455 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2456 } 2457 2458 void 2459 radeonfb_blank(struct radeonfb_display *dp, int blank) 2460 { 2461 struct radeonfb_softc *sc = dp->rd_softc; 2462 uint32_t reg, mask; 2463 uint32_t fpreg, fpval; 2464 int i; 2465 2466 if (!sc->sc_mapped) 2467 return; 2468 2469 for (i = 0; i < dp->rd_ncrtcs; i++) { 2470 2471 if (dp->rd_crtcs[i].rc_number) { 2472 reg = RADEON_CRTC2_GEN_CNTL; 2473 mask = RADEON_CRTC2_DISP_DIS; 2474 fpreg = RADEON_FP2_GEN_CNTL; 2475 fpval = RADEON_FP2_ON; 2476 } else { 2477 reg = RADEON_CRTC_EXT_CNTL; 2478 mask = RADEON_CRTC_DISPLAY_DIS; 2479 fpreg = RADEON_FP_GEN_CNTL; 2480 fpval = RADEON_FP_FPON; 2481 } 2482 2483 if (blank) { 2484 SET32(sc, reg, mask); 2485 CLR32(sc, fpreg, fpval); 2486 } else { 2487 CLR32(sc, reg, mask); 2488 SET32(sc, fpreg, fpval); 2489 } 2490 } 2491 PRINTREG(RADEON_FP_GEN_CNTL); 2492 PRINTREG(RADEON_FP2_GEN_CNTL); 2493 } 2494 2495 void 2496 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2497 long *defattr) 2498 { 2499 struct radeonfb_display *dp = cookie; 2500 struct rasops_info *ri = &scr->scr_ri; 2501 2502 /* initialize font subsystem */ 2503 wsfont_init(); 2504 2505 scr->scr_flags |= VCONS_LOADFONT; 2506 2507 DPRINTF(("init screen called, existing %d\n", existing)); 2508 2509 ri->ri_depth = dp->rd_bpp; 2510 ri->ri_width = dp->rd_virtx; 2511 ri->ri_height = dp->rd_virty; 2512 ri->ri_stride = dp->rd_stride; 2513 ri->ri_flg = RI_CENTER; 2514 switch (ri->ri_depth) { 2515 case 8: 2516 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2517 break; 2518 case 32: 2519 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2520 /* we run radeons in RGB even on SPARC hardware */ 2521 ri->ri_rnum = 8; 2522 ri->ri_gnum = 8; 2523 ri->ri_bnum = 8; 2524 ri->ri_rpos = 16; 2525 ri->ri_gpos = 8; 2526 ri->ri_bpos = 0; 2527 break; 2528 } 2529 2530 ri->ri_bits = (void *)dp->rd_fbptr; 2531 2532 #ifdef VCONS_DRAW_INTR 2533 scr->scr_flags |= VCONS_DONT_READ; 2534 #endif 2535 2536 if (existing) { 2537 ri->ri_flg |= RI_CLEAR; 2538 2539 /* start a modeswitch now */ 2540 radeonfb_modeswitch(dp); 2541 } 2542 2543 /* 2544 * XXX: font selection should be based on properties, with some 2545 * normal/reasonable default. 2546 */ 2547 2548 /* initialize and look for an initial font */ 2549 rasops_init(ri, 0, 0); 2550 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2551 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2552 2553 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2554 dp->rd_virtx / ri->ri_font->fontwidth); 2555 2556 /* enable acceleration */ 2557 dp->rd_putchar = ri->ri_ops.putchar; 2558 ri->ri_ops.copyrows = radeonfb_copyrows; 2559 ri->ri_ops.copycols = radeonfb_copycols; 2560 ri->ri_ops.eraserows = radeonfb_eraserows; 2561 ri->ri_ops.erasecols = radeonfb_erasecols; 2562 /* pick a putchar method based on font and Radeon model */ 2563 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2564 /* got a bitmap font */ 2565 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2566 if (IS_R300(dp->rd_softc)) { 2567 /* 2568 * radeonfb_putchar() doesn't work right on some R3xx 2569 * so we use software drawing here, the wrapper just 2570 * makes sure the engine is idle before scribbling 2571 * into vram 2572 */ 2573 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2574 } else 2575 #endif 2576 ri->ri_ops.putchar = radeonfb_putchar; 2577 } else { 2578 /* got an alpha font */ 2579 switch(ri->ri_depth) { 2580 case 32: 2581 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2582 break; 2583 case 8: 2584 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2585 break; 2586 default: 2587 /* XXX this should never happen */ 2588 panic("%s: depth is not 8 or 32 but we got an" \ 2589 " alpha font?!", __func__); 2590 } 2591 } 2592 ri->ri_ops.cursor = radeonfb_cursor; 2593 } 2594 2595 void 2596 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2597 { 2598 uint32_t gen, ext, gen2 = 0; 2599 uint32_t agploc, aperbase, apersize, mcfbloc; 2600 2601 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2602 /* XXX */ 2603 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2604 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2605 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2606 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2607 2608 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2609 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2610 #if 0 2611 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2612 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2613 #endif 2614 2615 if (HAS_CRTC2(sc)) { 2616 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2617 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2618 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2619 } 2620 2621 delay(100000); 2622 2623 mcfbloc = (aperbase >> 16) | 2624 ((aperbase + (apersize - 1)) & 0xffff0000); 2625 2626 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2627 sc->sc_memsz = apersize; 2628 2629 if (((agploc & 0xffff) << 16) != 2630 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2631 agploc = mcfbloc & 0xffff0000U; 2632 agploc |= ((agploc + 0x10000) >> 16); 2633 } 2634 2635 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2636 2637 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2638 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2639 2640 DPRINTF(("aperbase = %u\n", aperbase)); 2641 PRINTREG(RADEON_MC_FB_LOCATION); 2642 PRINTREG(RADEON_MC_AGP_LOCATION); 2643 2644 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2645 2646 if (HAS_CRTC2(sc)) 2647 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2648 2649 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2650 2651 #if 0 2652 /* XXX: what is this AGP garbage? :-) */ 2653 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2654 #endif 2655 2656 delay(100000); 2657 2658 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2659 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2660 2661 if (HAS_CRTC2(sc)) 2662 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2663 } 2664 2665 void 2666 radeonfb_init_misc(struct radeonfb_softc *sc) 2667 { 2668 PUT32(sc, RADEON_BUS_CNTL, 2669 RADEON_BUS_MASTER_DIS | 2670 RADEON_BUS_PREFETCH_MODE_ACT | 2671 RADEON_BUS_PCI_READ_RETRY_EN | 2672 RADEON_BUS_PCI_WRT_RETRY_EN | 2673 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2674 RADEON_BUS_MSTR_RD_MULT | 2675 RADEON_BUS_MSTR_RD_LINE | 2676 RADEON_BUS_RD_DISCARD_EN | 2677 RADEON_BUS_MSTR_DISCONNECT_EN | 2678 RADEON_BUS_READ_BURST); 2679 2680 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2681 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2682 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2683 PUT32(sc, RADEON_RBBM_CNTL, 2684 (3 << RADEON_RB_SETTLE_SHIFT) | 2685 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2686 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2687 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2688 2689 /* XXX: figure out what these mean! */ 2690 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2691 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2692 #if 0 2693 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2694 #endif 2695 2696 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2697 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2698 } 2699 2700 static void 2701 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2702 { 2703 struct radeonfb_softc *sc = dp->rd_softc; 2704 int crtc, cc; 2705 uint32_t vclk; 2706 2707 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2708 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2709 2710 /* initialize the palette for every CRTC used by this display */ 2711 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2712 crtc = dp->rd_crtcs[cc].rc_number; 2713 2714 if (crtc) 2715 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2716 else 2717 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2718 2719 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2720 PUT32(sc, RADEON_PALETTE_30_DATA, 2721 (r << 22) | (g << 12) | (b << 2)); 2722 } 2723 2724 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2725 } 2726 2727 /* 2728 * This loads a linear color map for true color. 2729 */ 2730 void 2731 radeonfb_init_palette(struct radeonfb_display *dp) 2732 { 2733 int i; 2734 2735 #define DAC_WIDTH ((1 << 10) - 1) 2736 #define CLUT_WIDTH ((1 << 8) - 1) 2737 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2738 2739 if (dp->rd_bpp == 8) { 2740 2741 /* R3G3B2 palette */ 2742 uint32_t tmp, r, g, b; 2743 2744 for (i = 0; i <= CLUT_WIDTH; ++i) { 2745 tmp = i & 0xe0; 2746 2747 /* 2748 * replicate bits so 0xe0 maps to a red value of 0xff 2749 * in order to make white look actually white 2750 */ 2751 tmp |= (tmp >> 3) | (tmp >> 6); 2752 r = tmp; 2753 2754 tmp = (i & 0x1c) << 3; 2755 tmp |= (tmp >> 3) | (tmp >> 6); 2756 g = tmp; 2757 2758 tmp = (i & 0x03) << 6; 2759 tmp |= tmp >> 2; 2760 tmp |= tmp >> 4; 2761 b = tmp; 2762 2763 radeonfb_putpal(dp, i, r, g, b); 2764 } 2765 } else { 2766 /* linear ramp */ 2767 for (i = 0; i <= CLUT_WIDTH; ++i) { 2768 radeonfb_putpal(dp, i, i, i, i); 2769 } 2770 } 2771 } 2772 2773 static int 2774 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2775 { 2776 u_char *r, *g, *b; 2777 u_int index = cm->index; 2778 u_int count = cm->count; 2779 int i, error; 2780 u_char rbuf[256], gbuf[256], bbuf[256]; 2781 2782 #ifdef GENFB_DEBUG 2783 aprint_debug("putcmap: %d %d\n",index, count); 2784 #endif 2785 if (index >= 256 || count > 256 - index) 2786 return EINVAL; 2787 error = copyin(cm->red, &rbuf[index], count); 2788 if (error) 2789 return error; 2790 error = copyin(cm->green, &gbuf[index], count); 2791 if (error) 2792 return error; 2793 error = copyin(cm->blue, &bbuf[index], count); 2794 if (error) 2795 return error; 2796 2797 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2798 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2799 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2800 2801 r = &dp->rd_cmap_red[index]; 2802 g = &dp->rd_cmap_green[index]; 2803 b = &dp->rd_cmap_blue[index]; 2804 2805 for (i = 0; i < count; i++) { 2806 radeonfb_putpal(dp, index, *r, *g, *b); 2807 index++; 2808 r++, g++, b++; 2809 } 2810 return 0; 2811 } 2812 2813 static int 2814 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2815 { 2816 u_int index = cm->index; 2817 u_int count = cm->count; 2818 int error; 2819 2820 if (index >= 256 || count > 256 - index) 2821 return EINVAL; 2822 2823 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2824 if (error) 2825 return error; 2826 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2827 if (error) 2828 return error; 2829 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2830 if (error) 2831 return error; 2832 2833 return 0; 2834 } 2835 2836 /* 2837 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2838 */ 2839 void 2840 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2841 { 2842 uint32_t tmp, save; 2843 2844 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2845 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2846 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2847 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2848 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2849 } 2850 2851 /* 2852 * Acceleration entry points. 2853 */ 2854 2855 /* this one draws characters using bitmap fonts */ 2856 static void 2857 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2858 { 2859 struct rasops_info *ri = cookie; 2860 struct vcons_screen *scr = ri->ri_hw; 2861 struct radeonfb_display *dp = scr->scr_cookie; 2862 struct radeonfb_softc *sc = dp->rd_softc; 2863 struct wsdisplay_font *font = PICK_FONT(ri, c); 2864 uint32_t w, h; 2865 int xd, yd, offset, i; 2866 uint32_t bg, fg, gmc; 2867 uint32_t reg; 2868 uint8_t *data8; 2869 uint16_t *data16; 2870 void *data; 2871 2872 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2873 return; 2874 2875 if (!CHAR_IN_FONT(c, font)) 2876 return; 2877 2878 w = font->fontwidth; 2879 h = font->fontheight; 2880 2881 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2882 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2883 2884 xd = ri->ri_xorigin + col * w; 2885 yd = ri->ri_yorigin + row * h; 2886 2887 if (c == 0x20) { 2888 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2889 return; 2890 } 2891 data = WSFONT_GLYPH(c, font); 2892 2893 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2894 2895 radeonfb_wait_fifo(sc, 9); 2896 2897 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2898 RADEON_GMC_BRUSH_NONE | 2899 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2900 RADEON_GMC_DST_CLIPPING | 2901 RADEON_ROP3_S | 2902 RADEON_DP_SRC_SOURCE_HOST_DATA | 2903 RADEON_GMC_CLR_CMP_CNTL_DIS | 2904 RADEON_GMC_WR_MSK_DIS | 2905 gmc); 2906 2907 PUT32(sc, RADEON_SC_LEFT, xd); 2908 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2909 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2910 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2911 PUT32(sc, RADEON_DP_CNTL, 2912 RADEON_DST_X_LEFT_TO_RIGHT | 2913 RADEON_DST_Y_TOP_TO_BOTTOM); 2914 2915 PUT32(sc, RADEON_SRC_X_Y, 0); 2916 offset = 32 - (font->stride << 3); 2917 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2918 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2919 2920 radeonfb_wait_fifo(sc, h); 2921 switch (font->stride) { 2922 case 1: { 2923 data8 = data; 2924 for (i = 0; i < h; i++) { 2925 reg = *data8; 2926 #if BYTE_ORDER == LITTLE_ENDIAN 2927 reg = reg << 24; 2928 #endif 2929 bus_space_write_stream_4(sc->sc_regt, 2930 sc->sc_regh, RADEON_HOST_DATA0, reg); 2931 data8++; 2932 } 2933 break; 2934 } 2935 case 2: { 2936 data16 = data; 2937 for (i = 0; i < h; i++) { 2938 reg = *data16; 2939 #if BYTE_ORDER == LITTLE_ENDIAN 2940 reg = reg << 16; 2941 #endif 2942 bus_space_write_stream_4(sc->sc_regt, 2943 sc->sc_regh, RADEON_HOST_DATA0, reg); 2944 data16++; 2945 } 2946 break; 2947 } 2948 } 2949 if (attr & 1) 2950 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2951 } 2952 2953 /* ... while this one is for anti-aliased ones */ 2954 static void 2955 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 2956 { 2957 struct rasops_info *ri = cookie; 2958 struct vcons_screen *scr = ri->ri_hw; 2959 struct radeonfb_display *dp = scr->scr_cookie; 2960 struct radeonfb_softc *sc = dp->rd_softc; 2961 struct wsdisplay_font *font = PICK_FONT(ri, c); 2962 uint32_t bg, fg, gmc; 2963 uint8_t *data; 2964 int w, h, xd, yd; 2965 int i, r, g, b, aval; 2966 int rf, gf, bf, rb, gb, bb; 2967 uint32_t pixel; 2968 int rv; 2969 2970 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2971 return; 2972 2973 if (!CHAR_IN_FONT(c, font)) 2974 return; 2975 2976 w = font->fontwidth; 2977 h = font->fontheight; 2978 2979 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2980 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2981 2982 xd = ri->ri_xorigin + col * w; 2983 yd = ri->ri_yorigin + row * h; 2984 2985 if (c == 0x20) { 2986 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2987 if (attr & 1) 2988 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 2989 return; 2990 } 2991 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 2992 if (rv == GC_OK) 2993 return; 2994 2995 data = WSFONT_GLYPH(c, font); 2996 2997 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2998 2999 radeonfb_wait_fifo(sc, 5); 3000 3001 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3002 RADEON_GMC_BRUSH_NONE | 3003 RADEON_GMC_SRC_DATATYPE_COLOR | 3004 RADEON_ROP3_S | 3005 RADEON_DP_SRC_SOURCE_HOST_DATA | 3006 RADEON_GMC_CLR_CMP_CNTL_DIS | 3007 RADEON_GMC_WR_MSK_DIS | 3008 gmc); 3009 3010 PUT32(sc, RADEON_DP_CNTL, 3011 RADEON_DST_X_LEFT_TO_RIGHT | 3012 RADEON_DST_Y_TOP_TO_BOTTOM); 3013 3014 PUT32(sc, RADEON_SRC_X_Y, 0); 3015 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3016 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3017 3018 rf = (fg >> 16) & 0xff; 3019 rb = (bg >> 16) & 0xff; 3020 gf = (fg >> 8) & 0xff; 3021 gb = (bg >> 8) & 0xff; 3022 bf = fg & 0xff; 3023 bb = bg & 0xff; 3024 3025 /* 3026 * I doubt we can upload data faster than even the slowest Radeon 3027 * could process them, especially when doing the alpha blending stuff 3028 * along the way, so just make sure there's some room in the FIFO and 3029 * then hammer away 3030 * As it turns out we can, so make periodic stops to let the FIFO 3031 * drain. 3032 */ 3033 radeonfb_wait_fifo(sc, 20); 3034 for (i = 0; i < ri->ri_fontscale; i++) { 3035 aval = *data; 3036 data++; 3037 if (aval == 0) { 3038 pixel = bg; 3039 } else if (aval == 255) { 3040 pixel = fg; 3041 } else { 3042 r = aval * rf + (255 - aval) * rb; 3043 g = aval * gf + (255 - aval) * gb; 3044 b = aval * bf + (255 - aval) * bb; 3045 pixel = (r & 0xff00) << 8 | 3046 (g & 0xff00) | 3047 (b & 0xff00) >> 8; 3048 } 3049 if (i & 16) 3050 radeonfb_wait_fifo(sc, 20); 3051 PUT32(sc, RADEON_HOST_DATA0, pixel); 3052 } 3053 if (rv == GC_ADD) { 3054 glyphcache_add(&dp->rd_gc, c, xd, yd); 3055 } else if (attr & 1) 3056 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3057 } 3058 3059 static void 3060 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3061 { 3062 struct rasops_info *ri = cookie; 3063 struct vcons_screen *scr = ri->ri_hw; 3064 struct radeonfb_display *dp = scr->scr_cookie; 3065 struct radeonfb_softc *sc = dp->rd_softc; 3066 struct wsdisplay_font *font = PICK_FONT(ri, c); 3067 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3068 int i, x, y, wi, he, r, g, b, aval; 3069 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3070 uint8_t *data8; 3071 int rv, cnt; 3072 3073 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3074 return; 3075 3076 if (!CHAR_IN_FONT(c, font)) 3077 return; 3078 3079 wi = font->fontwidth; 3080 he = font->fontheight; 3081 3082 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3083 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3084 3085 x = ri->ri_xorigin + col * wi; 3086 y = ri->ri_yorigin + row * he; 3087 3088 if (c == 0x20) { 3089 radeonfb_rectfill(dp, x, y, wi, he, bg); 3090 if (attr & 1) 3091 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3092 return; 3093 } 3094 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3095 if (rv == GC_OK) 3096 return; 3097 3098 data8 = WSFONT_GLYPH(c, font); 3099 3100 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3101 3102 radeonfb_wait_fifo(sc, 5); 3103 3104 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3105 RADEON_GMC_BRUSH_NONE | 3106 RADEON_GMC_SRC_DATATYPE_COLOR | 3107 RADEON_ROP3_S | 3108 RADEON_DP_SRC_SOURCE_HOST_DATA | 3109 RADEON_GMC_CLR_CMP_CNTL_DIS | 3110 RADEON_GMC_WR_MSK_DIS | 3111 gmc); 3112 3113 PUT32(sc, RADEON_DP_CNTL, 3114 RADEON_DST_X_LEFT_TO_RIGHT | 3115 RADEON_DST_Y_TOP_TO_BOTTOM); 3116 3117 PUT32(sc, RADEON_SRC_X_Y, 0); 3118 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3119 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3120 3121 /* 3122 * we need the RGB colours here, so get offsets into rasops_cmap 3123 */ 3124 fgo = ((attr >> 24) & 0xf) * 3; 3125 bgo = ((attr >> 16) & 0xf) * 3; 3126 3127 r0 = rasops_cmap[bgo]; 3128 r1 = rasops_cmap[fgo]; 3129 g0 = rasops_cmap[bgo + 1]; 3130 g1 = rasops_cmap[fgo + 1]; 3131 b0 = rasops_cmap[bgo + 2]; 3132 b1 = rasops_cmap[fgo + 2]; 3133 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3134 bg8 = R3G3B2(r0, g0, b0); 3135 fg8 = R3G3B2(r1, g1, b1); 3136 3137 radeonfb_wait_fifo(sc, 20); 3138 cnt = 0; 3139 for (i = 0; i < ri->ri_fontscale; i++) { 3140 aval = *data8; 3141 if (aval == 0) { 3142 pixel = bg8; 3143 } else if (aval == 255) { 3144 pixel = fg8; 3145 } else { 3146 r = aval * r1 + (255 - aval) * r0; 3147 g = aval * g1 + (255 - aval) * g0; 3148 b = aval * b1 + (255 - aval) * b0; 3149 pixel = ((r & 0xe000) >> 8) | 3150 ((g & 0xe000) >> 11) | 3151 ((b & 0xc000) >> 14); 3152 } 3153 latch |= pixel << (8 * (i & 3)); 3154 /* write in 32bit chunks */ 3155 if ((i & 3) == 3) { 3156 PUT32(sc, RADEON_HOST_DATA0, latch); 3157 /* 3158 * not strictly necessary, old data should be shifted 3159 * out 3160 */ 3161 latch = 0; 3162 cnt++; 3163 if (cnt > 16) { 3164 cnt = 0; 3165 radeonfb_wait_fifo(sc, 20); 3166 } 3167 } 3168 data8++; 3169 } 3170 /* if we have pixels left in latch write them out */ 3171 if ((i & 3) != 0) { 3172 /* 3173 * radeon is weird - apparently leftover pixels are written 3174 * from the middle, not from the left as everything else 3175 */ 3176 PUT32(sc, RADEON_HOST_DATA0, latch); 3177 } 3178 3179 if (rv == GC_ADD) { 3180 glyphcache_add(&dp->rd_gc, c, x, y); 3181 } else 3182 if (attr & 1) 3183 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3184 } 3185 3186 /* 3187 * wrapper for software character drawing 3188 * just sync the engine and call rasops*_putchar() 3189 */ 3190 3191 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3192 static void 3193 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3194 { 3195 struct rasops_info *ri = cookie; 3196 struct vcons_screen *scr = ri->ri_hw; 3197 struct radeonfb_display *dp = scr->scr_cookie; 3198 3199 radeonfb_engine_idle(dp->rd_softc); 3200 dp->rd_putchar(ri, row, col, c, attr); 3201 } 3202 #endif 3203 3204 static void 3205 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3206 { 3207 struct rasops_info *ri = cookie; 3208 struct vcons_screen *scr = ri->ri_hw; 3209 struct radeonfb_display *dp = scr->scr_cookie; 3210 uint32_t x, y, w, h, fg, bg, ul; 3211 3212 /* XXX: check for full emulation mode? */ 3213 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3214 x = ri->ri_xorigin; 3215 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3216 w = ri->ri_emuwidth; 3217 h = ri->ri_font->fontheight * nrows; 3218 3219 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3220 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3221 } 3222 } 3223 3224 static void 3225 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3226 { 3227 struct rasops_info *ri = cookie; 3228 struct vcons_screen *scr = ri->ri_hw; 3229 struct radeonfb_display *dp = scr->scr_cookie; 3230 uint32_t x, ys, yd, w, h; 3231 3232 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3233 x = ri->ri_xorigin; 3234 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3235 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3236 w = ri->ri_emuwidth; 3237 h = ri->ri_font->fontheight * nrows; 3238 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3239 RADEON_ROP3_S); 3240 } 3241 } 3242 3243 static void 3244 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3245 { 3246 struct rasops_info *ri = cookie; 3247 struct vcons_screen *scr = ri->ri_hw; 3248 struct radeonfb_display *dp = scr->scr_cookie; 3249 uint32_t xs, xd, y, w, h; 3250 3251 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3252 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3253 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3254 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3255 w = ri->ri_font->fontwidth * ncols; 3256 h = ri->ri_font->fontheight; 3257 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3258 RADEON_ROP3_S); 3259 } 3260 } 3261 3262 static void 3263 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3264 long fillattr) 3265 { 3266 struct rasops_info *ri = cookie; 3267 struct vcons_screen *scr = ri->ri_hw; 3268 struct radeonfb_display *dp = scr->scr_cookie; 3269 uint32_t x, y, w, h, fg, bg, ul; 3270 3271 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3272 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3273 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3274 w = ri->ri_font->fontwidth * ncols; 3275 h = ri->ri_font->fontheight; 3276 3277 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3278 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3279 } 3280 } 3281 3282 static void 3283 radeonfb_cursor(void *cookie, int on, int row, int col) 3284 { 3285 struct rasops_info *ri = cookie; 3286 struct vcons_screen *scr = ri->ri_hw; 3287 struct radeonfb_display *dp = scr->scr_cookie; 3288 int x, y, wi, he; 3289 3290 wi = ri->ri_font->fontwidth; 3291 he = ri->ri_font->fontheight; 3292 3293 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3294 x = ri->ri_ccol * wi + ri->ri_xorigin; 3295 y = ri->ri_crow * he + ri->ri_yorigin; 3296 /* first turn off the old cursor */ 3297 if (ri->ri_flg & RI_CURSOR) { 3298 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3299 RADEON_ROP3_Dn); 3300 ri->ri_flg &= ~RI_CURSOR; 3301 } 3302 ri->ri_crow = row; 3303 ri->ri_ccol = col; 3304 /* then (possibly) turn on the new one */ 3305 if (on) { 3306 x = ri->ri_ccol * wi + ri->ri_xorigin; 3307 y = ri->ri_crow * he + ri->ri_yorigin; 3308 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3309 RADEON_ROP3_Dn); 3310 ri->ri_flg |= RI_CURSOR; 3311 } 3312 } else { 3313 scr->scr_ri.ri_crow = row; 3314 scr->scr_ri.ri_ccol = col; 3315 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3316 } 3317 } 3318 3319 /* 3320 * Underlying acceleration support. 3321 */ 3322 3323 static void 3324 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3325 int width, int height, uint32_t color) 3326 { 3327 struct radeonfb_softc *sc = dp->rd_softc; 3328 uint32_t gmc; 3329 3330 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3331 3332 radeonfb_wait_fifo(sc, 6); 3333 3334 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3335 RADEON_GMC_BRUSH_SOLID_COLOR | 3336 RADEON_GMC_SRC_DATATYPE_COLOR | 3337 RADEON_GMC_CLR_CMP_CNTL_DIS | 3338 RADEON_ROP3_P | gmc); 3339 3340 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3341 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3342 PUT32(sc, RADEON_DP_CNTL, 3343 RADEON_DST_X_LEFT_TO_RIGHT | 3344 RADEON_DST_Y_TOP_TO_BOTTOM); 3345 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3346 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3347 } 3348 3349 static void 3350 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3351 int width, int height, long attr) 3352 { 3353 struct radeonfb_display *dp = cookie; 3354 3355 radeonfb_rectfill(dp, dstx, dsty, width, height, 3356 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3357 } 3358 3359 static void 3360 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3361 int dstx, int dsty, int width, int height, int rop) 3362 { 3363 struct radeonfb_display *dp = cookie; 3364 struct radeonfb_softc *sc = dp->rd_softc; 3365 uint32_t gmc; 3366 uint32_t dir; 3367 3368 if (dsty < srcy) { 3369 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3370 } else { 3371 srcy += height - 1; 3372 dsty += height - 1; 3373 dir = 0; 3374 } 3375 if (dstx < srcx) { 3376 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3377 } else { 3378 srcx += width - 1; 3379 dstx += width - 1; 3380 } 3381 3382 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3383 3384 radeonfb_wait_fifo(sc, 6); 3385 3386 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3387 RADEON_GMC_BRUSH_SOLID_COLOR | 3388 RADEON_GMC_SRC_DATATYPE_COLOR | 3389 RADEON_GMC_CLR_CMP_CNTL_DIS | 3390 RADEON_DP_SRC_SOURCE_MEMORY | 3391 rop | gmc); 3392 3393 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3394 PUT32(sc, RADEON_DP_CNTL, dir); 3395 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3396 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3397 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3398 } 3399 3400 static void 3401 radeonfb_engine_idle(struct radeonfb_softc *sc) 3402 { 3403 3404 radeonfb_wait_fifo(sc, 64); 3405 while ((GET32(sc, RADEON_RBBM_STATUS) & 3406 RADEON_RBBM_ACTIVE) != 0); 3407 radeonfb_engine_flush(sc); 3408 } 3409 3410 static inline void 3411 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3412 { 3413 int i; 3414 3415 for (i = RADEON_TIMEOUT; i; i--) { 3416 if ((GET32(sc, RADEON_RBBM_STATUS) & 3417 RADEON_RBBM_FIFOCNT_MASK) >= n) 3418 return; 3419 } 3420 #ifdef DIAGNOSTIC 3421 if (!i) 3422 printf("%s: timed out waiting for fifo (%x)\n", 3423 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3424 #endif 3425 } 3426 3427 static void 3428 radeonfb_engine_flush(struct radeonfb_softc *sc) 3429 { 3430 int i = 0; 3431 3432 if (IS_R300(sc)) { 3433 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3434 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3435 i++; 3436 } 3437 } else { 3438 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3439 RADEON_RB2D_DC_FLUSH_ALL); 3440 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3441 RADEON_RB2D_DC_BUSY) { 3442 i++; 3443 } 3444 } 3445 #ifdef DIAGNOSTIC 3446 if (i > RADEON_TIMEOUT) 3447 printf("%s: engine flush timed out!\n", XNAME(sc)); 3448 #endif 3449 } 3450 3451 static inline void 3452 radeonfb_unclip(struct radeonfb_softc *sc) 3453 { 3454 3455 radeonfb_wait_fifo(sc, 2); 3456 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3457 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3458 } 3459 3460 static void 3461 radeonfb_engine_init(struct radeonfb_display *dp) 3462 { 3463 struct radeonfb_softc *sc = dp->rd_softc; 3464 uint32_t pitch; 3465 3466 /* no 3D */ 3467 PUT32(sc, RADEON_RB3D_CNTL, 0); 3468 3469 radeonfb_engine_reset(sc); 3470 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3471 3472 radeonfb_wait_fifo(sc, 1); 3473 if (!IS_R300(sc)) 3474 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3475 3476 radeonfb_wait_fifo(sc, 3); 3477 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3478 (pitch << 22) | (sc->sc_aperbase >> 10)); 3479 3480 3481 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3482 (pitch << 22) | (sc->sc_aperbase >> 10)); 3483 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3484 (pitch << 22) | (sc->sc_aperbase >> 10)); 3485 3486 (void)GET32(sc, RADEON_DP_DATATYPE); 3487 3488 /* default scissors -- no clipping */ 3489 radeonfb_wait_fifo(sc, 1); 3490 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3491 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3492 3493 radeonfb_wait_fifo(sc, 1); 3494 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3495 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3496 RADEON_GMC_CLR_CMP_CNTL_DIS | 3497 RADEON_GMC_BRUSH_SOLID_COLOR | 3498 RADEON_GMC_SRC_DATATYPE_COLOR); 3499 3500 radeonfb_wait_fifo(sc, 10); 3501 PUT32(sc, RADEON_DST_LINE_START, 0); 3502 PUT32(sc, RADEON_DST_LINE_END, 0); 3503 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3504 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3505 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3506 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3507 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3508 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3509 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3510 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3511 radeonfb_engine_idle(sc); 3512 } 3513 3514 static void 3515 radeonfb_engine_reset(struct radeonfb_softc *sc) 3516 { 3517 uint32_t hpc, rbbm, mclkcntl, clkindex; 3518 3519 radeonfb_engine_flush(sc); 3520 3521 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3522 if (HAS_R300CG(sc)) 3523 radeonfb_r300cg_workaround(sc); 3524 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3525 3526 /* 3527 * According to comments in XFree code, resetting the HDP via 3528 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3529 * So we use HOST_PATH_CNTL instead. 3530 */ 3531 3532 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3533 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3534 if (IS_R300(sc)) { 3535 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3536 RADEON_SOFT_RESET_CP | 3537 RADEON_SOFT_RESET_HI | 3538 RADEON_SOFT_RESET_E2); 3539 GET32(sc, RADEON_RBBM_SOFT_RESET); 3540 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3541 /* 3542 * XXX: this bit is not defined in any ATI docs I have, 3543 * nor in the XFree code, but XFree does it. Why? 3544 */ 3545 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3546 } else { 3547 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3548 RADEON_SOFT_RESET_CP | 3549 RADEON_SOFT_RESET_SE | 3550 RADEON_SOFT_RESET_RE | 3551 RADEON_SOFT_RESET_PP | 3552 RADEON_SOFT_RESET_E2 | 3553 RADEON_SOFT_RESET_RB); 3554 GET32(sc, RADEON_RBBM_SOFT_RESET); 3555 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3556 ~(RADEON_SOFT_RESET_CP | 3557 RADEON_SOFT_RESET_SE | 3558 RADEON_SOFT_RESET_RE | 3559 RADEON_SOFT_RESET_PP | 3560 RADEON_SOFT_RESET_E2 | 3561 RADEON_SOFT_RESET_RB)); 3562 GET32(sc, RADEON_RBBM_SOFT_RESET); 3563 } 3564 3565 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3566 GET32(sc, RADEON_HOST_PATH_CNTL); 3567 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3568 3569 if (IS_R300(sc)) 3570 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3571 3572 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3573 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3574 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3575 3576 if (HAS_R300CG(sc)) 3577 radeonfb_r300cg_workaround(sc); 3578 } 3579 3580 static int 3581 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3582 { 3583 int x, y; 3584 3585 x = pos->x; 3586 y = pos->y; 3587 3588 /* 3589 * This doesn't let a cursor move off the screen. I'm not 3590 * sure if this will have negative effects for e.g. Xinerama. 3591 * I'd guess Xinerama handles it by changing the cursor shape, 3592 * but that needs verification. 3593 */ 3594 if (x >= dp->rd_virtx) 3595 x = dp->rd_virtx - 1; 3596 if (x < 0) 3597 x = 0; 3598 if (y >= dp->rd_virty) 3599 y = dp->rd_virty - 1; 3600 if (y < 0) 3601 y = 0; 3602 3603 dp->rd_cursor.rc_pos.x = x; 3604 dp->rd_cursor.rc_pos.y = y; 3605 3606 radeonfb_cursor_position(dp); 3607 return 0; 3608 } 3609 3610 static int 3611 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3612 { 3613 unsigned flags; 3614 3615 uint8_t r[2], g[2], b[2]; 3616 unsigned index, count; 3617 int i, err; 3618 int pitch, size; 3619 struct radeonfb_cursor nc; 3620 3621 flags = wc->which; 3622 3623 /* copy old values */ 3624 nc = dp->rd_cursor; 3625 3626 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3627 index = wc->cmap.index; 3628 count = wc->cmap.count; 3629 3630 if (index >= 2 || count > 2 - index) 3631 return EINVAL; 3632 3633 err = copyin(wc->cmap.red, &r[index], count); 3634 if (err) 3635 return err; 3636 err = copyin(wc->cmap.green, &g[index], count); 3637 if (err) 3638 return err; 3639 err = copyin(wc->cmap.blue, &b[index], count); 3640 if (err) 3641 return err; 3642 3643 for (i = index; i < index + count; i++) { 3644 nc.rc_cmap[i] = 3645 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3646 } 3647 } 3648 3649 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3650 if ((wc->size.x > RADEON_CURSORMAXX) || 3651 (wc->size.y > RADEON_CURSORMAXY)) 3652 return EINVAL; 3653 3654 /* figure bytes per line */ 3655 pitch = (wc->size.x + 7) / 8; 3656 size = pitch * wc->size.y; 3657 3658 /* clear the old cursor and mask */ 3659 memset(nc.rc_image, 0, 512); 3660 memset(nc.rc_mask, 0, 512); 3661 3662 nc.rc_size = wc->size; 3663 3664 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3665 return err; 3666 3667 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3668 return err; 3669 } 3670 3671 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3672 nc.rc_hot = wc->hot; 3673 if (nc.rc_hot.x >= nc.rc_size.x) 3674 nc.rc_hot.x = nc.rc_size.x - 1; 3675 if (nc.rc_hot.y >= nc.rc_size.y) 3676 nc.rc_hot.y = nc.rc_size.y - 1; 3677 } 3678 3679 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3680 nc.rc_pos = wc->pos; 3681 if (nc.rc_pos.x >= dp->rd_virtx) 3682 nc.rc_pos.x = dp->rd_virtx - 1; 3683 #if 0 3684 if (nc.rc_pos.x < 0) 3685 nc.rc_pos.x = 0; 3686 #endif 3687 if (nc.rc_pos.y >= dp->rd_virty) 3688 nc.rc_pos.y = dp->rd_virty - 1; 3689 #if 0 3690 if (nc.rc_pos.y < 0) 3691 nc.rc_pos.y = 0; 3692 #endif 3693 } 3694 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3695 nc.rc_visible = wc->enable; 3696 } 3697 3698 dp->rd_cursor = nc; 3699 radeonfb_cursor_update(dp, wc->which); 3700 3701 return 0; 3702 } 3703 3704 static uint8_t 3705 radeonfb_backwards(uint8_t d) 3706 { 3707 uint8_t l; 3708 3709 l = d << 7; 3710 l |= ((d & 0x02) << 5); 3711 l |= ((d & 0x04) << 3); 3712 l |= ((d & 0x08) << 1); 3713 l |= ((d & 0x10) >> 1); 3714 l |= ((d & 0x20) >> 3); 3715 l |= ((d & 0x40) >> 5); 3716 l |= ((d & 0x80) >> 7); 3717 return l; 3718 } 3719 3720 /* 3721 * Change the cursor shape. Call this with the cursor locked to avoid 3722 * flickering/tearing. 3723 */ 3724 static void 3725 radeonfb_cursor_shape(struct radeonfb_display *dp) 3726 { 3727 uint8_t and[512], xor[512]; 3728 int i, j, src, dst /* , pitch */; 3729 const uint8_t *msk = dp->rd_cursor.rc_mask; 3730 const uint8_t *img = dp->rd_cursor.rc_image; 3731 3732 /* 3733 * Radeon cursor data interleaves one line of AND data followed 3734 * by a line of XOR data. (Each line corresponds to a whole hardware 3735 * pitch - i.e. 64 pixels or 8 bytes.) 3736 * 3737 * The cursor is displayed using the following table: 3738 * 3739 * AND XOR Result 3740 * ---------------------- 3741 * 0 0 Cursor color 0 3742 * 0 1 Cursor color 1 3743 * 1 0 Transparent 3744 * 1 1 Complement of background 3745 * 3746 * Our masks are therefore different from what we were passed. 3747 * Passed in, I'm assuming the data represents either color 0 or 1, 3748 * and a mask, so the passed in table looks like: 3749 * 3750 * IMG Mask Result 3751 * ----------------------- 3752 * 0 0 Transparent 3753 * 0 1 Cursor color 0 3754 * 1 0 Transparent 3755 * 1 1 Cursor color 1 3756 * 3757 * IF mask bit == 1, AND = 0, XOR = color. 3758 * IF mask bit == 0, AND = 1, XOR = 0. 3759 * 3760 * hence: AND = ~(mask); XOR = color & ~(mask); 3761 */ 3762 3763 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3764 3765 /* start by assuming all bits are transparent */ 3766 memset(and, 0xff, 512); 3767 memset(xor, 0x00, 512); 3768 3769 src = 0; 3770 dst = 0; 3771 for (i = 0; i < 64; i++) { 3772 for (j = 0; j < 64; j += 8) { 3773 if ((i < dp->rd_cursor.rc_size.y) && 3774 (j < dp->rd_cursor.rc_size.x)) { 3775 3776 /* take care to leave odd bits alone */ 3777 and[dst] &= ~(msk[src]); 3778 xor[dst] = img[src] & msk[src]; 3779 src++; 3780 } 3781 dst++; 3782 } 3783 } 3784 3785 for (i = 0; i < 512; i++) { 3786 and[i] = radeonfb_backwards(and[i]); 3787 xor[i] = radeonfb_backwards(xor[i]); 3788 } 3789 3790 /* copy the image into place */ 3791 for (i = 0; i < 64; i++) { 3792 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3793 &and[i * 8], 8); 3794 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3795 &xor[i * 8], 8); 3796 } 3797 } 3798 3799 static void 3800 radeonfb_cursor_position(struct radeonfb_display *dp) 3801 { 3802 struct radeonfb_softc *sc = dp->rd_softc; 3803 uint32_t offset, hvoff, hvpos; /* registers */ 3804 uint32_t coff; /* cursor offset */ 3805 int i, x, y, xoff, yoff, crtcoff; 3806 3807 /* 3808 * XXX: this also needs to handle pan/scan 3809 */ 3810 for (i = 0; i < dp->rd_ncrtcs; i++) { 3811 3812 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3813 3814 if (rcp->rc_number) { 3815 offset = RADEON_CUR2_OFFSET; 3816 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3817 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3818 crtcoff = RADEON_CRTC2_OFFSET; 3819 } else { 3820 offset = RADEON_CUR_OFFSET; 3821 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3822 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3823 crtcoff = RADEON_CRTC_OFFSET; 3824 } 3825 3826 x = dp->rd_cursor.rc_pos.x; 3827 y = dp->rd_cursor.rc_pos.y; 3828 3829 while (y < rcp->rc_yoffset) { 3830 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3831 } 3832 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3833 rcp->rc_yoffset += RADEON_PANINCREMENT; 3834 } 3835 while (x < rcp->rc_xoffset) { 3836 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3837 } 3838 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3839 rcp->rc_xoffset += RADEON_PANINCREMENT; 3840 } 3841 3842 /* adjust for the cursor's hotspot */ 3843 x -= dp->rd_cursor.rc_hot.x; 3844 y -= dp->rd_cursor.rc_hot.y; 3845 xoff = yoff = 0; 3846 3847 if (x >= dp->rd_virtx) 3848 x = dp->rd_virtx - 1; 3849 if (y >= dp->rd_virty) 3850 y = dp->rd_virty - 1; 3851 3852 /* now adjust cursor so it is relative to viewport */ 3853 x -= rcp->rc_xoffset; 3854 y -= rcp->rc_yoffset; 3855 3856 /* 3857 * no need to check for fall off, because we should 3858 * never move off the screen entirely! 3859 */ 3860 coff = 0; 3861 if (x < 0) { 3862 xoff = -x; 3863 x = 0; 3864 } 3865 if (y < 0) { 3866 yoff = -y; 3867 y = 0; 3868 coff = (yoff * 2) * 8; 3869 } 3870 3871 /* pan the display */ 3872 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3873 rcp->rc_xoffset); 3874 3875 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3876 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3877 /* NB: this unlocks the cursor */ 3878 PUT32(sc, hvpos, (x << 16) | y); 3879 } 3880 } 3881 3882 static void 3883 radeonfb_cursor_visible(struct radeonfb_display *dp) 3884 { 3885 int i; 3886 uint32_t gencntl, bit; 3887 3888 for (i = 0; i < dp->rd_ncrtcs; i++) { 3889 if (dp->rd_crtcs[i].rc_number) { 3890 gencntl = RADEON_CRTC2_GEN_CNTL; 3891 bit = RADEON_CRTC2_CUR_EN; 3892 } else { 3893 gencntl = RADEON_CRTC_GEN_CNTL; 3894 bit = RADEON_CRTC_CUR_EN; 3895 } 3896 3897 if (dp->rd_cursor.rc_visible) 3898 SET32(dp->rd_softc, gencntl, bit); 3899 else 3900 CLR32(dp->rd_softc, gencntl, bit); 3901 } 3902 } 3903 3904 static void 3905 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3906 { 3907 int i; 3908 uint32_t c0reg, c1reg; 3909 struct radeonfb_softc *sc = dp->rd_softc; 3910 3911 for (i = 0; i < dp->rd_ncrtcs; i++) { 3912 if (dp->rd_crtcs[i].rc_number) { 3913 c0reg = RADEON_CUR2_CLR0; 3914 c1reg = RADEON_CUR2_CLR1; 3915 } else { 3916 c0reg = RADEON_CUR_CLR0; 3917 c1reg = RADEON_CUR_CLR1; 3918 } 3919 3920 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3921 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 3922 } 3923 } 3924 3925 static void 3926 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 3927 { 3928 struct radeonfb_softc *sc; 3929 int i; 3930 3931 sc = dp->rd_softc; 3932 for (i = 0; i < dp->rd_ncrtcs; i++) { 3933 if (dp->rd_crtcs[i].rc_number) { 3934 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 3935 } else { 3936 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 3937 } 3938 } 3939 3940 if (which & WSDISPLAY_CURSOR_DOCMAP) 3941 radeonfb_cursor_cmap(dp); 3942 3943 if (which & WSDISPLAY_CURSOR_DOSHAPE) 3944 radeonfb_cursor_shape(dp); 3945 3946 if (which & WSDISPLAY_CURSOR_DOCUR) 3947 radeonfb_cursor_visible(dp); 3948 3949 /* this one is unconditional, because it updates other stuff */ 3950 radeonfb_cursor_position(dp); 3951 } 3952 3953 static struct videomode * 3954 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 3955 { 3956 int r1, r2; 3957 3958 /* otherwise pick the higher refresh rate */ 3959 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 3960 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 3961 3962 return (r1 < r2 ? m2 : m1); 3963 } 3964 3965 static const struct videomode * 3966 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 3967 int x, int y) 3968 { 3969 struct edid_info *ep = &rp->rp_edid; 3970 struct videomode *vmp = NULL; 3971 int i; 3972 3973 if (!rp->rp_edid_valid) { 3974 /* fallback to safe mode */ 3975 return radeonfb_modelookup(sc->sc_defaultmode); 3976 } 3977 3978 /* always choose the preferred mode first! */ 3979 if (ep->edid_preferred_mode) { 3980 3981 /* XXX: add auto-stretching support for native mode */ 3982 3983 /* this may want panning to occur, btw */ 3984 if ((ep->edid_preferred_mode->hdisplay <= x) && 3985 (ep->edid_preferred_mode->vdisplay <= y)) 3986 return ep->edid_preferred_mode; 3987 } 3988 3989 for (i = 0; i < ep->edid_nmodes; i++) { 3990 /* 3991 * We elect to pick a resolution that is too large for 3992 * the monitor than one that is too small. This means 3993 * that we will prefer to pan rather than to try to 3994 * center a smaller display on a larger screen. In 3995 * practice, this shouldn't matter because if a 3996 * monitor can support a larger resolution, it can 3997 * probably also support the smaller. A specific 3998 * exception is fixed format panels, but hopefully 3999 * they are properly dealt with by the "autostretch" 4000 * logic above. 4001 */ 4002 if ((ep->edid_modes[i].hdisplay > x) || 4003 (ep->edid_modes[i].vdisplay > y)) { 4004 continue; 4005 } 4006 4007 /* 4008 * at this point, the display mode is no larger than 4009 * what we've requested. 4010 */ 4011 if (vmp == NULL) 4012 vmp = &ep->edid_modes[i]; 4013 4014 /* eliminate smaller modes */ 4015 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4016 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4017 continue; 4018 4019 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4020 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4021 vmp = &ep->edid_modes[i]; 4022 continue; 4023 } 4024 4025 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4026 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4027 4028 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4029 } 4030 4031 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4032 } 4033 4034 static int 4035 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4036 { 4037 int i; 4038 4039 for (i = 0; i < nlist; i++) { 4040 if ((x == list[i].hdisplay) && 4041 (y == list[i].vdisplay)) { 4042 return 1; 4043 } 4044 } 4045 return 0; 4046 } 4047 4048 static void 4049 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4050 int pan) 4051 { 4052 struct radeonfb_port *rp; 4053 struct edid_info *ep; 4054 int i, j; 4055 4056 *x = 0; 4057 *y = 0; 4058 4059 if (pan) { 4060 for (i = 0; i < dp->rd_ncrtcs; i++) { 4061 rp = dp->rd_crtcs[i].rc_port; 4062 ep = &rp->rp_edid; 4063 if (!rp->rp_edid_valid) { 4064 /* monitor not present */ 4065 continue; 4066 } 4067 4068 /* 4069 * For now we are ignoring "conflict" that 4070 * could occur when mixing some modes like 4071 * 1280x1024 and 1400x800. It isn't clear 4072 * which is better, so the first one wins. 4073 */ 4074 for (j = 0; j < ep->edid_nmodes; j++) { 4075 /* 4076 * ignore resolutions that are too big for 4077 * the radeon 4078 */ 4079 if (ep->edid_modes[j].hdisplay > 4080 dp->rd_softc->sc_maxx) 4081 continue; 4082 if (ep->edid_modes[j].vdisplay > 4083 dp->rd_softc->sc_maxy) 4084 continue; 4085 4086 /* 4087 * pick largest resolution, the 4088 * smaller monitor will pan 4089 */ 4090 if ((ep->edid_modes[j].hdisplay >= *x) && 4091 (ep->edid_modes[j].vdisplay >= *y)) { 4092 *x = ep->edid_modes[j].hdisplay; 4093 *y = ep->edid_modes[j].vdisplay; 4094 } 4095 } 4096 } 4097 4098 } else { 4099 struct videomode modes[64]; 4100 int nmodes = 0; 4101 int valid = 0; 4102 4103 for (i = 0; i < dp->rd_ncrtcs; i++) { 4104 /* 4105 * pick the largest resolution in common. 4106 */ 4107 rp = dp->rd_crtcs[i].rc_port; 4108 ep = &rp->rp_edid; 4109 4110 if (!rp->rp_edid_valid) 4111 continue; 4112 4113 if (!valid) { 4114 /* 4115 * Pick the preferred mode for this port 4116 * if available. 4117 */ 4118 if (ep->edid_preferred_mode) { 4119 struct videomode *vmp = 4120 ep->edid_preferred_mode; 4121 4122 if ((vmp->hdisplay <= 4123 dp->rd_softc->sc_maxx) && 4124 (vmp->vdisplay <= 4125 dp->rd_softc->sc_maxy)) 4126 modes[nmodes++] = *vmp; 4127 } else { 4128 4129 /* initialize starting list */ 4130 for (j = 0; j < ep->edid_nmodes; j++) { 4131 /* 4132 * ignore resolutions that are 4133 * too big for the radeon 4134 */ 4135 if (ep->edid_modes[j].hdisplay > 4136 dp->rd_softc->sc_maxx) 4137 continue; 4138 if (ep->edid_modes[j].vdisplay > 4139 dp->rd_softc->sc_maxy) 4140 continue; 4141 4142 modes[nmodes] = 4143 ep->edid_modes[j]; 4144 nmodes++; 4145 } 4146 } 4147 valid = 1; 4148 } else { 4149 /* merge into preexisting list */ 4150 for (j = 0; j < nmodes; j++) { 4151 if (!radeonfb_hasres(ep->edid_modes, 4152 ep->edid_nmodes, 4153 modes[j].hdisplay, 4154 modes[j].vdisplay)) { 4155 modes[j] = modes[nmodes]; 4156 j--; 4157 nmodes--; 4158 } 4159 } 4160 } 4161 } 4162 4163 /* now we have to pick from the merged list */ 4164 for (i = 0; i < nmodes; i++) { 4165 if ((modes[i].hdisplay >= *x) && 4166 (modes[i].vdisplay >= *y)) { 4167 *x = modes[i].hdisplay; 4168 *y = modes[i].vdisplay; 4169 } 4170 } 4171 } 4172 4173 if ((*x == 0) || (*y == 0)) { 4174 /* fallback to safe mode */ 4175 *x = 640; 4176 *y = 480; 4177 } 4178 } 4179 4180 /* 4181 * backlight levels are linear on: 4182 * - RV200, RV250, RV280, RV350 4183 * - but NOT on PowerBook4,3 6,3 6,5 4184 * according to Linux' radeonfb 4185 */ 4186 4187 /* Get the current backlight level for the display. */ 4188 4189 static int 4190 radeonfb_get_backlight(struct radeonfb_display *dp) 4191 { 4192 int s; 4193 uint32_t level; 4194 4195 s = spltty(); 4196 4197 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4198 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4199 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4200 4201 /* 4202 * On some chips, we should negate the backlight level. 4203 * XXX Find out on which chips. 4204 */ 4205 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4206 level = RADEONFB_BACKLIGHT_MAX - level; 4207 4208 splx(s); 4209 4210 return level; 4211 } 4212 4213 /* Set the backlight to the given level for the display. */ 4214 static void 4215 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4216 { 4217 if (dp->rd_bl_on == on) 4218 return; 4219 dp->rd_bl_on = on; 4220 radeonfb_set_backlight(dp, dp->rd_bl_level); 4221 } 4222 4223 static int 4224 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4225 { 4226 struct radeonfb_softc *sc = dp->rd_softc; 4227 int rlevel, s; 4228 uint32_t lvds; 4229 4230 if(!sc->sc_mapped) 4231 return 0; 4232 4233 s = spltty(); 4234 4235 dp->rd_bl_level = level; 4236 if (dp->rd_bl_on == 0) 4237 level = 0; 4238 4239 if (level < 0) 4240 level = 0; 4241 else if (level >= RADEONFB_BACKLIGHT_MAX) 4242 level = RADEONFB_BACKLIGHT_MAX; 4243 4244 /* On some chips, we should negate the backlight level. */ 4245 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4246 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4247 } else 4248 rlevel = level; 4249 4250 callout_stop(&dp->rd_bl_lvds_co); 4251 radeonfb_engine_idle(sc); 4252 4253 /* 4254 * Turn off the display if the backlight is set to 0, since the 4255 * display is useless without backlight anyway. 4256 */ 4257 if (level == 0) 4258 radeonfb_blank(dp, 1); 4259 else if (radeonfb_get_backlight(dp) == 0) 4260 radeonfb_blank(dp, 0); 4261 4262 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4263 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4264 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4265 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4266 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4267 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4268 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4269 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4270 lvds |= RADEON_LVDS_ON; 4271 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4272 } else { 4273 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4274 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4275 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4276 } 4277 4278 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4279 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4280 /* XXX What is the correct delay? */ 4281 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4282 4283 splx(s); 4284 4285 return 0; 4286 } 4287 4288 /* 4289 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4290 * Set the delayed bits in the register, and clear the stored delayed 4291 * value. 4292 */ 4293 4294 static void radeonfb_lvds_callout(void *arg) 4295 { 4296 struct radeonfb_display *dp = arg; 4297 int s; 4298 4299 s = splhigh(); 4300 4301 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4302 dp->rd_bl_lvds_val); 4303 dp->rd_bl_lvds_val = 0; 4304 4305 splx(s); 4306 } 4307 4308 static void 4309 radeonfb_brightness_up(device_t dev) 4310 { 4311 struct radeonfb_softc *sc = device_private(dev); 4312 struct radeonfb_display *dp = &sc->sc_displays[0]; 4313 int level; 4314 4315 /* we assume the main display is the first one - need a better way */ 4316 if (sc->sc_ndisplays < 1) return; 4317 /* make sure pushing the hotkeys always has an effect */ 4318 dp->rd_bl_on = 1; 4319 level = dp->rd_bl_level; 4320 level = min(RADEONFB_BACKLIGHT_MAX, level + 5); 4321 radeonfb_set_backlight(dp, level); 4322 } 4323 4324 static void 4325 radeonfb_brightness_down(device_t dev) 4326 { 4327 struct radeonfb_softc *sc = device_private(dev); 4328 struct radeonfb_display *dp = &sc->sc_displays[0]; 4329 int level; 4330 4331 /* we assume the main display is the first one - need a better way */ 4332 if (sc->sc_ndisplays < 1) return; 4333 /* make sure pushing the hotkeys always has an effect */ 4334 dp->rd_bl_on = 1; 4335 level = dp->rd_bl_level; 4336 level = max(0, level - 5); 4337 radeonfb_set_backlight(dp, level); 4338 } 4339
Indexes created Fri Sep 26 20:09:58 GMT 2025