radeonfb.c revision 1.99.2.3
1 /* $NetBSD: radeonfb.c,v 1.99.2.3 2020/04/13 08:04:45 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2006 Itronix Inc. 5 * All rights reserved. 6 * 7 * Written by Garrett D'Amore for Itronix Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of Itronix Inc. may not be used to endorse 18 * or promote products derived from this software without specific 19 * prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY ITRONIX INC. ``AS IS'' AND ANY EXPRESS 22 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL ITRONIX INC. BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 27 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 30 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 31 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * ATI Technologies Inc. ("ATI") has not assisted in the creation of, and 36 * does not endorse, this software. ATI will not be responsible or liable 37 * for any actual or alleged damage or loss caused by or in connection with 38 * the use of or reliance on this software. 39 */ 40 41 /* 42 * Portions of this code were taken from XFree86's Radeon driver, which bears 43 * this notice: 44 * 45 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 46 * VA Linux Systems Inc., Fremont, California. 47 * 48 * All Rights Reserved. 49 * 50 * Permission is hereby granted, free of charge, to any person obtaining 51 * a copy of this software and associated documentation files (the 52 * "Software"), to deal in the Software without restriction, including 53 * without limitation on the rights to use, copy, modify, merge, 54 * publish, distribute, sublicense, and/or sell copies of the Software, 55 * and to permit persons to whom the Software is furnished to do so, 56 * subject to the following conditions: 57 * 58 * The above copyright notice and this permission notice (including the 59 * next paragraph) shall be included in all copies or substantial 60 * portions of the Software. 61 * 62 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 63 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 64 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 65 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 66 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 67 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 68 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 69 * DEALINGS IN THE SOFTWARE. 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: radeonfb.c,v 1.99.2.3 2020/04/13 08:04:45 martin Exp $"); 74 75 #include <sys/param.h> 76 #include <sys/systm.h> 77 #include <sys/device.h> 78 #include <sys/malloc.h> 79 #include <sys/bus.h> 80 #include <sys/kernel.h> 81 #include <sys/lwp.h> 82 #include <sys/kauth.h> 83 84 #include <dev/wscons/wsdisplayvar.h> 85 #include <dev/wscons/wsconsio.h> 86 #include <dev/wsfont/wsfont.h> 87 #include <dev/rasops/rasops.h> 88 #include <dev/videomode/videomode.h> 89 #include <dev/videomode/edidvar.h> 90 #include <dev/wscons/wsdisplay_vconsvar.h> 91 #include <dev/pci/wsdisplay_pci.h> 92 #include <dev/wscons/wsdisplay_glyphcachevar.h> 93 94 #include <dev/pci/pcidevs.h> 95 #include <dev/pci/pcireg.h> 96 #include <dev/pci/pcivar.h> 97 #include <dev/pci/pciio.h> 98 #include <dev/pci/radeonfbreg.h> 99 #include <dev/pci/radeonfbvar.h> 100 #include "opt_radeonfb.h" 101 #include "opt_vcons.h" 102 103 #ifdef RADEONFB_DEPTH_32 104 #define RADEONFB_DEFAULT_DEPTH 32 105 #else 106 #define RADEONFB_DEFAULT_DEPTH 8 107 #endif 108 109 static int radeonfb_match(device_t, cfdata_t, void *); 110 static void radeonfb_attach(device_t, device_t, void *); 111 static int radeonfb_ioctl(void *, void *, unsigned long, void *, int, 112 struct lwp *); 113 static paddr_t radeonfb_mmap(void *, void *, off_t, int); 114 static int radeonfb_scratch_test(struct radeonfb_softc *, int, uint32_t); 115 static void radeonfb_loadbios(struct radeonfb_softc *, 116 const struct pci_attach_args *); 117 118 static uintmax_t radeonfb_getprop_num(struct radeonfb_softc *, const char *, 119 uintmax_t); 120 static int radeonfb_getclocks(struct radeonfb_softc *); 121 static int radeonfb_gettmds(struct radeonfb_softc *); 122 static int radeonfb_calc_dividers(struct radeonfb_softc *, uint32_t, 123 uint32_t *, uint32_t *, int); 124 /* flags for radeonfb_calc_dividers */ 125 #define NO_ODD_FBDIV 1 126 127 static int radeonfb_getconnectors(struct radeonfb_softc *); 128 static const struct videomode *radeonfb_modelookup(const char *); 129 static void radeonfb_init_screen(void *, struct vcons_screen *, int, long *); 130 static void radeonfb_pllwriteupdate(struct radeonfb_softc *, int); 131 static void radeonfb_pllwaitatomicread(struct radeonfb_softc *, int); 132 static void radeonfb_program_vclk(struct radeonfb_softc *, int, int, int); 133 static void radeonfb_modeswitch(struct radeonfb_display *); 134 static void radeonfb_setcrtc(struct radeonfb_display *, int); 135 static void radeonfb_init_misc(struct radeonfb_softc *); 136 static void radeonfb_set_fbloc(struct radeonfb_softc *); 137 static void radeonfb_init_palette(struct radeonfb_display *); 138 static void radeonfb_r300cg_workaround(struct radeonfb_softc *); 139 140 static int radeonfb_isblank(struct radeonfb_display *); 141 static void radeonfb_blank(struct radeonfb_display *, int); 142 static int radeonfb_set_cursor(struct radeonfb_display *, 143 struct wsdisplay_cursor *); 144 static int radeonfb_set_curpos(struct radeonfb_display *, 145 struct wsdisplay_curpos *); 146 static void radeonfb_putpal(struct radeonfb_display *, int, int, int, int); 147 static int radeonfb_putcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 148 static int radeonfb_getcmap(struct radeonfb_display *, struct wsdisplay_cmap *); 149 150 /* acceleration support */ 151 static void radeonfb_rectfill(struct radeonfb_display *, int dstx, int dsty, 152 int width, int height, uint32_t color); 153 static void radeonfb_rectfill_a(void *, int, int, int, int, long); 154 static void radeonfb_bitblt(void *, int srcx, int srcy, 155 int dstx, int dsty, int width, int height, int rop); 156 157 /* hw cursor support */ 158 static void radeonfb_cursor_cmap(struct radeonfb_display *); 159 static void radeonfb_cursor_shape(struct radeonfb_display *); 160 static void radeonfb_cursor_position(struct radeonfb_display *); 161 static void radeonfb_cursor_visible(struct radeonfb_display *); 162 static void radeonfb_cursor_update(struct radeonfb_display *, unsigned); 163 164 static inline void radeonfb_wait_fifo(struct radeonfb_softc *, int); 165 static void radeonfb_engine_idle(struct radeonfb_softc *); 166 static void radeonfb_engine_flush(struct radeonfb_softc *); 167 static void radeonfb_engine_reset(struct radeonfb_softc *); 168 static void radeonfb_engine_init(struct radeonfb_display *); 169 static inline void radeonfb_unclip(struct radeonfb_softc *) __unused; 170 171 static void radeonfb_eraserows(void *, int, int, long); 172 static void radeonfb_erasecols(void *, int, int, int, long); 173 static void radeonfb_copyrows(void *, int, int, int); 174 static void radeonfb_copycols(void *, int, int, int, int); 175 static void radeonfb_cursor(void *, int, int, int); 176 static void radeonfb_putchar(void *, int, int, unsigned, long); 177 static void radeonfb_putchar_aa32(void *, int, int, unsigned, long); 178 static void radeonfb_putchar_aa8(void *, int, int, unsigned, long); 179 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 180 static void radeonfb_putchar_wrapper(void *, int, int, unsigned, long); 181 #endif 182 183 static int radeonfb_set_backlight(struct radeonfb_display *, int); 184 static int radeonfb_get_backlight(struct radeonfb_display *); 185 static void radeonfb_switch_backlight(struct radeonfb_display *, int); 186 static void radeonfb_lvds_callout(void *); 187 188 static void radeonfb_brightness_up(device_t); 189 static void radeonfb_brightness_down(device_t); 190 191 static struct videomode *radeonfb_best_refresh(struct videomode *, 192 struct videomode *); 193 static void radeonfb_pickres(struct radeonfb_display *, uint16_t *, 194 uint16_t *, int); 195 static const struct videomode *radeonfb_port_mode(struct radeonfb_softc *, 196 struct radeonfb_port *, int, int); 197 198 static int radeonfb_drm_print(void *, const char *); 199 200 #ifdef RADEONFB_DEBUG 201 int radeon_debug = 1; 202 #define DPRINTF(x) \ 203 if (radeon_debug) printf x 204 #define PRINTREG(r) DPRINTF((#r " = %08x\n", GET32(sc, r))) 205 #define PRINTPLL(r) DPRINTF((#r " = %08x\n", GETPLL(sc, r))) 206 #else 207 #define DPRINTF(x) 208 #define PRINTREG(r) 209 #define PRINTPLL(r) 210 #endif 211 212 #define ROUNDUP(x,y) (((x) + ((y) - 1)) & ~((y) - 1)) 213 214 #ifndef RADEON_DEFAULT_MODE 215 /* any reasonably modern display should handle this */ 216 #define RADEON_DEFAULT_MODE "1024x768x60" 217 #endif 218 219 extern const u_char rasops_cmap[768]; 220 221 const char *radeonfb_default_mode = RADEON_DEFAULT_MODE; 222 223 static struct { 224 int size; /* minimum memory size (MB) */ 225 int maxx; /* maximum x dimension */ 226 int maxy; /* maximum y dimension */ 227 int maxbpp; /* maximum bpp */ 228 int maxdisp; /* maximum logical display count */ 229 } radeonfb_limits[] = { 230 { 32, 2048, 1536, 32, 2 }, 231 { 16, 1600, 1200, 32, 2 }, 232 { 8, 1600, 1200, 32, 1 }, 233 { 0, 0, 0, 0, 0 }, 234 }; 235 236 static struct wsscreen_descr radeonfb_stdscreen = { 237 "fb", /* name */ 238 0, 0, /* ncols, nrows */ 239 NULL, /* textops */ 240 8, 16, /* fontwidth, fontheight */ 241 WSSCREEN_WSCOLORS | WSSCREEN_UNDERLINE | WSSCREEN_RESIZE, /* capabilities */ 242 0, /* modecookie */ 243 }; 244 245 struct wsdisplay_accessops radeonfb_accessops = { 246 radeonfb_ioctl, 247 radeonfb_mmap, 248 NULL, /* vcons_alloc_screen */ 249 NULL, /* vcons_free_screen */ 250 NULL, /* vcons_show_screen */ 251 NULL, /* load_font */ 252 NULL, /* pollc */ 253 NULL, /* scroll */ 254 }; 255 256 static struct { 257 uint16_t devid; 258 uint16_t family; 259 uint16_t flags; 260 } radeonfb_devices[] = 261 { 262 /* R100 family */ 263 { PCI_PRODUCT_ATI_RADEON_R100_QD, RADEON_R100, 0 }, 264 { PCI_PRODUCT_ATI_RADEON_R100_QE, RADEON_R100, 0 }, 265 { PCI_PRODUCT_ATI_RADEON_R100_QF, RADEON_R100, 0 }, 266 { PCI_PRODUCT_ATI_RADEON_R100_QG, RADEON_R100, 0 }, 267 268 /* RV100 family */ 269 { PCI_PRODUCT_ATI_RADEON_RV100_LY, RADEON_RV100, RFB_MOB }, 270 { PCI_PRODUCT_ATI_RADEON_RV100_LZ, RADEON_RV100, RFB_MOB }, 271 { PCI_PRODUCT_ATI_RADEON_RV100_QY, RADEON_RV100, 0 }, 272 { PCI_PRODUCT_ATI_RADEON_RV100_QZ, RADEON_RV100, 0 }, 273 274 /* RS100 family */ 275 { PCI_PRODUCT_ATI_RADEON_RS100_4136, RADEON_RS100, 0 }, 276 { PCI_PRODUCT_ATI_RADEON_RS100_4336, RADEON_RS100, RFB_MOB }, 277 278 /* RS200/RS250 family */ 279 { PCI_PRODUCT_ATI_RADEON_RS200_4337, RADEON_RS200, RFB_MOB }, 280 { PCI_PRODUCT_ATI_RADEON_RS200_A7, RADEON_RS200, 0 }, 281 { PCI_PRODUCT_ATI_RADEON_RS250_B7, RADEON_RS200, RFB_MOB }, 282 { PCI_PRODUCT_ATI_RADEON_RS250_D7, RADEON_RS200, 0 }, 283 284 /* R200 family */ 285 /* add more R200 products? , 5148 */ 286 { PCI_PRODUCT_ATI_RADEON_R200_BB, RADEON_R200, 0 }, 287 { PCI_PRODUCT_ATI_RADEON_R200_BC, RADEON_R200, 0 }, 288 { PCI_PRODUCT_ATI_RADEON_R200_QH, RADEON_R200, 0 }, 289 { PCI_PRODUCT_ATI_RADEON_R200_QL, RADEON_R200, 0 }, 290 { PCI_PRODUCT_ATI_RADEON_R200_QM, RADEON_R200, 0 }, 291 292 /* RV200 family */ 293 { PCI_PRODUCT_ATI_RADEON_RV200_LW, RADEON_RV200, RFB_MOB }, 294 { PCI_PRODUCT_ATI_RADEON_RV200_LX, RADEON_RV200, RFB_MOB }, 295 { PCI_PRODUCT_ATI_RADEON_RV200_QW, RADEON_RV200, 0 }, 296 { PCI_PRODUCT_ATI_RADEON_RV200_QX, RADEON_RV200, 0 }, 297 298 /* RV250 family */ 299 { PCI_PRODUCT_ATI_RADEON_RV250_4966, RADEON_RV250, 0 }, 300 { PCI_PRODUCT_ATI_RADEON_RV250_4967, RADEON_RV250, 0 }, 301 { PCI_PRODUCT_ATI_RADEON_RV250_4C64, RADEON_RV250, RFB_MOB }, 302 { PCI_PRODUCT_ATI_RADEON_RV250_4C66, RADEON_RV250, RFB_MOB }, 303 { PCI_PRODUCT_ATI_RADEON_RV250_4C67, RADEON_RV250, RFB_MOB }, 304 305 /* RS300 family */ 306 { PCI_PRODUCT_ATI_RADEON_RS300_X5, RADEON_RS300, 0 }, 307 { PCI_PRODUCT_ATI_RADEON_RS300_X4, RADEON_RS300, 0 }, 308 { PCI_PRODUCT_ATI_RADEON_RS300_7834, RADEON_RS300, 0 }, 309 { PCI_PRODUCT_ATI_RADEON_RS300_7835, RADEON_RS300, RFB_MOB }, 310 311 /* RV280 family */ 312 { PCI_PRODUCT_ATI_RADEON_RV280_5960, RADEON_RV280, 0 }, 313 { PCI_PRODUCT_ATI_RADEON_RV280_5961, RADEON_RV280, 0 }, 314 { PCI_PRODUCT_ATI_RADEON_RV280_5962, RADEON_RV280, 0 }, 315 { PCI_PRODUCT_ATI_RADEON_RV280_5963, RADEON_RV280, 0 }, 316 { PCI_PRODUCT_ATI_RADEON_RV280_5964, RADEON_RV280, 0 }, 317 { PCI_PRODUCT_ATI_RADEON_RV280_5C61, RADEON_RV280, RFB_MOB }, 318 { PCI_PRODUCT_ATI_RADEON_RV280_5C63, RADEON_RV280, RFB_MOB }, 319 320 /* R300 family */ 321 { PCI_PRODUCT_ATI_RADEON_R300_AD, RADEON_R300, 0 }, 322 { PCI_PRODUCT_ATI_RADEON_R300_AE, RADEON_R300, 0 }, 323 { PCI_PRODUCT_ATI_RADEON_R300_AF, RADEON_R300, 0 }, 324 { PCI_PRODUCT_ATI_RADEON_R300_AG, RADEON_R300, 0 }, 325 { PCI_PRODUCT_ATI_RADEON_R300_ND, RADEON_R300, 0 }, 326 { PCI_PRODUCT_ATI_RADEON_R300_NE, RADEON_R300, 0 }, 327 { PCI_PRODUCT_ATI_RADEON_R300_NF, RADEON_R300, 0 }, 328 { PCI_PRODUCT_ATI_RADEON_R300_NG, RADEON_R300, 0 }, 329 330 /* RV350/RV360 family */ 331 { PCI_PRODUCT_ATI_RADEON_RV350_AP, RADEON_RV350, 0 }, 332 { PCI_PRODUCT_ATI_RADEON_RV350_AQ, RADEON_RV350, 0 }, 333 { PCI_PRODUCT_ATI_RADEON_RV360_AR, RADEON_RV350, 0 }, 334 { PCI_PRODUCT_ATI_RADEON_RV350_AS, RADEON_RV350, 0 }, 335 { PCI_PRODUCT_ATI_RADEON_RV350_AT, RADEON_RV350, 0 }, 336 { PCI_PRODUCT_ATI_RADEON_RV350_AV, RADEON_RV350, 0 }, 337 { PCI_PRODUCT_ATI_RADEON_RV350_NP, RADEON_RV350, RFB_MOB }, 338 { PCI_PRODUCT_ATI_RADEON_RV350_NQ, RADEON_RV350, RFB_MOB }, 339 { PCI_PRODUCT_ATI_RADEON_RV350_NR, RADEON_RV350, RFB_MOB }, 340 { PCI_PRODUCT_ATI_RADEON_RV350_NS, RADEON_RV350, RFB_MOB }, 341 { PCI_PRODUCT_ATI_RADEON_RV350_NT, RADEON_RV350, RFB_MOB }, 342 { PCI_PRODUCT_ATI_RADEON_RV350_NV, RADEON_RV350, RFB_MOB }, 343 344 /* R350/R360 family */ 345 { PCI_PRODUCT_ATI_RADEON_R350_AH, RADEON_R350, 0 }, 346 { PCI_PRODUCT_ATI_RADEON_R350_AI, RADEON_R350, 0 }, 347 { PCI_PRODUCT_ATI_RADEON_R350_AJ, RADEON_R350, 0 }, 348 { PCI_PRODUCT_ATI_RADEON_R350_AK, RADEON_R350, 0 }, 349 { PCI_PRODUCT_ATI_RADEON_R350_NH, RADEON_R350, 0 }, 350 { PCI_PRODUCT_ATI_RADEON_R350_NI, RADEON_R350, 0 }, 351 { PCI_PRODUCT_ATI_RADEON_R350_NK, RADEON_R350, 0 }, 352 { PCI_PRODUCT_ATI_RADEON_R360_NJ, RADEON_R350, 0 }, 353 354 /* RV380/RV370 family */ 355 { PCI_PRODUCT_ATI_RADEON_RV380_3150, RADEON_RV380, RFB_MOB }, 356 { PCI_PRODUCT_ATI_RADEON_RV380_3154, RADEON_RV380, RFB_MOB }, 357 { PCI_PRODUCT_ATI_RADEON_RV380_3E50, RADEON_RV380, 0 }, 358 { PCI_PRODUCT_ATI_RADEON_RV380_3E54, RADEON_RV380, 0 }, 359 { PCI_PRODUCT_ATI_RADEON_RV370_5460, RADEON_RV380, RFB_MOB }, 360 { PCI_PRODUCT_ATI_RADEON_RV370_5464, RADEON_RV380, RFB_MOB }, 361 { PCI_PRODUCT_ATI_RADEON_RV370_5B60, RADEON_RV380, 0 }, 362 { PCI_PRODUCT_ATI_RADEON_RV370_5B63, RADEON_RV380, 0 }, 363 { PCI_PRODUCT_ATI_RADEON_RV370_5B64, RADEON_RV380, 0 }, 364 { PCI_PRODUCT_ATI_RADEON_RV370_5B65, RADEON_RV380, 0 }, 365 366 #if notyet 367 /* R420/R423 family */ 368 { PCI_PRODUCT_ATI_RADEON_R420_JH, RADEON_R420, 0 }, 369 { PCI_PRODUCT_ATI_RADEON_R420_JI, RADEON_R420, 0 }, 370 { PCI_PRODUCT_ATI_RADEON_R420_JJ, RADEON_R420, 0 }, 371 { PCI_PRODUCT_ATI_RADEON_R420_JK, RADEON_R420, 0 }, 372 { PCI_PRODUCT_ATI_RADEON_R420_JL, RADEON_R420, 0 }, 373 { PCI_PRODUCT_ATI_RADEON_R420_JM, RADEON_R420, 0 }, 374 { PCI_PRODUCT_ATI_RADEON_R420_JN, RADEON_R420, RFB_MOB }, 375 { PCI_PRODUCT_ATI_RADEON_R420_JP, RADEON_R420, 0 }, 376 { PCI_PRODUCT_ATI_RADEON_R423_UH, RADEON_R420, 0 }, 377 { PCI_PRODUCT_ATI_RADEON_R423_UI, RADEON_R420, 0 }, 378 { PCI_PRODUCT_ATI_RADEON_R423_UJ, RADEON_R420, 0 }, 379 { PCI_PRODUCT_ATI_RADEON_R423_UK, RADEON_R420, 0 }, 380 { PCI_PRODUCT_ATI_RADEON_R423_UQ, RADEON_R420, 0 }, 381 { PCI_PRODUCT_ATI_RADEON_R423_UR, RADEON_R420, 0 }, 382 { PCI_PRODUCT_ATI_RADEON_R423_UT, RADEON_R420, 0 }, 383 { PCI_PRODUCT_ATI_RADEON_R423_5D57, RADEON_R420, 0 }, 384 { PCI_PRODUCT_ATI_RADEON_R430_554F, RADEON_R420, 0 }, 385 386 /* R5xx family */ 387 { 0x7240, RADEON_R420, 0 }, 388 #endif 389 { 0, 0, 0 } 390 }; 391 392 static struct { 393 int divider; 394 int mask; 395 } radeonfb_dividers[] = { 396 { 16, 5 }, 397 { 12, 7 }, 398 { 8, 3 }, 399 { 6, 6 }, 400 { 4, 2 }, 401 { 3, 4 }, 402 { 2, 1 }, 403 { 1, 0 }, 404 { 0, 0 } 405 }; 406 407 /* 408 * This table taken from X11. 409 */ 410 static const struct { 411 int family; 412 struct radeon_tmds_pll plls[4]; 413 } radeonfb_tmds_pll[] = { 414 { RADEON_R100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 415 { RADEON_RV100, {{12000, 0xa1b}, {-1, 0xa3f}}}, 416 { RADEON_RS100, {{0, 0}}}, 417 { RADEON_RV200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 418 { RADEON_RS200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 419 { RADEON_R200, {{15000, 0xa1b}, {-1, 0xa3f}}}, 420 { RADEON_RV250, {{15500, 0x81b}, {-1, 0x83f}}}, 421 { RADEON_RS300, {{0, 0}}}, 422 { RADEON_RV280, {{13000, 0x400f4}, {15000, 0x400f7}, {-1, 0x40111}}}, 423 { RADEON_R300, {{-1, 0xb01cb}}}, 424 { RADEON_R350, {{-1, 0xb01cb}}}, 425 { RADEON_RV350, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 426 { RADEON_RV380, {{15000, 0xb0155}, {-1, 0xb01cb}}}, 427 { RADEON_R420, {{-1, 0xb01cb}}}, 428 }; 429 430 #define RADEONFB_BACKLIGHT_MAX 255 /* Maximum backlight level. */ 431 432 433 CFATTACH_DECL_NEW(radeonfb, sizeof (struct radeonfb_softc), 434 radeonfb_match, radeonfb_attach, NULL, NULL); 435 436 static int 437 radeonfb_match(device_t parent, cfdata_t match, void *aux) 438 { 439 const struct pci_attach_args *pa = aux; 440 int i; 441 442 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_ATI) 443 return 0; 444 445 for (i = 0; radeonfb_devices[i].devid; i++) { 446 if (PCI_PRODUCT(pa->pa_id) == radeonfb_devices[i].devid) 447 return 100; /* high to defeat VGA/VESA */ 448 } 449 450 return 0; 451 } 452 453 static void 454 radeonfb_attach(device_t parent, device_t dev, void *aux) 455 { 456 struct radeonfb_softc *sc = device_private(dev); 457 const struct pci_attach_args *pa = aux; 458 const char *mptr; 459 bus_size_t bsz; 460 pcireg_t screg; 461 int i, j, fg, bg, ul, flags; 462 uint32_t v; 463 464 sc->sc_dev = dev; 465 sc->sc_id = pa->pa_id; 466 for (i = 0; radeonfb_devices[i].devid; i++) { 467 if (PCI_PRODUCT(sc->sc_id) == radeonfb_devices[i].devid) 468 break; 469 } 470 471 pci_aprint_devinfo(pa, NULL); 472 473 DPRINTF(("%s", prop_dictionary_externalize(device_properties(dev)))); 474 475 KASSERT(radeonfb_devices[i].devid != 0); 476 sc->sc_pt = pa->pa_tag; 477 sc->sc_iot = pa->pa_iot; 478 sc->sc_pc = pa->pa_pc; 479 sc->sc_family = radeonfb_devices[i].family; 480 sc->sc_flags = radeonfb_devices[i].flags; 481 sc->sc_bios = NULL; 482 sc->sc_biossz = 0; 483 484 /* enable memory and IO access */ 485 screg = pci_conf_read(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG); 486 screg |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE; 487 pci_conf_write(sc->sc_pc, sc->sc_pt, PCI_COMMAND_STATUS_REG, screg); 488 489 /* 490 * Some flags are general to entire chip families, and rather 491 * than clutter up the table with them, we go ahead and set 492 * them here. 493 */ 494 switch (sc->sc_family) { 495 case RADEON_RS100: 496 case RADEON_RS200: 497 sc->sc_flags |= RFB_IGP | RFB_RV100; 498 break; 499 500 case RADEON_RV100: 501 case RADEON_RV200: 502 case RADEON_RV250: 503 case RADEON_RV280: 504 sc->sc_flags |= RFB_RV100; 505 break; 506 507 case RADEON_RS300: 508 sc->sc_flags |= RFB_SDAC | RFB_IGP | RFB_RV100; 509 break; 510 511 case RADEON_R300: 512 case RADEON_RV350: 513 case RADEON_R350: 514 case RADEON_RV380: 515 case RADEON_R420: 516 /* newer chips */ 517 sc->sc_flags |= RFB_R300; 518 break; 519 520 case RADEON_R100: 521 sc->sc_flags |= RFB_NCRTC2; 522 break; 523 } 524 525 if ((sc->sc_family == RADEON_RV200) || 526 (sc->sc_family == RADEON_RV250) || 527 (sc->sc_family == RADEON_RV280) || 528 (sc->sc_family == RADEON_RV350)) { 529 bool inverted = 0; 530 /* backlight level is linear */ 531 DPRINTF(("found RV* chip, backlight is supposedly linear\n")); 532 prop_dictionary_get_bool(device_properties(sc->sc_dev), 533 "backlight_level_reverted", &inverted); 534 if (inverted) { 535 DPRINTF(("nope, it's inverted\n")); 536 sc->sc_flags |= RFB_INV_BLIGHT; 537 } 538 } else 539 sc->sc_flags |= RFB_INV_BLIGHT; 540 541 /* 542 * XXX: to support true multihead, this must change. 543 */ 544 sc->sc_ndisplays = 1; 545 546 /* XXX: */ 547 if (!HAS_CRTC2(sc)) { 548 sc->sc_ndisplays = 1; 549 } 550 551 if (pci_mapreg_map(pa, RADEON_MAPREG_MMIO, PCI_MAPREG_TYPE_MEM, 0, 552 &sc->sc_regt, &sc->sc_regh, &sc->sc_regaddr, 553 &sc->sc_regsz) != 0) { 554 aprint_error("%s: unable to map registers!\n", XNAME(sc)); 555 goto error; 556 } 557 558 if (pci_mapreg_info(sc->sc_pc, sc->sc_pt, PCI_MAPREG_ROM, 559 PCI_MAPREG_TYPE_ROM, &sc->sc_romaddr, &sc->sc_romsz, &flags) != 0) 560 { 561 aprint_error("%s: unable to find ROM!\n", XNAME(sc)); 562 goto error; 563 } 564 sc->sc_romt = sc->sc_memt; 565 566 sc->sc_mapped = TRUE; 567 568 /* scratch register test... */ 569 if (radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0x55555555) || 570 radeonfb_scratch_test(sc, RADEON_BIOS_0_SCRATCH, 0xaaaaaaaa)) { 571 aprint_error("%s: scratch register test failed!\n", XNAME(sc)); 572 goto error; 573 } 574 575 PRINTREG(RADEON_CRTC_EXT_CNTL); 576 PRINTREG(RADEON_CRTC_GEN_CNTL); 577 PRINTREG(RADEON_CRTC2_GEN_CNTL); 578 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 579 PRINTREG(RADEON_DAC_CNTL2); 580 PRINTREG(RADEON_BIOS_4_SCRATCH); 581 PRINTREG(RADEON_FP_GEN_CNTL); 582 sc->sc_fp_gen_cntl = GET32(sc, RADEON_FP_GEN_CNTL); 583 PRINTREG(RADEON_FP2_GEN_CNTL); 584 PRINTREG(RADEON_TMDS_CNTL); 585 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 586 PRINTREG(RADEON_TMDS_PLL_CNTL); 587 PRINTREG(RADEON_LVDS_GEN_CNTL); 588 PRINTREG(RADEON_DISP_HW_DEBUG); 589 PRINTREG(RADEON_PIXCLKS_CNTL); 590 PRINTREG(RADEON_CRTC_H_SYNC_STRT_WID); 591 PRINTREG(RADEON_FP_H_SYNC_STRT_WID); 592 PRINTREG(RADEON_CRTC2_H_SYNC_STRT_WID); 593 PRINTREG(RADEON_FP_H2_SYNC_STRT_WID); 594 595 /* 596 * XXX 597 * This was if (IS_RV100()), which is set for all pre-R3xx chips. 598 * I suspect this only makes sense on Sun XVR-100 with firmware that doesn't 599 * support DVI, so for now let's restrict it to only actual RV100 600 */ 601 if (sc->sc_family == RADEON_RV100) 602 PUT32(sc, RADEON_TMDS_PLL_CNTL, 0xa27); 603 604 /* XXX 605 * according to xf86-video-radeon R3xx has this bit backwards 606 */ 607 if (IS_R300(sc)) { 608 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 609 0, 610 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 611 } else { 612 PATCH32(sc, RADEON_TMDS_TRANSMITTER_CNTL, 613 RADEON_TMDS_TRANSMITTER_PLLEN, 614 ~(RADEON_TMDS_TRANSMITTER_PLLEN | RADEON_TMDS_TRANSMITTER_PLLRST)); 615 } 616 617 radeonfb_i2c_init(sc); 618 619 radeonfb_loadbios(sc, pa); 620 621 #ifdef RADEONFB_BIOS_INIT 622 if (radeonfb_bios_init(sc)) { 623 aprint_error("%s: BIOS inititialization failed\n", XNAME(sc)); 624 } 625 #endif 626 627 if (radeonfb_getclocks(sc)) { 628 aprint_error("%s: Unable to get reference clocks from BIOS\n", 629 XNAME(sc)); 630 goto error; 631 } 632 633 if (radeonfb_gettmds(sc)) { 634 aprint_error("%s: Unable to identify TMDS PLL settings\n", 635 XNAME(sc)); 636 goto error; 637 } 638 639 aprint_verbose("%s: refclk = %d.%03d MHz, refdiv = %d " 640 "minpll = %d, maxpll = %d\n", XNAME(sc), 641 (int)sc->sc_refclk / 1000, (int)sc->sc_refclk % 1000, 642 (int)sc->sc_refdiv, (int)sc->sc_minpll, (int)sc->sc_maxpll); 643 644 radeonfb_getconnectors(sc); 645 646 radeonfb_set_fbloc(sc); 647 648 /* 64 MB should be enough -- more just wastes map entries */ 649 if (sc->sc_memsz > (64 << 20)) 650 sc->sc_memsz = (64 << 20); 651 652 for (i = 0; radeonfb_limits[i].size; i++) { 653 if (sc->sc_memsz >= radeonfb_limits[i].size) { 654 sc->sc_maxx = radeonfb_limits[i].maxx; 655 sc->sc_maxy = radeonfb_limits[i].maxy; 656 sc->sc_maxbpp = radeonfb_limits[i].maxbpp; 657 /* framebuffer offset, start at a 4K page */ 658 sc->sc_fboffset = sc->sc_memsz / 659 radeonfb_limits[i].maxdisp; 660 /* 661 * we use the fbsize to figure out where we can store 662 * things like cursor data. 663 */ 664 sc->sc_fbsize = 665 ROUNDUP(ROUNDUP(sc->sc_maxx * sc->sc_maxbpp / 8 , 666 RADEON_STRIDEALIGN) * sc->sc_maxy, 667 4096); 668 break; 669 } 670 } 671 672 673 radeonfb_init_misc(sc); 674 675 /* program the DAC wirings */ 676 for (i = 0; i < (HAS_CRTC2(sc) ? 2 : 1); i++) { 677 switch (sc->sc_ports[i].rp_dac_type) { 678 case RADEON_DAC_PRIMARY: 679 PATCH32(sc, RADEON_DAC_CNTL2, 680 i ? RADEON_DAC2_DAC_CLK_SEL : 0, 681 ~RADEON_DAC2_DAC_CLK_SEL); 682 break; 683 case RADEON_DAC_TVDAC: 684 /* we always use the TVDAC to drive a secondary analog 685 * CRT for now. if we ever support TV-out this will 686 * have to change. 687 */ 688 SET32(sc, RADEON_DAC_CNTL2, 689 RADEON_DAC2_DAC2_CLK_SEL); 690 PATCH32(sc, RADEON_DISP_HW_DEBUG, 691 i ? 0 : RADEON_CRT2_DISP1_SEL, 692 ~RADEON_CRT2_DISP1_SEL); 693 /* we're using CRTC2 for the 2nd port */ 694 if (sc->sc_ports[i].rp_number == 1) { 695 PATCH32(sc, RADEON_DISP_OUTPUT_CNTL, 696 RADEON_DISP_DAC2_SOURCE_CRTC2, 697 ~RADEON_DISP_DAC2_SOURCE_MASK); 698 } 699 700 break; 701 } 702 DPRINTF(("%s: port %d tmds type %d\n", __func__, i, 703 sc->sc_ports[i].rp_tmds_type)); 704 switch (sc->sc_ports[i].rp_tmds_type) { 705 case RADEON_TMDS_INT: 706 /* point FP0 at the CRTC this port uses */ 707 DPRINTF(("%s: plugging internal TMDS into CRTC %d\n", 708 __func__, sc->sc_ports[i].rp_number)); 709 if (IS_R300(sc)) { 710 PATCH32(sc, RADEON_FP_GEN_CNTL, 711 sc->sc_ports[i].rp_number ? 712 R200_FP_SOURCE_SEL_CRTC2 : 713 R200_FP_SOURCE_SEL_CRTC1, 714 ~R200_FP_SOURCE_SEL_MASK); 715 } else { 716 PATCH32(sc, RADEON_FP_GEN_CNTL, 717 sc->sc_ports[i].rp_number ? 718 RADEON_FP_SEL_CRTC2 : 719 RADEON_FP_SEL_CRTC1, 720 ~RADEON_FP_SEL_MASK); 721 } 722 break; 723 case RADEON_TMDS_EXT: 724 /* point FP2 at the CRTC this port uses */ 725 DPRINTF(("%s: plugging external TMDS into CRTC %d\n", 726 __func__, sc->sc_ports[i].rp_number)); 727 if (IS_R300(sc)) { 728 PATCH32(sc, RADEON_FP2_GEN_CNTL, 729 sc->sc_ports[i].rp_number ? 730 R200_FP2_SOURCE_SEL_CRTC2 : 731 R200_FP2_SOURCE_SEL_CRTC1, 732 ~R200_FP2_SOURCE_SEL_CRTC2); 733 } else { 734 PATCH32(sc, RADEON_FP2_GEN_CNTL, 735 sc->sc_ports[i].rp_number ? 736 RADEON_FP2_SRC_SEL_CRTC2 : 737 RADEON_FP2_SRC_SEL_CRTC1, 738 ~RADEON_FP2_SRC_SEL_CRTC2); 739 } 740 break; 741 } 742 } 743 PRINTREG(RADEON_DAC_CNTL2); 744 PRINTREG(RADEON_DISP_HW_DEBUG); 745 746 PRINTREG(RADEON_DAC_CNTL); 747 /* other DAC programming */ 748 v = GET32(sc, RADEON_DAC_CNTL); 749 v &= (RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_BLANKING); 750 v |= RADEON_DAC_MASK_ALL | RADEON_DAC_8BIT_EN; 751 PUT32(sc, RADEON_DAC_CNTL, v); 752 PRINTREG(RADEON_DAC_CNTL); 753 754 /* XXX: this may need more investigation */ 755 PUT32(sc, RADEON_TV_DAC_CNTL, 0x00280203); 756 PRINTREG(RADEON_TV_DAC_CNTL); 757 758 /* enable TMDS */ 759 SET32(sc, RADEON_FP_GEN_CNTL, 760 RADEON_FP_TMDS_EN | 761 RADEON_FP_CRTC_DONT_SHADOW_VPAR | 762 RADEON_FP_CRTC_DONT_SHADOW_HEND); 763 /* 764 * XXX 765 * no idea why this is necessary - if I do not clear this bit on my 766 * iBook G4 the screen remains black, even though it's already clear. 767 * It needs to be set on my Sun XVR-100 for the DVI port to work 768 * TODO: 769 * see if this is still necessary now that CRTCs, DACs and outputs are 770 * getting wired up in a halfway sane way 771 */ 772 if (sc->sc_fp_gen_cntl & RADEON_FP_SEL_CRTC2) { 773 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 774 } else { 775 CLR32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_SEL_CRTC2); 776 } 777 778 /* 779 * we use bus_space_map instead of pci_mapreg, because we don't 780 * need the full aperature space. no point in wasting virtual 781 * address space we don't intend to use, right? 782 */ 783 if ((sc->sc_memsz < (4096 * 1024)) || 784 (pci_mapreg_info(sc->sc_pc, sc->sc_pt, RADEON_MAPREG_VRAM, 785 PCI_MAPREG_TYPE_MEM, &sc->sc_memaddr, &bsz, NULL) != 0) || 786 (bsz < sc->sc_memsz)) { 787 sc->sc_memsz = 0; 788 aprint_error("%s: Bad frame buffer configuration\n", 789 XNAME(sc)); 790 goto error; 791 } 792 793 sc->sc_memt = pa->pa_memt; 794 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 795 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 796 sc->sc_memsz = 0; 797 aprint_error("%s: Unable to map frame buffer\n", XNAME(sc)); 798 goto error; 799 } 800 801 aprint_normal("%s: %d MB aperture at 0x%08x, " 802 "%d KB registers at 0x%08x\n", XNAME(sc), 803 (int)sc->sc_memsz >> 20, (unsigned)sc->sc_memaddr, 804 (int)sc->sc_regsz >> 10, (unsigned)sc->sc_regaddr); 805 806 /* setup default video mode from devprop (allows PROM override) */ 807 sc->sc_defaultmode = radeonfb_default_mode; 808 if (prop_dictionary_get_cstring_nocopy(device_properties(sc->sc_dev), 809 "videomode", &mptr)) { 810 811 strncpy(sc->sc_modebuf, mptr, sizeof(sc->sc_modebuf)); 812 sc->sc_defaultmode = sc->sc_modebuf; 813 } 814 815 /* initialize some basic display parameters */ 816 for (i = 0; i < sc->sc_ndisplays; i++) { 817 struct radeonfb_display *dp = &sc->sc_displays[i]; 818 struct rasops_info *ri; 819 long defattr; 820 struct wsemuldisplaydev_attach_args aa; 821 822 /* 823 * Figure out how many "displays" (desktops) we are going to 824 * support. If more than one, then each CRTC gets its own 825 * programming. 826 * 827 * XXX: this code needs to change to support mergedfb. 828 * XXX: would be nice to allow this to be overridden 829 */ 830 if (HAS_CRTC2(sc) && (sc->sc_ndisplays == 1)) { 831 DPRINTF(("dual crtcs!\n")); 832 dp->rd_ncrtcs = 2; 833 dp->rd_crtcs[0].rc_port = 834 &sc->sc_ports[0]; 835 dp->rd_crtcs[0].rc_number = sc->sc_ports[0].rp_number; 836 dp->rd_crtcs[1].rc_port = 837 &sc->sc_ports[1]; 838 dp->rd_crtcs[1].rc_number = sc->sc_ports[1].rp_number; 839 } else { 840 dp->rd_ncrtcs = 1; 841 dp->rd_crtcs[0].rc_port = 842 &sc->sc_ports[i]; 843 dp->rd_crtcs[0].rc_number = sc->sc_ports[i].rp_number; 844 } 845 846 dp->rd_softc = sc; 847 dp->rd_wsmode = WSDISPLAYIO_MODE_EMUL; 848 dp->rd_bpp = RADEONFB_DEFAULT_DEPTH; /* XXX */ 849 850 /* for text mode, we pick a resolution that won't 851 * require panning */ 852 radeonfb_pickres(dp, &dp->rd_virtx, &dp->rd_virty, 0); 853 854 aprint_normal("%s: display %d: " 855 "initial virtual resolution %dx%d at %d bpp\n", 856 XNAME(sc), i, dp->rd_virtx, dp->rd_virty, dp->rd_bpp); 857 aprint_normal_dev(sc->sc_dev, "using %d MB per display\n", 858 sc->sc_fboffset >> 20); 859 /* now select the *video mode* that we will use */ 860 for (j = 0; j < dp->rd_ncrtcs; j++) { 861 const struct videomode *vmp; 862 vmp = radeonfb_port_mode(sc, dp->rd_crtcs[j].rc_port, 863 dp->rd_virtx, dp->rd_virty); 864 865 /* 866 * virtual resolution should be at least as high as 867 * physical 868 */ 869 if (dp->rd_virtx < vmp->hdisplay || 870 dp->rd_virty < vmp->vdisplay) { 871 dp->rd_virtx = vmp->hdisplay; 872 dp->rd_virty = vmp->vdisplay; 873 } 874 875 dp->rd_crtcs[j].rc_videomode = *vmp; 876 printf("%s: port %d: physical %dx%d %dHz\n", 877 XNAME(sc), j, vmp->hdisplay, vmp->vdisplay, 878 DIVIDE(DIVIDE(vmp->dot_clock * 1000, 879 vmp->htotal), vmp->vtotal)); 880 } 881 882 /* N.B.: radeon wants 64-byte aligned stride */ 883 dp->rd_stride = dp->rd_virtx * dp->rd_bpp / 8; 884 dp->rd_stride = ROUNDUP(dp->rd_stride, RADEON_STRIDEALIGN); 885 DPRINTF(("stride: %d %d\n", dp->rd_stride, dp->rd_virtx)); 886 887 dp->rd_offset = sc->sc_fboffset * i; 888 dp->rd_fbptr = (vaddr_t)bus_space_vaddr(sc->sc_memt, 889 sc->sc_memh) + dp->rd_offset; 890 dp->rd_curoff = sc->sc_fboffset - 4096; /* 4KB cursor space */ 891 dp->rd_curptr = dp->rd_fbptr + dp->rd_curoff; 892 893 DPRINTF(("fpbtr = %p\n", (void *)dp->rd_fbptr)); 894 895 switch (dp->rd_bpp) { 896 case 8: 897 dp->rd_format = 2; 898 break; 899 case 32: 900 dp->rd_format = 6; 901 break; 902 default: 903 aprint_error("%s: bad depth %d\n", XNAME(sc), 904 dp->rd_bpp); 905 goto error; 906 } 907 908 DPRINTF(("init engine\n")); 909 /* XXX: this seems suspicious - per display engine 910 initialization? */ 911 radeonfb_engine_init(dp); 912 913 /* copy the template into place */ 914 dp->rd_wsscreens_storage[0] = radeonfb_stdscreen; 915 dp->rd_wsscreens = dp->rd_wsscreens_storage; 916 917 /* and make up the list */ 918 dp->rd_wsscreenlist.nscreens = 1; 919 dp->rd_wsscreenlist.screens = (void *)&dp->rd_wsscreens; 920 921 vcons_init(&dp->rd_vd, dp, dp->rd_wsscreens, 922 &radeonfb_accessops); 923 924 dp->rd_vd.init_screen = radeonfb_init_screen; 925 926 #ifdef RADEONFB_DEBUG 927 dp->rd_virty -= 200; 928 #endif 929 930 dp->rd_console = 0; 931 prop_dictionary_get_bool(device_properties(sc->sc_dev), 932 "is_console", &dp->rd_console); 933 934 dp->rd_vscreen.scr_flags |= VCONS_SCREEN_IS_STATIC; 935 936 937 vcons_init_screen(&dp->rd_vd, &dp->rd_vscreen, 938 dp->rd_console, &defattr); 939 940 ri = &dp->rd_vscreen.scr_ri; 941 942 /* clear the screen */ 943 rasops_unpack_attr(defattr, &fg, &bg, &ul); 944 dp->rd_bg = ri->ri_devcmap[bg & 0xf]; 945 radeonfb_rectfill(dp, 0, 0, ri->ri_width, ri->ri_height, 946 dp->rd_bg); 947 948 dp->rd_wsscreens->textops = &ri->ri_ops; 949 dp->rd_wsscreens->capabilities = ri->ri_caps; 950 dp->rd_wsscreens->nrows = ri->ri_rows; 951 dp->rd_wsscreens->ncols = ri->ri_cols; 952 953 #ifdef SPLASHSCREEN 954 dp->rd_splash.si_depth = ri->ri_depth; 955 dp->rd_splash.si_bits = ri->ri_bits; 956 dp->rd_splash.si_hwbits = ri->ri_hwbits; 957 dp->rd_splash.si_width = ri->ri_width; 958 dp->rd_splash.si_height = ri->ri_height; 959 dp->rd_splash.si_stride = ri->ri_stride; 960 dp->rd_splash.si_fillrect = NULL; 961 #endif 962 dp->rd_gc.gc_bitblt = radeonfb_bitblt; 963 dp->rd_gc.gc_rectfill = radeonfb_rectfill_a; 964 dp->rd_gc.gc_rop = RADEON_ROP3_S; 965 dp->rd_gc.gc_blitcookie = dp; 966 /* 967 * use memory between framebuffer and cursor area as glyph 968 * cache, cap at 4096 lines 969 */ 970 glyphcache_init(&dp->rd_gc, dp->rd_virty + 4, 971 uimin(4096, 972 (dp->rd_curoff / dp->rd_stride) - (dp->rd_virty + 4)), 973 dp->rd_virtx, 974 ri->ri_font->fontwidth, 975 ri->ri_font->fontheight, 976 defattr); 977 dp->rd_vd.show_screen_cookie = &dp->rd_gc; 978 dp->rd_vd.show_screen_cb = glyphcache_adapt; 979 980 if (dp->rd_console) { 981 982 radeonfb_modeswitch(dp); 983 wsdisplay_cnattach(dp->rd_wsscreens, ri, 0, 0, 984 defattr); 985 #ifdef SPLASHSCREEN 986 if (splash_render(&dp->rd_splash, 987 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 988 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 989 else 990 #endif 991 vcons_replay_msgbuf(&dp->rd_vscreen); 992 } else { 993 994 /* 995 * since we're not the console we can postpone 996 * the rest until someone actually allocates a 997 * screen for us. but we do clear the screen 998 * at least. 999 */ 1000 memset(ri->ri_bits, 0, 1024); 1001 1002 radeonfb_modeswitch(dp); 1003 #ifdef SPLASHSCREEN 1004 if (splash_render(&dp->rd_splash, 1005 SPLASH_F_CENTER|SPLASH_F_FILL) == 0) 1006 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1007 #endif 1008 } 1009 1010 aa.console = dp->rd_console; 1011 aa.scrdata = &dp->rd_wsscreenlist; 1012 aa.accessops = &radeonfb_accessops; 1013 aa.accesscookie = &dp->rd_vd; 1014 1015 config_found(sc->sc_dev, &aa, wsemuldisplaydevprint); 1016 1017 radeonfb_blank(dp, 0); 1018 1019 /* Initialise delayed lvds operations for backlight. */ 1020 callout_init(&dp->rd_bl_lvds_co, 0); 1021 callout_setfunc(&dp->rd_bl_lvds_co, 1022 radeonfb_lvds_callout, dp); 1023 dp->rd_bl_on = 1; 1024 dp->rd_bl_level = radeonfb_get_backlight(dp); 1025 radeonfb_set_backlight(dp, dp->rd_bl_level); 1026 } 1027 1028 for (i = 0; i < RADEON_NDISPLAYS; i++) 1029 radeonfb_init_palette(&sc->sc_displays[i]); 1030 1031 if (HAS_CRTC2(sc)) { 1032 CLR32(sc, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_DIS); 1033 } 1034 1035 CLR32(sc, RADEON_CRTC_EXT_CNTL, RADEON_CRTC_DISPLAY_DIS); 1036 SET32(sc, RADEON_FP_GEN_CNTL, RADEON_FP_FPON); 1037 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_UP, 1038 radeonfb_brightness_up, TRUE); 1039 pmf_event_register(dev, PMFE_DISPLAY_BRIGHTNESS_DOWN, 1040 radeonfb_brightness_down, TRUE); 1041 1042 /* 1043 * if we attach a DRM we need to unmap registers in 1044 * WSDISPLAYIO_MODE_MAPPED, since this keeps us from doing things like 1045 * screen blanking we only do it if needed 1046 */ 1047 sc->sc_needs_unmap = 1048 (config_found_ia(dev, "drm", aux, radeonfb_drm_print) != 0); 1049 DPRINTF(("needs_unmap: %d\n", sc->sc_needs_unmap)); 1050 1051 PRINTREG(RADEON_CRTC_EXT_CNTL); 1052 PRINTREG(RADEON_CRTC_GEN_CNTL); 1053 PRINTREG(RADEON_CRTC2_GEN_CNTL); 1054 PRINTREG(RADEON_DISP_OUTPUT_CNTL); 1055 PRINTREG(RADEON_DAC_CNTL2); 1056 PRINTREG(RADEON_FP_GEN_CNTL); 1057 PRINTREG(RADEON_FP2_GEN_CNTL); 1058 PRINTREG(RADEON_TMDS_CNTL); 1059 PRINTREG(RADEON_TMDS_TRANSMITTER_CNTL); 1060 PRINTREG(RADEON_TMDS_PLL_CNTL); 1061 PRINTREG(RADEON_PIXCLKS_CNTL); 1062 1063 return; 1064 1065 error: 1066 if (sc->sc_biossz) 1067 free(sc->sc_bios, M_DEVBUF); 1068 1069 if (sc->sc_regsz) 1070 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1071 1072 if (sc->sc_memsz) 1073 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1074 } 1075 1076 static void 1077 radeonfb_map(struct radeonfb_softc *sc) 1078 { 1079 if (!sc->sc_mapped) { 1080 if (bus_space_map(sc->sc_regt, sc->sc_regaddr, sc->sc_regsz, 0, 1081 &sc->sc_regh) != 0) { 1082 aprint_error_dev(sc->sc_dev, 1083 "unable to map registers!\n"); 1084 return; 1085 } 1086 if (bus_space_map(sc->sc_memt, sc->sc_memaddr, sc->sc_memsz, 1087 BUS_SPACE_MAP_LINEAR, &sc->sc_memh) != 0) { 1088 sc->sc_memsz = 0; 1089 aprint_error_dev(sc->sc_dev, 1090 "Unable to map frame buffer\n"); 1091 return; 1092 } 1093 sc->sc_mapped = TRUE; 1094 } 1095 } 1096 1097 static void 1098 radeonfb_unmap(struct radeonfb_softc *sc) 1099 { 1100 if (!sc->sc_needs_unmap) 1101 return; 1102 1103 if (sc->sc_mapped) { 1104 bus_space_unmap(sc->sc_regt, sc->sc_regh, sc->sc_regsz); 1105 bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsz); 1106 sc->sc_mapped = FALSE; 1107 } 1108 } 1109 1110 static int 1111 radeonfb_drm_print(void *aux, const char *pnp) 1112 { 1113 if (pnp) 1114 aprint_normal("drm at %s", pnp); 1115 return (UNCONF); 1116 } 1117 1118 int 1119 radeonfb_ioctl(void *v, void *vs, 1120 unsigned long cmd, void *d, int flag, struct lwp *l) 1121 { 1122 struct vcons_data *vd; 1123 struct radeonfb_display *dp; 1124 struct radeonfb_softc *sc; 1125 struct wsdisplay_param *param; 1126 struct vcons_screen *ms; 1127 1128 vd = (struct vcons_data *)v; 1129 ms = vd->active; 1130 dp = (struct radeonfb_display *)vd->cookie; 1131 sc = dp->rd_softc; 1132 1133 /* can't do these without registers being mapped */ 1134 if (!sc->sc_mapped) { 1135 switch (cmd) { 1136 case WSDISPLAYIO_GVIDEO: 1137 case WSDISPLAYIO_SVIDEO: 1138 case WSDISPLAYIO_GETCMAP: 1139 case WSDISPLAYIO_PUTCMAP: 1140 case WSDISPLAYIO_SCURSOR: 1141 case WSDISPLAYIO_GCURPOS: 1142 case WSDISPLAYIO_SCURPOS: 1143 case WSDISPLAYIO_SETPARAM: 1144 return EINVAL; 1145 } 1146 } 1147 1148 switch (cmd) { 1149 case WSDISPLAYIO_GTYPE: 1150 *(unsigned *)d = WSDISPLAY_TYPE_PCIMISC; 1151 return 0; 1152 1153 case WSDISPLAYIO_GINFO: 1154 if (vd->active != NULL) { 1155 struct wsdisplay_fbinfo *fb; 1156 fb = (struct wsdisplay_fbinfo *)d; 1157 fb->width = dp->rd_virtx; 1158 fb->height = dp->rd_virty; 1159 fb->depth = dp->rd_bpp; 1160 fb->cmsize = 256; 1161 return 0; 1162 } else 1163 return ENODEV; 1164 case WSDISPLAYIO_GVIDEO: 1165 if (radeonfb_isblank(dp)) 1166 *(unsigned *)d = WSDISPLAYIO_VIDEO_OFF; 1167 else 1168 *(unsigned *)d = WSDISPLAYIO_VIDEO_ON; 1169 return 0; 1170 1171 case WSDISPLAYIO_SVIDEO: 1172 radeonfb_blank(dp, 1173 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_OFF)); 1174 radeonfb_switch_backlight(dp, 1175 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON)); 1176 pmf_event_inject(NULL, 1177 (*(unsigned int *)d == WSDISPLAYIO_VIDEO_ON) ? 1178 PMFE_DISPLAY_ON : PMFE_DISPLAY_OFF); 1179 return 0; 1180 1181 case WSDISPLAYIO_GETCMAP: 1182 if (dp->rd_bpp == 8) 1183 return radeonfb_getcmap(dp, 1184 (struct wsdisplay_cmap *)d); 1185 return EINVAL; 1186 1187 case WSDISPLAYIO_PUTCMAP: 1188 if (dp->rd_bpp == 8) 1189 return radeonfb_putcmap(dp, 1190 (struct wsdisplay_cmap *)d); 1191 return EINVAL; 1192 1193 case WSDISPLAYIO_LINEBYTES: 1194 *(unsigned *)d = dp->rd_stride; 1195 return 0; 1196 1197 case WSDISPLAYIO_SMODE: 1198 if (*(int *)d != dp->rd_wsmode) { 1199 dp->rd_wsmode = *(int *)d; 1200 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) || 1201 (dp->rd_wsmode == WSDISPLAYIO_MODE_DUMBFB)) 1202 radeonfb_map(sc); 1203 1204 if ((dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) && 1205 (dp->rd_vd.active)) { 1206 radeonfb_engine_init(dp); 1207 glyphcache_wipe(&dp->rd_gc); 1208 radeonfb_init_palette(dp); 1209 radeonfb_modeswitch(dp); 1210 radeonfb_rectfill(dp, 0, 0, dp->rd_virtx, 1211 dp->rd_virty, dp->rd_bg); 1212 vcons_redraw_screen(dp->rd_vd.active); 1213 } 1214 if (dp->rd_wsmode == WSDISPLAYIO_MODE_MAPPED) 1215 radeonfb_unmap(sc); 1216 } 1217 return 0; 1218 1219 case WSDISPLAYIO_GCURMAX: 1220 ((struct wsdisplay_curpos *)d)->x = RADEON_CURSORMAXX; 1221 ((struct wsdisplay_curpos *)d)->y = RADEON_CURSORMAXY; 1222 return 0; 1223 1224 case WSDISPLAYIO_SCURSOR: 1225 return radeonfb_set_cursor(dp, (struct wsdisplay_cursor *)d); 1226 1227 case WSDISPLAYIO_GCURSOR: 1228 return EPASSTHROUGH; 1229 1230 case WSDISPLAYIO_GCURPOS: 1231 ((struct wsdisplay_curpos *)d)->x = dp->rd_cursor.rc_pos.x; 1232 ((struct wsdisplay_curpos *)d)->y = dp->rd_cursor.rc_pos.y; 1233 return 0; 1234 1235 case WSDISPLAYIO_SCURPOS: 1236 return radeonfb_set_curpos(dp, (struct wsdisplay_curpos *)d); 1237 1238 case WSDISPLAYIO_SSPLASH: 1239 #if defined(SPLASHSCREEN) 1240 if (*(int *)d == 1) { 1241 SCREEN_DISABLE_DRAWING(&dp->rd_vscreen); 1242 splash_render(&dp->rd_splash, 1243 SPLASH_F_CENTER|SPLASH_F_FILL); 1244 } else 1245 SCREEN_ENABLE_DRAWING(&dp->rd_vscreen); 1246 return 0; 1247 #else 1248 return ENODEV; 1249 #endif 1250 case WSDISPLAYIO_GETPARAM: 1251 param = (struct wsdisplay_param *)d; 1252 switch (param->param) { 1253 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1254 param->min = 0; 1255 param->max = 255; 1256 param->curval = dp->rd_bl_level; 1257 return 0; 1258 case WSDISPLAYIO_PARAM_BACKLIGHT: 1259 param->min = 0; 1260 param->max = RADEONFB_BACKLIGHT_MAX; 1261 param->curval = dp->rd_bl_on; 1262 return 0; 1263 } 1264 return EPASSTHROUGH; 1265 1266 case WSDISPLAYIO_SETPARAM: 1267 param = (struct wsdisplay_param *)d; 1268 switch (param->param) { 1269 case WSDISPLAYIO_PARAM_BRIGHTNESS: 1270 radeonfb_set_backlight(dp, param->curval); 1271 return 0; 1272 case WSDISPLAYIO_PARAM_BACKLIGHT: 1273 radeonfb_switch_backlight(dp, param->curval); 1274 return 0; 1275 } 1276 return EPASSTHROUGH; 1277 1278 /* PCI config read/write passthrough. */ 1279 case PCI_IOC_CFGREAD: 1280 case PCI_IOC_CFGWRITE: 1281 return pci_devioctl(sc->sc_pc, sc->sc_pt, cmd, d, flag, l); 1282 1283 case WSDISPLAYIO_GET_BUSID: 1284 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 1285 sc->sc_pt, d); 1286 1287 case WSDISPLAYIO_GET_EDID: { 1288 struct wsdisplayio_edid_info *ei = d; 1289 return wsdisplayio_get_edid(sc->sc_dev, ei); 1290 } 1291 1292 case WSDISPLAYIO_GET_FBINFO: { 1293 struct wsdisplayio_fbinfo *fbi = d; 1294 return wsdisplayio_get_fbinfo(&ms->scr_ri, fbi); 1295 } 1296 1297 default: 1298 return EPASSTHROUGH; 1299 } 1300 } 1301 1302 paddr_t 1303 radeonfb_mmap(void *v, void *vs, off_t offset, int prot) 1304 { 1305 struct vcons_data *vd; 1306 struct radeonfb_display *dp; 1307 struct radeonfb_softc *sc; 1308 paddr_t pa; 1309 1310 vd = (struct vcons_data *)v; 1311 dp = (struct radeonfb_display *)vd->cookie; 1312 sc = dp->rd_softc; 1313 1314 if ((offset >= 0) && (offset < (dp->rd_virty * dp->rd_stride))) { 1315 pa = bus_space_mmap(sc->sc_memt, 1316 sc->sc_memaddr + dp->rd_offset + offset, 0, 1317 prot, BUS_SPACE_MAP_LINEAR); 1318 return pa; 1319 } 1320 1321 /* 1322 * restrict all other mappings to processes with superuser privileges 1323 * or the kernel itself 1324 */ 1325 if (kauth_authorize_machdep(kauth_cred_get(), KAUTH_MACHDEP_UNMANAGEDMEM, 1326 NULL, NULL, NULL, NULL) != 0) { 1327 aprint_error_dev(sc->sc_dev, "mmap() rejected.\n"); 1328 return -1; 1329 } 1330 1331 if ((offset >= sc->sc_regaddr) && 1332 (offset < sc->sc_regaddr + sc->sc_regsz)) { 1333 return bus_space_mmap(sc->sc_regt, offset, 0, prot, 1334 BUS_SPACE_MAP_LINEAR); 1335 } 1336 1337 if ((offset >= sc->sc_memaddr) && 1338 (offset < sc->sc_memaddr + sc->sc_memsz)) { 1339 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1340 BUS_SPACE_MAP_LINEAR); 1341 } 1342 1343 if ((offset >= sc->sc_romaddr) && 1344 (offset < sc->sc_romaddr + sc->sc_romsz)) { 1345 return bus_space_mmap(sc->sc_memt, offset, 0, prot, 1346 BUS_SPACE_MAP_LINEAR); 1347 } 1348 1349 #ifdef PCI_MAGIC_IO_RANGE 1350 /* allow mapping of IO space */ 1351 if ((offset >= PCI_MAGIC_IO_RANGE) && 1352 (offset < PCI_MAGIC_IO_RANGE + 0x10000)) { 1353 pa = bus_space_mmap(sc->sc_iot, offset - PCI_MAGIC_IO_RANGE, 1354 0, prot, 0); 1355 return pa; 1356 } 1357 #endif /* PCI_MAGIC_IO_RANGE */ 1358 1359 return -1; 1360 } 1361 1362 static void 1363 radeonfb_loadbios(struct radeonfb_softc *sc, const struct pci_attach_args *pa) 1364 { 1365 bus_space_tag_t romt; 1366 bus_space_handle_t romh, biosh; 1367 bus_size_t romsz; 1368 bus_addr_t ptr; 1369 uint32_t busctl, crtcg, crtc2g = 0, viphctl, seprom, extc; 1370 int bios_voodoo = 0; 1371 1372 if (pci_mapreg_map(pa, PCI_MAPREG_ROM, PCI_MAPREG_TYPE_ROM, 1373 BUS_SPACE_MAP_PREFETCHABLE, &romt, &romh, NULL, &romsz) != 0) { 1374 aprint_verbose("%s: unable to map BIOS!\n", XNAME(sc)); 1375 return; 1376 } 1377 1378 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1379 &sc->sc_biossz); 1380 if (sc->sc_biossz != 0) goto foundit; 1381 1382 aprint_verbose("trying to read disabled BIOS...\n"); 1383 1384 bios_voodoo = 1; 1385 seprom = radeonfb_get32(sc, RADEON_SEPROM_CNTL1); 1386 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, 1387 (seprom & ~RADEON_SCK_PRESCALE_MASK) | 1388 (0xc << RADEON_SCK_PRESCALE_SHIFT)); 1389 viphctl = radeonfb_get32(sc, RADEON_VIPH_CONTROL); 1390 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl & ~RADEON_VIPH_EN); 1391 busctl = radeonfb_get32(sc, RADEON_BUS_CNTL); 1392 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl & ~RADEON_BUS_BIOS_DIS_ROM); 1393 crtcg = radeonfb_get32(sc, RADEON_CRTC_GEN_CNTL); 1394 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, ((crtcg & ~RADEON_CRTC_EN) | 1395 (RADEON_CRTC_DISP_REQ_EN_B | 1396 RADEON_CRTC_EXT_DISP_EN))); 1397 if (HAS_CRTC2(sc)) { 1398 crtc2g = radeonfb_get32(sc, RADEON_CRTC2_GEN_CNTL); 1399 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, 1400 (crtc2g & ~RADEON_CRTC2_EN) | 1401 RADEON_CRTC2_DISP_REQ_EN_B); 1402 } 1403 extc = radeonfb_get32(sc, RADEON_CRTC_EXT_CNTL); 1404 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, (extc & ~RADEON_CRTC_CRT_ON) | 1405 (RADEON_CRTC_SYNC_TRISTAT | 1406 RADEON_CRTC_DISPLAY_DIS)); 1407 pci_find_rom(pa, romt, romh, romsz, PCI_ROM_CODE_TYPE_X86, &biosh, 1408 &sc->sc_biossz); 1409 1410 foundit: 1411 if (sc->sc_biossz > 0) { 1412 sc->sc_bios = malloc(sc->sc_biossz, M_DEVBUF, M_WAITOK); 1413 bus_space_read_region_1(romt, biosh, 0, sc->sc_bios, 1414 sc->sc_biossz); 1415 } 1416 1417 if (bios_voodoo != 0) { 1418 radeonfb_put32(sc, RADEON_CRTC_EXT_CNTL, extc); 1419 if (HAS_CRTC2(sc)) { 1420 radeonfb_put32(sc, RADEON_CRTC2_GEN_CNTL, crtc2g); 1421 } 1422 radeonfb_put32(sc, RADEON_CRTC_GEN_CNTL, crtcg); 1423 radeonfb_put32(sc, RADEON_BUS_CNTL, busctl); 1424 radeonfb_put32(sc, RADEON_VIPH_CONTROL, viphctl); 1425 radeonfb_put32(sc, RADEON_SEPROM_CNTL1, seprom); 1426 } 1427 1428 /* unmap the PCI expansion rom */ 1429 bus_space_unmap(romt, romh, romsz); 1430 1431 /* turn off rom decoder now */ 1432 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, 1433 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM) & 1434 ~PCI_MAPREG_ROM_ENABLE); 1435 1436 if (sc->sc_biossz > 0) { 1437 ptr = GETBIOS16(sc, 0x48); 1438 if ((GETBIOS32(sc, ptr + 4) == 0x41544f4d /* "ATOM" */) || 1439 (GETBIOS32(sc, ptr + 4) == 0x4d4f5441 /* "MOTA" */)) { 1440 sc->sc_flags |= RFB_ATOM; 1441 } 1442 1443 aprint_verbose("%s: Found %d KB %s BIOS\n", XNAME(sc), 1444 (unsigned)sc->sc_biossz >> 10, 1445 IS_ATOM(sc) ? "ATOM" : "Legacy"); 1446 } 1447 } 1448 1449 1450 uint32_t 1451 radeonfb_get32(struct radeonfb_softc *sc, uint32_t reg) 1452 { 1453 1454 return bus_space_read_4(sc->sc_regt, sc->sc_regh, reg); 1455 } 1456 1457 void 1458 radeonfb_put32(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1459 { 1460 1461 bus_space_write_4(sc->sc_regt, sc->sc_regh, reg, val); 1462 } 1463 1464 void 1465 radeonfb_put32s(struct radeonfb_softc *sc, uint32_t reg, uint32_t val) 1466 { 1467 1468 bus_space_write_stream_4(sc->sc_regt, sc->sc_regh, reg, val); 1469 } 1470 1471 void 1472 radeonfb_mask32(struct radeonfb_softc *sc, uint32_t reg, 1473 uint32_t andmask, uint32_t ormask) 1474 { 1475 int s; 1476 uint32_t val; 1477 1478 s = splhigh(); 1479 val = radeonfb_get32(sc, reg); 1480 val = (val & andmask) | ormask; 1481 radeonfb_put32(sc, reg, val); 1482 splx(s); 1483 } 1484 1485 uint32_t 1486 radeonfb_getindex(struct radeonfb_softc *sc, uint32_t idx) 1487 { 1488 int s; 1489 uint32_t val; 1490 1491 s = splhigh(); 1492 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1493 val = radeonfb_get32(sc, RADEON_MM_DATA); 1494 splx(s); 1495 1496 return (val); 1497 } 1498 1499 void 1500 radeonfb_putindex(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1501 { 1502 int s; 1503 1504 s = splhigh(); 1505 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1506 radeonfb_put32(sc, RADEON_MM_DATA, val); 1507 splx(s); 1508 } 1509 1510 void 1511 radeonfb_maskindex(struct radeonfb_softc *sc, uint32_t idx, 1512 uint32_t andmask, uint32_t ormask) 1513 { 1514 int s; 1515 uint32_t val; 1516 1517 s = splhigh(); 1518 radeonfb_put32(sc, RADEON_MM_INDEX, idx); 1519 val = radeonfb_get32(sc, RADEON_MM_DATA); 1520 val = (val & andmask) | ormask; 1521 radeonfb_put32(sc, RADEON_MM_DATA, val); 1522 splx(s); 1523 } 1524 1525 uint32_t 1526 radeonfb_getpll(struct radeonfb_softc *sc, uint32_t idx) 1527 { 1528 int s; 1529 uint32_t val; 1530 1531 s = splhigh(); 1532 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f)); 1533 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1534 if (HAS_R300CG(sc)) 1535 radeonfb_r300cg_workaround(sc); 1536 splx(s); 1537 1538 return (val); 1539 } 1540 1541 void 1542 radeonfb_putpll(struct radeonfb_softc *sc, uint32_t idx, uint32_t val) 1543 { 1544 int s; 1545 1546 s = splhigh(); 1547 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1548 RADEON_PLL_WR_EN); 1549 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1550 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1551 splx(s); 1552 } 1553 1554 void 1555 radeonfb_maskpll(struct radeonfb_softc *sc, uint32_t idx, 1556 uint32_t andmask, uint32_t ormask) 1557 { 1558 int s; 1559 uint32_t val; 1560 1561 s = splhigh(); 1562 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, (idx & 0x3f) | 1563 RADEON_PLL_WR_EN); 1564 val = radeonfb_get32(sc, RADEON_CLOCK_CNTL_DATA); 1565 val = (val & andmask) | ormask; 1566 radeonfb_put32(sc, RADEON_CLOCK_CNTL_DATA, val); 1567 radeonfb_put32(sc, RADEON_CLOCK_CNTL_INDEX, 0); 1568 splx(s); 1569 } 1570 1571 int 1572 radeonfb_scratch_test(struct radeonfb_softc *sc, int reg, uint32_t v) 1573 { 1574 uint32_t saved; 1575 1576 saved = GET32(sc, reg); 1577 PUT32(sc, reg, v); 1578 if (GET32(sc, reg) != v) { 1579 return -1; 1580 } 1581 PUT32(sc, reg, saved); 1582 return 0; 1583 } 1584 1585 uintmax_t 1586 radeonfb_getprop_num(struct radeonfb_softc *sc, const char *name, 1587 uintmax_t defval) 1588 { 1589 prop_number_t pn; 1590 pn = prop_dictionary_get(device_properties(sc->sc_dev), name); 1591 if (pn == NULL) { 1592 return defval; 1593 } 1594 KASSERT(prop_object_type(pn) == PROP_TYPE_NUMBER); 1595 return (prop_number_integer_value(pn)); 1596 } 1597 1598 int 1599 radeonfb_getclocks(struct radeonfb_softc *sc) 1600 { 1601 bus_addr_t ptr; 1602 int refclk = 0; 1603 int refdiv = 0; 1604 int minpll = 0; 1605 int maxpll = 0; 1606 1607 /* load initial property values if port/board provides them */ 1608 refclk = radeonfb_getprop_num(sc, "refclk", 0) & 0xffff; 1609 refdiv = radeonfb_getprop_num(sc, "refdiv", 0) & 0xffff; 1610 minpll = radeonfb_getprop_num(sc, "minpll", 0) & 0xffffffffU; 1611 maxpll = radeonfb_getprop_num(sc, "maxpll", 0) & 0xffffffffU; 1612 1613 PRINTPLL(RADEON_PPLL_REF_DIV); 1614 PRINTPLL(RADEON_PPLL_DIV_0); 1615 PRINTPLL(RADEON_PPLL_DIV_1); 1616 PRINTPLL(RADEON_PPLL_DIV_2); 1617 PRINTPLL(RADEON_PPLL_DIV_3); 1618 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 1619 PRINTPLL(RADEON_P2PLL_REF_DIV); 1620 PRINTPLL(RADEON_P2PLL_DIV_0); 1621 1622 if (refclk && refdiv && minpll && maxpll) 1623 goto dontprobe; 1624 1625 if (!sc->sc_biossz) { 1626 /* no BIOS */ 1627 aprint_verbose("%s: No video BIOS, using default clocks\n", 1628 XNAME(sc)); 1629 if (IS_IGP(sc)) 1630 refclk = refclk ? refclk : 1432; 1631 else 1632 refclk = refclk ? refclk : 2700; 1633 refdiv = refdiv ? refdiv : 12; 1634 minpll = minpll ? minpll : 12500; 1635 /* XXX 1636 * Need to check if the firmware or something programmed a 1637 * higher value than this, and if so, bump it. 1638 * The RV280 in my iBook is unhappy if the PLL input is less 1639 * than 360MHz 1640 */ 1641 maxpll = maxpll ? maxpll : 40000/*35000*/; 1642 } else if (IS_ATOM(sc)) { 1643 /* ATOM BIOS */ 1644 ptr = GETBIOS16(sc, 0x48); 1645 ptr = GETBIOS16(sc, ptr + 32); /* aka MasterDataStart */ 1646 ptr = GETBIOS16(sc, ptr + 12); /* pll info block */ 1647 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 82); 1648 minpll = minpll ? minpll : GETBIOS16(sc, ptr + 78); 1649 maxpll = maxpll ? maxpll : GETBIOS16(sc, ptr + 32); 1650 /* 1651 * ATOM BIOS doesn't supply a reference divider, so we 1652 * have to probe for it. 1653 */ 1654 if (refdiv < 2) 1655 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV) & 1656 RADEON_PPLL_REF_DIV_MASK; 1657 /* 1658 * if probe is zero, just assume one that should work 1659 * for most parts 1660 */ 1661 if (refdiv < 2) 1662 refdiv = 12; 1663 1664 } else { 1665 uint32_t tmp = GETPLL(sc, RADEON_PPLL_REF_DIV); 1666 /* Legacy BIOS */ 1667 ptr = GETBIOS16(sc, 0x48); 1668 ptr = GETBIOS16(sc, ptr + 0x30); 1669 if (IS_R300(sc)) { 1670 refdiv = refdiv ? refdiv : 1671 (tmp & R300_PPLL_REF_DIV_ACC_MASK) >> 1672 R300_PPLL_REF_DIV_ACC_SHIFT; 1673 } else { 1674 refdiv = refdiv ? refdiv : 1675 tmp & RADEON_PPLL_REF_DIV_MASK; 1676 } 1677 refclk = refclk ? refclk : GETBIOS16(sc, ptr + 0x0E); 1678 refdiv = refdiv ? refdiv : GETBIOS16(sc, ptr + 0x10); 1679 minpll = minpll ? minpll : GETBIOS32(sc, ptr + 0x12); 1680 maxpll = maxpll ? maxpll : GETBIOS32(sc, ptr + 0x16); 1681 } 1682 1683 1684 dontprobe: 1685 sc->sc_refclk = refclk * 10; 1686 sc->sc_refdiv = refdiv; 1687 sc->sc_minpll = minpll * 10; 1688 sc->sc_maxpll = maxpll * 10; 1689 return 0; 1690 } 1691 1692 int 1693 radeonfb_calc_dividers(struct radeonfb_softc *sc, uint32_t dotclock, 1694 uint32_t *postdivbit, uint32_t *feedbackdiv, int flags) 1695 { 1696 int i; 1697 uint32_t outfreq; 1698 int div; 1699 1700 DPRINTF(("dot clock: %u\n", dotclock)); 1701 for (i = 0; (div = radeonfb_dividers[i].divider) != 0; i++) { 1702 1703 if ((flags & NO_ODD_FBDIV) && ((div & 1) != 0)) 1704 continue; 1705 1706 /* 1707 * XXX 1708 * the rv350 in my last generation 14" iBook G4 produces 1709 * garbage with dividers > 4. No idea if this is a hardware 1710 * limitation or an error in the divider table. 1711 */ 1712 if ((sc->sc_family == RADEON_RV350) && (div > 4)) 1713 continue; 1714 1715 outfreq = div * dotclock; 1716 if ((outfreq >= sc->sc_minpll) && 1717 (outfreq <= sc->sc_maxpll)) { 1718 DPRINTF(("outfreq: %u\n", outfreq)); 1719 *postdivbit = 1720 ((uint32_t)radeonfb_dividers[i].mask << 16); 1721 DPRINTF(("post divider: %d (mask %x)\n", div, 1722 *postdivbit)); 1723 break; 1724 } 1725 } 1726 1727 if (div == 0) 1728 return 1; 1729 1730 *feedbackdiv = DIVIDE(sc->sc_refdiv * outfreq, sc->sc_refclk); 1731 DPRINTF(("feedback divider: %d\n", *feedbackdiv)); 1732 return 0; 1733 } 1734 1735 #if 0 1736 #ifdef RADEONFB_DEBUG 1737 static void 1738 dump_buffer(const char *pfx, void *buffer, unsigned int size) 1739 { 1740 char asc[17]; 1741 unsigned ptr = (unsigned)buffer; 1742 char *start = (char *)(ptr & ~0xf); 1743 char *end = (char *)(ptr + size); 1744 1745 end = (char *)(((unsigned)end + 0xf) & ~0xf); 1746 1747 if (pfx == NULL) { 1748 pfx = ""; 1749 } 1750 1751 while (start < end) { 1752 unsigned offset = (unsigned)start & 0xf; 1753 if (offset == 0) { 1754 printf("%s%x: ", pfx, (unsigned)start); 1755 } 1756 if (((unsigned)start < ptr) || 1757 ((unsigned)start >= (ptr + size))) { 1758 printf(" "); 1759 asc[offset] = ' '; 1760 } else { 1761 printf("%02x", *(unsigned char *)start); 1762 if ((*start >= ' ') && (*start <= '~')) { 1763 asc[offset] = *start; 1764 } else { 1765 asc[offset] = '.'; 1766 } 1767 } 1768 asc[offset + 1] = 0; 1769 if (offset % 2) { 1770 printf(" "); 1771 } 1772 if (offset == 15) { 1773 printf(" %s\n", asc); 1774 } 1775 start++; 1776 } 1777 } 1778 #endif 1779 #endif 1780 1781 int 1782 radeonfb_getconnectors(struct radeonfb_softc *sc) 1783 { 1784 int i; 1785 int found = 0; 1786 1787 for (i = 0; i < 2; i++) { 1788 sc->sc_ports[i].rp_mon_type = RADEON_MT_UNKNOWN; 1789 sc->sc_ports[i].rp_ddc_type = RADEON_DDC_NONE; 1790 sc->sc_ports[i].rp_dac_type = RADEON_DAC_UNKNOWN; 1791 sc->sc_ports[i].rp_conn_type = RADEON_CONN_NONE; 1792 sc->sc_ports[i].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1793 } 1794 1795 /* 1796 * This logic is borrowed from Xorg's radeon driver. 1797 */ 1798 if (!sc->sc_biossz) 1799 goto nobios; 1800 1801 if (IS_ATOM(sc)) { 1802 /* not done yet */ 1803 } else { 1804 uint16_t ptr; 1805 int port = 0; 1806 1807 ptr = GETBIOS16(sc, 0x48); 1808 ptr = GETBIOS16(sc, ptr + 0x50); 1809 for (i = 1; i < 4; i++) { 1810 uint16_t entry; 1811 uint8_t conn, ddc, dac, tmds; 1812 1813 /* 1814 * Parse the connector table. From reading the code, 1815 * it appears to made up of 16-bit entries for each 1816 * connector. The 16-bits are defined as: 1817 * 1818 * bits 12-15 - connector type (0 == end of table) 1819 * bits 8-11 - DDC type 1820 * bits 5-7 - ??? 1821 * bit 4 - TMDS type (1 = EXT, 0 = INT) 1822 * bits 1-3 - ??? 1823 * bit 0 - DAC, 1 = TVDAC, 0 = primary 1824 */ 1825 if (!GETBIOS8(sc, ptr + i * 2) && i > 1) 1826 break; 1827 entry = GETBIOS16(sc, ptr + i * 2); 1828 1829 conn = (entry >> 12) & 0xf; 1830 ddc = (entry >> 8) & 0xf; 1831 dac = (entry & 0x1) ? RADEON_DAC_TVDAC : 1832 RADEON_DAC_PRIMARY; 1833 tmds = ((entry >> 4) & 0x1) ? RADEON_TMDS_EXT : 1834 RADEON_TMDS_INT; 1835 1836 if (conn == RADEON_CONN_NONE) 1837 continue; /* no connector */ 1838 1839 /* 1840 * XXX 1841 * both Mac Mini variants have both outputs wired to 1842 * the same connector and share the DDC lines 1843 */ 1844 if ((found > 0) && 1845 (sc->sc_ports[port].rp_ddc_type == ddc)) { 1846 /* duplicate entry for same connector */ 1847 continue; 1848 } 1849 1850 /* internal DDC_DVI port gets priority */ 1851 if ((ddc == RADEON_DDC_DVI) || (port == 1)) 1852 port = 0; 1853 else 1854 port = 1; 1855 1856 sc->sc_ports[port].rp_ddc_type = 1857 ddc > RADEON_DDC_CRT2 ? RADEON_DDC_NONE : ddc; 1858 sc->sc_ports[port].rp_dac_type = dac; 1859 sc->sc_ports[port].rp_conn_type = 1860 uimin(conn, RADEON_CONN_UNSUPPORTED) ; 1861 1862 sc->sc_ports[port].rp_tmds_type = tmds; 1863 1864 if ((conn != RADEON_CONN_DVI_I) && 1865 (conn != RADEON_CONN_DVI_D) && 1866 (tmds == RADEON_TMDS_INT)) 1867 sc->sc_ports[port].rp_tmds_type = 1868 RADEON_TMDS_UNKNOWN; 1869 sc->sc_ports[port].rp_number = i - 1; 1870 1871 found += (port + 1); 1872 } 1873 } 1874 1875 nobios: 1876 if (!found) { 1877 bool dvi_ext = FALSE, dvi_int = FALSE; 1878 DPRINTF(("No connector info in BIOS!\n")); 1879 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1880 "dvi-internal", &dvi_int); 1881 prop_dictionary_get_bool(device_properties(sc->sc_dev), 1882 "dvi-external", &dvi_ext); 1883 if (dvi_ext) { 1884 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1885 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1886 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1887 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1888 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_EXT; /* output to fp2 */ 1889 sc->sc_ports[0].rp_number = 0; 1890 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1891 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1892 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1893 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1894 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1895 sc->sc_ports[1].rp_number = 1; 1896 } else if (dvi_int) { 1897 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1898 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_CRT2; 1899 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1900 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_I; 1901 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1902 sc->sc_ports[0].rp_number = 0; 1903 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1904 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_NONE; 1905 sc->sc_ports[1].rp_dac_type = RADEON_DAC_UNKNOWN; 1906 sc->sc_ports[1].rp_conn_type = RADEON_CONN_NONE; 1907 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1908 sc->sc_ports[1].rp_number = 1; 1909 } else if IS_MOBILITY(sc) { 1910 /* default, port 0 = internal TMDS, port 1 = CRT */ 1911 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1912 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1913 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1914 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1915 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1916 sc->sc_ports[0].rp_number = 0; 1917 1918 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1919 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1920 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1921 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1922 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_EXT; 1923 sc->sc_ports[1].rp_number = 1; 1924 } else { 1925 /* default, port 0 = DVI, port 1 = CRT */ 1926 sc->sc_ports[0].rp_mon_type = RADEON_MT_UNKNOWN; 1927 sc->sc_ports[0].rp_ddc_type = RADEON_DDC_DVI; 1928 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1929 sc->sc_ports[0].rp_conn_type = RADEON_CONN_DVI_D; 1930 sc->sc_ports[0].rp_tmds_type = RADEON_TMDS_INT; 1931 sc->sc_ports[0].rp_number = 0; 1932 1933 sc->sc_ports[1].rp_mon_type = RADEON_MT_UNKNOWN; 1934 sc->sc_ports[1].rp_ddc_type = RADEON_DDC_VGA; 1935 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1936 sc->sc_ports[1].rp_conn_type = RADEON_CONN_CRT; 1937 sc->sc_ports[1].rp_tmds_type = RADEON_TMDS_UNKNOWN; 1938 sc->sc_ports[1].rp_number = 1; 1939 } 1940 } 1941 1942 /* 1943 * Fixup for RS300/RS350/RS400 chips, that lack a primary DAC. 1944 * these chips should use TVDAC for the VGA port. 1945 */ 1946 if (HAS_SDAC(sc)) { 1947 if (sc->sc_ports[0].rp_conn_type == RADEON_CONN_CRT) { 1948 sc->sc_ports[0].rp_dac_type = RADEON_DAC_TVDAC; 1949 sc->sc_ports[1].rp_dac_type = RADEON_DAC_PRIMARY; 1950 } else { 1951 sc->sc_ports[1].rp_dac_type = RADEON_DAC_TVDAC; 1952 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1953 } 1954 } else if (!HAS_CRTC2(sc)) { 1955 sc->sc_ports[0].rp_dac_type = RADEON_DAC_PRIMARY; 1956 } 1957 1958 for (i = 0; i < 2; i++) { 1959 char edid[128]; 1960 uint8_t ddc; 1961 struct edid_info *eip = &sc->sc_ports[i].rp_edid; 1962 prop_data_t edid_data; 1963 1964 DPRINTF(("Port #%d:\n", i)); 1965 DPRINTF((" conn = %d\n", sc->sc_ports[i].rp_conn_type)); 1966 DPRINTF((" ddc = %d\n", sc->sc_ports[i].rp_ddc_type)); 1967 DPRINTF((" dac = %d\n", sc->sc_ports[i].rp_dac_type)); 1968 DPRINTF((" tmds = %d\n", sc->sc_ports[i].rp_tmds_type)); 1969 DPRINTF((" crtc = %d\n", sc->sc_ports[i].rp_number)); 1970 1971 sc->sc_ports[i].rp_edid_valid = 0; 1972 /* first look for static EDID data */ 1973 if ((edid_data = prop_dictionary_get(device_properties( 1974 sc->sc_dev), "EDID")) != NULL) { 1975 1976 aprint_debug_dev(sc->sc_dev, "using static EDID\n"); 1977 memcpy(edid, prop_data_data_nocopy(edid_data), 128); 1978 if (edid_parse(edid, eip) == 0) { 1979 1980 sc->sc_ports[i].rp_edid_valid = 1; 1981 #ifdef RADEONFB_DEBUG 1982 edid_print(eip); 1983 #endif 1984 } 1985 } 1986 /* if we didn't find any we'll try to talk to the monitor */ 1987 if (sc->sc_ports[i].rp_edid_valid != 1) { 1988 1989 ddc = sc->sc_ports[i].rp_ddc_type; 1990 if (ddc != RADEON_DDC_NONE) { 1991 if ((radeonfb_i2c_read_edid(sc, ddc, edid) 1992 == 0) && (edid_parse(edid, eip) == 0)) { 1993 1994 sc->sc_ports[i].rp_edid_valid = 1; 1995 #ifdef RADEONFB_DEBUG 1996 edid_print(eip); 1997 #endif 1998 } 1999 } 2000 } 2001 } 2002 2003 return found; 2004 } 2005 2006 int 2007 radeonfb_gettmds(struct radeonfb_softc *sc) 2008 { 2009 int i; 2010 2011 if (!sc->sc_biossz) { 2012 goto nobios; 2013 } 2014 2015 if (IS_ATOM(sc)) { 2016 /* XXX: not done yet */ 2017 } else { 2018 uint16_t ptr; 2019 int n; 2020 2021 ptr = GETBIOS16(sc, 0x48); 2022 ptr = GETBIOS16(sc, ptr + 0x34); 2023 DPRINTF(("DFP table revision %d\n", GETBIOS8(sc, ptr))); 2024 if (GETBIOS8(sc, ptr) == 3) { 2025 /* revision three table */ 2026 n = GETBIOS8(sc, ptr + 5) + 1; 2027 n = uimin(n, 4); 2028 2029 memset(sc->sc_tmds_pll, 0, sizeof (sc->sc_tmds_pll)); 2030 for (i = 0; i < n; i++) { 2031 sc->sc_tmds_pll[i].rtp_pll = GETBIOS32(sc, 2032 ptr + i * 10 + 8); 2033 sc->sc_tmds_pll[i].rtp_freq = GETBIOS16(sc, 2034 ptr + i * 10 + 0x10); 2035 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2036 sc->sc_tmds_pll[i].rtp_freq, 2037 sc->sc_tmds_pll[i].rtp_pll)); 2038 } 2039 return 0; 2040 } 2041 } 2042 2043 nobios: 2044 DPRINTF(("no suitable DFP table present\n")); 2045 for (i = 0; 2046 i < sizeof (radeonfb_tmds_pll) / sizeof (radeonfb_tmds_pll[0]); 2047 i++) { 2048 int j; 2049 2050 if (radeonfb_tmds_pll[i].family != sc->sc_family) 2051 continue; 2052 2053 for (j = 0; j < 4; j++) { 2054 sc->sc_tmds_pll[j] = radeonfb_tmds_pll[i].plls[j]; 2055 DPRINTF(("TMDS_PLL dot clock %d pll %x\n", 2056 sc->sc_tmds_pll[j].rtp_freq, 2057 sc->sc_tmds_pll[j].rtp_pll)); 2058 } 2059 return 0; 2060 } 2061 2062 return -1; 2063 } 2064 2065 const struct videomode * 2066 radeonfb_modelookup(const char *name) 2067 { 2068 int i; 2069 2070 for (i = 0; i < videomode_count; i++) { 2071 if (!strcmp(name, videomode_list[i].name)) 2072 return &videomode_list[i]; 2073 } 2074 return NULL; 2075 } 2076 2077 void 2078 radeonfb_pllwriteupdate(struct radeonfb_softc *sc, int crtc) 2079 { 2080 if (crtc) { 2081 while (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2082 RADEON_P2PLL_ATOMIC_UPDATE_R); 2083 SETPLL(sc, RADEON_P2PLL_REF_DIV, RADEON_P2PLL_ATOMIC_UPDATE_W); 2084 } else { 2085 while (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2086 RADEON_PPLL_ATOMIC_UPDATE_R); 2087 SETPLL(sc, RADEON_PPLL_REF_DIV, RADEON_PPLL_ATOMIC_UPDATE_W); 2088 } 2089 } 2090 2091 void 2092 radeonfb_pllwaitatomicread(struct radeonfb_softc *sc, int crtc) 2093 { 2094 int i; 2095 2096 for (i = 10000; i; i--) { 2097 if (crtc) { 2098 if (GETPLL(sc, RADEON_P2PLL_REF_DIV) & 2099 RADEON_P2PLL_ATOMIC_UPDATE_R) 2100 break; 2101 } else { 2102 if (GETPLL(sc, RADEON_PPLL_REF_DIV) & 2103 RADEON_PPLL_ATOMIC_UPDATE_R) 2104 break; 2105 } 2106 } 2107 } 2108 2109 void 2110 radeonfb_program_vclk(struct radeonfb_softc *sc, int dotclock, int crtc, int flags) 2111 { 2112 uint32_t pbit = 0; 2113 uint32_t feed = 0; 2114 uint32_t data, refdiv, div0, r2xxref; 2115 2116 radeonfb_calc_dividers(sc, dotclock, &pbit, &feed, flags); 2117 2118 if (crtc == 0) { 2119 2120 refdiv = GETPLL(sc, RADEON_PPLL_REF_DIV); 2121 2122 /* 2123 * XXX 2124 * the RV350 in my last generation iBook G4 behaves like an 2125 * r2xx here - try to detect that and not screw up the reference 2126 * divider. 2127 * xf86-video-radeon just skips PLL programming altogether 2128 * on iBooks, probably for this reason. 2129 */ 2130 r2xxref = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | sc->sc_refdiv; 2131 if (IS_R300(sc) && (r2xxref != refdiv)) { 2132 refdiv = (refdiv & ~R300_PPLL_REF_DIV_ACC_MASK) | 2133 (sc->sc_refdiv << R300_PPLL_REF_DIV_ACC_SHIFT); 2134 } else { 2135 refdiv = (refdiv & ~RADEON_PPLL_REF_DIV_MASK) | 2136 sc->sc_refdiv; 2137 } 2138 DPRINTF(("refdiv %08x\n", refdiv)); 2139 div0 = GETPLL(sc, RADEON_PPLL_DIV_0); 2140 DPRINTF(("div0 %08x\n", div0)); 2141 div0 &= ~(RADEON_PPLL_FB3_DIV_MASK | 2142 RADEON_PPLL_POST3_DIV_MASK); 2143 div0 |= pbit; 2144 div0 |= (feed & RADEON_PPLL_FB3_DIV_MASK); 2145 DPRINTF(("div0 %08x\n", div0)); 2146 2147 if ((refdiv == GETPLL(sc, RADEON_PPLL_REF_DIV)) && 2148 (div0 == GETPLL(sc, RADEON_PPLL_DIV_0))) { 2149 /* 2150 * nothing to do here, the PLL is already where we 2151 * want it 2152 */ 2153 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2154 ~RADEON_PLL_DIV_SEL); 2155 aprint_debug_dev(sc->sc_dev, "no need to touch the PLL\n"); 2156 return; 2157 } 2158 2159 /* alright, we do need to reprogram stuff */ 2160 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2161 RADEON_VCLK_SRC_SEL_CPUCLK, 2162 ~RADEON_VCLK_SRC_SEL_MASK); 2163 2164 /* put vclk into reset, use atomic updates */ 2165 SETPLL(sc, RADEON_PPLL_CNTL, 2166 RADEON_PPLL_REFCLK_SEL | 2167 RADEON_PPLL_FBCLK_SEL | 2168 RADEON_PPLL_RESET | 2169 RADEON_PPLL_ATOMIC_UPDATE_EN | 2170 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2171 2172 /* select clock 0 */ 2173 PATCH32(sc, RADEON_CLOCK_CNTL_INDEX, 0, 2174 ~RADEON_PLL_DIV_SEL); 2175 2176 PUTPLL(sc, RADEON_PPLL_REF_DIV, refdiv); 2177 2178 /* xf86-video-radeon does this, not sure why */ 2179 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2180 PUTPLL(sc, RADEON_PPLL_DIV_0, div0); 2181 2182 /* use the atomic update */ 2183 radeonfb_pllwriteupdate(sc, crtc); 2184 2185 /* and wait for it to complete */ 2186 radeonfb_pllwaitatomicread(sc, crtc); 2187 2188 /* program HTOTAL (why?) */ 2189 PUTPLL(sc, RADEON_HTOTAL_CNTL, 0); 2190 2191 /* drop reset */ 2192 CLRPLL(sc, RADEON_PPLL_CNTL, 2193 RADEON_PPLL_RESET | RADEON_PPLL_SLEEP | 2194 RADEON_PPLL_ATOMIC_UPDATE_EN | 2195 RADEON_PPLL_VGA_ATOMIC_UPDATE_EN); 2196 2197 PRINTPLL(RADEON_PPLL_CNTL); 2198 PRINTPLL(RADEON_PPLL_REF_DIV); 2199 PRINTPLL(RADEON_PPLL_DIV_3); 2200 2201 /* give clock time to lock */ 2202 delay(50000); 2203 2204 PATCHPLL(sc, RADEON_VCLK_ECP_CNTL, 2205 RADEON_VCLK_SRC_SEL_PPLLCLK, 2206 ~RADEON_VCLK_SRC_SEL_MASK); 2207 2208 } else { 2209 2210 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2211 RADEON_PIX2CLK_SRC_SEL_CPUCLK, 2212 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2213 2214 /* put vclk into reset, use atomic updates */ 2215 SETPLL(sc, RADEON_P2PLL_CNTL, 2216 RADEON_P2PLL_RESET | 2217 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2218 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2219 2220 /* program reference divider */ 2221 PATCHPLL(sc, RADEON_P2PLL_REF_DIV, sc->sc_refdiv, 2222 ~RADEON_P2PLL_REF_DIV_MASK); 2223 2224 /* program feedback and post dividers */ 2225 data = GETPLL(sc, RADEON_P2PLL_DIV_0); 2226 data &= ~(RADEON_P2PLL_FB0_DIV_MASK | 2227 RADEON_P2PLL_POST0_DIV_MASK); 2228 data |= pbit; 2229 data |= (feed & RADEON_P2PLL_FB0_DIV_MASK); 2230 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2231 PUTPLL(sc, RADEON_P2PLL_DIV_0, data); 2232 2233 PRINTPLL(RADEON_P2PLL_REF_DIV); 2234 PRINTPLL(RADEON_P2PLL_DIV_0); 2235 2236 /* use the atomic update */ 2237 radeonfb_pllwriteupdate(sc, crtc); 2238 2239 /* and wait for it to complete */ 2240 radeonfb_pllwaitatomicread(sc, crtc); 2241 2242 /* program HTOTAL (why?) */ 2243 PUTPLL(sc, RADEON_HTOTAL2_CNTL, 0); 2244 2245 /* drop reset */ 2246 CLRPLL(sc, RADEON_P2PLL_CNTL, 2247 RADEON_P2PLL_RESET | RADEON_P2PLL_SLEEP | 2248 RADEON_P2PLL_ATOMIC_UPDATE_EN | 2249 RADEON_P2PLL_VGA_ATOMIC_UPDATE_EN); 2250 2251 /* allow time for clock to lock */ 2252 delay(50000); 2253 2254 PATCHPLL(sc, RADEON_PIXCLKS_CNTL, 2255 RADEON_PIX2CLK_SRC_SEL_P2PLLCLK, 2256 ~RADEON_PIX2CLK_SRC_SEL_MASK); 2257 } 2258 PRINTREG(RADEON_CRTC_MORE_CNTL); 2259 } 2260 2261 void 2262 radeonfb_modeswitch(struct radeonfb_display *dp) 2263 { 2264 struct radeonfb_softc *sc = dp->rd_softc; 2265 int i; 2266 2267 /* blank the display while we switch modes */ 2268 radeonfb_blank(dp, 1); 2269 2270 #if 0 2271 SET32(sc, RADEON_CRTC_EXT_CNTL, 2272 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2273 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2274 #endif 2275 2276 /* these registers might get in the way... */ 2277 PUT32(sc, RADEON_OVR_CLR, 0); 2278 PUT32(sc, RADEON_OVR_WID_LEFT_RIGHT, 0); 2279 PUT32(sc, RADEON_OVR_WID_TOP_BOTTOM, 0); 2280 PUT32(sc, RADEON_OV0_SCALE_CNTL, 0); 2281 PUT32(sc, RADEON_SUBPIC_CNTL, 0); 2282 PUT32(sc, RADEON_VIPH_CONTROL, 0); 2283 PUT32(sc, RADEON_I2C_CNTL_1, 0); 2284 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2285 PUT32(sc, RADEON_CAP0_TRIG_CNTL, 0); 2286 PUT32(sc, RADEON_CAP1_TRIG_CNTL, 0); 2287 /* 2288 * Apple OF hands us R3xx radeons with tiling enabled - explicitly 2289 * disable it here 2290 */ 2291 PUT32(sc, RADEON_SURFACE_CNTL, RADEON_SURF_TRANSLATION_DIS); 2292 2293 for (i = 0; i < dp->rd_ncrtcs; i++) 2294 radeonfb_setcrtc(dp, i); 2295 2296 #if 0 2297 /* 2298 * DVO chip voodoo from xf86-video-radeon 2299 * apparently this is needed for some powerbooks with DVI outputs 2300 */ 2301 2302 uint8_t data[5][2] = {{0x8, 0x030}, {0x9, 0}, {0xa, 0x90}, {0xc, 0x89}, {0x8, 0x3b}}; 2303 int n = 0; 2304 iic_acquire_bus(&sc->sc_i2c[0].ric_controller, 0); 2305 for (i = 0; i < 5; i++) 2306 n += iic_exec(&sc->sc_i2c[0].ric_controller, I2C_OP_WRITE, 0x38, data[i], 2, NULL, 0, 0); 2307 iic_release_bus(&sc->sc_i2c[0].ric_controller, 0); 2308 printf("n = %d\n", n); 2309 #endif 2310 2311 /* activate the display */ 2312 radeonfb_blank(dp, 0); 2313 } 2314 2315 void 2316 radeonfb_setcrtc(struct radeonfb_display *dp, int index) 2317 { 2318 int crtc, flags = 0; 2319 struct videomode *mode; 2320 struct radeonfb_softc *sc; 2321 struct radeonfb_crtc *cp; 2322 uint32_t v; 2323 uint32_t gencntl; 2324 uint32_t htotaldisp; 2325 uint32_t hsyncstrt; 2326 uint32_t vtotaldisp; 2327 uint32_t vsyncstrt; 2328 uint32_t fphsyncstrt; 2329 uint32_t fpvsyncstrt; 2330 uint32_t fphtotaldisp; 2331 uint32_t fpvtotaldisp; 2332 uint32_t pitch; 2333 2334 sc = dp->rd_softc; 2335 2336 if ((sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_INT) || 2337 (sc->sc_ports[index].rp_tmds_type == RADEON_TMDS_EXT)) { 2338 flags |= NO_ODD_FBDIV; 2339 } 2340 2341 cp = &dp->rd_crtcs[index]; 2342 crtc = cp->rc_number; 2343 mode = &cp->rc_videomode; 2344 2345 #if 1 2346 pitch = dp->rd_stride / dp->rd_bpp; 2347 #else 2348 pitch = (((sc->sc_maxx * sc->sc_maxbpp) + ((sc->sc_maxbpp * 8) - 1)) / 2349 (sc->sc_maxbpp * 8)); 2350 #endif 2351 switch (crtc) { 2352 case 0: 2353 gencntl = RADEON_CRTC_GEN_CNTL; 2354 htotaldisp = RADEON_CRTC_H_TOTAL_DISP; 2355 hsyncstrt = RADEON_CRTC_H_SYNC_STRT_WID; 2356 vtotaldisp = RADEON_CRTC_V_TOTAL_DISP; 2357 vsyncstrt = RADEON_CRTC_V_SYNC_STRT_WID; 2358 /* should probably leave those alone on non-LVDS */ 2359 fpvsyncstrt = RADEON_FP_V_SYNC_STRT_WID; 2360 fphsyncstrt = RADEON_FP_H_SYNC_STRT_WID; 2361 fpvtotaldisp = RADEON_FP_CRTC_V_TOTAL_DISP; 2362 fphtotaldisp = RADEON_FP_CRTC_H_TOTAL_DISP; 2363 break; 2364 case 1: 2365 gencntl = RADEON_CRTC2_GEN_CNTL; 2366 htotaldisp = RADEON_CRTC2_H_TOTAL_DISP; 2367 hsyncstrt = RADEON_CRTC2_H_SYNC_STRT_WID; 2368 vtotaldisp = RADEON_CRTC2_V_TOTAL_DISP; 2369 vsyncstrt = RADEON_CRTC2_V_SYNC_STRT_WID; 2370 fpvsyncstrt = RADEON_FP_V2_SYNC_STRT_WID; 2371 fphsyncstrt = RADEON_FP_H2_SYNC_STRT_WID; 2372 /* XXX these registers don't seem to exist */ 2373 fpvtotaldisp = 0;//RADEON_FP_CRTC2_V_TOTAL_DISP; 2374 fphtotaldisp = 0;//RADEON_FP_CRTC2_H_TOTAL_DISP; 2375 break; 2376 default: 2377 panic("Bad CRTC!"); 2378 break; 2379 } 2380 2381 /* 2382 * CRTC_GEN_CNTL - depth, accelerator mode, etc. 2383 */ 2384 /* only bother with 32bpp and 8bpp */ 2385 v = dp->rd_format << RADEON_CRTC_PIX_WIDTH_SHIFT; 2386 2387 if (crtc == 1) { 2388 v |= RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_EN; 2389 } else { 2390 v |= RADEON_CRTC_EXT_DISP_EN | RADEON_CRTC_EN; 2391 } 2392 2393 if (mode->flags & VID_DBLSCAN) 2394 v |= RADEON_CRTC2_DBL_SCAN_EN; 2395 2396 if (mode->flags & VID_INTERLACE) 2397 v |= RADEON_CRTC2_INTERLACE_EN; 2398 2399 if (mode->flags & VID_CSYNC) { 2400 v |= RADEON_CRTC2_CSYNC_EN; 2401 if (crtc == 1) 2402 v |= RADEON_CRTC2_VSYNC_TRISTAT; 2403 } 2404 2405 PUT32(sc, gencntl, v); 2406 DPRINTF(("CRTC%s_GEN_CNTL = %08x\n", crtc ? "2" : "", v)); 2407 2408 /* 2409 * CRTC_EXT_CNTL - preserve disable flags, set ATI linear and EXT_CNT 2410 */ 2411 v = GET32(sc, RADEON_CRTC_EXT_CNTL); 2412 if (crtc == 0) { 2413 v &= (RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2414 RADEON_CRTC_DISPLAY_DIS); 2415 v |= RADEON_XCRT_CNT_EN | RADEON_VGA_ATI_LINEAR; 2416 if (mode->flags & VID_CSYNC) 2417 v |= RADEON_CRTC_VSYNC_TRISTAT; 2418 } 2419 /* unconditional turn on CRT, in case first CRTC is DFP */ 2420 v |= RADEON_CRTC_CRT_ON; 2421 PUT32(sc, RADEON_CRTC_EXT_CNTL, v); 2422 PRINTREG(RADEON_CRTC_EXT_CNTL); 2423 2424 /* 2425 * H_TOTAL_DISP 2426 */ 2427 v = ((mode->hdisplay / 8) - 1) << 16; 2428 v |= (mode->htotal / 8) - 1; 2429 PUT32(sc, htotaldisp, v); 2430 DPRINTF(("CRTC%s_H_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2431 if (fphtotaldisp) { 2432 PUT32(sc, fphtotaldisp, v); 2433 DPRINTF(("FP_H%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2434 } 2435 /* 2436 * H_SYNC_STRT_WID 2437 */ 2438 v = (((mode->hsync_end - mode->hsync_start) / 8) << 16); 2439 v |= (mode->hsync_start - 8); /* match xf86-video-radeon */ 2440 if (mode->flags & VID_NHSYNC) 2441 v |= RADEON_CRTC_H_SYNC_POL; 2442 PUT32(sc, hsyncstrt, v); 2443 DPRINTF(("CRTC%s_H_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2444 if (fphsyncstrt) { 2445 PUT32(sc, fphsyncstrt, v); 2446 DPRINTF(("FP_H%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2447 } 2448 2449 /* 2450 * V_TOTAL_DISP 2451 */ 2452 v = ((mode->vdisplay - 1) << 16); 2453 v |= (mode->vtotal - 1); 2454 PUT32(sc, vtotaldisp, v); 2455 DPRINTF(("CRTC%s_V_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2456 if (fpvtotaldisp) { 2457 PUT32(sc, fpvtotaldisp, v); 2458 DPRINTF(("FP_V%s_TOTAL_DISP = %08x\n", crtc ? "2" : "", v)); 2459 } 2460 2461 /* 2462 * V_SYNC_STRT_WID 2463 */ 2464 v = ((mode->vsync_end - mode->vsync_start) << 16); 2465 v |= (mode->vsync_start - 1); 2466 if (mode->flags & VID_NVSYNC) 2467 v |= RADEON_CRTC_V_SYNC_POL; 2468 PUT32(sc, vsyncstrt, v); 2469 DPRINTF(("CRTC%s_V_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2470 if (fpvsyncstrt) { 2471 PUT32(sc, fpvsyncstrt, v); 2472 DPRINTF(("FP_V%s_SYNC_STRT_WID = %08x\n", crtc ? "2" : "", v)); 2473 } 2474 2475 radeonfb_program_vclk(sc, mode->dot_clock, crtc, flags); 2476 2477 switch (crtc) { 2478 case 0: 2479 PUT32(sc, RADEON_CRTC_OFFSET, 0); 2480 PUT32(sc, RADEON_CRTC_OFFSET_CNTL, 0); 2481 PUT32(sc, RADEON_CRTC_PITCH, pitch); 2482 CLR32(sc, RADEON_DISP_MERGE_CNTL, RADEON_DISP_RGB_OFFSET_EN); 2483 2484 CLR32(sc, RADEON_CRTC_EXT_CNTL, 2485 RADEON_CRTC_VSYNC_DIS | RADEON_CRTC_HSYNC_DIS | 2486 RADEON_CRTC_DISPLAY_DIS /* | RADEON_CRTC_DISP_REQ_EN_B */); 2487 CLR32(sc, RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B); 2488 PRINTREG(RADEON_CRTC_EXT_CNTL); 2489 PRINTREG(RADEON_CRTC_GEN_CNTL); 2490 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 2491 break; 2492 2493 case 1: 2494 PUT32(sc, RADEON_CRTC2_OFFSET, 0); 2495 PUT32(sc, RADEON_CRTC2_OFFSET_CNTL, 0); 2496 PUT32(sc, RADEON_CRTC2_PITCH, pitch); 2497 CLR32(sc, RADEON_DISP2_MERGE_CNTL, RADEON_DISP2_RGB_OFFSET_EN); 2498 CLR32(sc, RADEON_CRTC2_GEN_CNTL, 2499 RADEON_CRTC2_VSYNC_DIS | 2500 RADEON_CRTC2_HSYNC_DIS | 2501 RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_DISP_REQ_EN_B); 2502 PRINTREG(RADEON_CRTC2_GEN_CNTL); 2503 break; 2504 } 2505 } 2506 2507 int 2508 radeonfb_isblank(struct radeonfb_display *dp) 2509 { 2510 uint32_t reg, mask; 2511 2512 if(!dp->rd_softc->sc_mapped) 2513 return 1; 2514 2515 if (dp->rd_crtcs[0].rc_number) { 2516 reg = RADEON_CRTC2_GEN_CNTL; 2517 mask = RADEON_CRTC2_DISP_DIS; 2518 } else { 2519 reg = RADEON_CRTC_EXT_CNTL; 2520 mask = RADEON_CRTC_DISPLAY_DIS; 2521 } 2522 return ((GET32(dp->rd_softc, reg) & mask) ? 1 : 0); 2523 } 2524 2525 void 2526 radeonfb_blank(struct radeonfb_display *dp, int blank) 2527 { 2528 struct radeonfb_softc *sc = dp->rd_softc; 2529 uint32_t reg, mask; 2530 uint32_t fpreg, fpval; 2531 int i; 2532 2533 if (!sc->sc_mapped) 2534 return; 2535 2536 for (i = 0; i < dp->rd_ncrtcs; i++) { 2537 2538 if (dp->rd_crtcs[i].rc_number) { 2539 reg = RADEON_CRTC2_GEN_CNTL; 2540 mask = RADEON_CRTC2_DISP_DIS; 2541 fpreg = RADEON_FP2_GEN_CNTL; 2542 fpval = RADEON_FP2_ON; 2543 } else { 2544 reg = RADEON_CRTC_EXT_CNTL; 2545 mask = RADEON_CRTC_DISPLAY_DIS; 2546 fpreg = RADEON_FP_GEN_CNTL; 2547 fpval = RADEON_FP_FPON; 2548 } 2549 2550 if (blank) { 2551 SET32(sc, reg, mask); 2552 CLR32(sc, fpreg, fpval); 2553 } else { 2554 CLR32(sc, reg, mask); 2555 SET32(sc, fpreg, fpval); 2556 } 2557 } 2558 PRINTREG(RADEON_FP_GEN_CNTL); 2559 PRINTREG(RADEON_FP2_GEN_CNTL); 2560 } 2561 2562 void 2563 radeonfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 2564 long *defattr) 2565 { 2566 struct radeonfb_display *dp = cookie; 2567 struct rasops_info *ri = &scr->scr_ri; 2568 2569 /* initialize font subsystem */ 2570 wsfont_init(); 2571 2572 scr->scr_flags |= VCONS_LOADFONT; 2573 2574 DPRINTF(("init screen called, existing %d\n", existing)); 2575 2576 ri->ri_depth = dp->rd_bpp; 2577 ri->ri_width = dp->rd_virtx; 2578 ri->ri_height = dp->rd_virty; 2579 ri->ri_stride = dp->rd_stride; 2580 ri->ri_flg = RI_CENTER; 2581 switch (ri->ri_depth) { 2582 case 8: 2583 ri->ri_flg |= RI_ENABLE_ALPHA | RI_8BIT_IS_RGB | RI_PREFER_ALPHA; 2584 break; 2585 case 32: 2586 ri->ri_flg |= RI_ENABLE_ALPHA | RI_PREFER_ALPHA; 2587 /* we run radeons in RGB even on SPARC hardware */ 2588 ri->ri_rnum = 8; 2589 ri->ri_gnum = 8; 2590 ri->ri_bnum = 8; 2591 ri->ri_rpos = 16; 2592 ri->ri_gpos = 8; 2593 ri->ri_bpos = 0; 2594 break; 2595 } 2596 2597 ri->ri_bits = (void *)dp->rd_fbptr; 2598 2599 #ifdef VCONS_DRAW_INTR 2600 scr->scr_flags |= VCONS_DONT_READ; 2601 #endif 2602 2603 if (existing) { 2604 ri->ri_flg |= RI_CLEAR; 2605 2606 /* start a modeswitch now */ 2607 radeonfb_modeswitch(dp); 2608 } 2609 2610 /* 2611 * XXX: font selection should be based on properties, with some 2612 * normal/reasonable default. 2613 */ 2614 2615 /* initialize and look for an initial font */ 2616 rasops_init(ri, 0, 0); 2617 ri->ri_caps = WSSCREEN_UNDERLINE | WSSCREEN_HILIT | 2618 WSSCREEN_WSCOLORS | WSSCREEN_REVERSE | WSSCREEN_RESIZE; 2619 2620 rasops_reconfig(ri, dp->rd_virty / ri->ri_font->fontheight, 2621 dp->rd_virtx / ri->ri_font->fontwidth); 2622 2623 /* enable acceleration */ 2624 dp->rd_putchar = ri->ri_ops.putchar; 2625 ri->ri_ops.copyrows = radeonfb_copyrows; 2626 ri->ri_ops.copycols = radeonfb_copycols; 2627 ri->ri_ops.eraserows = radeonfb_eraserows; 2628 ri->ri_ops.erasecols = radeonfb_erasecols; 2629 /* pick a putchar method based on font and Radeon model */ 2630 if (ri->ri_font->stride < ri->ri_font->fontwidth) { 2631 /* got a bitmap font */ 2632 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 2633 if (IS_R300(dp->rd_softc)) { 2634 /* 2635 * radeonfb_putchar() doesn't work right on some R3xx 2636 * so we use software drawing here, the wrapper just 2637 * makes sure the engine is idle before scribbling 2638 * into vram 2639 */ 2640 ri->ri_ops.putchar = radeonfb_putchar_wrapper; 2641 } else 2642 #endif 2643 ri->ri_ops.putchar = radeonfb_putchar; 2644 } else { 2645 /* got an alpha font */ 2646 switch(ri->ri_depth) { 2647 case 32: 2648 ri->ri_ops.putchar = radeonfb_putchar_aa32; 2649 break; 2650 case 8: 2651 ri->ri_ops.putchar = radeonfb_putchar_aa8; 2652 break; 2653 default: 2654 /* XXX this should never happen */ 2655 panic("%s: depth is not 8 or 32 but we got an" \ 2656 " alpha font?!", __func__); 2657 } 2658 } 2659 ri->ri_ops.cursor = radeonfb_cursor; 2660 } 2661 2662 void 2663 radeonfb_set_fbloc(struct radeonfb_softc *sc) 2664 { 2665 uint32_t gen, ext, gen2 = 0; 2666 uint32_t agploc, aperbase, apersize, mcfbloc; 2667 2668 gen = GET32(sc, RADEON_CRTC_GEN_CNTL); 2669 /* XXX */ 2670 ext = GET32(sc, RADEON_CRTC_EXT_CNTL) & ~RADEON_CRTC_DISPLAY_DIS; 2671 agploc = GET32(sc, RADEON_MC_AGP_LOCATION); 2672 aperbase = GET32(sc, RADEON_CONFIG_APER_0_BASE); 2673 apersize = GET32(sc, RADEON_CONFIG_APER_SIZE); 2674 2675 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISP_REQ_EN_B); 2676 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISPLAY_DIS); 2677 #if 0 2678 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen | RADEON_CRTC_DISPLAY_DIS); 2679 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext | RADEON_CRTC_DISP_REQ_EN_B); 2680 #endif 2681 2682 if (HAS_CRTC2(sc)) { 2683 gen2 = GET32(sc, RADEON_CRTC2_GEN_CNTL); 2684 PUT32(sc, RADEON_CRTC2_GEN_CNTL, 2685 gen2 | RADEON_CRTC2_DISP_REQ_EN_B); 2686 } 2687 2688 delay(100000); 2689 2690 mcfbloc = (aperbase >> 16) | 2691 ((aperbase + (apersize - 1)) & 0xffff0000); 2692 2693 sc->sc_aperbase = (mcfbloc & 0xffff) << 16; 2694 sc->sc_memsz = apersize; 2695 2696 if (((agploc & 0xffff) << 16) != 2697 ((mcfbloc & 0xffff0000U) + 0x10000)) { 2698 agploc = mcfbloc & 0xffff0000U; 2699 agploc |= ((agploc + 0x10000) >> 16); 2700 } 2701 2702 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2703 2704 PUT32(sc, RADEON_MC_FB_LOCATION, mcfbloc); 2705 PUT32(sc, RADEON_MC_AGP_LOCATION, agploc); 2706 2707 DPRINTF(("aperbase = %u\n", aperbase)); 2708 PRINTREG(RADEON_MC_FB_LOCATION); 2709 PRINTREG(RADEON_MC_AGP_LOCATION); 2710 2711 PUT32(sc, RADEON_DISPLAY_BASE_ADDR, sc->sc_aperbase); 2712 2713 if (HAS_CRTC2(sc)) 2714 PUT32(sc, RADEON_DISPLAY2_BASE_ADDR, sc->sc_aperbase); 2715 2716 PUT32(sc, RADEON_OV0_BASE_ADDR, sc->sc_aperbase); 2717 2718 #if 0 2719 /* XXX: what is this AGP garbage? :-) */ 2720 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2721 #endif 2722 2723 delay(100000); 2724 2725 PUT32(sc, RADEON_CRTC_GEN_CNTL, gen); 2726 PUT32(sc, RADEON_CRTC_EXT_CNTL, ext); 2727 2728 if (HAS_CRTC2(sc)) 2729 PUT32(sc, RADEON_CRTC2_GEN_CNTL, gen2); 2730 } 2731 2732 void 2733 radeonfb_init_misc(struct radeonfb_softc *sc) 2734 { 2735 PUT32(sc, RADEON_BUS_CNTL, 2736 RADEON_BUS_MASTER_DIS | 2737 RADEON_BUS_PREFETCH_MODE_ACT | 2738 RADEON_BUS_PCI_READ_RETRY_EN | 2739 RADEON_BUS_PCI_WRT_RETRY_EN | 2740 (3 << RADEON_BUS_RETRY_WS_SHIFT) | 2741 RADEON_BUS_MSTR_RD_MULT | 2742 RADEON_BUS_MSTR_RD_LINE | 2743 RADEON_BUS_RD_DISCARD_EN | 2744 RADEON_BUS_MSTR_DISCONNECT_EN | 2745 RADEON_BUS_READ_BURST); 2746 2747 PUT32(sc, RADEON_BUS_CNTL1, 0xf0); 2748 /* PUT32(sc, RADEON_SEPROM_CNTL1, 0x09ff0000); */ 2749 PUT32(sc, RADEON_FCP_CNTL, RADEON_FCP0_SRC_GND); 2750 PUT32(sc, RADEON_RBBM_CNTL, 2751 (3 << RADEON_RB_SETTLE_SHIFT) | 2752 (4 << RADEON_ABORTCLKS_HI_SHIFT) | 2753 (4 << RADEON_ABORTCLKS_CP_SHIFT) | 2754 (4 << RADEON_ABORTCLKS_CFIFO_SHIFT)); 2755 2756 /* XXX: figure out what these mean! */ 2757 PUT32(sc, RADEON_AGP_CNTL, 0x00100000); 2758 PUT32(sc, RADEON_HOST_PATH_CNTL, 0); 2759 #if 0 2760 PUT32(sc, RADEON_DISP_MISC_CNTL, 0x5bb00400); 2761 #endif 2762 2763 PUT32(sc, RADEON_GEN_INT_CNTL, 0); 2764 PUT32(sc, RADEON_GEN_INT_STATUS, GET32(sc, RADEON_GEN_INT_STATUS)); 2765 } 2766 2767 static void 2768 radeonfb_putpal(struct radeonfb_display *dp, int idx, int r, int g, int b) 2769 { 2770 struct radeonfb_softc *sc = dp->rd_softc; 2771 int crtc, cc; 2772 uint32_t vclk; 2773 2774 vclk = GETPLL(sc, RADEON_VCLK_ECP_CNTL); 2775 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk & ~RADEON_PIXCLK_DAC_ALWAYS_ONb); 2776 2777 /* initialize the palette for every CRTC used by this display */ 2778 for (cc = 0; cc < dp->rd_ncrtcs; cc++) { 2779 crtc = dp->rd_crtcs[cc].rc_number; 2780 2781 if (crtc) 2782 SET32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2783 else 2784 CLR32(sc, RADEON_DAC_CNTL2, RADEON_DAC2_PALETTE_ACC_CTL); 2785 2786 PUT32(sc, RADEON_PALETTE_INDEX, idx); 2787 PUT32(sc, RADEON_PALETTE_30_DATA, 2788 (r << 22) | (g << 12) | (b << 2)); 2789 } 2790 2791 PUTPLL(sc, RADEON_VCLK_ECP_CNTL, vclk); 2792 } 2793 2794 /* 2795 * This loads a linear color map for true color. 2796 */ 2797 void 2798 radeonfb_init_palette(struct radeonfb_display *dp) 2799 { 2800 int i; 2801 2802 #define DAC_WIDTH ((1 << 10) - 1) 2803 #define CLUT_WIDTH ((1 << 8) - 1) 2804 #define CLUT_COLOR(i) ((i * DAC_WIDTH * 2 / CLUT_WIDTH + 1) / 2) 2805 2806 if (dp->rd_bpp == 8) { 2807 2808 /* R3G3B2 palette */ 2809 uint32_t tmp, r, g, b; 2810 2811 for (i = 0; i <= CLUT_WIDTH; ++i) { 2812 tmp = i & 0xe0; 2813 2814 /* 2815 * replicate bits so 0xe0 maps to a red value of 0xff 2816 * in order to make white look actually white 2817 */ 2818 tmp |= (tmp >> 3) | (tmp >> 6); 2819 r = tmp; 2820 2821 tmp = (i & 0x1c) << 3; 2822 tmp |= (tmp >> 3) | (tmp >> 6); 2823 g = tmp; 2824 2825 tmp = (i & 0x03) << 6; 2826 tmp |= tmp >> 2; 2827 tmp |= tmp >> 4; 2828 b = tmp; 2829 2830 radeonfb_putpal(dp, i, r, g, b); 2831 } 2832 } else { 2833 /* linear ramp */ 2834 for (i = 0; i <= CLUT_WIDTH; ++i) { 2835 radeonfb_putpal(dp, i, i, i, i); 2836 } 2837 } 2838 } 2839 2840 static int 2841 radeonfb_putcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2842 { 2843 u_char *r, *g, *b; 2844 u_int index = cm->index; 2845 u_int count = cm->count; 2846 int i, error; 2847 u_char rbuf[256], gbuf[256], bbuf[256]; 2848 2849 #ifdef GENFB_DEBUG 2850 aprint_debug("putcmap: %d %d\n",index, count); 2851 #endif 2852 if (index >= 256 || count > 256 - index) 2853 return EINVAL; 2854 error = copyin(cm->red, &rbuf[index], count); 2855 if (error) 2856 return error; 2857 error = copyin(cm->green, &gbuf[index], count); 2858 if (error) 2859 return error; 2860 error = copyin(cm->blue, &bbuf[index], count); 2861 if (error) 2862 return error; 2863 2864 memcpy(&dp->rd_cmap_red[index], &rbuf[index], count); 2865 memcpy(&dp->rd_cmap_green[index], &gbuf[index], count); 2866 memcpy(&dp->rd_cmap_blue[index], &bbuf[index], count); 2867 2868 r = &dp->rd_cmap_red[index]; 2869 g = &dp->rd_cmap_green[index]; 2870 b = &dp->rd_cmap_blue[index]; 2871 2872 for (i = 0; i < count; i++) { 2873 radeonfb_putpal(dp, index, *r, *g, *b); 2874 index++; 2875 r++, g++, b++; 2876 } 2877 return 0; 2878 } 2879 2880 static int 2881 radeonfb_getcmap(struct radeonfb_display *dp, struct wsdisplay_cmap *cm) 2882 { 2883 u_int index = cm->index; 2884 u_int count = cm->count; 2885 int error; 2886 2887 if (index >= 256 || count > 256 - index) 2888 return EINVAL; 2889 2890 error = copyout(&dp->rd_cmap_red[index], cm->red, count); 2891 if (error) 2892 return error; 2893 error = copyout(&dp->rd_cmap_green[index], cm->green, count); 2894 if (error) 2895 return error; 2896 error = copyout(&dp->rd_cmap_blue[index], cm->blue, count); 2897 if (error) 2898 return error; 2899 2900 return 0; 2901 } 2902 2903 /* 2904 * Bugs in some R300 hardware requires this when accessing CLOCK_CNTL_INDEX. 2905 */ 2906 void 2907 radeonfb_r300cg_workaround(struct radeonfb_softc *sc) 2908 { 2909 uint32_t tmp, save; 2910 2911 save = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 2912 tmp = save & ~(0x3f | RADEON_PLL_WR_EN); 2913 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, tmp); 2914 tmp = GET32(sc, RADEON_CLOCK_CNTL_DATA); 2915 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, save); 2916 } 2917 2918 /* 2919 * Acceleration entry points. 2920 */ 2921 2922 /* this one draws characters using bitmap fonts */ 2923 static void 2924 radeonfb_putchar(void *cookie, int row, int col, u_int c, long attr) 2925 { 2926 struct rasops_info *ri = cookie; 2927 struct vcons_screen *scr = ri->ri_hw; 2928 struct radeonfb_display *dp = scr->scr_cookie; 2929 struct radeonfb_softc *sc = dp->rd_softc; 2930 struct wsdisplay_font *font = PICK_FONT(ri, c); 2931 uint32_t w, h; 2932 int xd, yd, offset, i; 2933 uint32_t bg, fg, gmc; 2934 uint32_t reg; 2935 uint8_t *data8; 2936 uint16_t *data16; 2937 uint32_t *data32; 2938 void *data; 2939 2940 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 2941 return; 2942 2943 if (!CHAR_IN_FONT(c, font)) 2944 return; 2945 2946 w = font->fontwidth; 2947 h = font->fontheight; 2948 2949 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 2950 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 2951 2952 xd = ri->ri_xorigin + col * w; 2953 yd = ri->ri_yorigin + row * h; 2954 2955 if (c == 0x20) { 2956 radeonfb_rectfill(dp, xd, yd, w, h, bg); 2957 return; 2958 } 2959 data = WSFONT_GLYPH(c, font); 2960 2961 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 2962 2963 radeonfb_wait_fifo(sc, 9); 2964 2965 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 2966 RADEON_GMC_BRUSH_NONE | 2967 RADEON_GMC_SRC_DATATYPE_MONO_FG_BG | 2968 RADEON_GMC_DST_CLIPPING | 2969 RADEON_ROP3_S | 2970 RADEON_DP_SRC_SOURCE_HOST_DATA | 2971 RADEON_GMC_CLR_CMP_CNTL_DIS | 2972 RADEON_GMC_WR_MSK_DIS | 2973 gmc); 2974 2975 PUT32(sc, RADEON_SC_LEFT, xd); 2976 PUT32(sc, RADEON_SC_RIGHT, xd + w); 2977 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, fg); 2978 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, bg); 2979 PUT32(sc, RADEON_DP_CNTL, 2980 RADEON_DST_X_LEFT_TO_RIGHT | 2981 RADEON_DST_Y_TOP_TO_BOTTOM); 2982 2983 PUT32(sc, RADEON_SRC_X_Y, 0); 2984 offset = 32 - (font->stride << 3); 2985 PUT32(sc, RADEON_DST_X_Y, ((xd - offset) << 16) | yd); 2986 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (32 << 16) | h); 2987 2988 radeonfb_wait_fifo(sc, h); 2989 switch (font->stride) { 2990 case 1: { 2991 data8 = data; 2992 for (i = 0; i < h; i++) { 2993 reg = *data8; 2994 #if BYTE_ORDER == LITTLE_ENDIAN 2995 reg = reg << 24; 2996 #endif 2997 bus_space_write_stream_4(sc->sc_regt, 2998 sc->sc_regh, RADEON_HOST_DATA0, reg); 2999 data8++; 3000 } 3001 break; 3002 } 3003 case 2: { 3004 data16 = data; 3005 for (i = 0; i < h; i++) { 3006 reg = *data16; 3007 #if BYTE_ORDER == LITTLE_ENDIAN 3008 reg = reg << 16; 3009 #endif 3010 bus_space_write_stream_4(sc->sc_regt, 3011 sc->sc_regh, RADEON_HOST_DATA0, reg); 3012 data16++; 3013 } 3014 break; 3015 } 3016 case 4: { 3017 data32 = data; 3018 for (i = 0; i < h; i++) { 3019 reg = *data32; 3020 bus_space_write_stream_4(sc->sc_regt, 3021 sc->sc_regh, RADEON_HOST_DATA0, reg); 3022 data32++; 3023 } 3024 break; 3025 } 3026 } 3027 if (attr & 1) 3028 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3029 } 3030 3031 /* ... while this one is for anti-aliased ones */ 3032 static void 3033 radeonfb_putchar_aa32(void *cookie, int row, int col, u_int c, long attr) 3034 { 3035 struct rasops_info *ri = cookie; 3036 struct vcons_screen *scr = ri->ri_hw; 3037 struct radeonfb_display *dp = scr->scr_cookie; 3038 struct radeonfb_softc *sc = dp->rd_softc; 3039 struct wsdisplay_font *font = PICK_FONT(ri, c); 3040 uint32_t bg, fg, gmc; 3041 uint8_t *data; 3042 int w, h, xd, yd; 3043 int i, r, g, b, aval; 3044 int rf, gf, bf, rb, gb, bb; 3045 uint32_t pixel; 3046 int rv; 3047 3048 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3049 return; 3050 3051 if (!CHAR_IN_FONT(c, font)) 3052 return; 3053 3054 w = font->fontwidth; 3055 h = font->fontheight; 3056 3057 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3058 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3059 3060 xd = ri->ri_xorigin + col * w; 3061 yd = ri->ri_yorigin + row * h; 3062 3063 if (c == 0x20) { 3064 radeonfb_rectfill(dp, xd, yd, w, h, bg); 3065 if (attr & 1) 3066 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3067 return; 3068 } 3069 rv = glyphcache_try(&dp->rd_gc, c, xd, yd, attr); 3070 if (rv == GC_OK) 3071 return; 3072 3073 data = WSFONT_GLYPH(c, font); 3074 3075 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3076 3077 radeonfb_wait_fifo(sc, 5); 3078 3079 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3080 RADEON_GMC_BRUSH_NONE | 3081 RADEON_GMC_SRC_DATATYPE_COLOR | 3082 RADEON_ROP3_S | 3083 RADEON_DP_SRC_SOURCE_HOST_DATA | 3084 RADEON_GMC_CLR_CMP_CNTL_DIS | 3085 RADEON_GMC_WR_MSK_DIS | 3086 gmc); 3087 3088 PUT32(sc, RADEON_DP_CNTL, 3089 RADEON_DST_X_LEFT_TO_RIGHT | 3090 RADEON_DST_Y_TOP_TO_BOTTOM); 3091 3092 PUT32(sc, RADEON_SRC_X_Y, 0); 3093 PUT32(sc, RADEON_DST_X_Y, (xd << 16) | yd); 3094 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (w << 16) | h); 3095 3096 rf = (fg >> 16) & 0xff; 3097 rb = (bg >> 16) & 0xff; 3098 gf = (fg >> 8) & 0xff; 3099 gb = (bg >> 8) & 0xff; 3100 bf = fg & 0xff; 3101 bb = bg & 0xff; 3102 3103 /* 3104 * I doubt we can upload data faster than even the slowest Radeon 3105 * could process them, especially when doing the alpha blending stuff 3106 * along the way, so just make sure there's some room in the FIFO and 3107 * then hammer away 3108 * As it turns out we can, so make periodic stops to let the FIFO 3109 * drain. 3110 */ 3111 radeonfb_wait_fifo(sc, 20); 3112 for (i = 0; i < ri->ri_fontscale; i++) { 3113 aval = *data; 3114 data++; 3115 if (aval == 0) { 3116 pixel = bg; 3117 } else if (aval == 255) { 3118 pixel = fg; 3119 } else { 3120 r = aval * rf + (255 - aval) * rb; 3121 g = aval * gf + (255 - aval) * gb; 3122 b = aval * bf + (255 - aval) * bb; 3123 pixel = (r & 0xff00) << 8 | 3124 (g & 0xff00) | 3125 (b & 0xff00) >> 8; 3126 } 3127 if (i & 16) 3128 radeonfb_wait_fifo(sc, 20); 3129 PUT32(sc, RADEON_HOST_DATA0, pixel); 3130 } 3131 if (rv == GC_ADD) { 3132 glyphcache_add(&dp->rd_gc, c, xd, yd); 3133 } else if (attr & 1) 3134 radeonfb_rectfill(dp, xd, yd + h - 2, w, 1, fg); 3135 } 3136 3137 static void 3138 radeonfb_putchar_aa8(void *cookie, int row, int col, u_int c, long attr) 3139 { 3140 struct rasops_info *ri = cookie; 3141 struct vcons_screen *scr = ri->ri_hw; 3142 struct radeonfb_display *dp = scr->scr_cookie; 3143 struct radeonfb_softc *sc = dp->rd_softc; 3144 struct wsdisplay_font *font = PICK_FONT(ri, c); 3145 uint32_t bg, fg, latch = 0, bg8, fg8, pixel, gmc; 3146 int i, x, y, wi, he, r, g, b, aval; 3147 int r1, g1, b1, r0, g0, b0, fgo, bgo; 3148 uint8_t *data8; 3149 int rv, cnt; 3150 3151 if (dp->rd_wsmode != WSDISPLAYIO_MODE_EMUL) 3152 return; 3153 3154 if (!CHAR_IN_FONT(c, font)) 3155 return; 3156 3157 wi = font->fontwidth; 3158 he = font->fontheight; 3159 3160 bg = ri->ri_devcmap[(attr >> 16) & 0xf]; 3161 fg = ri->ri_devcmap[(attr >> 24) & 0xf]; 3162 3163 x = ri->ri_xorigin + col * wi; 3164 y = ri->ri_yorigin + row * he; 3165 3166 if (c == 0x20) { 3167 radeonfb_rectfill(dp, x, y, wi, he, bg); 3168 if (attr & 1) 3169 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3170 return; 3171 } 3172 rv = glyphcache_try(&dp->rd_gc, c, x, y, attr); 3173 if (rv == GC_OK) 3174 return; 3175 3176 data8 = WSFONT_GLYPH(c, font); 3177 3178 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3179 3180 radeonfb_wait_fifo(sc, 5); 3181 3182 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3183 RADEON_GMC_BRUSH_NONE | 3184 RADEON_GMC_SRC_DATATYPE_COLOR | 3185 RADEON_ROP3_S | 3186 RADEON_DP_SRC_SOURCE_HOST_DATA | 3187 RADEON_GMC_CLR_CMP_CNTL_DIS | 3188 RADEON_GMC_WR_MSK_DIS | 3189 gmc); 3190 3191 PUT32(sc, RADEON_DP_CNTL, 3192 RADEON_DST_X_LEFT_TO_RIGHT | 3193 RADEON_DST_Y_TOP_TO_BOTTOM); 3194 3195 PUT32(sc, RADEON_SRC_X_Y, 0); 3196 PUT32(sc, RADEON_DST_X_Y, (x << 16) | y); 3197 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (wi << 16) | he); 3198 3199 /* 3200 * we need the RGB colours here, so get offsets into rasops_cmap 3201 */ 3202 fgo = ((attr >> 24) & 0xf) * 3; 3203 bgo = ((attr >> 16) & 0xf) * 3; 3204 3205 r0 = rasops_cmap[bgo]; 3206 r1 = rasops_cmap[fgo]; 3207 g0 = rasops_cmap[bgo + 1]; 3208 g1 = rasops_cmap[fgo + 1]; 3209 b0 = rasops_cmap[bgo + 2]; 3210 b1 = rasops_cmap[fgo + 2]; 3211 #define R3G3B2(r, g, b) ((r & 0xe0) | ((g >> 3) & 0x1c) | (b >> 6)) 3212 bg8 = R3G3B2(r0, g0, b0); 3213 fg8 = R3G3B2(r1, g1, b1); 3214 3215 radeonfb_wait_fifo(sc, 20); 3216 cnt = 0; 3217 for (i = 0; i < ri->ri_fontscale; i++) { 3218 aval = *data8; 3219 if (aval == 0) { 3220 pixel = bg8; 3221 } else if (aval == 255) { 3222 pixel = fg8; 3223 } else { 3224 r = aval * r1 + (255 - aval) * r0; 3225 g = aval * g1 + (255 - aval) * g0; 3226 b = aval * b1 + (255 - aval) * b0; 3227 pixel = ((r & 0xe000) >> 8) | 3228 ((g & 0xe000) >> 11) | 3229 ((b & 0xc000) >> 14); 3230 } 3231 latch |= pixel << (8 * (i & 3)); 3232 /* write in 32bit chunks */ 3233 if ((i & 3) == 3) { 3234 PUT32(sc, RADEON_HOST_DATA0, latch); 3235 /* 3236 * not strictly necessary, old data should be shifted 3237 * out 3238 */ 3239 latch = 0; 3240 cnt++; 3241 if (cnt > 16) { 3242 cnt = 0; 3243 radeonfb_wait_fifo(sc, 20); 3244 } 3245 } 3246 data8++; 3247 } 3248 /* if we have pixels left in latch write them out */ 3249 if ((i & 3) != 0) { 3250 /* 3251 * radeon is weird - apparently leftover pixels are written 3252 * from the middle, not from the left as everything else 3253 */ 3254 PUT32(sc, RADEON_HOST_DATA0, latch); 3255 } 3256 3257 if (rv == GC_ADD) { 3258 glyphcache_add(&dp->rd_gc, c, x, y); 3259 } else 3260 if (attr & 1) 3261 radeonfb_rectfill(dp, x, y + he - 2, wi, 1, fg); 3262 } 3263 3264 /* 3265 * wrapper for software character drawing 3266 * just sync the engine and call rasops*_putchar() 3267 */ 3268 3269 #ifndef RADEONFB_ALWAYS_ACCEL_PUTCHAR 3270 static void 3271 radeonfb_putchar_wrapper(void *cookie, int row, int col, u_int c, long attr) 3272 { 3273 struct rasops_info *ri = cookie; 3274 struct vcons_screen *scr = ri->ri_hw; 3275 struct radeonfb_display *dp = scr->scr_cookie; 3276 3277 radeonfb_engine_idle(dp->rd_softc); 3278 dp->rd_putchar(ri, row, col, c, attr); 3279 } 3280 #endif 3281 3282 static void 3283 radeonfb_eraserows(void *cookie, int row, int nrows, long fillattr) 3284 { 3285 struct rasops_info *ri = cookie; 3286 struct vcons_screen *scr = ri->ri_hw; 3287 struct radeonfb_display *dp = scr->scr_cookie; 3288 uint32_t x, y, w, h, fg, bg, ul; 3289 3290 /* XXX: check for full emulation mode? */ 3291 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3292 x = ri->ri_xorigin; 3293 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3294 w = ri->ri_emuwidth; 3295 h = ri->ri_font->fontheight * nrows; 3296 3297 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3298 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3299 } 3300 } 3301 3302 static void 3303 radeonfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 3304 { 3305 struct rasops_info *ri = cookie; 3306 struct vcons_screen *scr = ri->ri_hw; 3307 struct radeonfb_display *dp = scr->scr_cookie; 3308 uint32_t x, ys, yd, w, h; 3309 3310 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3311 x = ri->ri_xorigin; 3312 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 3313 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 3314 w = ri->ri_emuwidth; 3315 h = ri->ri_font->fontheight * nrows; 3316 radeonfb_bitblt(dp, x, ys, x, yd, w, h, 3317 RADEON_ROP3_S); 3318 } 3319 } 3320 3321 static void 3322 radeonfb_copycols(void *cookie, int row, int srccol, int dstcol, int ncols) 3323 { 3324 struct rasops_info *ri = cookie; 3325 struct vcons_screen *scr = ri->ri_hw; 3326 struct radeonfb_display *dp = scr->scr_cookie; 3327 uint32_t xs, xd, y, w, h; 3328 3329 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3330 xs = ri->ri_xorigin + ri->ri_font->fontwidth * srccol; 3331 xd = ri->ri_xorigin + ri->ri_font->fontwidth * dstcol; 3332 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3333 w = ri->ri_font->fontwidth * ncols; 3334 h = ri->ri_font->fontheight; 3335 radeonfb_bitblt(dp, xs, y, xd, y, w, h, 3336 RADEON_ROP3_S); 3337 } 3338 } 3339 3340 static void 3341 radeonfb_erasecols(void *cookie, int row, int startcol, int ncols, 3342 long fillattr) 3343 { 3344 struct rasops_info *ri = cookie; 3345 struct vcons_screen *scr = ri->ri_hw; 3346 struct radeonfb_display *dp = scr->scr_cookie; 3347 uint32_t x, y, w, h, fg, bg, ul; 3348 3349 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3350 x = ri->ri_xorigin + ri->ri_font->fontwidth * startcol; 3351 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 3352 w = ri->ri_font->fontwidth * ncols; 3353 h = ri->ri_font->fontheight; 3354 3355 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 3356 radeonfb_rectfill(dp, x, y, w, h, ri->ri_devcmap[bg & 0xf]); 3357 } 3358 } 3359 3360 static void 3361 radeonfb_cursor(void *cookie, int on, int row, int col) 3362 { 3363 struct rasops_info *ri = cookie; 3364 struct vcons_screen *scr = ri->ri_hw; 3365 struct radeonfb_display *dp = scr->scr_cookie; 3366 int x, y, wi, he; 3367 3368 wi = ri->ri_font->fontwidth; 3369 he = ri->ri_font->fontheight; 3370 3371 if (dp->rd_wsmode == WSDISPLAYIO_MODE_EMUL) { 3372 x = ri->ri_ccol * wi + ri->ri_xorigin; 3373 y = ri->ri_crow * he + ri->ri_yorigin; 3374 /* first turn off the old cursor */ 3375 if (ri->ri_flg & RI_CURSOR) { 3376 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3377 RADEON_ROP3_Dn); 3378 ri->ri_flg &= ~RI_CURSOR; 3379 } 3380 ri->ri_crow = row; 3381 ri->ri_ccol = col; 3382 /* then (possibly) turn on the new one */ 3383 if (on) { 3384 x = ri->ri_ccol * wi + ri->ri_xorigin; 3385 y = ri->ri_crow * he + ri->ri_yorigin; 3386 radeonfb_bitblt(dp, x, y, x, y, wi, he, 3387 RADEON_ROP3_Dn); 3388 ri->ri_flg |= RI_CURSOR; 3389 } 3390 } else { 3391 scr->scr_ri.ri_crow = row; 3392 scr->scr_ri.ri_ccol = col; 3393 scr->scr_ri.ri_flg &= ~RI_CURSOR; 3394 } 3395 } 3396 3397 /* 3398 * Underlying acceleration support. 3399 */ 3400 3401 static void 3402 radeonfb_rectfill(struct radeonfb_display *dp, int dstx, int dsty, 3403 int width, int height, uint32_t color) 3404 { 3405 struct radeonfb_softc *sc = dp->rd_softc; 3406 uint32_t gmc; 3407 3408 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3409 3410 radeonfb_wait_fifo(sc, 6); 3411 3412 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3413 RADEON_GMC_BRUSH_SOLID_COLOR | 3414 RADEON_GMC_SRC_DATATYPE_COLOR | 3415 RADEON_GMC_CLR_CMP_CNTL_DIS | 3416 RADEON_ROP3_P | gmc); 3417 3418 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, color); 3419 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3420 PUT32(sc, RADEON_DP_CNTL, 3421 RADEON_DST_X_LEFT_TO_RIGHT | 3422 RADEON_DST_Y_TOP_TO_BOTTOM); 3423 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3424 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3425 } 3426 3427 static void 3428 radeonfb_rectfill_a(void *cookie, int dstx, int dsty, 3429 int width, int height, long attr) 3430 { 3431 struct radeonfb_display *dp = cookie; 3432 3433 radeonfb_rectfill(dp, dstx, dsty, width, height, 3434 dp->rd_vscreen.scr_ri.ri_devcmap[(attr >> 24 & 0xf)]); 3435 } 3436 3437 static void 3438 radeonfb_bitblt(void *cookie, int srcx, int srcy, 3439 int dstx, int dsty, int width, int height, int rop) 3440 { 3441 struct radeonfb_display *dp = cookie; 3442 struct radeonfb_softc *sc = dp->rd_softc; 3443 uint32_t gmc; 3444 uint32_t dir; 3445 3446 if (dsty < srcy) { 3447 dir = RADEON_DST_Y_TOP_TO_BOTTOM; 3448 } else { 3449 srcy += height - 1; 3450 dsty += height - 1; 3451 dir = 0; 3452 } 3453 if (dstx < srcx) { 3454 dir |= RADEON_DST_X_LEFT_TO_RIGHT; 3455 } else { 3456 srcx += width - 1; 3457 dstx += width - 1; 3458 } 3459 3460 gmc = dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT; 3461 3462 radeonfb_wait_fifo(sc, 6); 3463 3464 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3465 RADEON_GMC_BRUSH_SOLID_COLOR | 3466 RADEON_GMC_SRC_DATATYPE_COLOR | 3467 RADEON_GMC_CLR_CMP_CNTL_DIS | 3468 RADEON_DP_SRC_SOURCE_MEMORY | 3469 rop | gmc); 3470 3471 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3472 PUT32(sc, RADEON_DP_CNTL, dir); 3473 PUT32(sc, RADEON_SRC_Y_X, (srcy << 16) | srcx); 3474 PUT32(sc, RADEON_DST_Y_X, (dsty << 16) | dstx); 3475 PUT32(sc, RADEON_DST_WIDTH_HEIGHT, (width << 16) | (height)); 3476 } 3477 3478 static void 3479 radeonfb_engine_idle(struct radeonfb_softc *sc) 3480 { 3481 3482 radeonfb_wait_fifo(sc, 64); 3483 while ((GET32(sc, RADEON_RBBM_STATUS) & 3484 RADEON_RBBM_ACTIVE) != 0); 3485 radeonfb_engine_flush(sc); 3486 } 3487 3488 static inline void 3489 radeonfb_wait_fifo(struct radeonfb_softc *sc, int n) 3490 { 3491 int i; 3492 3493 for (i = RADEON_TIMEOUT; i; i--) { 3494 if ((GET32(sc, RADEON_RBBM_STATUS) & 3495 RADEON_RBBM_FIFOCNT_MASK) >= n) 3496 return; 3497 } 3498 #ifdef DIAGNOSTIC 3499 if (!i) 3500 printf("%s: timed out waiting for fifo (%x)\n", 3501 XNAME(sc), GET32(sc, RADEON_RBBM_STATUS)); 3502 #endif 3503 } 3504 3505 static void 3506 radeonfb_engine_flush(struct radeonfb_softc *sc) 3507 { 3508 int i = 0; 3509 3510 if (IS_R300(sc)) { 3511 SET32(sc, R300_DSTCACHE_CTLSTAT, R300_RB2D_DC_FLUSH_ALL); 3512 while (GET32(sc, R300_DSTCACHE_CTLSTAT) & R300_RB2D_DC_BUSY) { 3513 i++; 3514 } 3515 } else { 3516 SET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT, 3517 RADEON_RB2D_DC_FLUSH_ALL); 3518 while (GET32(sc, RADEON_RB2D_DSTCACHE_CTLSTAT) & 3519 RADEON_RB2D_DC_BUSY) { 3520 i++; 3521 } 3522 } 3523 #ifdef DIAGNOSTIC 3524 if (i > RADEON_TIMEOUT) 3525 printf("%s: engine flush timed out!\n", XNAME(sc)); 3526 #endif 3527 } 3528 3529 static inline void 3530 radeonfb_unclip(struct radeonfb_softc *sc) 3531 { 3532 3533 radeonfb_wait_fifo(sc, 2); 3534 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3535 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3536 } 3537 3538 static void 3539 radeonfb_engine_init(struct radeonfb_display *dp) 3540 { 3541 struct radeonfb_softc *sc = dp->rd_softc; 3542 uint32_t pitch; 3543 3544 /* no 3D */ 3545 PUT32(sc, RADEON_RB3D_CNTL, 0); 3546 3547 radeonfb_engine_reset(sc); 3548 pitch = ((dp->rd_virtx * (dp->rd_bpp / 8) + 0x3f)) >> 6; 3549 3550 radeonfb_wait_fifo(sc, 1); 3551 if (!IS_R300(sc)) 3552 PUT32(sc, RADEON_RB2D_DSTCACHE_MODE, 0); 3553 3554 radeonfb_wait_fifo(sc, 3); 3555 PUT32(sc, RADEON_DEFAULT_PITCH_OFFSET, 3556 (pitch << 22) | (sc->sc_aperbase >> 10)); 3557 3558 3559 PUT32(sc, RADEON_DST_PITCH_OFFSET, 3560 (pitch << 22) | (sc->sc_aperbase >> 10)); 3561 PUT32(sc, RADEON_SRC_PITCH_OFFSET, 3562 (pitch << 22) | (sc->sc_aperbase >> 10)); 3563 3564 (void)GET32(sc, RADEON_DP_DATATYPE); 3565 3566 /* default scissors -- no clipping */ 3567 radeonfb_wait_fifo(sc, 1); 3568 PUT32(sc, RADEON_DEFAULT_SC_BOTTOM_RIGHT, 3569 RADEON_DEFAULT_SC_RIGHT_MAX | RADEON_DEFAULT_SC_BOTTOM_MAX); 3570 3571 radeonfb_wait_fifo(sc, 1); 3572 PUT32(sc, RADEON_DP_GUI_MASTER_CNTL, 3573 (dp->rd_format << RADEON_GMC_DST_DATATYPE_SHIFT) | 3574 RADEON_GMC_CLR_CMP_CNTL_DIS | 3575 RADEON_GMC_BRUSH_SOLID_COLOR | 3576 RADEON_GMC_SRC_DATATYPE_COLOR); 3577 3578 radeonfb_wait_fifo(sc, 10); 3579 PUT32(sc, RADEON_DST_LINE_START, 0); 3580 PUT32(sc, RADEON_DST_LINE_END, 0); 3581 PUT32(sc, RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff); 3582 PUT32(sc, RADEON_DP_BRUSH_BKGD_CLR, 0); 3583 PUT32(sc, RADEON_DP_SRC_FRGD_CLR, 0xffffffff); 3584 PUT32(sc, RADEON_DP_SRC_BKGD_CLR, 0); 3585 PUT32(sc, RADEON_DP_WRITE_MASK, 0xffffffff); 3586 PUT32(sc, RADEON_SC_TOP_LEFT, 0); 3587 PUT32(sc, RADEON_SC_BOTTOM_RIGHT, 0x1fff1fff); 3588 PUT32(sc, RADEON_AUX_SC_CNTL, 0); 3589 radeonfb_engine_idle(sc); 3590 } 3591 3592 static void 3593 radeonfb_engine_reset(struct radeonfb_softc *sc) 3594 { 3595 uint32_t hpc, rbbm, mclkcntl, clkindex; 3596 3597 radeonfb_engine_flush(sc); 3598 3599 clkindex = GET32(sc, RADEON_CLOCK_CNTL_INDEX); 3600 if (HAS_R300CG(sc)) 3601 radeonfb_r300cg_workaround(sc); 3602 mclkcntl = GETPLL(sc, RADEON_MCLK_CNTL); 3603 3604 /* 3605 * According to comments in XFree code, resetting the HDP via 3606 * the RBBM_SOFT_RESET can cause bad behavior on some systems. 3607 * So we use HOST_PATH_CNTL instead. 3608 */ 3609 3610 hpc = GET32(sc, RADEON_HOST_PATH_CNTL); 3611 rbbm = GET32(sc, RADEON_RBBM_SOFT_RESET); 3612 if (IS_R300(sc)) { 3613 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3614 RADEON_SOFT_RESET_CP | 3615 RADEON_SOFT_RESET_HI | 3616 RADEON_SOFT_RESET_E2); 3617 GET32(sc, RADEON_RBBM_SOFT_RESET); 3618 PUT32(sc, RADEON_RBBM_SOFT_RESET, 0); 3619 /* 3620 * XXX: this bit is not defined in any ATI docs I have, 3621 * nor in the XFree code, but XFree does it. Why? 3622 */ 3623 SET32(sc, RADEON_RB2D_DSTCACHE_MODE, (1<<17)); 3624 } else { 3625 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm | 3626 RADEON_SOFT_RESET_CP | 3627 RADEON_SOFT_RESET_SE | 3628 RADEON_SOFT_RESET_RE | 3629 RADEON_SOFT_RESET_PP | 3630 RADEON_SOFT_RESET_E2 | 3631 RADEON_SOFT_RESET_RB); 3632 GET32(sc, RADEON_RBBM_SOFT_RESET); 3633 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm & 3634 ~(RADEON_SOFT_RESET_CP | 3635 RADEON_SOFT_RESET_SE | 3636 RADEON_SOFT_RESET_RE | 3637 RADEON_SOFT_RESET_PP | 3638 RADEON_SOFT_RESET_E2 | 3639 RADEON_SOFT_RESET_RB)); 3640 GET32(sc, RADEON_RBBM_SOFT_RESET); 3641 } 3642 3643 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc | RADEON_HDP_SOFT_RESET); 3644 GET32(sc, RADEON_HOST_PATH_CNTL); 3645 PUT32(sc, RADEON_HOST_PATH_CNTL, hpc); 3646 3647 if (IS_R300(sc)) 3648 PUT32(sc, RADEON_RBBM_SOFT_RESET, rbbm); 3649 3650 PUT32(sc, RADEON_CLOCK_CNTL_INDEX, clkindex); 3651 PRINTREG(RADEON_CLOCK_CNTL_INDEX); 3652 PUTPLL(sc, RADEON_MCLK_CNTL, mclkcntl); 3653 3654 if (HAS_R300CG(sc)) 3655 radeonfb_r300cg_workaround(sc); 3656 } 3657 3658 static int 3659 radeonfb_set_curpos(struct radeonfb_display *dp, struct wsdisplay_curpos *pos) 3660 { 3661 int x, y; 3662 3663 x = pos->x; 3664 y = pos->y; 3665 3666 /* 3667 * This doesn't let a cursor move off the screen. I'm not 3668 * sure if this will have negative effects for e.g. Xinerama. 3669 * I'd guess Xinerama handles it by changing the cursor shape, 3670 * but that needs verification. 3671 */ 3672 if (x >= dp->rd_virtx) 3673 x = dp->rd_virtx - 1; 3674 if (x < 0) 3675 x = 0; 3676 if (y >= dp->rd_virty) 3677 y = dp->rd_virty - 1; 3678 if (y < 0) 3679 y = 0; 3680 3681 dp->rd_cursor.rc_pos.x = x; 3682 dp->rd_cursor.rc_pos.y = y; 3683 3684 radeonfb_cursor_position(dp); 3685 return 0; 3686 } 3687 3688 static int 3689 radeonfb_set_cursor(struct radeonfb_display *dp, struct wsdisplay_cursor *wc) 3690 { 3691 unsigned flags; 3692 3693 uint8_t r[2], g[2], b[2]; 3694 unsigned index, count; 3695 int i, err; 3696 int pitch, size; 3697 struct radeonfb_cursor nc; 3698 3699 flags = wc->which; 3700 3701 /* copy old values */ 3702 nc = dp->rd_cursor; 3703 3704 if (flags & WSDISPLAY_CURSOR_DOCMAP) { 3705 index = wc->cmap.index; 3706 count = wc->cmap.count; 3707 3708 if (index >= 2 || count > 2 - index) 3709 return EINVAL; 3710 3711 err = copyin(wc->cmap.red, &r[index], count); 3712 if (err) 3713 return err; 3714 err = copyin(wc->cmap.green, &g[index], count); 3715 if (err) 3716 return err; 3717 err = copyin(wc->cmap.blue, &b[index], count); 3718 if (err) 3719 return err; 3720 3721 for (i = index; i < index + count; i++) { 3722 nc.rc_cmap[i] = 3723 (r[i] << 16) + (g[i] << 8) + (b[i] << 0); 3724 } 3725 } 3726 3727 if (flags & WSDISPLAY_CURSOR_DOSHAPE) { 3728 if ((wc->size.x > RADEON_CURSORMAXX) || 3729 (wc->size.y > RADEON_CURSORMAXY)) 3730 return EINVAL; 3731 3732 /* figure bytes per line */ 3733 pitch = (wc->size.x + 7) / 8; 3734 size = pitch * wc->size.y; 3735 3736 /* clear the old cursor and mask */ 3737 memset(nc.rc_image, 0, 512); 3738 memset(nc.rc_mask, 0, 512); 3739 3740 nc.rc_size = wc->size; 3741 3742 if ((err = copyin(wc->image, nc.rc_image, size)) != 0) 3743 return err; 3744 3745 if ((err = copyin(wc->mask, nc.rc_mask, size)) != 0) 3746 return err; 3747 } 3748 3749 if (flags & WSDISPLAY_CURSOR_DOHOT) { 3750 nc.rc_hot = wc->hot; 3751 if (nc.rc_hot.x >= nc.rc_size.x) 3752 nc.rc_hot.x = nc.rc_size.x - 1; 3753 if (nc.rc_hot.y >= nc.rc_size.y) 3754 nc.rc_hot.y = nc.rc_size.y - 1; 3755 } 3756 3757 if (flags & WSDISPLAY_CURSOR_DOPOS) { 3758 nc.rc_pos = wc->pos; 3759 if (nc.rc_pos.x >= dp->rd_virtx) 3760 nc.rc_pos.x = dp->rd_virtx - 1; 3761 #if 0 3762 if (nc.rc_pos.x < 0) 3763 nc.rc_pos.x = 0; 3764 #endif 3765 if (nc.rc_pos.y >= dp->rd_virty) 3766 nc.rc_pos.y = dp->rd_virty - 1; 3767 #if 0 3768 if (nc.rc_pos.y < 0) 3769 nc.rc_pos.y = 0; 3770 #endif 3771 } 3772 if (flags & WSDISPLAY_CURSOR_DOCUR) { 3773 nc.rc_visible = wc->enable; 3774 } 3775 3776 dp->rd_cursor = nc; 3777 radeonfb_cursor_update(dp, wc->which); 3778 3779 return 0; 3780 } 3781 3782 static uint8_t 3783 radeonfb_backwards(uint8_t d) 3784 { 3785 uint8_t l; 3786 3787 l = d << 7; 3788 l |= ((d & 0x02) << 5); 3789 l |= ((d & 0x04) << 3); 3790 l |= ((d & 0x08) << 1); 3791 l |= ((d & 0x10) >> 1); 3792 l |= ((d & 0x20) >> 3); 3793 l |= ((d & 0x40) >> 5); 3794 l |= ((d & 0x80) >> 7); 3795 return l; 3796 } 3797 3798 /* 3799 * Change the cursor shape. Call this with the cursor locked to avoid 3800 * flickering/tearing. 3801 */ 3802 static void 3803 radeonfb_cursor_shape(struct radeonfb_display *dp) 3804 { 3805 uint8_t and[512], xor[512]; 3806 int i, j, src, dst /* , pitch */; 3807 const uint8_t *msk = dp->rd_cursor.rc_mask; 3808 const uint8_t *img = dp->rd_cursor.rc_image; 3809 3810 /* 3811 * Radeon cursor data interleaves one line of AND data followed 3812 * by a line of XOR data. (Each line corresponds to a whole hardware 3813 * pitch - i.e. 64 pixels or 8 bytes.) 3814 * 3815 * The cursor is displayed using the following table: 3816 * 3817 * AND XOR Result 3818 * ---------------------- 3819 * 0 0 Cursor color 0 3820 * 0 1 Cursor color 1 3821 * 1 0 Transparent 3822 * 1 1 Complement of background 3823 * 3824 * Our masks are therefore different from what we were passed. 3825 * Passed in, I'm assuming the data represents either color 0 or 1, 3826 * and a mask, so the passed in table looks like: 3827 * 3828 * IMG Mask Result 3829 * ----------------------- 3830 * 0 0 Transparent 3831 * 0 1 Cursor color 0 3832 * 1 0 Transparent 3833 * 1 1 Cursor color 1 3834 * 3835 * IF mask bit == 1, AND = 0, XOR = color. 3836 * IF mask bit == 0, AND = 1, XOR = 0. 3837 * 3838 * hence: AND = ~(mask); XOR = color & ~(mask); 3839 */ 3840 3841 /* pitch = ((dp->rd_cursor.rc_size.x + 7) / 8); */ 3842 3843 /* start by assuming all bits are transparent */ 3844 memset(and, 0xff, 512); 3845 memset(xor, 0x00, 512); 3846 3847 src = 0; 3848 dst = 0; 3849 for (i = 0; i < 64; i++) { 3850 for (j = 0; j < 64; j += 8) { 3851 if ((i < dp->rd_cursor.rc_size.y) && 3852 (j < dp->rd_cursor.rc_size.x)) { 3853 3854 /* take care to leave odd bits alone */ 3855 and[dst] &= ~(msk[src]); 3856 xor[dst] = img[src] & msk[src]; 3857 src++; 3858 } 3859 dst++; 3860 } 3861 } 3862 3863 for (i = 0; i < 512; i++) { 3864 and[i] = radeonfb_backwards(and[i]); 3865 xor[i] = radeonfb_backwards(xor[i]); 3866 } 3867 3868 /* copy the image into place */ 3869 for (i = 0; i < 64; i++) { 3870 memcpy((uint8_t *)dp->rd_curptr + (i * 16), 3871 &and[i * 8], 8); 3872 memcpy((uint8_t *)dp->rd_curptr + (i * 16) + 8, 3873 &xor[i * 8], 8); 3874 } 3875 } 3876 3877 static void 3878 radeonfb_cursor_position(struct radeonfb_display *dp) 3879 { 3880 struct radeonfb_softc *sc = dp->rd_softc; 3881 uint32_t offset, hvoff, hvpos; /* registers */ 3882 uint32_t coff; /* cursor offset */ 3883 int i, x, y, xoff, yoff, crtcoff; 3884 3885 /* 3886 * XXX: this also needs to handle pan/scan 3887 */ 3888 for (i = 0; i < dp->rd_ncrtcs; i++) { 3889 3890 struct radeonfb_crtc *rcp = &dp->rd_crtcs[i]; 3891 3892 if (rcp->rc_number) { 3893 offset = RADEON_CUR2_OFFSET; 3894 hvoff = RADEON_CUR2_HORZ_VERT_OFF; 3895 hvpos = RADEON_CUR2_HORZ_VERT_POSN; 3896 crtcoff = RADEON_CRTC2_OFFSET; 3897 } else { 3898 offset = RADEON_CUR_OFFSET; 3899 hvoff = RADEON_CUR_HORZ_VERT_OFF; 3900 hvpos = RADEON_CUR_HORZ_VERT_POSN; 3901 crtcoff = RADEON_CRTC_OFFSET; 3902 } 3903 3904 x = dp->rd_cursor.rc_pos.x; 3905 y = dp->rd_cursor.rc_pos.y; 3906 3907 while (y < rcp->rc_yoffset) { 3908 rcp->rc_yoffset -= RADEON_PANINCREMENT; 3909 } 3910 while (y >= (rcp->rc_yoffset + rcp->rc_videomode.vdisplay)) { 3911 rcp->rc_yoffset += RADEON_PANINCREMENT; 3912 } 3913 while (x < rcp->rc_xoffset) { 3914 rcp->rc_xoffset -= RADEON_PANINCREMENT; 3915 } 3916 while (x >= (rcp->rc_xoffset + rcp->rc_videomode.hdisplay)) { 3917 rcp->rc_xoffset += RADEON_PANINCREMENT; 3918 } 3919 3920 /* adjust for the cursor's hotspot */ 3921 x -= dp->rd_cursor.rc_hot.x; 3922 y -= dp->rd_cursor.rc_hot.y; 3923 xoff = yoff = 0; 3924 3925 if (x >= dp->rd_virtx) 3926 x = dp->rd_virtx - 1; 3927 if (y >= dp->rd_virty) 3928 y = dp->rd_virty - 1; 3929 3930 /* now adjust cursor so it is relative to viewport */ 3931 x -= rcp->rc_xoffset; 3932 y -= rcp->rc_yoffset; 3933 3934 /* 3935 * no need to check for fall off, because we should 3936 * never move off the screen entirely! 3937 */ 3938 coff = 0; 3939 if (x < 0) { 3940 xoff = -x; 3941 x = 0; 3942 } 3943 if (y < 0) { 3944 yoff = -y; 3945 y = 0; 3946 coff = (yoff * 2) * 8; 3947 } 3948 3949 /* pan the display */ 3950 PUT32(sc, crtcoff, (rcp->rc_yoffset * dp->rd_stride) + 3951 rcp->rc_xoffset); 3952 3953 PUT32(sc, offset, (dp->rd_curoff + coff) | RADEON_CUR_LOCK); 3954 PUT32(sc, hvoff, (xoff << 16) | (yoff) | RADEON_CUR_LOCK); 3955 /* NB: this unlocks the cursor */ 3956 PUT32(sc, hvpos, (x << 16) | y); 3957 } 3958 } 3959 3960 static void 3961 radeonfb_cursor_visible(struct radeonfb_display *dp) 3962 { 3963 int i; 3964 uint32_t gencntl, bit; 3965 3966 for (i = 0; i < dp->rd_ncrtcs; i++) { 3967 if (dp->rd_crtcs[i].rc_number) { 3968 gencntl = RADEON_CRTC2_GEN_CNTL; 3969 bit = RADEON_CRTC2_CUR_EN; 3970 } else { 3971 gencntl = RADEON_CRTC_GEN_CNTL; 3972 bit = RADEON_CRTC_CUR_EN; 3973 } 3974 3975 if (dp->rd_cursor.rc_visible) 3976 SET32(dp->rd_softc, gencntl, bit); 3977 else 3978 CLR32(dp->rd_softc, gencntl, bit); 3979 } 3980 } 3981 3982 static void 3983 radeonfb_cursor_cmap(struct radeonfb_display *dp) 3984 { 3985 int i; 3986 uint32_t c0reg, c1reg; 3987 struct radeonfb_softc *sc = dp->rd_softc; 3988 3989 for (i = 0; i < dp->rd_ncrtcs; i++) { 3990 if (dp->rd_crtcs[i].rc_number) { 3991 c0reg = RADEON_CUR2_CLR0; 3992 c1reg = RADEON_CUR2_CLR1; 3993 } else { 3994 c0reg = RADEON_CUR_CLR0; 3995 c1reg = RADEON_CUR_CLR1; 3996 } 3997 3998 PUT32(sc, c0reg, dp->rd_cursor.rc_cmap[0]); 3999 PUT32(sc, c1reg, dp->rd_cursor.rc_cmap[1]); 4000 } 4001 } 4002 4003 static void 4004 radeonfb_cursor_update(struct radeonfb_display *dp, unsigned which) 4005 { 4006 struct radeonfb_softc *sc; 4007 int i; 4008 4009 sc = dp->rd_softc; 4010 for (i = 0; i < dp->rd_ncrtcs; i++) { 4011 if (dp->rd_crtcs[i].rc_number) { 4012 SET32(sc, RADEON_CUR2_OFFSET, RADEON_CUR_LOCK); 4013 } else { 4014 SET32(sc, RADEON_CUR_OFFSET,RADEON_CUR_LOCK); 4015 } 4016 } 4017 4018 if (which & WSDISPLAY_CURSOR_DOCMAP) 4019 radeonfb_cursor_cmap(dp); 4020 4021 if (which & WSDISPLAY_CURSOR_DOSHAPE) 4022 radeonfb_cursor_shape(dp); 4023 4024 if (which & WSDISPLAY_CURSOR_DOCUR) 4025 radeonfb_cursor_visible(dp); 4026 4027 /* this one is unconditional, because it updates other stuff */ 4028 radeonfb_cursor_position(dp); 4029 } 4030 4031 static struct videomode * 4032 radeonfb_best_refresh(struct videomode *m1, struct videomode *m2) 4033 { 4034 int r1, r2; 4035 4036 /* otherwise pick the higher refresh rate */ 4037 r1 = DIVIDE(DIVIDE(m1->dot_clock, m1->htotal), m1->vtotal); 4038 r2 = DIVIDE(DIVIDE(m2->dot_clock, m2->htotal), m2->vtotal); 4039 4040 return (r1 < r2 ? m2 : m1); 4041 } 4042 4043 static const struct videomode * 4044 radeonfb_port_mode(struct radeonfb_softc *sc, struct radeonfb_port *rp, 4045 int x, int y) 4046 { 4047 struct edid_info *ep = &rp->rp_edid; 4048 struct videomode *vmp = NULL; 4049 int i; 4050 4051 if (!rp->rp_edid_valid) { 4052 /* fallback to safe mode */ 4053 return radeonfb_modelookup(sc->sc_defaultmode); 4054 } 4055 4056 /* always choose the preferred mode first! */ 4057 if (ep->edid_preferred_mode) { 4058 4059 /* XXX: add auto-stretching support for native mode */ 4060 4061 /* this may want panning to occur, btw */ 4062 if ((ep->edid_preferred_mode->hdisplay <= x) && 4063 (ep->edid_preferred_mode->vdisplay <= y)) 4064 return ep->edid_preferred_mode; 4065 } 4066 4067 for (i = 0; i < ep->edid_nmodes; i++) { 4068 /* 4069 * We elect to pick a resolution that is too large for 4070 * the monitor than one that is too small. This means 4071 * that we will prefer to pan rather than to try to 4072 * center a smaller display on a larger screen. In 4073 * practice, this shouldn't matter because if a 4074 * monitor can support a larger resolution, it can 4075 * probably also support the smaller. A specific 4076 * exception is fixed format panels, but hopefully 4077 * they are properly dealt with by the "autostretch" 4078 * logic above. 4079 */ 4080 if ((ep->edid_modes[i].hdisplay > x) || 4081 (ep->edid_modes[i].vdisplay > y)) { 4082 continue; 4083 } 4084 4085 /* 4086 * at this point, the display mode is no larger than 4087 * what we've requested. 4088 */ 4089 if (vmp == NULL) 4090 vmp = &ep->edid_modes[i]; 4091 4092 /* eliminate smaller modes */ 4093 if ((vmp->hdisplay >= ep->edid_modes[i].hdisplay) || 4094 (vmp->vdisplay >= ep->edid_modes[i].vdisplay)) 4095 continue; 4096 4097 if ((vmp->hdisplay < ep->edid_modes[i].hdisplay) || 4098 (vmp->vdisplay < ep->edid_modes[i].vdisplay)) { 4099 vmp = &ep->edid_modes[i]; 4100 continue; 4101 } 4102 4103 KASSERT(vmp->hdisplay == ep->edid_modes[i].hdisplay); 4104 KASSERT(vmp->vdisplay == ep->edid_modes[i].vdisplay); 4105 4106 vmp = radeonfb_best_refresh(vmp, &ep->edid_modes[i]); 4107 } 4108 4109 return (vmp ? vmp : radeonfb_modelookup(sc->sc_defaultmode)); 4110 } 4111 4112 static int 4113 radeonfb_hasres(struct videomode *list, int nlist, int x, int y) 4114 { 4115 int i; 4116 4117 for (i = 0; i < nlist; i++) { 4118 if ((x == list[i].hdisplay) && 4119 (y == list[i].vdisplay)) { 4120 return 1; 4121 } 4122 } 4123 return 0; 4124 } 4125 4126 static void 4127 radeonfb_pickres(struct radeonfb_display *dp, uint16_t *x, uint16_t *y, 4128 int pan) 4129 { 4130 struct radeonfb_port *rp; 4131 struct edid_info *ep; 4132 int i, j; 4133 4134 *x = 0; 4135 *y = 0; 4136 4137 if (pan) { 4138 for (i = 0; i < dp->rd_ncrtcs; i++) { 4139 rp = dp->rd_crtcs[i].rc_port; 4140 ep = &rp->rp_edid; 4141 if (!rp->rp_edid_valid) { 4142 /* monitor not present */ 4143 continue; 4144 } 4145 4146 /* 4147 * For now we are ignoring "conflict" that 4148 * could occur when mixing some modes like 4149 * 1280x1024 and 1400x800. It isn't clear 4150 * which is better, so the first one wins. 4151 */ 4152 for (j = 0; j < ep->edid_nmodes; j++) { 4153 /* 4154 * ignore resolutions that are too big for 4155 * the radeon 4156 */ 4157 if (ep->edid_modes[j].hdisplay > 4158 dp->rd_softc->sc_maxx) 4159 continue; 4160 if (ep->edid_modes[j].vdisplay > 4161 dp->rd_softc->sc_maxy) 4162 continue; 4163 4164 /* 4165 * pick largest resolution, the 4166 * smaller monitor will pan 4167 */ 4168 if ((ep->edid_modes[j].hdisplay >= *x) && 4169 (ep->edid_modes[j].vdisplay >= *y)) { 4170 *x = ep->edid_modes[j].hdisplay; 4171 *y = ep->edid_modes[j].vdisplay; 4172 } 4173 } 4174 } 4175 4176 } else { 4177 struct videomode modes[64]; 4178 int nmodes = 0; 4179 int valid = 0; 4180 4181 for (i = 0; i < dp->rd_ncrtcs; i++) { 4182 /* 4183 * pick the largest resolution in common. 4184 */ 4185 rp = dp->rd_crtcs[i].rc_port; 4186 ep = &rp->rp_edid; 4187 4188 if (!rp->rp_edid_valid) 4189 continue; 4190 4191 if (!valid) { 4192 /* 4193 * Pick the preferred mode for this port 4194 * if available. 4195 */ 4196 if (ep->edid_preferred_mode) { 4197 struct videomode *vmp = 4198 ep->edid_preferred_mode; 4199 4200 if ((vmp->hdisplay <= 4201 dp->rd_softc->sc_maxx) && 4202 (vmp->vdisplay <= 4203 dp->rd_softc->sc_maxy)) 4204 modes[nmodes++] = *vmp; 4205 } else { 4206 4207 /* initialize starting list */ 4208 for (j = 0; j < ep->edid_nmodes; j++) { 4209 /* 4210 * ignore resolutions that are 4211 * too big for the radeon 4212 */ 4213 if (ep->edid_modes[j].hdisplay > 4214 dp->rd_softc->sc_maxx) 4215 continue; 4216 if (ep->edid_modes[j].vdisplay > 4217 dp->rd_softc->sc_maxy) 4218 continue; 4219 4220 modes[nmodes] = 4221 ep->edid_modes[j]; 4222 nmodes++; 4223 } 4224 } 4225 valid = 1; 4226 } else { 4227 /* merge into preexisting list */ 4228 for (j = 0; j < nmodes; j++) { 4229 if (!radeonfb_hasres(ep->edid_modes, 4230 ep->edid_nmodes, 4231 modes[j].hdisplay, 4232 modes[j].vdisplay)) { 4233 modes[j] = modes[nmodes]; 4234 j--; 4235 nmodes--; 4236 } 4237 } 4238 } 4239 } 4240 4241 /* now we have to pick from the merged list */ 4242 for (i = 0; i < nmodes; i++) { 4243 if ((modes[i].hdisplay >= *x) && 4244 (modes[i].vdisplay >= *y)) { 4245 *x = modes[i].hdisplay; 4246 *y = modes[i].vdisplay; 4247 } 4248 } 4249 } 4250 4251 if ((*x == 0) || (*y == 0)) { 4252 /* fallback to safe mode */ 4253 *x = 640; 4254 *y = 480; 4255 } 4256 } 4257 4258 /* 4259 * backlight levels are linear on: 4260 * - RV200, RV250, RV280, RV350 4261 * - but NOT on PowerBook4,3 6,3 6,5 4262 * according to Linux' radeonfb 4263 */ 4264 4265 /* Get the current backlight level for the display. */ 4266 4267 static int 4268 radeonfb_get_backlight(struct radeonfb_display *dp) 4269 { 4270 int s; 4271 uint32_t level; 4272 4273 s = spltty(); 4274 4275 level = radeonfb_get32(dp->rd_softc, RADEON_LVDS_GEN_CNTL); 4276 level &= RADEON_LVDS_BL_MOD_LEV_MASK; 4277 level >>= RADEON_LVDS_BL_MOD_LEV_SHIFT; 4278 4279 /* 4280 * On some chips, we should negate the backlight level. 4281 * XXX Find out on which chips. 4282 */ 4283 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) 4284 level = RADEONFB_BACKLIGHT_MAX - level; 4285 4286 splx(s); 4287 4288 return level; 4289 } 4290 4291 /* Set the backlight to the given level for the display. */ 4292 static void 4293 radeonfb_switch_backlight(struct radeonfb_display *dp, int on) 4294 { 4295 if (dp->rd_bl_on == on) 4296 return; 4297 dp->rd_bl_on = on; 4298 radeonfb_set_backlight(dp, dp->rd_bl_level); 4299 } 4300 4301 static int 4302 radeonfb_set_backlight(struct radeonfb_display *dp, int level) 4303 { 4304 struct radeonfb_softc *sc = dp->rd_softc; 4305 int rlevel, s; 4306 uint32_t lvds; 4307 4308 if(!sc->sc_mapped) 4309 return 0; 4310 4311 s = spltty(); 4312 4313 dp->rd_bl_level = level; 4314 if (dp->rd_bl_on == 0) 4315 level = 0; 4316 4317 if (level < 0) 4318 level = 0; 4319 else if (level >= RADEONFB_BACKLIGHT_MAX) 4320 level = RADEONFB_BACKLIGHT_MAX; 4321 4322 /* On some chips, we should negate the backlight level. */ 4323 if (dp->rd_softc->sc_flags & RFB_INV_BLIGHT) { 4324 rlevel = RADEONFB_BACKLIGHT_MAX - level; 4325 } else 4326 rlevel = level; 4327 4328 callout_stop(&dp->rd_bl_lvds_co); 4329 radeonfb_engine_idle(sc); 4330 4331 /* 4332 * Turn off the display if the backlight is set to 0, since the 4333 * display is useless without backlight anyway. 4334 */ 4335 if (level == 0) 4336 radeonfb_blank(dp, 1); 4337 else if (radeonfb_get_backlight(dp) == 0) 4338 radeonfb_blank(dp, 0); 4339 4340 lvds = radeonfb_get32(sc, RADEON_LVDS_GEN_CNTL); 4341 lvds &= ~RADEON_LVDS_DISPLAY_DIS; 4342 if (!(lvds & RADEON_LVDS_BLON) || !(lvds & RADEON_LVDS_ON)) { 4343 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_DIGON; 4344 lvds |= RADEON_LVDS_BLON | RADEON_LVDS_EN; 4345 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4346 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4347 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4348 lvds |= RADEON_LVDS_ON; 4349 lvds |= dp->rd_bl_lvds_val & RADEON_LVDS_BL_MOD_EN; 4350 } else { 4351 lvds &= ~RADEON_LVDS_BL_MOD_LEV_MASK; 4352 lvds |= rlevel << RADEON_LVDS_BL_MOD_LEV_SHIFT; 4353 radeonfb_put32(sc, RADEON_LVDS_GEN_CNTL, lvds); 4354 } 4355 4356 dp->rd_bl_lvds_val &= ~RADEON_LVDS_STATE_MASK; 4357 dp->rd_bl_lvds_val |= lvds & RADEON_LVDS_STATE_MASK; 4358 /* XXX What is the correct delay? */ 4359 callout_schedule(&dp->rd_bl_lvds_co, 200 * hz); 4360 4361 splx(s); 4362 4363 return 0; 4364 } 4365 4366 /* 4367 * Callout function for delayed operations on the LVDS_GEN_CNTL register. 4368 * Set the delayed bits in the register, and clear the stored delayed 4369 * value. 4370 */ 4371 4372 static void radeonfb_lvds_callout(void *arg) 4373 { 4374 struct radeonfb_display *dp = arg; 4375 int s; 4376 4377 s = splhigh(); 4378 4379 radeonfb_mask32(dp->rd_softc, RADEON_LVDS_GEN_CNTL, ~0, 4380 dp->rd_bl_lvds_val); 4381 dp->rd_bl_lvds_val = 0; 4382 4383 splx(s); 4384 } 4385 4386 static void 4387 radeonfb_brightness_up(device_t dev) 4388 { 4389 struct radeonfb_softc *sc = device_private(dev); 4390 struct radeonfb_display *dp = &sc->sc_displays[0]; 4391 int level; 4392 4393 /* we assume the main display is the first one - need a better way */ 4394 if (sc->sc_ndisplays < 1) return; 4395 /* make sure pushing the hotkeys always has an effect */ 4396 dp->rd_bl_on = 1; 4397 level = dp->rd_bl_level; 4398 level = uimin(RADEONFB_BACKLIGHT_MAX, level + 5); 4399 radeonfb_set_backlight(dp, level); 4400 } 4401 4402 static void 4403 radeonfb_brightness_down(device_t dev) 4404 { 4405 struct radeonfb_softc *sc = device_private(dev); 4406 struct radeonfb_display *dp = &sc->sc_displays[0]; 4407 int level; 4408 4409 /* we assume the main display is the first one - need a better way */ 4410 if (sc->sc_ndisplays < 1) return; 4411 /* make sure pushing the hotkeys always has an effect */ 4412 dp->rd_bl_on = 1; 4413 level = dp->rd_bl_level; 4414 level = uimax(0, level - 5); 4415 radeonfb_set_backlight(dp, level); 4416 } 4417
Indexes created Tue Oct 21 19:09:51 GMT 2025