rccide.c revision 1.1
1 /* $NetBSD: rccide.c,v 1.1 2003/11/04 16:57:57 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.1 2003/11/04 16:57:57 mycroft Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 void serverworks_chip_map(struct pciide_softc *, struct pci_attach_args *); 41 void serverworks_setup_channel(struct channel_softc *); 42 int serverworks_pci_intr(void *); 43 44 int rccide_match(struct device *, struct cfdata *, void *); 45 void rccide_attach(struct device *, struct device *, void *); 46 47 CFATTACH_DECL(rccide, sizeof(struct pciide_softc), 48 rccide_match, rccide_attach, NULL, NULL); 49 50 const struct pciide_product_desc pciide_serverworks_products[] = { 51 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 52 0, 53 "ServerWorks OSB4 IDE Controller", 54 serverworks_chip_map, 55 }, 56 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 57 0, 58 "ServerWorks CSB5 IDE Controller", 59 serverworks_chip_map, 60 }, 61 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 62 0, 63 "ServerWorks CSB6 RAID/IDE Controller", 64 serverworks_chip_map, 65 }, 66 { 0, 67 0, 68 NULL, 69 NULL, 70 } 71 }; 72 73 int 74 rccide_match(struct device *parent, struct cfdata *match, void *aux) 75 { 76 struct pci_attach_args *pa = aux; 77 78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 79 if (pciide_lookup_product(pa->pa_id, pciide_serverworks_products)) 80 return (2); 81 } 82 return (0); 83 } 84 85 void 86 rccide_attach(struct device *parent, struct device *self, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 struct pciide_softc *sc = (void *)self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 93 } 94 95 void 96 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 97 { 98 struct pciide_channel *cp; 99 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 100 pcitag_t pcib_tag; 101 int channel; 102 bus_size_t cmdsize, ctlsize; 103 104 if (pciide_chipen(sc, pa) == 0) 105 return; 106 107 aprint_normal("%s: bus-master DMA support present", 108 sc->sc_wdcdev.sc_dev.dv_xname); 109 pciide_mapreg_dma(sc, pa); 110 aprint_normal("\n"); 111 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 112 WDC_CAPABILITY_MODE; 113 114 if (sc->sc_dma_ok) { 115 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 116 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 117 sc->sc_wdcdev.irqack = pciide_irqack; 118 } 119 sc->sc_wdcdev.PIO_cap = 4; 120 sc->sc_wdcdev.DMA_cap = 2; 121 switch (sc->sc_pp->ide_product) { 122 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 123 sc->sc_wdcdev.UDMA_cap = 2; 124 break; 125 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 126 if (PCI_REVISION(pa->pa_class) < 0x92) 127 sc->sc_wdcdev.UDMA_cap = 4; 128 else 129 sc->sc_wdcdev.UDMA_cap = 5; 130 break; 131 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 132 sc->sc_wdcdev.UDMA_cap = 5; 133 break; 134 } 135 136 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 137 sc->sc_wdcdev.channels = sc->wdc_chanarray; 138 sc->sc_wdcdev.nchannels = 2; 139 140 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 141 cp = &sc->pciide_channels[channel]; 142 if (pciide_chansetup(sc, channel, interface) == 0) 143 continue; 144 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 145 serverworks_pci_intr); 146 } 147 148 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 149 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 150 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 151 } 152 153 void 154 serverworks_setup_channel(struct channel_softc *chp) 155 { 156 struct ata_drive_datas *drvp; 157 struct pciide_channel *cp = (struct pciide_channel*)chp; 158 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 159 int channel = chp->channel; 160 int drive, unit; 161 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 162 u_int32_t idedma_ctl; 163 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 164 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 165 166 /* setup DMA if needed */ 167 pciide_channel_dma_setup(cp); 168 169 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 170 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 171 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 172 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 173 174 pio_time &= ~(0xffff << (16 * channel)); 175 dma_time &= ~(0xffff << (16 * channel)); 176 pio_mode &= ~(0xff << (8 * channel + 16)); 177 udma_mode &= ~(0xff << (8 * channel + 16)); 178 udma_mode &= ~(3 << (2 * channel)); 179 180 idedma_ctl = 0; 181 182 /* Per drive settings */ 183 for (drive = 0; drive < 2; drive++) { 184 drvp = &chp->ch_drive[drive]; 185 /* If no drive, skip */ 186 if ((drvp->drive_flags & DRIVE) == 0) 187 continue; 188 unit = drive + 2 * channel; 189 /* add timing values, setup DMA if needed */ 190 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 191 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 192 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 193 (drvp->drive_flags & DRIVE_UDMA)) { 194 /* use Ultra/DMA, check for 80-pin cable */ 195 if (drvp->UDMA_mode > 2 && 196 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 197 drvp->UDMA_mode = 2; 198 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 199 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 200 udma_mode |= 1 << unit; 201 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 202 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 203 (drvp->drive_flags & DRIVE_DMA)) { 204 /* use Multiword DMA */ 205 drvp->drive_flags &= ~DRIVE_UDMA; 206 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 207 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 208 } else { 209 /* PIO only */ 210 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 211 } 212 } 213 214 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 215 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 216 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 217 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 218 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 219 220 if (idedma_ctl != 0) { 221 /* Add software bits in status register */ 222 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 223 IDEDMA_CTL + IDEDMA_SCH_OFFSET * channel, idedma_ctl); 224 } 225 } 226 227 int 228 serverworks_pci_intr(arg) 229 void *arg; 230 { 231 struct pciide_softc *sc = arg; 232 struct pciide_channel *cp; 233 struct channel_softc *wdc_cp; 234 int rv = 0; 235 int dmastat, i, crv; 236 237 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 238 dmastat = bus_space_read_1(sc->sc_dma_iot, sc->sc_dma_ioh, 239 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i); 240 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 241 IDEDMA_CTL_INTR) 242 continue; 243 cp = &sc->pciide_channels[i]; 244 wdc_cp = &cp->wdc_channel; 245 crv = wdcintr(wdc_cp); 246 if (crv == 0) { 247 printf("%s:%d: bogus intr\n", 248 sc->sc_wdcdev.sc_dev.dv_xname, i); 249 bus_space_write_1(sc->sc_dma_iot, sc->sc_dma_ioh, 250 IDEDMA_CTL + IDEDMA_SCH_OFFSET * i, dmastat); 251 } else 252 rv = 1; 253 } 254 return rv; 255 } 256
Indexes created Fri Sep 26 08:10:20 GMT 2025