rccide.c revision 1.12
1 /* $NetBSD: rccide.c,v 1.12 2004/08/21 00:28:34 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.12 2004/08/21 00:28:34 thorpej Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 static void serverworks_chip_map(struct pciide_softc *, 41 struct pci_attach_args *); 42 static void serverworks_setup_channel(struct ata_channel *); 43 static int serverworks_pci_intr(void *); 44 static int serverworkscsb6_pci_intr(void *); 45 46 static int rccide_match(struct device *, struct cfdata *, void *); 47 static void rccide_attach(struct device *, struct device *, void *); 48 49 CFATTACH_DECL(rccide, sizeof(struct pciide_softc), 50 rccide_match, rccide_attach, NULL, NULL); 51 52 static const struct pciide_product_desc pciide_serverworks_products[] = { 53 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 54 0, 55 "ServerWorks OSB4 IDE Controller", 56 serverworks_chip_map, 57 }, 58 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 59 0, 60 "ServerWorks CSB5 IDE Controller", 61 serverworks_chip_map, 62 }, 63 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 64 0, 65 "ServerWorks CSB6 RAID/IDE Controller", 66 serverworks_chip_map, 67 }, 68 { PCI_PRODUCT_SERVERWORKS_CSB6_RAID, 69 0, 70 "ServerWorks CSB6 RAID/IDE Controller", 71 serverworks_chip_map, 72 }, 73 { 0, 74 0, 75 NULL, 76 NULL, 77 } 78 }; 79 80 static int 81 rccide_match(struct device *parent, struct cfdata *match, void *aux) 82 { 83 struct pci_attach_args *pa = aux; 84 85 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS && 86 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 87 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 88 if (pciide_lookup_product(pa->pa_id, 89 pciide_serverworks_products)) 90 return (2); 91 } 92 return (0); 93 } 94 95 static void 96 rccide_attach(struct device *parent, struct device *self, void *aux) 97 { 98 struct pci_attach_args *pa = aux; 99 struct pciide_softc *sc = (void *)self; 100 101 pciide_common_attach(sc, pa, 102 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 103 } 104 105 static void 106 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 107 { 108 struct pciide_channel *cp; 109 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 110 pcitag_t pcib_tag; 111 int channel; 112 bus_size_t cmdsize, ctlsize; 113 114 if (pciide_chipen(sc, pa) == 0) 115 return; 116 117 aprint_normal("%s: bus-master DMA support present", 118 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 119 pciide_mapreg_dma(sc, pa); 120 aprint_normal("\n"); 121 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 122 123 if (sc->sc_dma_ok) { 124 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 125 sc->sc_wdcdev.irqack = pciide_irqack; 126 } 127 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 128 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 129 switch (sc->sc_pp->ide_product) { 130 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 131 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 132 break; 133 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 134 if (PCI_REVISION(pa->pa_class) < 0x92) 135 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 136 else 137 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 138 break; 139 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 140 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 141 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 142 break; 143 } 144 145 sc->sc_wdcdev.sc_atac.atac_set_modes = serverworks_setup_channel; 146 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 147 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 148 149 wdc_allocate_regs(&sc->sc_wdcdev); 150 151 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 152 channel++) { 153 cp = &sc->pciide_channels[channel]; 154 if (pciide_chansetup(sc, channel, interface) == 0) 155 continue; 156 switch (sc->sc_pp->ide_product) { 157 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 158 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 159 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 160 serverworkscsb6_pci_intr); 161 break; 162 default: 163 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 164 serverworks_pci_intr); 165 } 166 } 167 168 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 169 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 170 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 171 } 172 173 static void 174 serverworks_setup_channel(struct ata_channel *chp) 175 { 176 struct ata_drive_datas *drvp; 177 struct atac_softc *atac = chp->ch_atac; 178 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 179 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 180 int channel = chp->ch_channel; 181 int drive, unit, s; 182 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 183 u_int32_t idedma_ctl; 184 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 185 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 186 187 /* setup DMA if needed */ 188 pciide_channel_dma_setup(cp); 189 190 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 191 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 192 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 193 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 194 195 pio_time &= ~(0xffff << (16 * channel)); 196 dma_time &= ~(0xffff << (16 * channel)); 197 pio_mode &= ~(0xff << (8 * channel + 16)); 198 udma_mode &= ~(0xff << (8 * channel + 16)); 199 udma_mode &= ~(3 << (2 * channel)); 200 201 idedma_ctl = 0; 202 203 /* Per drive settings */ 204 for (drive = 0; drive < 2; drive++) { 205 drvp = &chp->ch_drive[drive]; 206 /* If no drive, skip */ 207 if ((drvp->drive_flags & DRIVE) == 0) 208 continue; 209 unit = drive + 2 * channel; 210 /* add timing values, setup DMA if needed */ 211 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 212 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 213 if ((atac->atac_cap & ATAC_CAP_UDMA) && 214 (drvp->drive_flags & DRIVE_UDMA)) { 215 /* use Ultra/DMA, check for 80-pin cable */ 216 if (drvp->UDMA_mode > 2 && 217 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 218 PCI_SUBSYS_ID_REG)) 219 & (1 << (14 + channel))) == 0) 220 drvp->UDMA_mode = 2; 221 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 222 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 223 udma_mode |= 1 << unit; 224 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 225 } else if ((atac->atac_cap & ATAC_CAP_DMA) && 226 (drvp->drive_flags & DRIVE_DMA)) { 227 /* use Multiword DMA */ 228 s = splbio(); 229 drvp->drive_flags &= ~DRIVE_UDMA; 230 splx(s); 231 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 232 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 233 } else { 234 /* PIO only */ 235 s = splbio(); 236 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 237 splx(s); 238 } 239 } 240 241 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 242 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 243 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 244 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 245 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 246 247 if (idedma_ctl != 0) { 248 /* Add software bits in status register */ 249 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 250 idedma_ctl); 251 } 252 } 253 254 static int 255 serverworks_pci_intr(arg) 256 void *arg; 257 { 258 struct pciide_softc *sc = arg; 259 struct pciide_channel *cp; 260 struct ata_channel *wdc_cp; 261 int rv = 0; 262 int dmastat, i, crv; 263 264 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 265 cp = &sc->pciide_channels[i]; 266 dmastat = bus_space_read_1(sc->sc_dma_iot, 267 cp->dma_iohs[IDEDMA_CTL], 0); 268 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 269 IDEDMA_CTL_INTR) 270 continue; 271 wdc_cp = &cp->ata_channel; 272 crv = wdcintr(wdc_cp); 273 if (crv == 0) { 274 printf("%s:%d: bogus intr\n", 275 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 276 bus_space_write_1(sc->sc_dma_iot, 277 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 278 } else 279 rv = 1; 280 } 281 return rv; 282 } 283 284 static int 285 serverworkscsb6_pci_intr(arg) 286 void *arg; 287 { 288 struct pciide_softc *sc = arg; 289 struct pciide_channel *cp; 290 struct ata_channel *wdc_cp; 291 int rv = 0; 292 int i, crv; 293 294 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 295 cp = &sc->pciide_channels[i]; 296 wdc_cp = &cp->ata_channel; 297 /* 298 * The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands. 299 * Until we find a way to know if the controller posted an 300 * interrupt, always call wdcintr(), which will try to guess 301 * if the interrupt was for us or not (and checks 302 * IDEDMA_CTL_INTR for DMA commands only). 303 */ 304 crv = wdcintr(wdc_cp); 305 if (crv != 0) 306 rv = 1; 307 } 308 return rv; 309 } 310
Indexes created Fri Sep 26 08:10:20 GMT 2025