rccide.c revision 1.15
1 /* $NetBSD: rccide.c,v 1.15 2006/11/16 01:33:10 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.15 2006/11/16 01:33:10 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 static void serverworks_chip_map(struct pciide_softc *, 41 struct pci_attach_args *); 42 static void serverworks_setup_channel(struct ata_channel *); 43 static int serverworks_pci_intr(void *); 44 static int serverworkscsb6_pci_intr(void *); 45 46 static int rccide_match(struct device *, struct cfdata *, void *); 47 static void rccide_attach(struct device *, struct device *, void *); 48 49 CFATTACH_DECL(rccide, sizeof(struct pciide_softc), 50 rccide_match, rccide_attach, NULL, NULL); 51 52 static const struct pciide_product_desc pciide_serverworks_products[] = { 53 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 54 0, 55 "ServerWorks OSB4 IDE Controller", 56 serverworks_chip_map, 57 }, 58 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 59 0, 60 "ServerWorks CSB5 IDE Controller", 61 serverworks_chip_map, 62 }, 63 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 64 0, 65 "ServerWorks CSB6 RAID/IDE Controller", 66 serverworks_chip_map, 67 }, 68 { PCI_PRODUCT_SERVERWORKS_CSB6_RAID, 69 0, 70 "ServerWorks CSB6 RAID/IDE Controller", 71 serverworks_chip_map, 72 }, 73 { 0, 74 0, 75 NULL, 76 NULL, 77 } 78 }; 79 80 static int 81 rccide_match(struct device *parent, struct cfdata *match, 82 void *aux) 83 { 84 struct pci_attach_args *pa = aux; 85 86 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS && 87 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 88 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 89 if (pciide_lookup_product(pa->pa_id, 90 pciide_serverworks_products)) 91 return (2); 92 } 93 return (0); 94 } 95 96 static void 97 rccide_attach(struct device *parent, struct device *self, void *aux) 98 { 99 struct pci_attach_args *pa = aux; 100 struct pciide_softc *sc = (void *)self; 101 102 pciide_common_attach(sc, pa, 103 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 104 } 105 106 static void 107 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 108 { 109 struct pciide_channel *cp; 110 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 111 pcitag_t pcib_tag; 112 int channel; 113 bus_size_t cmdsize, ctlsize; 114 115 if (pciide_chipen(sc, pa) == 0) 116 return; 117 118 aprint_normal("%s: bus-master DMA support present", 119 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 120 pciide_mapreg_dma(sc, pa); 121 aprint_normal("\n"); 122 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 123 124 if (sc->sc_dma_ok) { 125 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 126 sc->sc_wdcdev.irqack = pciide_irqack; 127 } 128 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 129 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 130 switch (sc->sc_pp->ide_product) { 131 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 132 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 133 break; 134 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 135 if (PCI_REVISION(pa->pa_class) < 0x92) 136 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 137 else 138 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 139 break; 140 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 141 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 142 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 143 break; 144 } 145 146 sc->sc_wdcdev.sc_atac.atac_set_modes = serverworks_setup_channel; 147 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 148 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 149 150 wdc_allocate_regs(&sc->sc_wdcdev); 151 152 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 153 channel++) { 154 cp = &sc->pciide_channels[channel]; 155 if (pciide_chansetup(sc, channel, interface) == 0) 156 continue; 157 switch (sc->sc_pp->ide_product) { 158 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 159 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 160 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 161 serverworkscsb6_pci_intr); 162 break; 163 default: 164 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 165 serverworks_pci_intr); 166 } 167 } 168 169 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 170 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 171 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 172 } 173 174 static void 175 serverworks_setup_channel(struct ata_channel *chp) 176 { 177 struct ata_drive_datas *drvp; 178 struct atac_softc *atac = chp->ch_atac; 179 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 180 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 181 int channel = chp->ch_channel; 182 int drive, unit, s; 183 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 184 u_int32_t idedma_ctl; 185 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 186 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 187 188 /* setup DMA if needed */ 189 pciide_channel_dma_setup(cp); 190 191 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 192 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 193 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 194 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 195 196 pio_time &= ~(0xffff << (16 * channel)); 197 dma_time &= ~(0xffff << (16 * channel)); 198 pio_mode &= ~(0xff << (8 * channel + 16)); 199 udma_mode &= ~(0xff << (8 * channel + 16)); 200 udma_mode &= ~(3 << (2 * channel)); 201 202 idedma_ctl = 0; 203 204 /* Per drive settings */ 205 for (drive = 0; drive < 2; drive++) { 206 drvp = &chp->ch_drive[drive]; 207 /* If no drive, skip */ 208 if ((drvp->drive_flags & DRIVE) == 0) 209 continue; 210 unit = drive + 2 * channel; 211 /* add timing values, setup DMA if needed */ 212 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 213 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 214 if ((atac->atac_cap & ATAC_CAP_UDMA) && 215 (drvp->drive_flags & DRIVE_UDMA)) { 216 /* use Ultra/DMA, check for 80-pin cable */ 217 if (drvp->UDMA_mode > 2 && 218 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 219 PCI_SUBSYS_ID_REG)) 220 & (1 << (14 + channel))) == 0) 221 drvp->UDMA_mode = 2; 222 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 223 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 224 udma_mode |= 1 << unit; 225 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 226 } else if ((atac->atac_cap & ATAC_CAP_DMA) && 227 (drvp->drive_flags & DRIVE_DMA)) { 228 /* use Multiword DMA */ 229 s = splbio(); 230 drvp->drive_flags &= ~DRIVE_UDMA; 231 splx(s); 232 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 233 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 234 } else { 235 /* PIO only */ 236 s = splbio(); 237 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 238 splx(s); 239 } 240 } 241 242 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 243 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 244 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 245 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 246 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 247 248 if (idedma_ctl != 0) { 249 /* Add software bits in status register */ 250 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 251 idedma_ctl); 252 } 253 } 254 255 static int 256 serverworks_pci_intr(arg) 257 void *arg; 258 { 259 struct pciide_softc *sc = arg; 260 struct pciide_channel *cp; 261 struct ata_channel *wdc_cp; 262 int rv = 0; 263 int dmastat, i, crv; 264 265 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 266 cp = &sc->pciide_channels[i]; 267 dmastat = bus_space_read_1(sc->sc_dma_iot, 268 cp->dma_iohs[IDEDMA_CTL], 0); 269 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 270 IDEDMA_CTL_INTR) 271 continue; 272 wdc_cp = &cp->ata_channel; 273 crv = wdcintr(wdc_cp); 274 if (crv == 0) { 275 printf("%s:%d: bogus intr\n", 276 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, i); 277 bus_space_write_1(sc->sc_dma_iot, 278 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 279 } else 280 rv = 1; 281 } 282 return rv; 283 } 284 285 static int 286 serverworkscsb6_pci_intr(arg) 287 void *arg; 288 { 289 struct pciide_softc *sc = arg; 290 struct pciide_channel *cp; 291 struct ata_channel *wdc_cp; 292 int rv = 0; 293 int i, crv; 294 295 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 296 cp = &sc->pciide_channels[i]; 297 wdc_cp = &cp->ata_channel; 298 /* 299 * The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands. 300 * Until we find a way to know if the controller posted an 301 * interrupt, always call wdcintr(), which will try to guess 302 * if the interrupt was for us or not (and checks 303 * IDEDMA_CTL_INTR for DMA commands only). 304 */ 305 crv = wdcintr(wdc_cp); 306 if (crv != 0) 307 rv = 1; 308 } 309 return rv; 310 } 311
Indexes created Fri Sep 26 20:09:58 GMT 2025