rccide.c revision 1.26.2.2
1 /* $NetBSD: rccide.c,v 1.26.2.2 2014/08/20 00:03:48 tls Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.26.2.2 2014/08/20 00:03:48 tls Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 static void serverworks_chip_map(struct pciide_softc *, 41 const struct pci_attach_args *); 42 static void serverworks_setup_channel(struct ata_channel *); 43 static int serverworks_pci_intr(void *); 44 static int serverworkscsb6_pci_intr(void *); 45 46 static int rccide_match(device_t, cfdata_t, void *); 47 static void rccide_attach(device_t, device_t, void *); 48 49 CFATTACH_DECL_NEW(rccide, sizeof(struct pciide_softc), 50 rccide_match, rccide_attach, pciide_detach, NULL); 51 52 static const struct pciide_product_desc pciide_serverworks_products[] = { 53 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 54 0, 55 "ServerWorks OSB4 IDE Controller", 56 serverworks_chip_map, 57 }, 58 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 59 0, 60 "ServerWorks CSB5 IDE Controller", 61 serverworks_chip_map, 62 }, 63 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 64 0, 65 "ServerWorks CSB6 RAID/IDE Controller", 66 serverworks_chip_map, 67 }, 68 { PCI_PRODUCT_SERVERWORKS_CSB6_RAID, 69 0, 70 "ServerWorks CSB6 RAID/IDE Controller", 71 serverworks_chip_map, 72 }, 73 { PCI_PRODUCT_SERVERWORKS_HT1000_IDE, 74 0, 75 "ServerWorks HT-1000 IDE Controller", 76 serverworks_chip_map, 77 }, 78 { 0, 79 0, 80 NULL, 81 NULL, 82 } 83 }; 84 85 static int 86 rccide_match(device_t parent, cfdata_t match, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 90 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS && 91 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 92 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 93 if (pciide_lookup_product(pa->pa_id, 94 pciide_serverworks_products)) 95 return (2); 96 } 97 return (0); 98 } 99 100 static void 101 rccide_attach(device_t parent, device_t self, void *aux) 102 { 103 struct pci_attach_args *pa = aux; 104 struct pciide_softc *sc = device_private(self); 105 106 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 107 108 sc->sc_wdcdev.sc_atac.atac_dev = self; 109 110 pciide_common_attach(sc, pa, 111 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 112 } 113 114 static void 115 serverworks_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 116 { 117 struct pciide_channel *cp; 118 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 119 pcitag_t pcib_tag; 120 int channel; 121 122 if (pciide_chipen(sc, pa) == 0) 123 return; 124 125 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 126 "bus-master DMA support present"); 127 pciide_mapreg_dma(sc, pa); 128 aprint_verbose("\n"); 129 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 130 131 if (sc->sc_dma_ok) { 132 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 133 sc->sc_wdcdev.irqack = pciide_irqack; 134 } 135 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 136 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 137 switch (sc->sc_pp->ide_product) { 138 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 139 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 140 break; 141 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 142 if (PCI_REVISION(pa->pa_class) < 0x92) 143 sc->sc_wdcdev.sc_atac.atac_udma_cap = 4; 144 else 145 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 146 break; 147 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 148 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 149 case PCI_PRODUCT_SERVERWORKS_HT1000_IDE: 150 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 151 break; 152 } 153 154 sc->sc_wdcdev.sc_atac.atac_set_modes = serverworks_setup_channel; 155 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 156 sc->sc_wdcdev.sc_atac.atac_nchannels = 2; 157 sc->sc_wdcdev.wdc_maxdrives = 2; 158 159 wdc_allocate_regs(&sc->sc_wdcdev); 160 161 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 162 channel++) { 163 cp = &sc->pciide_channels[channel]; 164 if (pciide_chansetup(sc, channel, interface) == 0) 165 continue; 166 switch (sc->sc_pp->ide_product) { 167 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 168 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 169 pciide_mapchan(pa, cp, interface, 170 serverworkscsb6_pci_intr); 171 break; 172 default: 173 pciide_mapchan(pa, cp, interface, 174 serverworks_pci_intr); 175 } 176 } 177 178 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 179 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 180 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 181 } 182 183 static void 184 serverworks_setup_channel(struct ata_channel *chp) 185 { 186 struct ata_drive_datas *drvp; 187 struct atac_softc *atac = chp->ch_atac; 188 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 189 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 190 int channel = chp->ch_channel; 191 int drive, unit, s; 192 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 193 u_int32_t idedma_ctl; 194 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 195 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 196 197 /* setup DMA if needed */ 198 pciide_channel_dma_setup(cp); 199 200 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 201 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 202 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 203 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 204 205 pio_time &= ~(0xffff << (16 * channel)); 206 dma_time &= ~(0xffff << (16 * channel)); 207 pio_mode &= ~(0xff << (8 * channel + 16)); 208 udma_mode &= ~(0xff << (8 * channel + 16)); 209 udma_mode &= ~(3 << (2 * channel)); 210 211 idedma_ctl = 0; 212 213 /* Per drive settings */ 214 for (drive = 0; drive < 2; drive++) { 215 drvp = &chp->ch_drive[drive]; 216 /* If no drive, skip */ 217 if (drvp->drive_type == ATA_DRIVET_NONE) 218 continue; 219 unit = drive + 2 * channel; 220 /* add timing values, setup DMA if needed */ 221 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 222 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 223 if ((atac->atac_cap & ATAC_CAP_UDMA) && 224 (drvp->drive_flags & ATA_DRIVE_UDMA)) { 225 /* use Ultra/DMA, check for 80-pin cable */ 226 if (drvp->UDMA_mode > 2 && 227 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 228 PCI_SUBSYS_ID_REG)) 229 & (1 << (14 + channel))) == 0) 230 drvp->UDMA_mode = 2; 231 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 232 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 233 udma_mode |= 1 << unit; 234 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 235 } else if ((atac->atac_cap & ATAC_CAP_DMA) && 236 (drvp->drive_flags & ATA_DRIVE_DMA)) { 237 /* use Multiword DMA */ 238 s = splbio(); 239 drvp->drive_flags &= ~ATA_DRIVE_UDMA; 240 splx(s); 241 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 242 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 243 } else { 244 /* PIO only */ 245 s = splbio(); 246 drvp->drive_flags &= ~(ATA_DRIVE_UDMA | ATA_DRIVE_DMA); 247 splx(s); 248 } 249 } 250 251 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 252 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 253 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 254 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 255 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 256 257 if (idedma_ctl != 0) { 258 /* Add software bits in status register */ 259 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 260 idedma_ctl); 261 } 262 } 263 264 static int 265 serverworks_pci_intr(void *arg) 266 { 267 struct pciide_softc *sc = arg; 268 struct pciide_channel *cp; 269 struct ata_channel *wdc_cp; 270 int rv = 0; 271 int dmastat, i, crv; 272 273 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 274 cp = &sc->pciide_channels[i]; 275 dmastat = bus_space_read_1(sc->sc_dma_iot, 276 cp->dma_iohs[IDEDMA_CTL], 0); 277 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 278 IDEDMA_CTL_INTR) 279 continue; 280 wdc_cp = &cp->ata_channel; 281 crv = wdcintr(wdc_cp); 282 if (crv == 0) { 283 aprint_error("%s:%d: bogus intr\n", 284 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), i); 285 bus_space_write_1(sc->sc_dma_iot, 286 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 287 } else 288 rv = 1; 289 } 290 return rv; 291 } 292 293 static int 294 serverworkscsb6_pci_intr(void *arg) 295 { 296 struct pciide_softc *sc = arg; 297 struct pciide_channel *cp; 298 struct ata_channel *wdc_cp; 299 int rv = 0; 300 int i, crv; 301 302 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 303 cp = &sc->pciide_channels[i]; 304 wdc_cp = &cp->ata_channel; 305 /* 306 * The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands. 307 * Until we find a way to know if the controller posted an 308 * interrupt, always call wdcintr(), which will try to guess 309 * if the interrupt was for us or not (and checks 310 * IDEDMA_CTL_INTR for DMA commands only). 311 */ 312 crv = wdcintr(wdc_cp); 313 if (crv != 0) 314 rv = 1; 315 } 316 return rv; 317 } 318
Indexes created Fri Oct 03 02:09:57 GMT 2025