rccide.c revision 1.4
1 /* $NetBSD: rccide.c,v 1.4 2003/12/02 12:20:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2003 By Noon Software, Inc. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. The names of the authors may not be used to endorse or promote products 15 * derived from this software without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: rccide.c,v 1.4 2003/12/02 12:20:06 bouyer Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 40 void serverworks_chip_map(struct pciide_softc *, struct pci_attach_args *); 41 void serverworks_setup_channel(struct channel_softc *); 42 int serverworks_pci_intr(void *); 43 int serverworkscsb6_pci_intr(void *); 44 45 int rccide_match(struct device *, struct cfdata *, void *); 46 void rccide_attach(struct device *, struct device *, void *); 47 48 CFATTACH_DECL(rccide, sizeof(struct pciide_softc), 49 rccide_match, rccide_attach, NULL, NULL); 50 51 const struct pciide_product_desc pciide_serverworks_products[] = { 52 { PCI_PRODUCT_SERVERWORKS_OSB4_IDE, 53 0, 54 "ServerWorks OSB4 IDE Controller", 55 serverworks_chip_map, 56 }, 57 { PCI_PRODUCT_SERVERWORKS_CSB5_IDE, 58 0, 59 "ServerWorks CSB5 IDE Controller", 60 serverworks_chip_map, 61 }, 62 { PCI_PRODUCT_SERVERWORKS_CSB6_IDE, 63 0, 64 "ServerWorks CSB6 RAID/IDE Controller", 65 serverworks_chip_map, 66 }, 67 { PCI_PRODUCT_SERVERWORKS_CSB6_RAID, 68 0, 69 "ServerWorks CSB6 RAID/IDE Controller", 70 serverworks_chip_map, 71 }, 72 { 0, 73 0, 74 NULL, 75 NULL, 76 } 77 }; 78 79 int 80 rccide_match(struct device *parent, struct cfdata *match, void *aux) 81 { 82 struct pci_attach_args *pa = aux; 83 84 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS && 85 PCI_CLASS(pa->pa_class) == PCI_CLASS_MASS_STORAGE && 86 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 87 if (pciide_lookup_product(pa->pa_id, 88 pciide_serverworks_products)) 89 return (2); 90 } 91 return (0); 92 } 93 94 void 95 rccide_attach(struct device *parent, struct device *self, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 struct pciide_softc *sc = (void *)self; 99 100 pciide_common_attach(sc, pa, 101 pciide_lookup_product(pa->pa_id, pciide_serverworks_products)); 102 } 103 104 void 105 serverworks_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 106 { 107 struct pciide_channel *cp; 108 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 109 pcitag_t pcib_tag; 110 int channel; 111 bus_size_t cmdsize, ctlsize; 112 113 if (pciide_chipen(sc, pa) == 0) 114 return; 115 116 aprint_normal("%s: bus-master DMA support present", 117 sc->sc_wdcdev.sc_dev.dv_xname); 118 pciide_mapreg_dma(sc, pa); 119 aprint_normal("\n"); 120 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 121 WDC_CAPABILITY_MODE; 122 123 if (sc->sc_dma_ok) { 124 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 125 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 126 sc->sc_wdcdev.irqack = pciide_irqack; 127 } 128 sc->sc_wdcdev.PIO_cap = 4; 129 sc->sc_wdcdev.DMA_cap = 2; 130 switch (sc->sc_pp->ide_product) { 131 case PCI_PRODUCT_SERVERWORKS_OSB4_IDE: 132 sc->sc_wdcdev.UDMA_cap = 2; 133 break; 134 case PCI_PRODUCT_SERVERWORKS_CSB5_IDE: 135 if (PCI_REVISION(pa->pa_class) < 0x92) 136 sc->sc_wdcdev.UDMA_cap = 4; 137 else 138 sc->sc_wdcdev.UDMA_cap = 5; 139 break; 140 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 141 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 142 sc->sc_wdcdev.UDMA_cap = 5; 143 break; 144 } 145 146 sc->sc_wdcdev.set_modes = serverworks_setup_channel; 147 sc->sc_wdcdev.channels = sc->wdc_chanarray; 148 sc->sc_wdcdev.nchannels = 2; 149 150 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 151 cp = &sc->pciide_channels[channel]; 152 if (pciide_chansetup(sc, channel, interface) == 0) 153 continue; 154 switch (sc->sc_pp->ide_product) { 155 case PCI_PRODUCT_SERVERWORKS_CSB6_IDE: 156 case PCI_PRODUCT_SERVERWORKS_CSB6_RAID: 157 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 158 serverworkscsb6_pci_intr); 159 break; 160 default: 161 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 162 serverworks_pci_intr); 163 } 164 } 165 166 pcib_tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 0); 167 pci_conf_write(pa->pa_pc, pcib_tag, 0x64, 168 (pci_conf_read(pa->pa_pc, pcib_tag, 0x64) & ~0x2000) | 0x4000); 169 } 170 171 void 172 serverworks_setup_channel(struct channel_softc *chp) 173 { 174 struct ata_drive_datas *drvp; 175 struct pciide_channel *cp = (struct pciide_channel*)chp; 176 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 177 int channel = chp->channel; 178 int drive, unit; 179 u_int32_t pio_time, dma_time, pio_mode, udma_mode; 180 u_int32_t idedma_ctl; 181 static const u_int8_t pio_modes[5] = {0x5d, 0x47, 0x34, 0x22, 0x20}; 182 static const u_int8_t dma_modes[3] = {0x77, 0x21, 0x20}; 183 184 /* setup DMA if needed */ 185 pciide_channel_dma_setup(cp); 186 187 pio_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x40); 188 dma_time = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x44); 189 pio_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x48); 190 udma_mode = pci_conf_read(sc->sc_pc, sc->sc_tag, 0x54); 191 192 pio_time &= ~(0xffff << (16 * channel)); 193 dma_time &= ~(0xffff << (16 * channel)); 194 pio_mode &= ~(0xff << (8 * channel + 16)); 195 udma_mode &= ~(0xff << (8 * channel + 16)); 196 udma_mode &= ~(3 << (2 * channel)); 197 198 idedma_ctl = 0; 199 200 /* Per drive settings */ 201 for (drive = 0; drive < 2; drive++) { 202 drvp = &chp->ch_drive[drive]; 203 /* If no drive, skip */ 204 if ((drvp->drive_flags & DRIVE) == 0) 205 continue; 206 unit = drive + 2 * channel; 207 /* add timing values, setup DMA if needed */ 208 pio_time |= pio_modes[drvp->PIO_mode] << (8 * (unit^1)); 209 pio_mode |= drvp->PIO_mode << (4 * unit + 16); 210 if ((chp->wdc->cap & WDC_CAPABILITY_UDMA) && 211 (drvp->drive_flags & DRIVE_UDMA)) { 212 /* use Ultra/DMA, check for 80-pin cable */ 213 if (drvp->UDMA_mode > 2 && 214 (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_SUBSYS_ID_REG)) & (1 << (14 + channel))) == 0) 215 drvp->UDMA_mode = 2; 216 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 217 udma_mode |= drvp->UDMA_mode << (4 * unit + 16); 218 udma_mode |= 1 << unit; 219 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 220 } else if ((chp->wdc->cap & WDC_CAPABILITY_DMA) && 221 (drvp->drive_flags & DRIVE_DMA)) { 222 /* use Multiword DMA */ 223 drvp->drive_flags &= ~DRIVE_UDMA; 224 dma_time |= dma_modes[drvp->DMA_mode] << (8 * (unit^1)); 225 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 226 } else { 227 /* PIO only */ 228 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 229 } 230 } 231 232 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x40, pio_time); 233 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x44, dma_time); 234 if (sc->sc_pp->ide_product != PCI_PRODUCT_SERVERWORKS_OSB4_IDE) 235 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x48, pio_mode); 236 pci_conf_write(sc->sc_pc, sc->sc_tag, 0x54, udma_mode); 237 238 if (idedma_ctl != 0) { 239 /* Add software bits in status register */ 240 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 241 idedma_ctl); 242 } 243 } 244 245 int 246 serverworks_pci_intr(arg) 247 void *arg; 248 { 249 struct pciide_softc *sc = arg; 250 struct pciide_channel *cp; 251 struct channel_softc *wdc_cp; 252 int rv = 0; 253 int dmastat, i, crv; 254 255 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 256 cp = &sc->pciide_channels[i]; 257 dmastat = bus_space_read_1(sc->sc_dma_iot, 258 cp->dma_iohs[IDEDMA_CTL], 0); 259 if ((dmastat & (IDEDMA_CTL_ACT | IDEDMA_CTL_INTR)) != 260 IDEDMA_CTL_INTR) 261 continue; 262 wdc_cp = &cp->wdc_channel; 263 crv = wdcintr(wdc_cp); 264 if (crv == 0) { 265 printf("%s:%d: bogus intr\n", 266 sc->sc_wdcdev.sc_dev.dv_xname, i); 267 bus_space_write_1(sc->sc_dma_iot, 268 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 269 } else 270 rv = 1; 271 } 272 return rv; 273 } 274 275 int 276 serverworkscsb6_pci_intr(arg) 277 void *arg; 278 { 279 struct pciide_softc *sc = arg; 280 struct pciide_channel *cp; 281 struct channel_softc *wdc_cp; 282 int rv = 0; 283 int i, crv; 284 285 for (i = 0; i < sc->sc_wdcdev.nchannels; i++) { 286 cp = &sc->pciide_channels[i]; 287 wdc_cp = &cp->wdc_channel; 288 /* 289 * The CSB6 doesn't assert IDEDMA_CTL_INTR for non-DMA commands. 290 * Until we find a way to know if the controller posted an 291 * interrupt, always call wdcintr(), which will try to guess 292 * if the interrupt was for us or not (and checks 293 * IDEDMA_CTL_INTR for DMA commands only). 294 */ 295 crv = wdcintr(wdc_cp); 296 if (crv != 0) 297 rv = 1; 298 } 299 return rv; 300 } 301
Indexes created Fri Sep 26 20:09:58 GMT 2025