1 1.8 msaitoh /* $NetBSD: rdcide.c,v 1.8 2014/07/08 18:01:26 msaitoh Exp $ */ 2 1.1 bouyer 3 1.1 bouyer /* 4 1.1 bouyer * Copyright (c) 2011 Manuel Bouyer. 5 1.1 bouyer * 6 1.1 bouyer * Redistribution and use in source and binary forms, with or without 7 1.1 bouyer * modification, are permitted provided that the following conditions 8 1.1 bouyer * are met: 9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright 10 1.1 bouyer * notice, this list of conditions and the following disclaimer. 11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright 12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the 13 1.1 bouyer * documentation and/or other materials provided with the distribution. 14 1.1 bouyer * 15 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 1.1 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 1.1 bouyer */ 26 1.1 bouyer 27 1.1 bouyer #include <sys/cdefs.h> 28 1.8 msaitoh __KERNEL_RCSID(0, "$NetBSD: rdcide.c,v 1.8 2014/07/08 18:01:26 msaitoh Exp $"); 29 1.1 bouyer 30 1.1 bouyer #include <sys/param.h> 31 1.1 bouyer #include <sys/systm.h> 32 1.1 bouyer 33 1.1 bouyer #include <dev/pci/pcivar.h> 34 1.1 bouyer #include <dev/pci/pcidevs.h> 35 1.1 bouyer #include <dev/pci/pciidereg.h> 36 1.1 bouyer #include <dev/pci/pciidevar.h> 37 1.1 bouyer #include <dev/pci/rdcide_reg.h> 38 1.1 bouyer 39 1.2 dyoung static void rdcide_chip_map(struct pciide_softc *, 40 1.2 dyoung const struct pci_attach_args *); 41 1.1 bouyer static void rdcide_setup_channel(struct ata_channel *); 42 1.1 bouyer 43 1.1 bouyer static bool rdcide_resume(device_t, const pmf_qual_t *); 44 1.1 bouyer static bool rdcide_suspend(device_t, const pmf_qual_t *); 45 1.1 bouyer static int rdcide_match(device_t, cfdata_t, void *); 46 1.1 bouyer static void rdcide_attach(device_t, device_t, void *); 47 1.1 bouyer 48 1.1 bouyer static const struct pciide_product_desc pciide_intel_products[] = { 49 1.8 msaitoh { PCI_PRODUCT_RDC_R1011_IDE, 50 1.1 bouyer 0, 51 1.8 msaitoh "RDC R1011 IDE controller", 52 1.8 msaitoh rdcide_chip_map, 53 1.8 msaitoh }, 54 1.8 msaitoh { PCI_PRODUCT_RDC_R1012_IDE, 55 1.8 msaitoh 0, 56 1.8 msaitoh "RDC R1012 IDE controller", 57 1.1 bouyer rdcide_chip_map, 58 1.1 bouyer }, 59 1.1 bouyer }; 60 1.1 bouyer 61 1.1 bouyer CFATTACH_DECL_NEW(rdcide, sizeof(struct pciide_softc), 62 1.1 bouyer rdcide_match, rdcide_attach, NULL, NULL); 63 1.1 bouyer 64 1.1 bouyer static int 65 1.1 bouyer rdcide_match(device_t parent, cfdata_t match, void *aux) 66 1.1 bouyer { 67 1.1 bouyer struct pci_attach_args *pa = aux; 68 1.1 bouyer 69 1.1 bouyer if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC) { 70 1.1 bouyer if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 71 1.1 bouyer return (2); 72 1.1 bouyer } 73 1.1 bouyer return (0); 74 1.1 bouyer } 75 1.1 bouyer 76 1.1 bouyer static void 77 1.1 bouyer rdcide_attach(device_t parent, device_t self, void *aux) 78 1.1 bouyer { 79 1.1 bouyer struct pci_attach_args *pa = aux; 80 1.1 bouyer struct pciide_softc *sc = device_private(self); 81 1.1 bouyer 82 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_dev = self; 83 1.1 bouyer 84 1.1 bouyer pciide_common_attach(sc, pa, 85 1.1 bouyer pciide_lookup_product(pa->pa_id, pciide_intel_products)); 86 1.1 bouyer 87 1.1 bouyer if (!pmf_device_register(self, rdcide_suspend, rdcide_resume)) 88 1.1 bouyer aprint_error_dev(self, "couldn't establish power handler\n"); 89 1.1 bouyer } 90 1.1 bouyer 91 1.1 bouyer static bool 92 1.1 bouyer rdcide_resume(device_t dv, const pmf_qual_t *qual) 93 1.1 bouyer { 94 1.1 bouyer struct pciide_softc *sc = device_private(dv); 95 1.1 bouyer 96 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, 97 1.1 bouyer sc->sc_pm_reg[0]); 98 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, 99 1.1 bouyer sc->sc_pm_reg[1]); 100 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, 101 1.1 bouyer sc->sc_pm_reg[2]); 102 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, 103 1.1 bouyer sc->sc_pm_reg[3]); 104 1.1 bouyer 105 1.1 bouyer return true; 106 1.1 bouyer } 107 1.1 bouyer 108 1.1 bouyer static bool 109 1.1 bouyer rdcide_suspend(device_t dv, const pmf_qual_t *qual) 110 1.1 bouyer { 111 1.1 bouyer struct pciide_softc *sc = device_private(dv); 112 1.1 bouyer 113 1.1 bouyer sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 114 1.1 bouyer RDCIDE_PATR); 115 1.1 bouyer sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 116 1.1 bouyer RDCIDE_PSD1ATR); 117 1.1 bouyer sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, 118 1.1 bouyer RDCIDE_UDCCR); 119 1.1 bouyer sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, 120 1.1 bouyer RDCIDE_IIOCR); 121 1.1 bouyer 122 1.1 bouyer return true; 123 1.1 bouyer } 124 1.1 bouyer 125 1.1 bouyer static void 126 1.2 dyoung rdcide_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 127 1.1 bouyer { 128 1.1 bouyer struct pciide_channel *cp; 129 1.1 bouyer int channel; 130 1.1 bouyer u_int32_t patr; 131 1.1 bouyer pcireg_t interface = PCI_INTERFACE(pa->pa_class); 132 1.1 bouyer 133 1.1 bouyer if (pciide_chipen(sc, pa) == 0) 134 1.1 bouyer return; 135 1.1 bouyer 136 1.1 bouyer aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 137 1.1 bouyer "bus-master DMA support present"); 138 1.1 bouyer pciide_mapreg_dma(sc, pa); 139 1.1 bouyer aprint_verbose("\n"); 140 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 141 1.1 bouyer if (sc->sc_dma_ok) { 142 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 143 1.1 bouyer sc->sc_wdcdev.irqack = pciide_irqack; 144 1.1 bouyer sc->sc_wdcdev.dma_init = pciide_dma_init; 145 1.1 bouyer } 146 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 147 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 148 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 149 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_set_modes = rdcide_setup_channel; 150 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 151 1.1 bouyer sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 152 1.7 bouyer sc->sc_wdcdev.wdc_maxdrives = 2; 153 1.1 bouyer 154 1.1 bouyer ATADEBUG_PRINT(("rdcide_setup_chip: old PATR=0x%x", 155 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 156 1.1 bouyer DEBUG_PROBE); 157 1.1 bouyer ATADEBUG_PRINT((", PSD1ATR=0x%x", 158 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 159 1.1 bouyer DEBUG_PROBE); 160 1.1 bouyer ATADEBUG_PRINT((", UDCCR 0x%x", 161 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 162 1.1 bouyer DEBUG_PROBE); 163 1.1 bouyer ATADEBUG_PRINT((", IIOCR 0x%x", 164 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 165 1.1 bouyer DEBUG_PROBE); 166 1.1 bouyer ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 167 1.1 bouyer 168 1.1 bouyer wdc_allocate_regs(&sc->sc_wdcdev); 169 1.1 bouyer 170 1.1 bouyer for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 171 1.1 bouyer channel++) { 172 1.1 bouyer cp = &sc->pciide_channels[channel]; 173 1.1 bouyer if (pciide_chansetup(sc, channel, interface) == 0) 174 1.1 bouyer continue; 175 1.1 bouyer patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 176 1.1 bouyer if ((patr & RDCIDE_PATR_EN(channel)) == 0) { 177 1.1 bouyer aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 178 1.1 bouyer "%s channel ignored (disabled)\n", cp->name); 179 1.1 bouyer cp->ata_channel.ch_flags |= ATACH_DISABLED; 180 1.1 bouyer continue; 181 1.1 bouyer } 182 1.1 bouyer pciide_mapchan(pa, cp, interface, pciide_pci_intr); 183 1.1 bouyer } 184 1.1 bouyer ATADEBUG_PRINT(("rdcide_setup_chip: PATR=0x%x", 185 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 186 1.1 bouyer DEBUG_PROBE); 187 1.1 bouyer ATADEBUG_PRINT((", PSD1ATR=0x%x", 188 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 189 1.1 bouyer DEBUG_PROBE); 190 1.1 bouyer ATADEBUG_PRINT((", UDCCR 0x%x", 191 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 192 1.1 bouyer DEBUG_PROBE); 193 1.1 bouyer ATADEBUG_PRINT((", IIOCR 0x%x", 194 1.1 bouyer pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 195 1.1 bouyer DEBUG_PROBE); 196 1.1 bouyer ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 197 1.1 bouyer 198 1.1 bouyer } 199 1.1 bouyer 200 1.1 bouyer static void 201 1.1 bouyer rdcide_setup_channel(struct ata_channel *chp) 202 1.1 bouyer { 203 1.1 bouyer u_int8_t drive; 204 1.1 bouyer u_int32_t patr, psd1atr, udccr, iiocr; 205 1.1 bouyer struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 206 1.1 bouyer struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 207 1.1 bouyer struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 208 1.1 bouyer 209 1.1 bouyer patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 210 1.1 bouyer psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR); 211 1.1 bouyer udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR); 212 1.1 bouyer iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR); 213 1.1 bouyer 214 1.1 bouyer /* setup DMA */ 215 1.1 bouyer pciide_channel_dma_setup(cp); 216 1.1 bouyer 217 1.1 bouyer /* clear modes */ 218 1.1 bouyer patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1)); 219 1.1 bouyer psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->ch_channel); 220 1.1 bouyer psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->ch_channel); 221 1.1 bouyer for (drive = 0; drive < 2; drive++) { 222 1.1 bouyer udccr &= ~RDCIDE_UDCCR_EN(chp->ch_channel, drive); 223 1.1 bouyer udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->ch_channel, drive); 224 1.1 bouyer iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->ch_channel, drive); 225 1.1 bouyer } 226 1.1 bouyer /* now setup modes */ 227 1.1 bouyer for (drive = 0; drive < 2; drive++) { 228 1.7 bouyer if (drvp[drive].drive_type == ATA_DRIVET_NONE) 229 1.1 bouyer continue; 230 1.7 bouyer if (drvp[drive].drive_type == ATA_DRIVET_ATAPI) 231 1.1 bouyer patr |= RDCIDE_PATR_ATA(chp->ch_channel, drive); 232 1.1 bouyer if (drive == 0) { 233 1.1 bouyer patr |= RDCIDE_PATR_SETUP( 234 1.1 bouyer rdcide_setup[drvp[drive].PIO_mode], 235 1.1 bouyer chp->ch_channel); 236 1.1 bouyer patr |= RDCIDE_PATR_HOLD( 237 1.1 bouyer rdcide_hold[drvp[drive].PIO_mode], 238 1.1 bouyer chp->ch_channel); 239 1.1 bouyer } else { 240 1.1 bouyer patr |= RDCIDE_PATR_DEV1_TEN(chp->ch_channel); 241 1.1 bouyer psd1atr |= RDCIDE_PSD1ATR_SETUP( 242 1.1 bouyer rdcide_setup[drvp[drive].PIO_mode], 243 1.1 bouyer chp->ch_channel); 244 1.1 bouyer psd1atr |= RDCIDE_PSD1ATR_HOLD( 245 1.1 bouyer rdcide_hold[drvp[drive].PIO_mode], 246 1.1 bouyer chp->ch_channel); 247 1.1 bouyer } 248 1.1 bouyer if (drvp[drive].PIO_mode > 0) { 249 1.1 bouyer patr |= RDCIDE_PATR_FTIM(chp->ch_channel, drive); 250 1.1 bouyer patr |= RDCIDE_PATR_IORDY(chp->ch_channel, drive); 251 1.1 bouyer } 252 1.7 bouyer if (drvp[drive].drive_flags & ATA_DRIVE_DMA) { 253 1.1 bouyer patr |= RDCIDE_PATR_DMAEN(chp->ch_channel, drive); 254 1.1 bouyer } 255 1.7 bouyer if ((drvp[drive].drive_flags & ATA_DRIVE_UDMA) == 0) 256 1.1 bouyer continue; 257 1.1 bouyer 258 1.1 bouyer if ((iiocr & RDCIDE_IIOCR_CABLE(chp->ch_channel, drive)) == 0 259 1.1 bouyer && drvp[drive].UDMA_mode > 2) 260 1.1 bouyer drvp[drive].UDMA_mode = 2; 261 1.1 bouyer udccr |= RDCIDE_UDCCR_EN(chp->ch_channel, drive); 262 1.1 bouyer udccr |= RDCIDE_UDCCR_TIM( 263 1.1 bouyer rdcide_udmatim[drvp[drive].UDMA_mode], 264 1.1 bouyer chp->ch_channel, drive); 265 1.1 bouyer iiocr |= RDCIDE_IIOCR_CLK( 266 1.1 bouyer rdcide_udmaclk[drvp[drive].UDMA_mode], 267 1.1 bouyer chp->ch_channel, drive); 268 1.1 bouyer } 269 1.1 bouyer 270 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr); 271 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr); 272 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr); 273 1.1 bouyer pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr); 274 1.1 bouyer } 275