rdcide.c revision 1.1
1 /* $NetBSD: rdcide.c,v 1.1 2011/04/04 14:33:51 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: rdcide.c,v 1.1 2011/04/04 14:33:51 bouyer Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/rdcide_reg.h> 38 39 static void rdcide_chip_map(struct pciide_softc*, struct pci_attach_args *); 40 static void rdcide_setup_channel(struct ata_channel *); 41 42 static bool rdcide_resume(device_t, const pmf_qual_t *); 43 static bool rdcide_suspend(device_t, const pmf_qual_t *); 44 static int rdcide_match(device_t, cfdata_t, void *); 45 static void rdcide_attach(device_t, device_t, void *); 46 47 static const struct pciide_product_desc pciide_intel_products[] = { 48 { PCI_PRODUCT_RDC_IDE, 49 0, 50 "RDC IDE controller", 51 rdcide_chip_map, 52 }, 53 }; 54 55 CFATTACH_DECL_NEW(rdcide, sizeof(struct pciide_softc), 56 rdcide_match, rdcide_attach, NULL, NULL); 57 58 static int 59 rdcide_match(device_t parent, cfdata_t match, void *aux) 60 { 61 struct pci_attach_args *pa = aux; 62 63 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RDC) { 64 if (pciide_lookup_product(pa->pa_id, pciide_intel_products)) 65 return (2); 66 } 67 return (0); 68 } 69 70 static void 71 rdcide_attach(device_t parent, device_t self, void *aux) 72 { 73 struct pci_attach_args *pa = aux; 74 struct pciide_softc *sc = device_private(self); 75 76 sc->sc_wdcdev.sc_atac.atac_dev = self; 77 78 pciide_common_attach(sc, pa, 79 pciide_lookup_product(pa->pa_id, pciide_intel_products)); 80 81 if (!pmf_device_register(self, rdcide_suspend, rdcide_resume)) 82 aprint_error_dev(self, "couldn't establish power handler\n"); 83 } 84 85 static bool 86 rdcide_resume(device_t dv, const pmf_qual_t *qual) 87 { 88 struct pciide_softc *sc = device_private(dv); 89 90 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, 91 sc->sc_pm_reg[0]); 92 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, 93 sc->sc_pm_reg[1]); 94 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, 95 sc->sc_pm_reg[2]); 96 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, 97 sc->sc_pm_reg[3]); 98 99 return true; 100 } 101 102 static bool 103 rdcide_suspend(device_t dv, const pmf_qual_t *qual) 104 { 105 struct pciide_softc *sc = device_private(dv); 106 107 sc->sc_pm_reg[0] = pci_conf_read(sc->sc_pc, sc->sc_tag, 108 RDCIDE_PATR); 109 sc->sc_pm_reg[1] = pci_conf_read(sc->sc_pc, sc->sc_tag, 110 RDCIDE_PSD1ATR); 111 sc->sc_pm_reg[2] = pci_conf_read(sc->sc_pc, sc->sc_tag, 112 RDCIDE_UDCCR); 113 sc->sc_pm_reg[3] = pci_conf_read(sc->sc_pc, sc->sc_tag, 114 RDCIDE_IIOCR); 115 116 return true; 117 } 118 119 static void 120 rdcide_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 121 { 122 struct pciide_channel *cp; 123 int channel; 124 u_int32_t patr; 125 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 126 127 if (pciide_chipen(sc, pa) == 0) 128 return; 129 130 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 131 "bus-master DMA support present"); 132 pciide_mapreg_dma(sc, pa); 133 aprint_verbose("\n"); 134 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 135 if (sc->sc_dma_ok) { 136 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 137 sc->sc_wdcdev.irqack = pciide_irqack; 138 sc->sc_wdcdev.dma_init = pciide_dma_init; 139 } 140 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 141 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 142 sc->sc_wdcdev.sc_atac.atac_udma_cap = 5; 143 sc->sc_wdcdev.sc_atac.atac_set_modes = rdcide_setup_channel; 144 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 145 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 146 147 ATADEBUG_PRINT(("rdcide_setup_chip: old PATR=0x%x", 148 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 149 DEBUG_PROBE); 150 ATADEBUG_PRINT((", PSD1ATR=0x%x", 151 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 152 DEBUG_PROBE); 153 ATADEBUG_PRINT((", UDCCR 0x%x", 154 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 155 DEBUG_PROBE); 156 ATADEBUG_PRINT((", IIOCR 0x%x", 157 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 158 DEBUG_PROBE); 159 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 160 161 wdc_allocate_regs(&sc->sc_wdcdev); 162 163 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 164 channel++) { 165 cp = &sc->pciide_channels[channel]; 166 if (pciide_chansetup(sc, channel, interface) == 0) 167 continue; 168 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 169 if ((patr & RDCIDE_PATR_EN(channel)) == 0) { 170 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 171 "%s channel ignored (disabled)\n", cp->name); 172 cp->ata_channel.ch_flags |= ATACH_DISABLED; 173 continue; 174 } 175 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 176 } 177 ATADEBUG_PRINT(("rdcide_setup_chip: PATR=0x%x", 178 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR)), 179 DEBUG_PROBE); 180 ATADEBUG_PRINT((", PSD1ATR=0x%x", 181 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR)), 182 DEBUG_PROBE); 183 ATADEBUG_PRINT((", UDCCR 0x%x", 184 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR)), 185 DEBUG_PROBE); 186 ATADEBUG_PRINT((", IIOCR 0x%x", 187 pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR)), 188 DEBUG_PROBE); 189 ATADEBUG_PRINT(("\n"), DEBUG_PROBE); 190 191 } 192 193 static void 194 rdcide_setup_channel(struct ata_channel *chp) 195 { 196 u_int8_t drive; 197 u_int32_t patr, psd1atr, udccr, iiocr; 198 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 199 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 200 struct ata_drive_datas *drvp = cp->ata_channel.ch_drive; 201 202 patr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PATR); 203 psd1atr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR); 204 udccr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR); 205 iiocr = pci_conf_read(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR); 206 207 /* setup DMA */ 208 pciide_channel_dma_setup(cp); 209 210 /* clear modes */ 211 patr = patr & (RDCIDE_PATR_EN(0) | RDCIDE_PATR_EN(1)); 212 psd1atr &= ~RDCIDE_PSD1ATR_SETUP_MASK(chp->ch_channel); 213 psd1atr &= ~RDCIDE_PSD1ATR_HOLD_MASK(chp->ch_channel); 214 for (drive = 0; drive < 2; drive++) { 215 udccr &= ~RDCIDE_UDCCR_EN(chp->ch_channel, drive); 216 udccr &= ~RDCIDE_UDCCR_TIM_MASK(chp->ch_channel, drive); 217 iiocr &= ~RDCIDE_IIOCR_CLK_MASK(chp->ch_channel, drive); 218 } 219 /* now setup modes */ 220 for (drive = 0; drive < 2; drive++) { 221 if ((drvp[drive].drive_flags & DRIVE) == 0) 222 continue; 223 if ((drvp[drive].drive_flags & DRIVE_ATAPI) == 0) 224 patr |= RDCIDE_PATR_ATA(chp->ch_channel, drive); 225 if (drive == 0) { 226 patr |= RDCIDE_PATR_SETUP( 227 rdcide_setup[drvp[drive].PIO_mode], 228 chp->ch_channel); 229 patr |= RDCIDE_PATR_HOLD( 230 rdcide_hold[drvp[drive].PIO_mode], 231 chp->ch_channel); 232 } else { 233 patr |= RDCIDE_PATR_DEV1_TEN(chp->ch_channel); 234 psd1atr |= RDCIDE_PSD1ATR_SETUP( 235 rdcide_setup[drvp[drive].PIO_mode], 236 chp->ch_channel); 237 psd1atr |= RDCIDE_PSD1ATR_HOLD( 238 rdcide_hold[drvp[drive].PIO_mode], 239 chp->ch_channel); 240 } 241 if (drvp[drive].PIO_mode > 0) { 242 patr |= RDCIDE_PATR_FTIM(chp->ch_channel, drive); 243 patr |= RDCIDE_PATR_IORDY(chp->ch_channel, drive); 244 } 245 if (drvp[drive].drive_flags & DRIVE_DMA) { 246 patr |= RDCIDE_PATR_DMAEN(chp->ch_channel, drive); 247 } 248 if ((drvp[drive].drive_flags & DRIVE_UDMA) == 0) 249 continue; 250 251 if ((iiocr & RDCIDE_IIOCR_CABLE(chp->ch_channel, drive)) == 0 252 && drvp[drive].UDMA_mode > 2) 253 drvp[drive].UDMA_mode = 2; 254 udccr |= RDCIDE_UDCCR_EN(chp->ch_channel, drive); 255 udccr |= RDCIDE_UDCCR_TIM( 256 rdcide_udmatim[drvp[drive].UDMA_mode], 257 chp->ch_channel, drive); 258 iiocr |= RDCIDE_IIOCR_CLK( 259 rdcide_udmaclk[drvp[drive].UDMA_mode], 260 chp->ch_channel, drive); 261 } 262 263 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PATR, patr); 264 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_PSD1ATR, psd1atr); 265 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_UDCCR, udccr); 266 pci_conf_write(sc->sc_pc, sc->sc_tag, RDCIDE_IIOCR, iiocr); 267 } 268
Indexes created Fri Sep 26 20:09:58 GMT 2025