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rdcide_reg.h revision 1.1 
      1 /*      $NetBSD: rdcide_reg.h,v 1.1 2011/04/04 14:33:51 bouyer Exp $    */
      2 
      3 /*
      4  * Copyright (c) 2011 Manuel Bouyer.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     25  *
     26  */
     27 
     28 /*
     29  * register definitions for the RDC ide controller as found in the
     30  * PMX-1000 SoC
     31  */
     32 /* ATA Timing Register */
     33 #define RDCIDE_PATR 0x40
     34 #define RDCIDE_PATR_EN(chan)		(0x8000 << ((chan) * 16))
     35 #define RDCIDE_PATR_DEV1_TEN(chan)	(0x4000 << ((chan) * 16))
     36 #define RDCIDE_PATR_SETUP(val, chan)	(((val) << 12) << ((chan) * 16))
     37 #define RDCIDE_PATR_SETUP_MASK(chan)	(0x3000 << ((chan) * 16))
     38 #define RDCIDE_PATR_HOLD(val, chan)	(((val) << 8) << ((chan) * 16))
     39 #define RDCIDE_PATR_HOLD_MASK(chan)	(0x0300 << ((chan) * 16))
     40 #define RDCIDE_PATR_DMAEN(chan, drv)	((0x0008 << (drv * 4)) << ((chan) * 16))
     41 #define RDCIDE_PATR_ATA(chan, drv)	((0x0004 << (drv * 4)) << ((chan) * 16))
     42 #define RDCIDE_PATR_IORDY(chan, drv)	((0x0002 << (drv * 4)) << ((chan) * 16))
     43 #define RDCIDE_PATR_FTIM(chan, drv)	((0x0001 << (drv * 4)) << ((chan) * 16))
     44 
     45 /* Primary and Secondary Device 1 ATA Timing */
     46 #define RDCIDE_PSD1ATR 0x44
     47 #define RDCIDE_PSD1ATR_SETUP(val, chan)	(((val) << 2) << (chan * 4))
     48 #define RDCIDE_PSD1ATR_SETUP_MASK(chan)	(0x0c << (chan * 4))
     49 #define RDCIDE_PSD1ATR_HOLD(val, chan)	(((val) << 0) << (chan * 4))
     50 #define RDCIDE_PSD1ATR_HOLD_MASK(chan)	(0x03 << (chan * 4))
     51 
     52 const uint8_t rdcide_setup[] = {0, 0, 1, 2, 2};
     53 const uint8_t rdcide_hold[] = {0, 0, 0, 1, 3};
     54 
     55 /* Ultra DMA Control and timing Register */
     56 #define RDCIDE_UDCCR	0x48
     57 #define RDCIDE_UDCCR_EN(chan, drv)	((1 << (drv)) << (chan * 2))
     58 #define RDCIDE_UDCCR_TIM(val, chan, drv) (((val) << ((drv) * 4)) << (chan * 8))
     59 #define RDCIDE_UDCCR_TIM_MASK(chan, drv) ((0x3 << ((drv) * 4)) << (chan * 8))
     60 
     61 const uint8_t rdcide_udmatim[] = {0, 1, 2, 1, 2, 1};
     62 
     63 /* IDE I/O Configuration Registers */
     64 #define RDCIDE_IIOCR	0x54
     65 #define RDCIDE_IIOCR_CABLE(chan, drv)	((0x10 << (drv)) << (chan * 2))
     66 #define RDCIDE_IIOCR_CLK(val, chan, drv) (((val) << drv) << (chan * 2))
     67 #define RDCIDE_IIOCR_CLK_MASK(chan, drv) ((0x1001 << drv) << (chan * 2))
     68 
     69 const uint32_t rdcide_udmaclk[] =
     70     {0x0000, 0x0000, 0x0000, 0x0001, 0x0001, 0x1000};
     71 
     72 /* Miscellaneous Control Register */
     73 #define RDCIDE_MCR	0x90
     74 #define RDCIDE_MCR_RESET(chan)	(0x01000000 << (chan))
     75