satalink.c revision 1.15
1 /* $NetBSD: satalink.c,v 1.15 2004/05/28 23:26:58 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 #include <dev/ata/satavar.h> 51 #include <dev/ata/atareg.h> 52 53 /* 54 * Register map for BA5 register space, indexed by channel. 55 */ 56 static const struct { 57 bus_addr_t ba5_IDEDMA_CMD; 58 bus_addr_t ba5_IDEDMA_CTL; 59 bus_addr_t ba5_IDEDMA_TBL; 60 bus_addr_t ba5_IDEDMA_CMD2; 61 bus_addr_t ba5_IDEDMA_CTL2; 62 bus_addr_t ba5_IDE_TF0; 63 bus_addr_t ba5_IDE_TF1; 64 bus_addr_t ba5_IDE_TF2; 65 bus_addr_t ba5_IDE_TF3; 66 bus_addr_t ba5_IDE_TF4; 67 bus_addr_t ba5_IDE_TF5; 68 bus_addr_t ba5_IDE_TF6; 69 bus_addr_t ba5_IDE_TF7; 70 bus_addr_t ba5_IDE_TF8; 71 bus_addr_t ba5_IDE_RAD; 72 bus_addr_t ba5_IDE_TF9; 73 bus_addr_t ba5_IDE_TF10; 74 bus_addr_t ba5_IDE_TF11; 75 bus_addr_t ba5_IDE_TF12; 76 bus_addr_t ba5_IDE_TF13; 77 bus_addr_t ba5_IDE_TF14; 78 bus_addr_t ba5_IDE_TF15; 79 bus_addr_t ba5_IDE_TF16; 80 bus_addr_t ba5_IDE_TF17; 81 bus_addr_t ba5_IDE_TF18; 82 bus_addr_t ba5_IDE_TF19; 83 bus_addr_t ba5_IDE_RABC; 84 bus_addr_t ba5_IDE_CMD_STS; 85 bus_addr_t ba5_IDE_CFG_STS; 86 bus_addr_t ba5_IDE_DTM; 87 bus_addr_t ba5_SControl; 88 bus_addr_t ba5_SStatus; 89 bus_addr_t ba5_SError; 90 bus_addr_t ba5_SActive; /* 3114 */ 91 bus_addr_t ba5_SMisc; 92 bus_addr_t ba5_PHY_CONFIG; 93 bus_addr_t ba5_SIEN; 94 bus_addr_t ba5_SFISCfg; 95 } satalink_ba5_regmap[] = { 96 { /* Channel 0 */ 97 .ba5_IDEDMA_CMD = 0x000, 98 .ba5_IDEDMA_CTL = 0x002, 99 .ba5_IDEDMA_TBL = 0x004, 100 .ba5_IDEDMA_CMD2 = 0x010, 101 .ba5_IDEDMA_CTL2 = 0x012, 102 .ba5_IDE_TF0 = 0x080, /* wd_data */ 103 .ba5_IDE_TF1 = 0x081, /* wd_error */ 104 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 105 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 106 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 107 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 108 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 109 .ba5_IDE_TF7 = 0x087, /* wd_command */ 110 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 111 .ba5_IDE_RAD = 0x08c, 112 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 113 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 114 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 115 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 116 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 117 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 118 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 119 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 120 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 121 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 122 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 123 .ba5_IDE_RABC = 0x09c, 124 .ba5_IDE_CMD_STS = 0x0a0, 125 .ba5_IDE_CFG_STS = 0x0a1, 126 .ba5_IDE_DTM = 0x0b4, 127 .ba5_SControl = 0x100, 128 .ba5_SStatus = 0x104, 129 .ba5_SError = 0x108, 130 .ba5_SActive = 0x10c, 131 .ba5_SMisc = 0x140, 132 .ba5_PHY_CONFIG = 0x144, 133 .ba5_SIEN = 0x148, 134 .ba5_SFISCfg = 0x14c, 135 }, 136 { /* Channel 1 */ 137 .ba5_IDEDMA_CMD = 0x008, 138 .ba5_IDEDMA_CTL = 0x00a, 139 .ba5_IDEDMA_TBL = 0x00c, 140 .ba5_IDEDMA_CMD2 = 0x018, 141 .ba5_IDEDMA_CTL2 = 0x01a, 142 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 143 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 144 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 145 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 146 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 147 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 148 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 149 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 150 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 151 .ba5_IDE_RAD = 0x0cc, 152 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 153 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 154 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 155 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 156 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 157 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 158 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 159 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 160 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 161 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 162 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 163 .ba5_IDE_RABC = 0x0dc, 164 .ba5_IDE_CMD_STS = 0x0e0, 165 .ba5_IDE_CFG_STS = 0x0e1, 166 .ba5_IDE_DTM = 0x0f4, 167 .ba5_SControl = 0x180, 168 .ba5_SStatus = 0x184, 169 .ba5_SError = 0x188, 170 .ba5_SActive = 0x18c, 171 .ba5_SMisc = 0x1c0, 172 .ba5_PHY_CONFIG = 0x1c4, 173 .ba5_SIEN = 0x1c8, 174 .ba5_SFISCfg = 0x1cc, 175 }, 176 { /* Channel 2 (3114) */ 177 .ba5_IDEDMA_CMD = 0x200, 178 .ba5_IDEDMA_CTL = 0x202, 179 .ba5_IDEDMA_TBL = 0x204, 180 .ba5_IDEDMA_CMD2 = 0x210, 181 .ba5_IDEDMA_CTL2 = 0x212, 182 .ba5_IDE_TF0 = 0x280, /* wd_data */ 183 .ba5_IDE_TF1 = 0x281, /* wd_error */ 184 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 185 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 186 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 187 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 188 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 189 .ba5_IDE_TF7 = 0x287, /* wd_command */ 190 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 191 .ba5_IDE_RAD = 0x28c, 192 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 193 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 194 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 195 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 196 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 197 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 198 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 199 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 200 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 201 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 202 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 203 .ba5_IDE_RABC = 0x29c, 204 .ba5_IDE_CMD_STS = 0x2a0, 205 .ba5_IDE_CFG_STS = 0x2a1, 206 .ba5_IDE_DTM = 0x2b4, 207 .ba5_SControl = 0x300, 208 .ba5_SStatus = 0x304, 209 .ba5_SError = 0x308, 210 .ba5_SActive = 0x30c, 211 .ba5_SMisc = 0x340, 212 .ba5_PHY_CONFIG = 0x344, 213 .ba5_SIEN = 0x348, 214 .ba5_SFISCfg = 0x34c, 215 }, 216 { /* Channel 3 (3114) */ 217 .ba5_IDEDMA_CMD = 0x208, 218 .ba5_IDEDMA_CTL = 0x20a, 219 .ba5_IDEDMA_TBL = 0x20c, 220 .ba5_IDEDMA_CMD2 = 0x218, 221 .ba5_IDEDMA_CTL2 = 0x21a, 222 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 223 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 224 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 225 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 226 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 227 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 228 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 229 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 230 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 231 .ba5_IDE_RAD = 0x2cc, 232 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 233 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 234 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 235 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 236 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 237 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 238 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 239 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 240 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 241 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 242 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 243 .ba5_IDE_RABC = 0x2dc, 244 .ba5_IDE_CMD_STS = 0x2e0, 245 .ba5_IDE_CFG_STS = 0x2e1, 246 .ba5_IDE_DTM = 0x2f4, 247 .ba5_SControl = 0x380, 248 .ba5_SStatus = 0x384, 249 .ba5_SError = 0x388, 250 .ba5_SActive = 0x38c, 251 .ba5_SMisc = 0x3c0, 252 .ba5_PHY_CONFIG = 0x3c4, 253 .ba5_SIEN = 0x3c8, 254 .ba5_SFISCfg = 0x3cc, 255 }, 256 }; 257 258 #define ba5_SIS 0x214 /* summary interrupt status */ 259 260 /* Interrupt steering bit in BA5[0x200]. */ 261 #define IDEDMA_CMD_INT_STEER (1U << 1) 262 263 static int satalink_match(struct device *, struct cfdata *, void *); 264 static void satalink_attach(struct device *, struct device *, void *); 265 266 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 267 satalink_match, satalink_attach, NULL, NULL); 268 269 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 270 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 271 static void sii3112_drv_probe(struct wdc_channel*); 272 static void sii3112_setup_channel(struct wdc_channel*); 273 274 static const struct pciide_product_desc pciide_satalink_products[] = { 275 { PCI_PRODUCT_CMDTECH_3112, 276 0, 277 "Silicon Image SATALink 3112", 278 sii3112_chip_map, 279 }, 280 { PCI_PRODUCT_CMDTECH_3512, 281 0, 282 "Silicon Image SATALink 3512", 283 sii3112_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_3114, 286 0, 287 "Silicon Image SATALink 3114", 288 sii3114_chip_map, 289 }, 290 { 0, 291 0, 292 NULL, 293 NULL 294 } 295 }; 296 297 static int 298 satalink_match(struct device *parent, struct cfdata *match, void *aux) 299 { 300 struct pci_attach_args *pa = aux; 301 302 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 303 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 304 return (2); 305 } 306 return (0); 307 } 308 309 static void 310 satalink_attach(struct device *parent, struct device *self, void *aux) 311 { 312 struct pci_attach_args *pa = aux; 313 struct pciide_softc *sc = (struct pciide_softc *)self; 314 315 pciide_common_attach(sc, pa, 316 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 317 318 } 319 320 static __inline uint32_t 321 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 322 { 323 uint32_t rv; 324 int s; 325 326 s = splbio(); 327 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 328 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 329 splx(s); 330 331 return (rv); 332 } 333 334 static __inline uint32_t 335 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 336 { 337 338 if (__predict_true(sc->sc_ba5_en != 0)) 339 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 340 341 return (ba5_read_4_ind(sc, reg)); 342 } 343 344 #define BA5_READ_4(sc, chan, reg) \ 345 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 346 347 static __inline void 348 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 349 { 350 int s; 351 352 s = splbio(); 353 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 354 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 355 splx(s); 356 } 357 358 static __inline void 359 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 360 { 361 362 if (__predict_true(sc->sc_ba5_en != 0)) 363 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 364 else 365 ba5_write_4_ind(sc, reg, val); 366 } 367 368 #define BA5_WRITE_4(sc, chan, reg, val) \ 369 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 370 371 static void 372 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 373 { 374 struct pciide_channel *cp; 375 bus_size_t cmdsize, ctlsize; 376 pcireg_t interface, scs_cmd, cfgctl; 377 int channel; 378 379 if (pciide_chipen(sc, pa) == 0) 380 return; 381 382 #define SII3112_RESET_BITS \ 383 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 384 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 385 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 386 387 /* 388 * Reset everything and then unblock all of the interrupts. 389 */ 390 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 391 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 392 scs_cmd | SII3112_RESET_BITS); 393 delay(50 * 1000); 394 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 395 scs_cmd & SCS_CMD_BA5_EN); 396 delay(50 * 1000); 397 398 if (scs_cmd & SCS_CMD_BA5_EN) { 399 aprint_verbose("%s: SATALink BA5 register space enabled\n", 400 sc->sc_wdcdev.sc_dev.dv_xname); 401 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 402 PCI_MAPREG_TYPE_MEM| 403 PCI_MAPREG_MEM_TYPE_32BIT, 0, 404 &sc->sc_ba5_st, &sc->sc_ba5_sh, 405 NULL, NULL) != 0) 406 aprint_error("%s: unable to map SATALink BA5 " 407 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 408 else 409 sc->sc_ba5_en = 1; 410 } else { 411 aprint_verbose("%s: SATALink BA5 register space disabled\n", 412 sc->sc_wdcdev.sc_dev.dv_xname); 413 414 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 415 SII3112_PCI_CFGCTL); 416 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 417 cfgctl | CFGCTL_BA5INDEN); 418 } 419 420 aprint_normal("%s: bus-master DMA support present", 421 sc->sc_wdcdev.sc_dev.dv_xname); 422 pciide_mapreg_dma(sc, pa); 423 aprint_normal("\n"); 424 425 /* 426 * Rev. <= 0x01 of the 3112 have a bug that can cause data 427 * corruption if DMA transfers cross an 8K boundary. This is 428 * apparently hard to tickle, but we'll go ahead and play it 429 * safe. 430 */ 431 if (PCI_REVISION(pa->pa_class) <= 0x01) { 432 sc->sc_dma_maxsegsz = 8192; 433 sc->sc_dma_boundary = 8192; 434 } 435 436 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 437 WDC_CAPABILITY_MODE; 438 sc->sc_wdcdev.PIO_cap = 4; 439 if (sc->sc_dma_ok) { 440 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 441 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 442 sc->sc_wdcdev.irqack = pciide_irqack; 443 sc->sc_wdcdev.DMA_cap = 2; 444 sc->sc_wdcdev.UDMA_cap = 6; 445 } 446 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 447 448 /* We can use SControl and SStatus to probe for drives. */ 449 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 450 451 sc->sc_wdcdev.channels = sc->wdc_chanarray; 452 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 453 454 /* 455 * The 3112 either identifies itself as a RAID storage device 456 * or a Misc storage device. Fake up the interface bits for 457 * what our driver expects. 458 */ 459 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 460 interface = PCI_INTERFACE(pa->pa_class); 461 } else { 462 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 463 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 464 } 465 466 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 467 cp = &sc->pciide_channels[channel]; 468 if (pciide_chansetup(sc, channel, interface) == 0) 469 continue; 470 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 471 pciide_pci_intr); 472 } 473 } 474 475 static void 476 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 477 { 478 struct pciide_channel *pc; 479 int chan, reg; 480 bus_size_t size; 481 482 sc->sc_wdcdev.dma_arg = sc; 483 sc->sc_wdcdev.dma_init = pciide_dma_init; 484 sc->sc_wdcdev.dma_start = pciide_dma_start; 485 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 486 487 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 488 PCIIDE_OPTIONS_NODMA) { 489 aprint_normal( 490 ", but unused (forced off by config file)"); 491 sc->sc_dma_ok = 0; 492 return; 493 } 494 495 /* 496 * Slice off a subregion of BA5 for each of the channel's DMA 497 * registers. 498 */ 499 500 sc->sc_dma_iot = sc->sc_ba5_st; 501 for (chan = 0; chan < 4; chan++) { 502 pc = &sc->pciide_channels[chan]; 503 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 504 size = 4; 505 if (size > (IDEDMA_SCH_OFFSET - reg)) 506 size = IDEDMA_SCH_OFFSET - reg; 507 if (bus_space_subregion(sc->sc_ba5_st, 508 sc->sc_ba5_sh, 509 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 510 size, &pc->dma_iohs[reg]) != 0) { 511 sc->sc_dma_ok = 0; 512 aprint_normal(", but can't subregion offset " 513 "%lu size %lu", 514 (u_long) satalink_ba5_regmap[ 515 chan].ba5_IDEDMA_CMD + reg, 516 (u_long) size); 517 return; 518 } 519 } 520 } 521 522 /* DMA registers all set up! */ 523 sc->sc_dmat = pa->pa_dmat; 524 sc->sc_dma_ok = 1; 525 } 526 527 static int 528 sii3114_chansetup(struct pciide_softc *sc, int channel) 529 { 530 static const char *channel_names[] = { 531 "port 0", 532 "port 1", 533 "port 2", 534 "port 3", 535 }; 536 struct pciide_channel *cp = &sc->pciide_channels[channel]; 537 538 sc->wdc_chanarray[channel] = &cp->wdc_channel; 539 540 /* 541 * We must always keep the Interrupt Steering bit set in channel 2's 542 * IDEDMA_CMD register. 543 */ 544 if (channel == 2) 545 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 546 547 cp->name = channel_names[channel]; 548 cp->wdc_channel.ch_channel = channel; 549 cp->wdc_channel.ch_wdc = &sc->sc_wdcdev; 550 cp->wdc_channel.ch_queue = 551 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 552 if (cp->wdc_channel.ch_queue == NULL) { 553 aprint_error("%s %s channel: " 554 "can't allocate memory for command queue", 555 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 556 return (0); 557 } 558 return (1); 559 } 560 561 static void 562 sii3114_mapchan(struct pciide_channel *cp) 563 { 564 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 565 struct wdc_channel *wdc_cp = &cp->wdc_channel; 566 int i; 567 568 cp->compat = 0; 569 cp->ih = sc->sc_pci_ih; 570 571 wdc_cp->cmd_iot = sc->sc_ba5_st; 572 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 573 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 574 9, &wdc_cp->cmd_baseioh) != 0) { 575 aprint_error("%s: couldn't subregion %s cmd base\n", 576 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 577 goto bad; 578 } 579 580 wdc_cp->ctl_iot = sc->sc_ba5_st; 581 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 582 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 583 1, &cp->ctl_baseioh) != 0) { 584 aprint_error("%s: couldn't subregion %s ctl base\n", 585 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 586 goto bad; 587 } 588 wdc_cp->ctl_ioh = cp->ctl_baseioh; 589 590 for (i = 0; i < WDC_NREG; i++) { 591 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 592 i, i == 0 ? 4 : 1, 593 &wdc_cp->cmd_iohs[i]) != 0) { 594 aprint_error("%s: couldn't subregion %s channel " 595 "cmd regs\n", 596 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 597 goto bad; 598 } 599 } 600 wdc_init_shadow_regs(wdc_cp); 601 wdc_cp->data32iot = wdc_cp->cmd_iot; 602 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 603 wdcattach(wdc_cp); 604 return; 605 606 bad: 607 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 608 } 609 610 static void 611 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 612 { 613 struct pciide_channel *cp; 614 pcireg_t scs_cmd; 615 pci_intr_handle_t intrhandle; 616 const char *intrstr; 617 int channel; 618 619 if (pciide_chipen(sc, pa) == 0) 620 return; 621 622 #define SII3114_RESET_BITS \ 623 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 624 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 625 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 626 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 627 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 628 629 /* 630 * Reset everything and then unblock all of the interrupts. 631 */ 632 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 633 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 634 scs_cmd | SII3114_RESET_BITS); 635 delay(50 * 1000); 636 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 637 scs_cmd & SCS_CMD_M66EN); 638 delay(50 * 1000); 639 640 /* 641 * On the 3114, the BA5 register space is always enabled. In 642 * order to use the 3114 in any sane way, we must use this BA5 643 * register space, and so we consider it an error if we cannot 644 * map it. 645 * 646 * As a consequence of using BA5, our register mapping is different 647 * from a normal PCI IDE controller's, and so we are unable to use 648 * most of the common PCI IDE register mapping functions. 649 */ 650 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 651 PCI_MAPREG_TYPE_MEM| 652 PCI_MAPREG_MEM_TYPE_32BIT, 0, 653 &sc->sc_ba5_st, &sc->sc_ba5_sh, 654 NULL, NULL) != 0) { 655 aprint_error("%s: unable to map SATALink BA5 " 656 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 657 return; 658 } 659 sc->sc_ba5_en = 1; 660 661 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_dev.dv_xname, 662 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 663 664 /* 665 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 666 * channel 2. This is required at all times for proper operation 667 * when using the BA5 register space (otherwise interrupts from 668 * all 4 channels won't work). 669 */ 670 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 671 672 aprint_normal("%s: bus-master DMA support present", 673 sc->sc_wdcdev.sc_dev.dv_xname); 674 sii3114_mapreg_dma(sc, pa); 675 aprint_normal("\n"); 676 677 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 678 WDC_CAPABILITY_MODE; 679 sc->sc_wdcdev.PIO_cap = 4; 680 if (sc->sc_dma_ok) { 681 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 682 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 683 sc->sc_wdcdev.irqack = pciide_irqack; 684 sc->sc_wdcdev.DMA_cap = 2; 685 sc->sc_wdcdev.UDMA_cap = 6; 686 } 687 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 688 689 /* We can use SControl and SStatus to probe for drives. */ 690 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 691 692 sc->sc_wdcdev.channels = sc->wdc_chanarray; 693 sc->sc_wdcdev.nchannels = 4; 694 695 /* Map and establish the interrupt handler. */ 696 if (pci_intr_map(pa, &intrhandle) != 0) { 697 aprint_error("%s: couldn't map native-PCI interrupt\n", 698 sc->sc_wdcdev.sc_dev.dv_xname); 699 return; 700 } 701 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 702 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 703 /* XXX */ 704 pciide_pci_intr, sc); 705 if (sc->sc_pci_ih != NULL) { 706 aprint_normal("%s: using %s for native-PCI interrupt\n", 707 sc->sc_wdcdev.sc_dev.dv_xname, 708 intrstr ? intrstr : "unknown interrupt"); 709 } else { 710 aprint_error("%s: couldn't establish native-PCI interrupt", 711 sc->sc_wdcdev.sc_dev.dv_xname); 712 if (intrstr != NULL) 713 aprint_normal(" at %s", intrstr); 714 aprint_normal("\n"); 715 return; 716 } 717 718 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 719 cp = &sc->pciide_channels[channel]; 720 if (sii3114_chansetup(sc, channel) == 0) 721 continue; 722 sii3114_mapchan(cp); 723 } 724 } 725 726 static void 727 sii3112_drv_probe(struct wdc_channel *chp) 728 { 729 struct pciide_channel *cp = (struct pciide_channel *)chp; 730 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 731 uint32_t scontrol, sstatus; 732 uint8_t scnt, sn, cl, ch; 733 int i; 734 735 /* XXX This should be done by other code. */ 736 for (i = 0; i < 2; i++) { 737 chp->ch_drive[i].chnl_softc = chp; 738 chp->ch_drive[i].drive = i; 739 } 740 741 /* 742 * The 3112 is a 2-port part, and only has one drive per channel 743 * (each port emulates a master drive). 744 * 745 * The 3114 is similar, but has 4 channels. 746 */ 747 748 /* 749 * Request communication initialization sequence, any speed. 750 * Performing this is the equivalent of an ATA Reset. 751 */ 752 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 753 754 /* 755 * XXX We don't yet support SATA power management; disable all 756 * power management state transitions. 757 */ 758 scontrol |= SControl_IPM_NONE; 759 760 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 761 delay(50 * 1000); 762 scontrol &= ~SControl_DET_INIT; 763 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 764 delay(50 * 1000); 765 766 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 767 #if 0 768 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 769 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel, sstatus, 770 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 771 #endif 772 switch (sstatus & SStatus_DET_mask) { 773 case SStatus_DET_NODEV: 774 /* No device; be silent. */ 775 break; 776 777 case SStatus_DET_DEV_NE: 778 aprint_error("%s: port %d: device connected, but " 779 "communication not established\n", 780 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel); 781 break; 782 783 case SStatus_DET_OFFLINE: 784 aprint_error("%s: port %d: PHY offline\n", 785 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel); 786 break; 787 788 case SStatus_DET_DEV: 789 /* 790 * XXX ATAPI detection doesn't currently work. Don't 791 * XXX know why. But, it's not like the standard method 792 * XXX can detect an ATAPI device connected via a SATA/PATA 793 * XXX bridge, so at least this is no worse. --thorpej 794 */ 795 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 796 WDSD_IBM | (0 << 4)); 797 delay(10); /* 400ns delay */ 798 /* Save register contents. */ 799 scnt = bus_space_read_1(chp->cmd_iot, 800 chp->cmd_iohs[wd_seccnt], 0); 801 sn = bus_space_read_1(chp->cmd_iot, 802 chp->cmd_iohs[wd_sector], 0); 803 cl = bus_space_read_1(chp->cmd_iot, 804 chp->cmd_iohs[wd_cyl_lo], 0); 805 ch = bus_space_read_1(chp->cmd_iot, 806 chp->cmd_iohs[wd_cyl_hi], 0); 807 #if 0 808 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 809 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel, 810 scnt, sn, cl, ch); 811 #endif 812 /* 813 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 814 * cases we get wrong values here, so ignore it. 815 */ 816 if (cl == 0x14 && ch == 0xeb) 817 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 818 else 819 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 820 821 aprint_normal("%s: port %d: device present, speed: %s\n", 822 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel, 823 sata_speed(sstatus)); 824 break; 825 826 default: 827 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 828 sc->sc_wdcdev.sc_dev.dv_xname, chp->ch_channel, sstatus); 829 } 830 } 831 832 static void 833 sii3112_setup_channel(struct wdc_channel *chp) 834 { 835 struct ata_drive_datas *drvp; 836 int drive; 837 u_int32_t idedma_ctl, dtm; 838 struct pciide_channel *cp = (struct pciide_channel*)chp; 839 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.ch_wdc; 840 841 /* setup DMA if needed */ 842 pciide_channel_dma_setup(cp); 843 844 idedma_ctl = 0; 845 dtm = 0; 846 847 for (drive = 0; drive < 2; drive++) { 848 drvp = &chp->ch_drive[drive]; 849 /* If no drive, skip */ 850 if ((drvp->drive_flags & DRIVE) == 0) 851 continue; 852 if (drvp->drive_flags & DRIVE_UDMA) { 853 /* use Ultra/DMA */ 854 drvp->drive_flags &= ~DRIVE_DMA; 855 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 856 dtm |= DTM_IDEx_DMA; 857 } else if (drvp->drive_flags & DRIVE_DMA) { 858 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 859 dtm |= DTM_IDEx_DMA; 860 } else { 861 dtm |= DTM_IDEx_PIO; 862 } 863 } 864 865 /* 866 * Nothing to do to setup modes; it is meaningless in S-ATA 867 * (but many S-ATA drives still want to get the SET_FEATURE 868 * command). 869 */ 870 if (idedma_ctl != 0) { 871 /* Add software bits in status register */ 872 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 873 idedma_ctl); 874 } 875 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 876 } 877
Indexes created Mon Sep 29 18:09:42 GMT 2025