satalink.c revision 1.17.2.6
1 /* $NetBSD: satalink.c,v 1.17.2.6 2005/03/04 16:45:26 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 #include <dev/ata/satavar.h> 51 #include <dev/ata/atareg.h> 52 53 /* 54 * Register map for BA5 register space, indexed by channel. 55 */ 56 static const struct { 57 bus_addr_t ba5_IDEDMA_CMD; 58 bus_addr_t ba5_IDEDMA_CTL; 59 bus_addr_t ba5_IDEDMA_TBL; 60 bus_addr_t ba5_IDEDMA_CMD2; 61 bus_addr_t ba5_IDEDMA_CTL2; 62 bus_addr_t ba5_IDE_TF0; 63 bus_addr_t ba5_IDE_TF1; 64 bus_addr_t ba5_IDE_TF2; 65 bus_addr_t ba5_IDE_TF3; 66 bus_addr_t ba5_IDE_TF4; 67 bus_addr_t ba5_IDE_TF5; 68 bus_addr_t ba5_IDE_TF6; 69 bus_addr_t ba5_IDE_TF7; 70 bus_addr_t ba5_IDE_TF8; 71 bus_addr_t ba5_IDE_RAD; 72 bus_addr_t ba5_IDE_TF9; 73 bus_addr_t ba5_IDE_TF10; 74 bus_addr_t ba5_IDE_TF11; 75 bus_addr_t ba5_IDE_TF12; 76 bus_addr_t ba5_IDE_TF13; 77 bus_addr_t ba5_IDE_TF14; 78 bus_addr_t ba5_IDE_TF15; 79 bus_addr_t ba5_IDE_TF16; 80 bus_addr_t ba5_IDE_TF17; 81 bus_addr_t ba5_IDE_TF18; 82 bus_addr_t ba5_IDE_TF19; 83 bus_addr_t ba5_IDE_RABC; 84 bus_addr_t ba5_IDE_CMD_STS; 85 bus_addr_t ba5_IDE_CFG_STS; 86 bus_addr_t ba5_IDE_DTM; 87 bus_addr_t ba5_SControl; 88 bus_addr_t ba5_SStatus; 89 bus_addr_t ba5_SError; 90 bus_addr_t ba5_SActive; /* 3114 */ 91 bus_addr_t ba5_SMisc; 92 bus_addr_t ba5_PHY_CONFIG; 93 bus_addr_t ba5_SIEN; 94 bus_addr_t ba5_SFISCfg; 95 } satalink_ba5_regmap[] = { 96 { /* Channel 0 */ 97 .ba5_IDEDMA_CMD = 0x000, 98 .ba5_IDEDMA_CTL = 0x002, 99 .ba5_IDEDMA_TBL = 0x004, 100 .ba5_IDEDMA_CMD2 = 0x010, 101 .ba5_IDEDMA_CTL2 = 0x012, 102 .ba5_IDE_TF0 = 0x080, /* wd_data */ 103 .ba5_IDE_TF1 = 0x081, /* wd_error */ 104 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 105 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 106 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 107 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 108 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 109 .ba5_IDE_TF7 = 0x087, /* wd_command */ 110 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 111 .ba5_IDE_RAD = 0x08c, 112 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 113 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 114 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 115 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 116 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 117 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 118 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 119 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 120 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 121 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 122 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 123 .ba5_IDE_RABC = 0x09c, 124 .ba5_IDE_CMD_STS = 0x0a0, 125 .ba5_IDE_CFG_STS = 0x0a1, 126 .ba5_IDE_DTM = 0x0b4, 127 .ba5_SControl = 0x100, 128 .ba5_SStatus = 0x104, 129 .ba5_SError = 0x108, 130 .ba5_SActive = 0x10c, 131 .ba5_SMisc = 0x140, 132 .ba5_PHY_CONFIG = 0x144, 133 .ba5_SIEN = 0x148, 134 .ba5_SFISCfg = 0x14c, 135 }, 136 { /* Channel 1 */ 137 .ba5_IDEDMA_CMD = 0x008, 138 .ba5_IDEDMA_CTL = 0x00a, 139 .ba5_IDEDMA_TBL = 0x00c, 140 .ba5_IDEDMA_CMD2 = 0x018, 141 .ba5_IDEDMA_CTL2 = 0x01a, 142 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 143 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 144 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 145 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 146 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 147 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 148 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 149 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 150 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 151 .ba5_IDE_RAD = 0x0cc, 152 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 153 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 154 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 155 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 156 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 157 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 158 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 159 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 160 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 161 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 162 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 163 .ba5_IDE_RABC = 0x0dc, 164 .ba5_IDE_CMD_STS = 0x0e0, 165 .ba5_IDE_CFG_STS = 0x0e1, 166 .ba5_IDE_DTM = 0x0f4, 167 .ba5_SControl = 0x180, 168 .ba5_SStatus = 0x184, 169 .ba5_SError = 0x188, 170 .ba5_SActive = 0x18c, 171 .ba5_SMisc = 0x1c0, 172 .ba5_PHY_CONFIG = 0x1c4, 173 .ba5_SIEN = 0x1c8, 174 .ba5_SFISCfg = 0x1cc, 175 }, 176 { /* Channel 2 (3114) */ 177 .ba5_IDEDMA_CMD = 0x200, 178 .ba5_IDEDMA_CTL = 0x202, 179 .ba5_IDEDMA_TBL = 0x204, 180 .ba5_IDEDMA_CMD2 = 0x210, 181 .ba5_IDEDMA_CTL2 = 0x212, 182 .ba5_IDE_TF0 = 0x280, /* wd_data */ 183 .ba5_IDE_TF1 = 0x281, /* wd_error */ 184 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 185 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 186 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 187 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 188 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 189 .ba5_IDE_TF7 = 0x287, /* wd_command */ 190 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 191 .ba5_IDE_RAD = 0x28c, 192 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 193 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 194 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 195 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 196 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 197 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 198 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 199 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 200 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 201 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 202 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 203 .ba5_IDE_RABC = 0x29c, 204 .ba5_IDE_CMD_STS = 0x2a0, 205 .ba5_IDE_CFG_STS = 0x2a1, 206 .ba5_IDE_DTM = 0x2b4, 207 .ba5_SControl = 0x300, 208 .ba5_SStatus = 0x304, 209 .ba5_SError = 0x308, 210 .ba5_SActive = 0x30c, 211 .ba5_SMisc = 0x340, 212 .ba5_PHY_CONFIG = 0x344, 213 .ba5_SIEN = 0x348, 214 .ba5_SFISCfg = 0x34c, 215 }, 216 { /* Channel 3 (3114) */ 217 .ba5_IDEDMA_CMD = 0x208, 218 .ba5_IDEDMA_CTL = 0x20a, 219 .ba5_IDEDMA_TBL = 0x20c, 220 .ba5_IDEDMA_CMD2 = 0x218, 221 .ba5_IDEDMA_CTL2 = 0x21a, 222 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 223 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 224 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 225 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 226 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 227 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 228 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 229 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 230 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 231 .ba5_IDE_RAD = 0x2cc, 232 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 233 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 234 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 235 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 236 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 237 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 238 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 239 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 240 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 241 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 242 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 243 .ba5_IDE_RABC = 0x2dc, 244 .ba5_IDE_CMD_STS = 0x2e0, 245 .ba5_IDE_CFG_STS = 0x2e1, 246 .ba5_IDE_DTM = 0x2f4, 247 .ba5_SControl = 0x380, 248 .ba5_SStatus = 0x384, 249 .ba5_SError = 0x388, 250 .ba5_SActive = 0x38c, 251 .ba5_SMisc = 0x3c0, 252 .ba5_PHY_CONFIG = 0x3c4, 253 .ba5_SIEN = 0x3c8, 254 .ba5_SFISCfg = 0x3cc, 255 }, 256 }; 257 258 #define ba5_SIS 0x214 /* summary interrupt status */ 259 260 /* Interrupt steering bit in BA5[0x200]. */ 261 #define IDEDMA_CMD_INT_STEER (1U << 1) 262 263 static int satalink_match(struct device *, struct cfdata *, void *); 264 static void satalink_attach(struct device *, struct device *, void *); 265 266 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 267 satalink_match, satalink_attach, NULL, NULL); 268 269 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 270 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 271 static void sii3112_drv_probe(struct ata_channel*); 272 static void sii3112_setup_channel(struct ata_channel*); 273 274 static const struct pciide_product_desc pciide_satalink_products[] = { 275 { PCI_PRODUCT_CMDTECH_3112, 276 0, 277 "Silicon Image SATALink 3112", 278 sii3112_chip_map, 279 }, 280 { PCI_PRODUCT_CMDTECH_3512, 281 0, 282 "Silicon Image SATALink 3512", 283 sii3112_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 286 0, 287 "Adaptec AAR-1210SA serial ATA RAID controller", 288 sii3112_chip_map, 289 }, 290 { PCI_PRODUCT_CMDTECH_3114, 291 0, 292 "Silicon Image SATALink 3114", 293 sii3114_chip_map, 294 }, 295 { 0, 296 0, 297 NULL, 298 NULL 299 } 300 }; 301 302 static int 303 satalink_match(struct device *parent, struct cfdata *match, void *aux) 304 { 305 struct pci_attach_args *pa = aux; 306 307 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 308 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 309 return (2); 310 } 311 return (0); 312 } 313 314 static void 315 satalink_attach(struct device *parent, struct device *self, void *aux) 316 { 317 struct pci_attach_args *pa = aux; 318 struct pciide_softc *sc = (struct pciide_softc *)self; 319 320 pciide_common_attach(sc, pa, 321 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 322 323 } 324 325 static __inline uint32_t 326 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 327 { 328 uint32_t rv; 329 int s; 330 331 s = splbio(); 332 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 333 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 334 splx(s); 335 336 return (rv); 337 } 338 339 static __inline uint32_t 340 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 341 { 342 343 if (__predict_true(sc->sc_ba5_en != 0)) 344 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 345 346 return (ba5_read_4_ind(sc, reg)); 347 } 348 349 #define BA5_READ_4(sc, chan, reg) \ 350 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 351 352 static __inline void 353 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 354 { 355 int s; 356 357 s = splbio(); 358 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 359 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 360 splx(s); 361 } 362 363 static __inline void 364 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 365 { 366 367 if (__predict_true(sc->sc_ba5_en != 0)) 368 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 369 else 370 ba5_write_4_ind(sc, reg, val); 371 } 372 373 #define BA5_WRITE_4(sc, chan, reg, val) \ 374 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 375 376 static void 377 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 378 { 379 struct pciide_channel *cp; 380 bus_size_t cmdsize, ctlsize; 381 pcireg_t interface, scs_cmd, cfgctl; 382 pcireg_t cls, reg40, reg44; 383 int channel; 384 385 if (pciide_chipen(sc, pa) == 0) 386 return; 387 388 #define SII3112_RESET_BITS \ 389 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 390 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 391 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 392 393 /* 394 * Reset everything and then unblock all of the interrupts. 395 */ 396 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 397 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 398 scs_cmd | SII3112_RESET_BITS); 399 delay(50 * 1000); 400 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 401 scs_cmd & SCS_CMD_BA5_EN); 402 delay(50 * 1000); 403 404 if (scs_cmd & SCS_CMD_BA5_EN) { 405 aprint_verbose("%s: SATALink BA5 register space enabled\n", 406 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 407 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 408 PCI_MAPREG_TYPE_MEM| 409 PCI_MAPREG_MEM_TYPE_32BIT, 0, 410 &sc->sc_ba5_st, &sc->sc_ba5_sh, 411 NULL, NULL) != 0) 412 aprint_error("%s: unable to map SATALink BA5 " 413 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 414 else 415 sc->sc_ba5_en = 1; 416 } else { 417 aprint_verbose("%s: SATALink BA5 register space disabled\n", 418 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 419 420 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 421 SII3112_PCI_CFGCTL); 422 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 423 cfgctl | CFGCTL_BA5INDEN); 424 } 425 426 aprint_normal("%s: bus-master DMA support present", 427 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 428 pciide_mapreg_dma(sc, pa); 429 aprint_normal("\n"); 430 431 /* 432 * Rev. <= 0x01 of the 3112 have a bug that can cause data 433 * corruption if DMA transfers cross an 8K boundary. This is 434 * apparently hard to tickle, but we'll go ahead and play it 435 * safe. 436 */ 437 if (PCI_REVISION(pa->pa_class) <= 0x01) { 438 sc->sc_dma_maxsegsz = 8192; 439 sc->sc_dma_boundary = 8192; 440 } 441 442 /* 443 * When the Silicon Image 3112 retries a PCI memory read command, 444 * it may retry it as a memory read multiple command under some 445 * circumstances. This can totally confuse some PCI controllers, 446 * so ensure that it will never do this by making sure that the 447 * Read Threshold (FIFO Read Request Control) field of the FIFO 448 * Valid Byte Count and Control registers for both channels (BA5 449 * offset 0x40 and 0x44) are set to be at least as large as the 450 * cacheline size register. 451 */ 452 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 453 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 454 cls *= 4; 455 if (cls > 224) { 456 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 457 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 458 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 459 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 460 cls = 224; 461 } 462 if (cls < 32) 463 cls = 32; 464 cls = (cls + 31) / 32; 465 reg40 = ba5_read_4(sc, 0x40); 466 reg44 = ba5_read_4(sc, 0x44); 467 if ((reg40 & 0x7) < cls) 468 ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls); 469 if ((reg44 & 0x7) < cls) 470 ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls); 471 472 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 473 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 474 if (sc->sc_dma_ok) { 475 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 476 sc->sc_wdcdev.irqack = pciide_irqack; 477 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 478 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 479 } 480 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 481 482 /* We can use SControl and SStatus to probe for drives. */ 483 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 484 485 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 486 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 487 488 wdc_allocate_regs(&sc->sc_wdcdev); 489 490 /* 491 * The 3112 either identifies itself as a RAID storage device 492 * or a Misc storage device. Fake up the interface bits for 493 * what our driver expects. 494 */ 495 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 496 interface = PCI_INTERFACE(pa->pa_class); 497 } else { 498 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 499 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 500 } 501 502 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 503 channel++) { 504 cp = &sc->pciide_channels[channel]; 505 if (pciide_chansetup(sc, channel, interface) == 0) 506 continue; 507 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 508 pciide_pci_intr); 509 } 510 } 511 512 static void 513 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 514 { 515 struct pciide_channel *pc; 516 int chan, reg; 517 bus_size_t size; 518 519 sc->sc_wdcdev.dma_arg = sc; 520 sc->sc_wdcdev.dma_init = pciide_dma_init; 521 sc->sc_wdcdev.dma_start = pciide_dma_start; 522 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 523 524 if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags & 525 PCIIDE_OPTIONS_NODMA) { 526 aprint_normal( 527 ", but unused (forced off by config file)"); 528 sc->sc_dma_ok = 0; 529 return; 530 } 531 532 /* 533 * Slice off a subregion of BA5 for each of the channel's DMA 534 * registers. 535 */ 536 537 sc->sc_dma_iot = sc->sc_ba5_st; 538 for (chan = 0; chan < 4; chan++) { 539 pc = &sc->pciide_channels[chan]; 540 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 541 size = 4; 542 if (size > (IDEDMA_SCH_OFFSET - reg)) 543 size = IDEDMA_SCH_OFFSET - reg; 544 if (bus_space_subregion(sc->sc_ba5_st, 545 sc->sc_ba5_sh, 546 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 547 size, &pc->dma_iohs[reg]) != 0) { 548 sc->sc_dma_ok = 0; 549 aprint_normal(", but can't subregion offset " 550 "%lu size %lu", 551 (u_long) satalink_ba5_regmap[ 552 chan].ba5_IDEDMA_CMD + reg, 553 (u_long) size); 554 return; 555 } 556 } 557 } 558 559 /* DMA registers all set up! */ 560 sc->sc_dmat = pa->pa_dmat; 561 sc->sc_dma_ok = 1; 562 } 563 564 static int 565 sii3114_chansetup(struct pciide_softc *sc, int channel) 566 { 567 static const char *channel_names[] = { 568 "port 0", 569 "port 1", 570 "port 2", 571 "port 3", 572 }; 573 struct pciide_channel *cp = &sc->pciide_channels[channel]; 574 575 sc->wdc_chanarray[channel] = &cp->ata_channel; 576 577 /* 578 * We must always keep the Interrupt Steering bit set in channel 2's 579 * IDEDMA_CMD register. 580 */ 581 if (channel == 2) 582 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 583 584 cp->name = channel_names[channel]; 585 cp->ata_channel.ch_channel = channel; 586 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 587 cp->ata_channel.ch_queue = 588 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 589 if (cp->ata_channel.ch_queue == NULL) { 590 aprint_error("%s %s channel: " 591 "can't allocate memory for command queue", 592 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 593 return (0); 594 } 595 return (1); 596 } 597 598 static void 599 sii3114_mapchan(struct pciide_channel *cp) 600 { 601 struct ata_channel *wdc_cp = &cp->ata_channel; 602 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 603 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 604 int i; 605 606 cp->compat = 0; 607 cp->ih = sc->sc_pci_ih; 608 609 wdr->cmd_iot = sc->sc_ba5_st; 610 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 611 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 612 9, &wdr->cmd_baseioh) != 0) { 613 aprint_error("%s: couldn't subregion %s cmd base\n", 614 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 615 goto bad; 616 } 617 618 wdr->ctl_iot = sc->sc_ba5_st; 619 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 620 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 621 1, &cp->ctl_baseioh) != 0) { 622 aprint_error("%s: couldn't subregion %s ctl base\n", 623 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 624 goto bad; 625 } 626 wdr->ctl_ioh = cp->ctl_baseioh; 627 628 for (i = 0; i < WDC_NREG; i++) { 629 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 630 i, i == 0 ? 4 : 1, 631 &wdr->cmd_iohs[i]) != 0) { 632 aprint_error("%s: couldn't subregion %s channel " 633 "cmd regs\n", 634 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 635 goto bad; 636 } 637 } 638 wdc_init_shadow_regs(wdc_cp); 639 wdr->data32iot = wdr->cmd_iot; 640 wdr->data32ioh = wdr->cmd_iohs[0]; 641 wdcattach(wdc_cp); 642 return; 643 644 bad: 645 cp->ata_channel.ch_flags |= ATACH_DISABLED; 646 } 647 648 static void 649 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 650 { 651 struct pciide_channel *cp; 652 pcireg_t scs_cmd; 653 pci_intr_handle_t intrhandle; 654 const char *intrstr; 655 int channel; 656 657 if (pciide_chipen(sc, pa) == 0) 658 return; 659 660 #define SII3114_RESET_BITS \ 661 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 662 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 663 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 664 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 665 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 666 667 /* 668 * Reset everything and then unblock all of the interrupts. 669 */ 670 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 671 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 672 scs_cmd | SII3114_RESET_BITS); 673 delay(50 * 1000); 674 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 675 scs_cmd & SCS_CMD_M66EN); 676 delay(50 * 1000); 677 678 /* 679 * On the 3114, the BA5 register space is always enabled. In 680 * order to use the 3114 in any sane way, we must use this BA5 681 * register space, and so we consider it an error if we cannot 682 * map it. 683 * 684 * As a consequence of using BA5, our register mapping is different 685 * from a normal PCI IDE controller's, and so we are unable to use 686 * most of the common PCI IDE register mapping functions. 687 */ 688 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 689 PCI_MAPREG_TYPE_MEM| 690 PCI_MAPREG_MEM_TYPE_32BIT, 0, 691 &sc->sc_ba5_st, &sc->sc_ba5_sh, 692 NULL, NULL) != 0) { 693 aprint_error("%s: unable to map SATALink BA5 " 694 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 695 return; 696 } 697 sc->sc_ba5_en = 1; 698 699 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 700 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 701 702 /* 703 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 704 * channel 2. This is required at all times for proper operation 705 * when using the BA5 register space (otherwise interrupts from 706 * all 4 channels won't work). 707 */ 708 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 709 710 aprint_normal("%s: bus-master DMA support present", 711 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 712 sii3114_mapreg_dma(sc, pa); 713 aprint_normal("\n"); 714 715 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 716 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 717 if (sc->sc_dma_ok) { 718 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 719 sc->sc_wdcdev.irqack = pciide_irqack; 720 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 721 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 722 } 723 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 724 725 /* We can use SControl and SStatus to probe for drives. */ 726 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 727 728 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 729 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 730 731 wdc_allocate_regs(&sc->sc_wdcdev); 732 733 /* Map and establish the interrupt handler. */ 734 if (pci_intr_map(pa, &intrhandle) != 0) { 735 aprint_error("%s: couldn't map native-PCI interrupt\n", 736 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 737 return; 738 } 739 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 740 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 741 /* XXX */ 742 pciide_pci_intr, sc); 743 if (sc->sc_pci_ih != NULL) { 744 aprint_normal("%s: using %s for native-PCI interrupt\n", 745 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 746 intrstr ? intrstr : "unknown interrupt"); 747 } else { 748 aprint_error("%s: couldn't establish native-PCI interrupt", 749 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 750 if (intrstr != NULL) 751 aprint_normal(" at %s", intrstr); 752 aprint_normal("\n"); 753 return; 754 } 755 756 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 757 channel++) { 758 cp = &sc->pciide_channels[channel]; 759 if (sii3114_chansetup(sc, channel) == 0) 760 continue; 761 sii3114_mapchan(cp); 762 } 763 } 764 765 static void 766 sii3112_drv_probe(struct ata_channel *chp) 767 { 768 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 769 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 770 uint32_t scontrol, sstatus; 771 uint8_t scnt, sn, cl, ch; 772 int i, s; 773 774 /* XXX This should be done by other code. */ 775 for (i = 0; i < 2; i++) { 776 chp->ch_drive[i].chnl_softc = chp; 777 chp->ch_drive[i].drive = i; 778 } 779 780 /* 781 * The 3112 is a 2-port part, and only has one drive per channel 782 * (each port emulates a master drive). 783 * 784 * The 3114 is similar, but has 4 channels. 785 */ 786 787 /* 788 * Request communication initialization sequence, any speed. 789 * Performing this is the equivalent of an ATA Reset. 790 */ 791 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 792 793 /* 794 * XXX We don't yet support SATA power management; disable all 795 * power management state transitions. 796 */ 797 scontrol |= SControl_IPM_NONE; 798 799 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 800 delay(50 * 1000); 801 scontrol &= ~SControl_DET_INIT; 802 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 803 delay(50 * 1000); 804 805 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 806 #if 0 807 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 808 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus, 809 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 810 #endif 811 switch (sstatus & SStatus_DET_mask) { 812 case SStatus_DET_NODEV: 813 /* No device; be silent. */ 814 break; 815 816 case SStatus_DET_DEV_NE: 817 aprint_error("%s: port %d: device connected, but " 818 "communication not established\n", 819 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 820 break; 821 822 case SStatus_DET_OFFLINE: 823 aprint_error("%s: port %d: PHY offline\n", 824 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 825 break; 826 827 case SStatus_DET_DEV: 828 /* 829 * XXX ATAPI detection doesn't currently work. Don't 830 * XXX know why. But, it's not like the standard method 831 * XXX can detect an ATAPI device connected via a SATA/PATA 832 * XXX bridge, so at least this is no worse. --thorpej 833 */ 834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 835 WDSD_IBM | (0 << 4)); 836 delay(10); /* 400ns delay */ 837 /* Save register contents. */ 838 scnt = bus_space_read_1(wdr->cmd_iot, 839 wdr->cmd_iohs[wd_seccnt], 0); 840 sn = bus_space_read_1(wdr->cmd_iot, 841 wdr->cmd_iohs[wd_sector], 0); 842 cl = bus_space_read_1(wdr->cmd_iot, 843 wdr->cmd_iohs[wd_cyl_lo], 0); 844 ch = bus_space_read_1(wdr->cmd_iot, 845 wdr->cmd_iohs[wd_cyl_hi], 0); 846 #if 0 847 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 848 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 849 scnt, sn, cl, ch); 850 #endif 851 /* 852 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 853 * cases we get wrong values here, so ignore it. 854 */ 855 s = splbio(); 856 if (cl == 0x14 && ch == 0xeb) 857 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 858 else 859 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 860 splx(s); 861 862 aprint_normal("%s: port %d: device present, speed: %s\n", 863 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 864 sata_speed(sstatus)); 865 break; 866 867 default: 868 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 869 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus); 870 } 871 } 872 873 static void 874 sii3112_setup_channel(struct ata_channel *chp) 875 { 876 struct ata_drive_datas *drvp; 877 int drive, s; 878 u_int32_t idedma_ctl, dtm; 879 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 880 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 881 882 /* setup DMA if needed */ 883 pciide_channel_dma_setup(cp); 884 885 idedma_ctl = 0; 886 dtm = 0; 887 888 for (drive = 0; drive < 2; drive++) { 889 drvp = &chp->ch_drive[drive]; 890 /* If no drive, skip */ 891 if ((drvp->drive_flags & DRIVE) == 0) 892 continue; 893 if (drvp->drive_flags & DRIVE_UDMA) { 894 /* use Ultra/DMA */ 895 s = splbio(); 896 drvp->drive_flags &= ~DRIVE_DMA; 897 splx(s); 898 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 899 dtm |= DTM_IDEx_DMA; 900 } else if (drvp->drive_flags & DRIVE_DMA) { 901 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 902 dtm |= DTM_IDEx_DMA; 903 } else { 904 dtm |= DTM_IDEx_PIO; 905 } 906 } 907 908 /* 909 * Nothing to do to setup modes; it is meaningless in S-ATA 910 * (but many S-ATA drives still want to get the SET_FEATURE 911 * command). 912 */ 913 if (idedma_ctl != 0) { 914 /* Add software bits in status register */ 915 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 916 idedma_ctl); 917 } 918 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 919 } 920
Indexes created Thu Oct 02 14:10:14 GMT 2025