satalink.c revision 1.2
1 /* $NetBSD: satalink.c,v 1.2 2003/12/15 00:36:23 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 41 * 42 * Redistribution and use in source and binary forms, with or without 43 * modification, are permitted provided that the following conditions 44 * are met: 45 * 1. Redistributions of source code must retain the above copyright 46 * notice, this list of conditions and the following disclaimer. 47 * 2. Redistributions in binary form must reproduce the above copyright 48 * notice, this list of conditions and the following disclaimer in the 49 * documentation and/or other materials provided with the distribution. 50 * 3. All advertising materials mentioning features or use of this software 51 * must display the following acknowledgement: 52 * This product includes software developed by Manuel Bouyer. 53 * 4. The name of the author may not be used to endorse or promote products 54 * derived from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 57 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 58 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 59 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 61 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 62 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 63 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 64 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 65 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 #include <sys/param.h> 69 #include <sys/systm.h> 70 #include <sys/malloc.h> 71 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pciidereg.h> 75 #include <dev/pci/pciidevar.h> 76 #include <dev/pci/pciide_sii3112_reg.h> 77 78 #include <dev/ata/satareg.h> 79 80 static int satalink_match(struct device *, struct cfdata *, void *); 81 static void satalink_attach(struct device *, struct device *, void *); 82 83 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 84 satalink_match, satalink_attach, NULL, NULL); 85 86 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 87 static int sii3112_drv_probe(struct channel_softc*); 88 static void sii3112_setup_channel(struct channel_softc*); 89 90 static const struct pciide_product_desc pciide_satalink_products[] = { 91 { PCI_PRODUCT_CMDTECH_3112, 92 0, 93 "Silicon Image SATALink 3112", 94 sii3112_chip_map, 95 }, 96 { 0, 97 0, 98 NULL, 99 NULL 100 } 101 }; 102 103 static int 104 satalink_match(struct device *parent, struct cfdata *match, void *aux) 105 { 106 struct pci_attach_args *pa = aux; 107 108 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 109 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 110 return (2); 111 } 112 return (0); 113 } 114 115 static void 116 satalink_attach(struct device *parent, struct device *self, void *aux) 117 { 118 struct pci_attach_args *pa = aux; 119 struct pciide_softc *sc = (struct pciide_softc *)self; 120 121 pciide_common_attach(sc, pa, 122 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 123 124 } 125 126 static __inline uint32_t 127 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 128 { 129 130 if (__predict_true(sc->sc_ba5_en != 0)) 131 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 132 133 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 134 return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA)); 135 } 136 137 static __inline void 138 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 139 { 140 141 if (__predict_true(sc->sc_ba5_en != 0)) 142 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 143 else { 144 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, 145 reg); 146 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, 147 val); 148 } 149 } 150 151 static void 152 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 153 { 154 struct pciide_channel *cp; 155 bus_size_t cmdsize, ctlsize; 156 pcireg_t interface, scs_cmd, cfgctl; 157 int channel; 158 159 if (pciide_chipen(sc, pa) == 0) 160 return; 161 162 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 163 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 164 scs_cmd & SCS_CMD_BA5_EN); 165 166 if (scs_cmd & SCS_CMD_BA5_EN) { 167 aprint_verbose("%s: SATALink BA5 register space enabled\n", 168 sc->sc_wdcdev.sc_dev.dv_xname); 169 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 170 PCI_MAPREG_TYPE_MEM| 171 PCI_MAPREG_MEM_TYPE_32BIT, 0, 172 &sc->sc_ba5_st, &sc->sc_ba5_sh, 173 NULL, NULL) != 0) 174 aprint_error("%s: unable to map SATALink BA5 " 175 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 176 else 177 sc->sc_ba5_en = 1; 178 } else { 179 aprint_verbose("%s: SATALink BA5 register space disabled\n", 180 sc->sc_wdcdev.sc_dev.dv_xname); 181 182 /* Enable indirect BA5 addressing. */ 183 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 184 SII3112_PCI_CFGCTL); 185 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 186 cfgctl | CFGCTL_BA5INDEN); 187 } 188 189 aprint_normal("%s: bus-master DMA support present", 190 sc->sc_wdcdev.sc_dev.dv_xname); 191 pciide_mapreg_dma(sc, pa); 192 aprint_normal("\n"); 193 194 /* 195 * Rev. <= 0x01 of the 3112 have a bug that can cause data 196 * corruption if DMA transfers cross an 8K boundary. This is 197 * apparently hard to tickle, but we'll go ahead and play it 198 * safe. 199 */ 200 if (PCI_REVISION(pa->pa_class) <= 0x01) { 201 sc->sc_dma_maxsegsz = 8192; 202 sc->sc_dma_boundary = 8192; 203 } 204 205 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 206 WDC_CAPABILITY_MODE; 207 sc->sc_wdcdev.PIO_cap = 4; 208 if (sc->sc_dma_ok) { 209 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 210 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 211 sc->sc_wdcdev.irqack = pciide_irqack; 212 sc->sc_wdcdev.DMA_cap = 2; 213 sc->sc_wdcdev.UDMA_cap = 6; 214 } 215 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 216 217 /* We can use SControl and SStatus to probe for drives. */ 218 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE; 219 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 220 221 sc->sc_wdcdev.channels = sc->wdc_chanarray; 222 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 223 224 /* 225 * The 3112 either identifies itself as a RAID storage device 226 * or a Misc storage device. Fake up the interface bits for 227 * what our driver expects. 228 */ 229 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 230 interface = PCI_INTERFACE(pa->pa_class); 231 } else { 232 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 233 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 234 } 235 236 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 237 cp = &sc->pciide_channels[channel]; 238 if (pciide_chansetup(sc, channel, interface) == 0) 239 continue; 240 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 241 pciide_pci_intr); 242 } 243 } 244 245 static const char *sata_speed[] = { 246 "no negotiated speed", 247 "1.5Gb/s", 248 "<unknown 2>", 249 "<unknown 3>", 250 "<unknown 4>", 251 "<unknown 5>", 252 "<unknown 6>", 253 "<unknown 7>", 254 "<unknown 8>", 255 "<unknown 9>", 256 "<unknown 10>", 257 "<unknown 11>", 258 "<unknown 12>", 259 "<unknown 13>", 260 "<unknown 14>", 261 "<unknown 15>", 262 }; 263 264 static int 265 sii3112_drv_probe(struct channel_softc *chp) 266 { 267 struct pciide_channel *cp = (struct pciide_channel *)chp; 268 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 269 uint32_t scontrol, sstatus; 270 int rv = 0; 271 uint8_t scnt, sn, cl, ch; 272 273 /* 274 * The 3112 is a 2-port part, and only has one drive per channel 275 * (each port emulates a master drive). 276 */ 277 278 /* 279 * Request communication initialization sequence, any speed. 280 * Performing this is the equivalent of an ATA Reset. 281 */ 282 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 283 284 /* 285 * XXX We don't yet support SATA power management; disable all 286 * power management state transitions. 287 */ 288 scontrol |= SControl_IPM_NONE; 289 290 ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); 291 delay(500); 292 scontrol &= ~SControl_DET_INIT; 293 ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); 294 delay(500); 295 296 sstatus = ba5_read_4(sc, chp->channel == 0 ? 0x104 : 0x184); 297 switch (sstatus & SStatus_DET_mask) { 298 case SStatus_DET_NODEV: 299 /* No device; be silent. */ 300 break; 301 302 case SStatus_DET_DEV_NE: 303 aprint_error("%s: port %d: device connected, but " 304 "communication not established\n", 305 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 306 break; 307 308 case SStatus_DET_OFFLINE: 309 aprint_error("%s: port %d: PHY offline\n", 310 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 311 break; 312 313 case SStatus_DET_DEV: 314 /* 315 * XXX ATAPI detection doesn't currently work. Don't 316 * XXX know why. But, it's not like the standard method 317 * XXX can detect an ATAPI device connected via a SATA/PATA 318 * XXX bridge, so at least this is no worse. --thorpej 319 */ 320 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 321 WDSD_IBM | (0 << 4)); 322 delay(10); /* 400ns delay */ 323 /* Save register contents. */ 324 scnt = bus_space_read_1(chp->cmd_iot, 325 chp->cmd_iohs[wd_seccnt], 0); 326 sn = bus_space_read_1(chp->cmd_iot, 327 chp->cmd_iohs[wd_sector], 0); 328 cl = bus_space_read_1(chp->cmd_iot, 329 chp->cmd_iohs[wd_cyl_lo], 0); 330 ch = bus_space_read_1(chp->cmd_iot, 331 chp->cmd_iohs[wd_cyl_hi], 0); 332 #if 0 333 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 334 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 335 scnt, sn, cl, ch); 336 #endif 337 /* 338 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 339 * cases we get wrong values here, so ignore it. 340 */ 341 if (cl == 0x14 && ch == 0xeb) 342 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 343 else 344 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 345 346 aprint_normal("%s: port %d: device present, speed: %s\n", 347 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 348 sata_speed[(sstatus & SStatus_SPD_mask) >> 349 SStatus_SPD_shift]); 350 rv |= (1 << 0); 351 break; 352 353 default: 354 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 355 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 356 } 357 358 return (rv); 359 } 360 361 static void 362 sii3112_setup_channel(struct channel_softc *chp) 363 { 364 struct ata_drive_datas *drvp; 365 int drive; 366 u_int32_t idedma_ctl, dtm; 367 struct pciide_channel *cp = (struct pciide_channel*)chp; 368 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 369 370 /* setup DMA if needed */ 371 pciide_channel_dma_setup(cp); 372 373 idedma_ctl = 0; 374 dtm = 0; 375 376 for (drive = 0; drive < 2; drive++) { 377 drvp = &chp->ch_drive[drive]; 378 /* If no drive, skip */ 379 if ((drvp->drive_flags & DRIVE) == 0) 380 continue; 381 if (drvp->drive_flags & DRIVE_UDMA) { 382 /* use Ultra/DMA */ 383 drvp->drive_flags &= ~DRIVE_DMA; 384 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 385 dtm |= DTM_IDEx_DMA; 386 } else if (drvp->drive_flags & DRIVE_DMA) { 387 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 388 dtm |= DTM_IDEx_DMA; 389 } else { 390 dtm |= DTM_IDEx_PIO; 391 } 392 } 393 394 /* 395 * Nothing to do to setup modes; it is meaningless in S-ATA 396 * (but many S-ATA drives still want to get the SET_FEATURE 397 * command). 398 */ 399 if (idedma_ctl != 0) { 400 /* Add software bits in status register */ 401 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 402 idedma_ctl); 403 } 404 pci_conf_write(sc->sc_pc, sc->sc_tag, 405 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 406 } 407
Indexes created Mon Sep 29 21:09:56 GMT 2025