satalink.c revision 1.25.2.5
1 /* $NetBSD: satalink.c,v 1.25.2.5 2008/03/24 09:38:51 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.25.2.5 2008/03/24 09:38:51 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/pci/pciide_sii3112_reg.h> 51 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 #include <dev/ata/atareg.h> 55 56 /* 57 * Register map for BA5 register space, indexed by channel. 58 */ 59 static const struct { 60 bus_addr_t ba5_IDEDMA_CMD; 61 bus_addr_t ba5_IDEDMA_CTL; 62 bus_addr_t ba5_IDEDMA_TBL; 63 bus_addr_t ba5_IDEDMA_CMD2; 64 bus_addr_t ba5_IDEDMA_CTL2; 65 bus_addr_t ba5_IDE_TF0; 66 bus_addr_t ba5_IDE_TF1; 67 bus_addr_t ba5_IDE_TF2; 68 bus_addr_t ba5_IDE_TF3; 69 bus_addr_t ba5_IDE_TF4; 70 bus_addr_t ba5_IDE_TF5; 71 bus_addr_t ba5_IDE_TF6; 72 bus_addr_t ba5_IDE_TF7; 73 bus_addr_t ba5_IDE_TF8; 74 bus_addr_t ba5_IDE_RAD; 75 bus_addr_t ba5_IDE_TF9; 76 bus_addr_t ba5_IDE_TF10; 77 bus_addr_t ba5_IDE_TF11; 78 bus_addr_t ba5_IDE_TF12; 79 bus_addr_t ba5_IDE_TF13; 80 bus_addr_t ba5_IDE_TF14; 81 bus_addr_t ba5_IDE_TF15; 82 bus_addr_t ba5_IDE_TF16; 83 bus_addr_t ba5_IDE_TF17; 84 bus_addr_t ba5_IDE_TF18; 85 bus_addr_t ba5_IDE_TF19; 86 bus_addr_t ba5_IDE_RABC; 87 bus_addr_t ba5_IDE_CMD_STS; 88 bus_addr_t ba5_IDE_CFG_STS; 89 bus_addr_t ba5_IDE_DTM; 90 bus_addr_t ba5_SControl; 91 bus_addr_t ba5_SStatus; 92 bus_addr_t ba5_SError; 93 bus_addr_t ba5_SActive; /* 3114 */ 94 bus_addr_t ba5_SMisc; 95 bus_addr_t ba5_PHY_CONFIG; 96 bus_addr_t ba5_SIEN; 97 bus_addr_t ba5_SFISCfg; 98 } satalink_ba5_regmap[] = { 99 { /* Channel 0 */ 100 .ba5_IDEDMA_CMD = 0x000, 101 .ba5_IDEDMA_CTL = 0x002, 102 .ba5_IDEDMA_TBL = 0x004, 103 .ba5_IDEDMA_CMD2 = 0x010, 104 .ba5_IDEDMA_CTL2 = 0x012, 105 .ba5_IDE_TF0 = 0x080, /* wd_data */ 106 .ba5_IDE_TF1 = 0x081, /* wd_error */ 107 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 108 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 109 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 110 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 111 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 112 .ba5_IDE_TF7 = 0x087, /* wd_command */ 113 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 114 .ba5_IDE_RAD = 0x08c, 115 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 116 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 117 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 118 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 119 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 120 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 121 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 122 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 123 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 124 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 125 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 126 .ba5_IDE_RABC = 0x09c, 127 .ba5_IDE_CMD_STS = 0x0a0, 128 .ba5_IDE_CFG_STS = 0x0a1, 129 .ba5_IDE_DTM = 0x0b4, 130 .ba5_SControl = 0x100, 131 .ba5_SStatus = 0x104, 132 .ba5_SError = 0x108, 133 .ba5_SActive = 0x10c, 134 .ba5_SMisc = 0x140, 135 .ba5_PHY_CONFIG = 0x144, 136 .ba5_SIEN = 0x148, 137 .ba5_SFISCfg = 0x14c, 138 }, 139 { /* Channel 1 */ 140 .ba5_IDEDMA_CMD = 0x008, 141 .ba5_IDEDMA_CTL = 0x00a, 142 .ba5_IDEDMA_TBL = 0x00c, 143 .ba5_IDEDMA_CMD2 = 0x018, 144 .ba5_IDEDMA_CTL2 = 0x01a, 145 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 146 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 147 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 148 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 149 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 150 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 151 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 152 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 153 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 154 .ba5_IDE_RAD = 0x0cc, 155 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 156 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 157 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 158 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 159 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 160 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 161 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 162 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 163 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 164 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 165 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 166 .ba5_IDE_RABC = 0x0dc, 167 .ba5_IDE_CMD_STS = 0x0e0, 168 .ba5_IDE_CFG_STS = 0x0e1, 169 .ba5_IDE_DTM = 0x0f4, 170 .ba5_SControl = 0x180, 171 .ba5_SStatus = 0x184, 172 .ba5_SError = 0x188, 173 .ba5_SActive = 0x18c, 174 .ba5_SMisc = 0x1c0, 175 .ba5_PHY_CONFIG = 0x1c4, 176 .ba5_SIEN = 0x1c8, 177 .ba5_SFISCfg = 0x1cc, 178 }, 179 { /* Channel 2 (3114) */ 180 .ba5_IDEDMA_CMD = 0x200, 181 .ba5_IDEDMA_CTL = 0x202, 182 .ba5_IDEDMA_TBL = 0x204, 183 .ba5_IDEDMA_CMD2 = 0x210, 184 .ba5_IDEDMA_CTL2 = 0x212, 185 .ba5_IDE_TF0 = 0x280, /* wd_data */ 186 .ba5_IDE_TF1 = 0x281, /* wd_error */ 187 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 188 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 189 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 190 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 191 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 192 .ba5_IDE_TF7 = 0x287, /* wd_command */ 193 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 194 .ba5_IDE_RAD = 0x28c, 195 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 196 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 197 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 198 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 199 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 200 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 201 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 202 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 203 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 204 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 205 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 206 .ba5_IDE_RABC = 0x29c, 207 .ba5_IDE_CMD_STS = 0x2a0, 208 .ba5_IDE_CFG_STS = 0x2a1, 209 .ba5_IDE_DTM = 0x2b4, 210 .ba5_SControl = 0x300, 211 .ba5_SStatus = 0x304, 212 .ba5_SError = 0x308, 213 .ba5_SActive = 0x30c, 214 .ba5_SMisc = 0x340, 215 .ba5_PHY_CONFIG = 0x344, 216 .ba5_SIEN = 0x348, 217 .ba5_SFISCfg = 0x34c, 218 }, 219 { /* Channel 3 (3114) */ 220 .ba5_IDEDMA_CMD = 0x208, 221 .ba5_IDEDMA_CTL = 0x20a, 222 .ba5_IDEDMA_TBL = 0x20c, 223 .ba5_IDEDMA_CMD2 = 0x218, 224 .ba5_IDEDMA_CTL2 = 0x21a, 225 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 226 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 227 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 228 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 229 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 230 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 231 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 232 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 233 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 234 .ba5_IDE_RAD = 0x2cc, 235 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 236 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 237 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 238 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 239 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 240 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 241 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 242 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 243 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 244 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 245 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 246 .ba5_IDE_RABC = 0x2dc, 247 .ba5_IDE_CMD_STS = 0x2e0, 248 .ba5_IDE_CFG_STS = 0x2e1, 249 .ba5_IDE_DTM = 0x2f4, 250 .ba5_SControl = 0x380, 251 .ba5_SStatus = 0x384, 252 .ba5_SError = 0x388, 253 .ba5_SActive = 0x38c, 254 .ba5_SMisc = 0x3c0, 255 .ba5_PHY_CONFIG = 0x3c4, 256 .ba5_SIEN = 0x3c8, 257 .ba5_SFISCfg = 0x3cc, 258 }, 259 }; 260 261 #define ba5_SIS 0x214 /* summary interrupt status */ 262 263 /* Interrupt steering bit in BA5[0x200]. */ 264 #define IDEDMA_CMD_INT_STEER (1U << 1) 265 266 static int satalink_match(device_t, cfdata_t, void *); 267 static void satalink_attach(device_t, device_t, void *); 268 269 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), 270 satalink_match, satalink_attach, NULL, NULL); 271 272 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 273 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 274 static void sii3112_drv_probe(struct ata_channel*); 275 static void sii3112_setup_channel(struct ata_channel*); 276 277 static const struct pciide_product_desc pciide_satalink_products[] = { 278 { PCI_PRODUCT_CMDTECH_3112, 279 0, 280 "Silicon Image SATALink 3112", 281 sii3112_chip_map, 282 }, 283 { PCI_PRODUCT_CMDTECH_3512, 284 0, 285 "Silicon Image SATALink 3512", 286 sii3112_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 289 0, 290 "Adaptec AAR-1210SA serial ATA RAID controller", 291 sii3112_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_3114, 294 0, 295 "Silicon Image SATALink 3114", 296 sii3114_chip_map, 297 }, 298 { 0, 299 0, 300 NULL, 301 NULL 302 } 303 }; 304 305 static int 306 satalink_match(device_t parent, cfdata_t match, void *aux) 307 { 308 struct pci_attach_args *pa = aux; 309 310 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 311 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 312 return (2); 313 } 314 return (0); 315 } 316 317 static void 318 satalink_attach(device_t parent, device_t self, void *aux) 319 { 320 struct pci_attach_args *pa = aux; 321 struct pciide_softc *sc = device_private(self); 322 323 sc->sc_wdcdev.sc_atac.atac_dev = self; 324 325 pciide_common_attach(sc, pa, 326 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 327 328 } 329 330 static inline uint32_t 331 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 332 { 333 uint32_t rv; 334 int s; 335 336 s = splbio(); 337 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 338 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 339 splx(s); 340 341 return (rv); 342 } 343 344 static inline uint32_t 345 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 346 { 347 348 if (__predict_true(sc->sc_ba5_en != 0)) 349 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 350 351 return (ba5_read_4_ind(sc, reg)); 352 } 353 354 #define BA5_READ_4(sc, chan, reg) \ 355 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 356 357 static inline void 358 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 359 { 360 int s; 361 362 s = splbio(); 363 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 364 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 365 splx(s); 366 } 367 368 static inline void 369 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 370 { 371 372 if (__predict_true(sc->sc_ba5_en != 0)) 373 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 374 else 375 ba5_write_4_ind(sc, reg, val); 376 } 377 378 #define BA5_WRITE_4(sc, chan, reg, val) \ 379 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 380 381 /* 382 * When the Silicon Image 3112 retries a PCI memory read command, 383 * it may retry it as a memory read multiple command under some 384 * circumstances. This can totally confuse some PCI controllers, 385 * so ensure that it will never do this by making sure that the 386 * Read Threshold (FIFO Read Request Control) field of the FIFO 387 * Valid Byte Count and Control registers for both channels (BA5 388 * offset 0x40 and 0x44) are set to be at least as large as the 389 * cacheline size register. 390 * This may also happen on the 3114 (ragge 050527) 391 */ 392 static void 393 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa, int n) 394 { 395 pcireg_t cls, reg; 396 int i; 397 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 398 399 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 400 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 401 cls *= 4; 402 if (cls > 224) { 403 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 404 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 405 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 406 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 407 cls = 224; 408 } 409 if (cls < 32) 410 cls = 32; 411 cls = (cls + 31) / 32; 412 for (i = 0; i < n; i++) { 413 reg = ba5_read_4(sc, addr[i]); 414 if ((reg & 0x7) < cls) 415 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 416 } 417 } 418 419 static void 420 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 421 { 422 struct pciide_channel *cp; 423 bus_size_t cmdsize, ctlsize; 424 pcireg_t interface, scs_cmd, cfgctl; 425 int channel; 426 427 if (pciide_chipen(sc, pa) == 0) 428 return; 429 430 #define SII3112_RESET_BITS \ 431 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 432 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 433 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 434 435 /* 436 * Reset everything and then unblock all of the interrupts. 437 */ 438 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 439 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 440 scs_cmd | SII3112_RESET_BITS); 441 delay(50 * 1000); 442 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 443 scs_cmd & SCS_CMD_BA5_EN); 444 delay(50 * 1000); 445 446 if (scs_cmd & SCS_CMD_BA5_EN) { 447 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 448 "SATALink BA5 register space enabled\n"); 449 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 450 PCI_MAPREG_TYPE_MEM| 451 PCI_MAPREG_MEM_TYPE_32BIT, 0, 452 &sc->sc_ba5_st, &sc->sc_ba5_sh, 453 NULL, NULL) != 0) 454 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 455 "unable to map SATALink BA5 register space\n"); 456 else 457 sc->sc_ba5_en = 1; 458 } else { 459 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 460 "SATALink BA5 register space disabled\n"); 461 462 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 463 SII3112_PCI_CFGCTL); 464 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 465 cfgctl | CFGCTL_BA5INDEN); 466 } 467 468 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 469 "bus-master DMA support present"); 470 pciide_mapreg_dma(sc, pa); 471 aprint_verbose("\n"); 472 473 /* 474 * Rev. <= 0x01 of the 3112 have a bug that can cause data 475 * corruption if DMA transfers cross an 8K boundary. This is 476 * apparently hard to tickle, but we'll go ahead and play it 477 * safe. 478 */ 479 if (PCI_REVISION(pa->pa_class) <= 0x01) { 480 sc->sc_dma_maxsegsz = 8192; 481 sc->sc_dma_boundary = 8192; 482 } 483 484 sii_fixup_cacheline(sc, pa, 2); 485 486 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 487 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 488 if (sc->sc_dma_ok) { 489 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 490 sc->sc_wdcdev.irqack = pciide_irqack; 491 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 492 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 493 } 494 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 495 496 /* We can use SControl and SStatus to probe for drives. */ 497 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 498 499 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 500 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 501 502 wdc_allocate_regs(&sc->sc_wdcdev); 503 504 /* 505 * The 3112 either identifies itself as a RAID storage device 506 * or a Misc storage device. Fake up the interface bits for 507 * what our driver expects. 508 */ 509 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 510 interface = PCI_INTERFACE(pa->pa_class); 511 } else { 512 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 513 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 514 } 515 516 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 517 channel++) { 518 cp = &sc->pciide_channels[channel]; 519 if (pciide_chansetup(sc, channel, interface) == 0) 520 continue; 521 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 522 pciide_pci_intr); 523 } 524 } 525 526 static void 527 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 528 { 529 struct pciide_channel *pc; 530 int chan, reg; 531 bus_size_t size; 532 533 sc->sc_wdcdev.dma_arg = sc; 534 sc->sc_wdcdev.dma_init = pciide_dma_init; 535 sc->sc_wdcdev.dma_start = pciide_dma_start; 536 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 537 538 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 539 PCIIDE_OPTIONS_NODMA) { 540 aprint_verbose( 541 ", but unused (forced off by config file)"); 542 sc->sc_dma_ok = 0; 543 return; 544 } 545 546 /* 547 * Slice off a subregion of BA5 for each of the channel's DMA 548 * registers. 549 */ 550 551 sc->sc_dma_iot = sc->sc_ba5_st; 552 for (chan = 0; chan < 4; chan++) { 553 pc = &sc->pciide_channels[chan]; 554 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 555 size = 4; 556 if (size > (IDEDMA_SCH_OFFSET - reg)) 557 size = IDEDMA_SCH_OFFSET - reg; 558 if (bus_space_subregion(sc->sc_ba5_st, 559 sc->sc_ba5_sh, 560 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 561 size, &pc->dma_iohs[reg]) != 0) { 562 sc->sc_dma_ok = 0; 563 aprint_verbose(", but can't subregion offset " 564 "%lu size %lu", 565 (u_long) satalink_ba5_regmap[ 566 chan].ba5_IDEDMA_CMD + reg, 567 (u_long) size); 568 return; 569 } 570 } 571 } 572 573 /* DMA registers all set up! */ 574 sc->sc_dmat = pa->pa_dmat; 575 sc->sc_dma_ok = 1; 576 } 577 578 static int 579 sii3114_chansetup(struct pciide_softc *sc, int channel) 580 { 581 static const char *channel_names[] = { 582 "port 0", 583 "port 1", 584 "port 2", 585 "port 3", 586 }; 587 struct pciide_channel *cp = &sc->pciide_channels[channel]; 588 589 sc->wdc_chanarray[channel] = &cp->ata_channel; 590 591 /* 592 * We must always keep the Interrupt Steering bit set in channel 2's 593 * IDEDMA_CMD register. 594 */ 595 if (channel == 2) 596 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 597 598 cp->name = channel_names[channel]; 599 cp->ata_channel.ch_channel = channel; 600 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 601 cp->ata_channel.ch_queue = 602 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 603 cp->ata_channel.ch_ndrive = 2; 604 if (cp->ata_channel.ch_queue == NULL) { 605 aprint_error("%s %s channel: " 606 "can't allocate memory for command queue", 607 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 608 return (0); 609 } 610 return (1); 611 } 612 613 static void 614 sii3114_mapchan(struct pciide_channel *cp) 615 { 616 struct ata_channel *wdc_cp = &cp->ata_channel; 617 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 618 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 619 int i; 620 621 cp->compat = 0; 622 cp->ih = sc->sc_pci_ih; 623 624 wdr->cmd_iot = sc->sc_ba5_st; 625 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 626 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 627 9, &wdr->cmd_baseioh) != 0) { 628 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 629 "couldn't subregion %s cmd base\n", cp->name); 630 goto bad; 631 } 632 633 wdr->ctl_iot = sc->sc_ba5_st; 634 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 635 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 636 1, &cp->ctl_baseioh) != 0) { 637 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 638 "couldn't subregion %s ctl base\n", cp->name); 639 goto bad; 640 } 641 wdr->ctl_ioh = cp->ctl_baseioh; 642 643 for (i = 0; i < WDC_NREG; i++) { 644 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 645 i, i == 0 ? 4 : 1, 646 &wdr->cmd_iohs[i]) != 0) { 647 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 648 "couldn't subregion %s channel cmd regs\n", 649 cp->name); 650 goto bad; 651 } 652 } 653 wdc_init_shadow_regs(wdc_cp); 654 wdr->data32iot = wdr->cmd_iot; 655 wdr->data32ioh = wdr->cmd_iohs[0]; 656 wdcattach(wdc_cp); 657 return; 658 659 bad: 660 cp->ata_channel.ch_flags |= ATACH_DISABLED; 661 } 662 663 static void 664 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 665 { 666 struct pciide_channel *cp; 667 pcireg_t scs_cmd; 668 pci_intr_handle_t intrhandle; 669 const char *intrstr; 670 int channel; 671 672 if (pciide_chipen(sc, pa) == 0) 673 return; 674 675 #define SII3114_RESET_BITS \ 676 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 677 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 678 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 679 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 680 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 681 682 /* 683 * Reset everything and then unblock all of the interrupts. 684 */ 685 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 686 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 687 scs_cmd | SII3114_RESET_BITS); 688 delay(50 * 1000); 689 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 690 scs_cmd & SCS_CMD_M66EN); 691 delay(50 * 1000); 692 693 /* 694 * On the 3114, the BA5 register space is always enabled. In 695 * order to use the 3114 in any sane way, we must use this BA5 696 * register space, and so we consider it an error if we cannot 697 * map it. 698 * 699 * As a consequence of using BA5, our register mapping is different 700 * from a normal PCI IDE controller's, and so we are unable to use 701 * most of the common PCI IDE register mapping functions. 702 */ 703 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 704 PCI_MAPREG_TYPE_MEM| 705 PCI_MAPREG_MEM_TYPE_32BIT, 0, 706 &sc->sc_ba5_st, &sc->sc_ba5_sh, 707 NULL, NULL) != 0) { 708 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 709 "unable to map SATALink BA5 register space\n"); 710 return; 711 } 712 sc->sc_ba5_en = 1; 713 714 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 715 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 716 717 /* 718 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 719 * channel 2. This is required at all times for proper operation 720 * when using the BA5 register space (otherwise interrupts from 721 * all 4 channels won't work). 722 */ 723 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 724 725 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 726 "bus-master DMA support present"); 727 sii3114_mapreg_dma(sc, pa); 728 aprint_verbose("\n"); 729 730 sii_fixup_cacheline(sc, pa, 4); 731 732 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 733 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 734 if (sc->sc_dma_ok) { 735 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 736 sc->sc_wdcdev.irqack = pciide_irqack; 737 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 738 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 739 } 740 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 741 742 /* We can use SControl and SStatus to probe for drives. */ 743 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 744 745 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 746 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 747 748 wdc_allocate_regs(&sc->sc_wdcdev); 749 750 /* Map and establish the interrupt handler. */ 751 if (pci_intr_map(pa, &intrhandle) != 0) { 752 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 753 "couldn't map native-PCI interrupt\n"); 754 return; 755 } 756 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 757 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 758 /* XXX */ 759 pciide_pci_intr, sc); 760 if (sc->sc_pci_ih != NULL) { 761 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 762 "using %s for native-PCI interrupt\n", 763 intrstr ? intrstr : "unknown interrupt"); 764 } else { 765 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 766 "couldn't establish native-PCI interrupt"); 767 if (intrstr != NULL) 768 aprint_normal(" at %s", intrstr); 769 aprint_normal("\n"); 770 return; 771 } 772 773 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 774 channel++) { 775 cp = &sc->pciide_channels[channel]; 776 if (sii3114_chansetup(sc, channel) == 0) 777 continue; 778 sii3114_mapchan(cp); 779 } 780 } 781 782 /* Probe the drives using SATA registers. 783 * Note we can't use wdc_sataprobe as we may not be able to map ba5 784 */ 785 static void 786 sii3112_drv_probe(struct ata_channel *chp) 787 { 788 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 789 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 790 uint32_t scontrol, sstatus; 791 uint8_t scnt, sn, cl, ch; 792 int i, s; 793 794 /* XXX This should be done by other code. */ 795 for (i = 0; i < 2; i++) { 796 chp->ch_drive[i].chnl_softc = chp; 797 chp->ch_drive[i].drive = i; 798 } 799 800 /* 801 * The 3112 is a 2-port part, and only has one drive per channel 802 * (each port emulates a master drive). 803 * 804 * The 3114 is similar, but has 4 channels. 805 */ 806 807 /* 808 * Request communication initialization sequence, any speed. 809 * Performing this is the equivalent of an ATA Reset. 810 */ 811 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 812 813 /* 814 * XXX We don't yet support SATA power management; disable all 815 * power management state transitions. 816 */ 817 scontrol |= SControl_IPM_NONE; 818 819 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 820 delay(50 * 1000); 821 scontrol &= ~SControl_DET_INIT; 822 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 823 delay(50 * 1000); 824 825 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 826 #if 0 827 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 828 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus, 829 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 830 #endif 831 switch (sstatus & SStatus_DET_mask) { 832 case SStatus_DET_NODEV: 833 /* No device; be silent. */ 834 break; 835 836 case SStatus_DET_DEV_NE: 837 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 838 "port %d: device connected, but " 839 "communication not established\n", chp->ch_channel); 840 break; 841 842 case SStatus_DET_OFFLINE: 843 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 844 "port %d: PHY offline\n", chp->ch_channel); 845 break; 846 847 case SStatus_DET_DEV: 848 /* 849 * XXX ATAPI detection doesn't currently work. Don't 850 * XXX know why. But, it's not like the standard method 851 * XXX can detect an ATAPI device connected via a SATA/PATA 852 * XXX bridge, so at least this is no worse. --thorpej 853 */ 854 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 855 WDSD_IBM | (0 << 4)); 856 delay(10); /* 400ns delay */ 857 /* Save register contents. */ 858 scnt = bus_space_read_1(wdr->cmd_iot, 859 wdr->cmd_iohs[wd_seccnt], 0); 860 sn = bus_space_read_1(wdr->cmd_iot, 861 wdr->cmd_iohs[wd_sector], 0); 862 cl = bus_space_read_1(wdr->cmd_iot, 863 wdr->cmd_iohs[wd_cyl_lo], 0); 864 ch = bus_space_read_1(wdr->cmd_iot, 865 wdr->cmd_iohs[wd_cyl_hi], 0); 866 #if 0 867 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 868 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 869 scnt, sn, cl, ch); 870 #endif 871 /* 872 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 873 * cases we get wrong values here, so ignore it. 874 */ 875 s = splbio(); 876 if (cl == 0x14 && ch == 0xeb) 877 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 878 else 879 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 880 splx(s); 881 882 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 883 "port %d: device present, speed: %s\n", 884 chp->ch_channel, 885 sata_speed(sstatus)); 886 break; 887 888 default: 889 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 890 "port %d: unknown SStatus: 0x%08x\n", 891 chp->ch_channel, sstatus); 892 } 893 } 894 895 static void 896 sii3112_setup_channel(struct ata_channel *chp) 897 { 898 struct ata_drive_datas *drvp; 899 int drive, s; 900 u_int32_t idedma_ctl, dtm; 901 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 902 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 903 904 /* setup DMA if needed */ 905 pciide_channel_dma_setup(cp); 906 907 idedma_ctl = 0; 908 dtm = 0; 909 910 for (drive = 0; drive < 2; drive++) { 911 drvp = &chp->ch_drive[drive]; 912 /* If no drive, skip */ 913 if ((drvp->drive_flags & DRIVE) == 0) 914 continue; 915 if (drvp->drive_flags & DRIVE_UDMA) { 916 /* use Ultra/DMA */ 917 s = splbio(); 918 drvp->drive_flags &= ~DRIVE_DMA; 919 splx(s); 920 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 921 dtm |= DTM_IDEx_DMA; 922 } else if (drvp->drive_flags & DRIVE_DMA) { 923 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 924 dtm |= DTM_IDEx_DMA; 925 } else { 926 dtm |= DTM_IDEx_PIO; 927 } 928 } 929 930 /* 931 * Nothing to do to setup modes; it is meaningless in S-ATA 932 * (but many S-ATA drives still want to get the SET_FEATURE 933 * command). 934 */ 935 if (idedma_ctl != 0) { 936 /* Add software bits in status register */ 937 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 938 idedma_ctl); 939 } 940 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 941 } 942
Indexes created Thu Oct 02 14:10:14 GMT 2025