satalink.c revision 1.28
1 /* $NetBSD: satalink.c,v 1.28 2006/01/16 20:30:19 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 #include <dev/ata/satavar.h> 51 #include <dev/ata/atareg.h> 52 53 /* 54 * Register map for BA5 register space, indexed by channel. 55 */ 56 static const struct { 57 bus_addr_t ba5_IDEDMA_CMD; 58 bus_addr_t ba5_IDEDMA_CTL; 59 bus_addr_t ba5_IDEDMA_TBL; 60 bus_addr_t ba5_IDEDMA_CMD2; 61 bus_addr_t ba5_IDEDMA_CTL2; 62 bus_addr_t ba5_IDE_TF0; 63 bus_addr_t ba5_IDE_TF1; 64 bus_addr_t ba5_IDE_TF2; 65 bus_addr_t ba5_IDE_TF3; 66 bus_addr_t ba5_IDE_TF4; 67 bus_addr_t ba5_IDE_TF5; 68 bus_addr_t ba5_IDE_TF6; 69 bus_addr_t ba5_IDE_TF7; 70 bus_addr_t ba5_IDE_TF8; 71 bus_addr_t ba5_IDE_RAD; 72 bus_addr_t ba5_IDE_TF9; 73 bus_addr_t ba5_IDE_TF10; 74 bus_addr_t ba5_IDE_TF11; 75 bus_addr_t ba5_IDE_TF12; 76 bus_addr_t ba5_IDE_TF13; 77 bus_addr_t ba5_IDE_TF14; 78 bus_addr_t ba5_IDE_TF15; 79 bus_addr_t ba5_IDE_TF16; 80 bus_addr_t ba5_IDE_TF17; 81 bus_addr_t ba5_IDE_TF18; 82 bus_addr_t ba5_IDE_TF19; 83 bus_addr_t ba5_IDE_RABC; 84 bus_addr_t ba5_IDE_CMD_STS; 85 bus_addr_t ba5_IDE_CFG_STS; 86 bus_addr_t ba5_IDE_DTM; 87 bus_addr_t ba5_SControl; 88 bus_addr_t ba5_SStatus; 89 bus_addr_t ba5_SError; 90 bus_addr_t ba5_SActive; /* 3114 */ 91 bus_addr_t ba5_SMisc; 92 bus_addr_t ba5_PHY_CONFIG; 93 bus_addr_t ba5_SIEN; 94 bus_addr_t ba5_SFISCfg; 95 } satalink_ba5_regmap[] = { 96 { /* Channel 0 */ 97 .ba5_IDEDMA_CMD = 0x000, 98 .ba5_IDEDMA_CTL = 0x002, 99 .ba5_IDEDMA_TBL = 0x004, 100 .ba5_IDEDMA_CMD2 = 0x010, 101 .ba5_IDEDMA_CTL2 = 0x012, 102 .ba5_IDE_TF0 = 0x080, /* wd_data */ 103 .ba5_IDE_TF1 = 0x081, /* wd_error */ 104 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 105 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 106 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 107 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 108 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 109 .ba5_IDE_TF7 = 0x087, /* wd_command */ 110 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 111 .ba5_IDE_RAD = 0x08c, 112 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 113 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 114 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 115 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 116 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 117 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 118 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 119 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 120 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 121 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 122 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 123 .ba5_IDE_RABC = 0x09c, 124 .ba5_IDE_CMD_STS = 0x0a0, 125 .ba5_IDE_CFG_STS = 0x0a1, 126 .ba5_IDE_DTM = 0x0b4, 127 .ba5_SControl = 0x100, 128 .ba5_SStatus = 0x104, 129 .ba5_SError = 0x108, 130 .ba5_SActive = 0x10c, 131 .ba5_SMisc = 0x140, 132 .ba5_PHY_CONFIG = 0x144, 133 .ba5_SIEN = 0x148, 134 .ba5_SFISCfg = 0x14c, 135 }, 136 { /* Channel 1 */ 137 .ba5_IDEDMA_CMD = 0x008, 138 .ba5_IDEDMA_CTL = 0x00a, 139 .ba5_IDEDMA_TBL = 0x00c, 140 .ba5_IDEDMA_CMD2 = 0x018, 141 .ba5_IDEDMA_CTL2 = 0x01a, 142 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 143 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 144 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 145 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 146 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 147 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 148 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 149 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 150 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 151 .ba5_IDE_RAD = 0x0cc, 152 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 153 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 154 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 155 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 156 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 157 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 158 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 159 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 160 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 161 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 162 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 163 .ba5_IDE_RABC = 0x0dc, 164 .ba5_IDE_CMD_STS = 0x0e0, 165 .ba5_IDE_CFG_STS = 0x0e1, 166 .ba5_IDE_DTM = 0x0f4, 167 .ba5_SControl = 0x180, 168 .ba5_SStatus = 0x184, 169 .ba5_SError = 0x188, 170 .ba5_SActive = 0x18c, 171 .ba5_SMisc = 0x1c0, 172 .ba5_PHY_CONFIG = 0x1c4, 173 .ba5_SIEN = 0x1c8, 174 .ba5_SFISCfg = 0x1cc, 175 }, 176 { /* Channel 2 (3114) */ 177 .ba5_IDEDMA_CMD = 0x200, 178 .ba5_IDEDMA_CTL = 0x202, 179 .ba5_IDEDMA_TBL = 0x204, 180 .ba5_IDEDMA_CMD2 = 0x210, 181 .ba5_IDEDMA_CTL2 = 0x212, 182 .ba5_IDE_TF0 = 0x280, /* wd_data */ 183 .ba5_IDE_TF1 = 0x281, /* wd_error */ 184 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 185 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 186 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 187 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 188 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 189 .ba5_IDE_TF7 = 0x287, /* wd_command */ 190 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 191 .ba5_IDE_RAD = 0x28c, 192 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 193 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 194 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 195 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 196 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 197 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 198 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 199 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 200 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 201 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 202 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 203 .ba5_IDE_RABC = 0x29c, 204 .ba5_IDE_CMD_STS = 0x2a0, 205 .ba5_IDE_CFG_STS = 0x2a1, 206 .ba5_IDE_DTM = 0x2b4, 207 .ba5_SControl = 0x300, 208 .ba5_SStatus = 0x304, 209 .ba5_SError = 0x308, 210 .ba5_SActive = 0x30c, 211 .ba5_SMisc = 0x340, 212 .ba5_PHY_CONFIG = 0x344, 213 .ba5_SIEN = 0x348, 214 .ba5_SFISCfg = 0x34c, 215 }, 216 { /* Channel 3 (3114) */ 217 .ba5_IDEDMA_CMD = 0x208, 218 .ba5_IDEDMA_CTL = 0x20a, 219 .ba5_IDEDMA_TBL = 0x20c, 220 .ba5_IDEDMA_CMD2 = 0x218, 221 .ba5_IDEDMA_CTL2 = 0x21a, 222 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 223 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 224 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 225 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 226 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 227 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 228 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 229 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 230 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 231 .ba5_IDE_RAD = 0x2cc, 232 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 233 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 234 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 235 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 236 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 237 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 238 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 239 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 240 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 241 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 242 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 243 .ba5_IDE_RABC = 0x2dc, 244 .ba5_IDE_CMD_STS = 0x2e0, 245 .ba5_IDE_CFG_STS = 0x2e1, 246 .ba5_IDE_DTM = 0x2f4, 247 .ba5_SControl = 0x380, 248 .ba5_SStatus = 0x384, 249 .ba5_SError = 0x388, 250 .ba5_SActive = 0x38c, 251 .ba5_SMisc = 0x3c0, 252 .ba5_PHY_CONFIG = 0x3c4, 253 .ba5_SIEN = 0x3c8, 254 .ba5_SFISCfg = 0x3cc, 255 }, 256 }; 257 258 #define ba5_SIS 0x214 /* summary interrupt status */ 259 260 /* Interrupt steering bit in BA5[0x200]. */ 261 #define IDEDMA_CMD_INT_STEER (1U << 1) 262 263 static int satalink_match(struct device *, struct cfdata *, void *); 264 static void satalink_attach(struct device *, struct device *, void *); 265 266 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 267 satalink_match, satalink_attach, NULL, NULL); 268 269 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 270 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 271 static void sii3112_drv_probe(struct ata_channel*); 272 static void sii3112_setup_channel(struct ata_channel*); 273 274 static const struct pciide_product_desc pciide_satalink_products[] = { 275 { PCI_PRODUCT_CMDTECH_3112, 276 0, 277 "Silicon Image SATALink 3112", 278 sii3112_chip_map, 279 }, 280 { PCI_PRODUCT_CMDTECH_3512, 281 0, 282 "Silicon Image SATALink 3512", 283 sii3112_chip_map, 284 }, 285 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 286 0, 287 "Adaptec AAR-1210SA serial ATA RAID controller", 288 sii3112_chip_map, 289 }, 290 { PCI_PRODUCT_CMDTECH_3114, 291 0, 292 "Silicon Image SATALink 3114", 293 sii3114_chip_map, 294 }, 295 { 0, 296 0, 297 NULL, 298 NULL 299 } 300 }; 301 302 static int 303 satalink_match(struct device *parent, struct cfdata *match, void *aux) 304 { 305 struct pci_attach_args *pa = aux; 306 307 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 308 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 309 return (2); 310 } 311 return (0); 312 } 313 314 static void 315 satalink_attach(struct device *parent, struct device *self, void *aux) 316 { 317 struct pci_attach_args *pa = aux; 318 struct pciide_softc *sc = (struct pciide_softc *)self; 319 320 pciide_common_attach(sc, pa, 321 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 322 323 } 324 325 static inline uint32_t 326 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 327 { 328 uint32_t rv; 329 int s; 330 331 s = splbio(); 332 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 333 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 334 splx(s); 335 336 return (rv); 337 } 338 339 static inline uint32_t 340 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 341 { 342 343 if (__predict_true(sc->sc_ba5_en != 0)) 344 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 345 346 return (ba5_read_4_ind(sc, reg)); 347 } 348 349 #define BA5_READ_4(sc, chan, reg) \ 350 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 351 352 static inline void 353 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 354 { 355 int s; 356 357 s = splbio(); 358 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 359 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 360 splx(s); 361 } 362 363 static inline void 364 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 365 { 366 367 if (__predict_true(sc->sc_ba5_en != 0)) 368 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 369 else 370 ba5_write_4_ind(sc, reg, val); 371 } 372 373 #define BA5_WRITE_4(sc, chan, reg, val) \ 374 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 375 376 /* 377 * When the Silicon Image 3112 retries a PCI memory read command, 378 * it may retry it as a memory read multiple command under some 379 * circumstances. This can totally confuse some PCI controllers, 380 * so ensure that it will never do this by making sure that the 381 * Read Threshold (FIFO Read Request Control) field of the FIFO 382 * Valid Byte Count and Control registers for both channels (BA5 383 * offset 0x40 and 0x44) are set to be at least as large as the 384 * cacheline size register. 385 * This may also happen on the 3114 (ragge 050527) 386 */ 387 static void 388 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa) 389 { 390 pcireg_t cls, reg40, reg44; 391 392 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 393 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 394 cls *= 4; 395 if (cls > 224) { 396 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 397 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 398 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 399 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 400 cls = 224; 401 } 402 if (cls < 32) 403 cls = 32; 404 cls = (cls + 31) / 32; 405 reg40 = ba5_read_4(sc, 0x40); 406 reg44 = ba5_read_4(sc, 0x44); 407 if ((reg40 & 0x7) < cls) 408 ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls); 409 if ((reg44 & 0x7) < cls) 410 ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls); 411 } 412 413 static void 414 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 415 { 416 struct pciide_channel *cp; 417 bus_size_t cmdsize, ctlsize; 418 pcireg_t interface, scs_cmd, cfgctl; 419 int channel; 420 421 if (pciide_chipen(sc, pa) == 0) 422 return; 423 424 #define SII3112_RESET_BITS \ 425 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 426 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 427 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 428 429 /* 430 * Reset everything and then unblock all of the interrupts. 431 */ 432 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 433 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 434 scs_cmd | SII3112_RESET_BITS); 435 delay(50 * 1000); 436 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 437 scs_cmd & SCS_CMD_BA5_EN); 438 delay(50 * 1000); 439 440 if (scs_cmd & SCS_CMD_BA5_EN) { 441 aprint_verbose("%s: SATALink BA5 register space enabled\n", 442 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 443 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 444 PCI_MAPREG_TYPE_MEM| 445 PCI_MAPREG_MEM_TYPE_32BIT, 0, 446 &sc->sc_ba5_st, &sc->sc_ba5_sh, 447 NULL, NULL) != 0) 448 aprint_error("%s: unable to map SATALink BA5 " 449 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 450 else 451 sc->sc_ba5_en = 1; 452 } else { 453 aprint_verbose("%s: SATALink BA5 register space disabled\n", 454 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 455 456 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 457 SII3112_PCI_CFGCTL); 458 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 459 cfgctl | CFGCTL_BA5INDEN); 460 } 461 462 aprint_normal("%s: bus-master DMA support present", 463 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 464 pciide_mapreg_dma(sc, pa); 465 aprint_normal("\n"); 466 467 /* 468 * Rev. <= 0x01 of the 3112 have a bug that can cause data 469 * corruption if DMA transfers cross an 8K boundary. This is 470 * apparently hard to tickle, but we'll go ahead and play it 471 * safe. 472 */ 473 if (PCI_REVISION(pa->pa_class) <= 0x01) { 474 sc->sc_dma_maxsegsz = 8192; 475 sc->sc_dma_boundary = 8192; 476 } 477 478 sii_fixup_cacheline(sc, pa); 479 480 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 481 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 482 if (sc->sc_dma_ok) { 483 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 484 sc->sc_wdcdev.irqack = pciide_irqack; 485 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 486 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 487 } 488 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 489 490 /* We can use SControl and SStatus to probe for drives. */ 491 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 492 493 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 494 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 495 496 wdc_allocate_regs(&sc->sc_wdcdev); 497 498 /* 499 * The 3112 either identifies itself as a RAID storage device 500 * or a Misc storage device. Fake up the interface bits for 501 * what our driver expects. 502 */ 503 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 504 interface = PCI_INTERFACE(pa->pa_class); 505 } else { 506 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 507 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 508 } 509 510 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 511 channel++) { 512 cp = &sc->pciide_channels[channel]; 513 if (pciide_chansetup(sc, channel, interface) == 0) 514 continue; 515 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 516 pciide_pci_intr); 517 } 518 } 519 520 static void 521 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 522 { 523 struct pciide_channel *pc; 524 int chan, reg; 525 bus_size_t size; 526 527 sc->sc_wdcdev.dma_arg = sc; 528 sc->sc_wdcdev.dma_init = pciide_dma_init; 529 sc->sc_wdcdev.dma_start = pciide_dma_start; 530 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 531 532 if (sc->sc_wdcdev.sc_atac.atac_dev.dv_cfdata->cf_flags & 533 PCIIDE_OPTIONS_NODMA) { 534 aprint_normal( 535 ", but unused (forced off by config file)"); 536 sc->sc_dma_ok = 0; 537 return; 538 } 539 540 /* 541 * Slice off a subregion of BA5 for each of the channel's DMA 542 * registers. 543 */ 544 545 sc->sc_dma_iot = sc->sc_ba5_st; 546 for (chan = 0; chan < 4; chan++) { 547 pc = &sc->pciide_channels[chan]; 548 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 549 size = 4; 550 if (size > (IDEDMA_SCH_OFFSET - reg)) 551 size = IDEDMA_SCH_OFFSET - reg; 552 if (bus_space_subregion(sc->sc_ba5_st, 553 sc->sc_ba5_sh, 554 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 555 size, &pc->dma_iohs[reg]) != 0) { 556 sc->sc_dma_ok = 0; 557 aprint_normal(", but can't subregion offset " 558 "%lu size %lu", 559 (u_long) satalink_ba5_regmap[ 560 chan].ba5_IDEDMA_CMD + reg, 561 (u_long) size); 562 return; 563 } 564 } 565 } 566 567 /* DMA registers all set up! */ 568 sc->sc_dmat = pa->pa_dmat; 569 sc->sc_dma_ok = 1; 570 } 571 572 static int 573 sii3114_chansetup(struct pciide_softc *sc, int channel) 574 { 575 static const char *channel_names[] = { 576 "port 0", 577 "port 1", 578 "port 2", 579 "port 3", 580 }; 581 struct pciide_channel *cp = &sc->pciide_channels[channel]; 582 583 sc->wdc_chanarray[channel] = &cp->ata_channel; 584 585 /* 586 * We must always keep the Interrupt Steering bit set in channel 2's 587 * IDEDMA_CMD register. 588 */ 589 if (channel == 2) 590 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 591 592 cp->name = channel_names[channel]; 593 cp->ata_channel.ch_channel = channel; 594 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 595 cp->ata_channel.ch_queue = 596 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 597 cp->ata_channel.ch_ndrive = 2; 598 if (cp->ata_channel.ch_queue == NULL) { 599 aprint_error("%s %s channel: " 600 "can't allocate memory for command queue", 601 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 602 return (0); 603 } 604 return (1); 605 } 606 607 static void 608 sii3114_mapchan(struct pciide_channel *cp) 609 { 610 struct ata_channel *wdc_cp = &cp->ata_channel; 611 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 612 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 613 int i; 614 615 cp->compat = 0; 616 cp->ih = sc->sc_pci_ih; 617 618 wdr->cmd_iot = sc->sc_ba5_st; 619 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 620 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 621 9, &wdr->cmd_baseioh) != 0) { 622 aprint_error("%s: couldn't subregion %s cmd base\n", 623 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 624 goto bad; 625 } 626 627 wdr->ctl_iot = sc->sc_ba5_st; 628 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 629 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 630 1, &cp->ctl_baseioh) != 0) { 631 aprint_error("%s: couldn't subregion %s ctl base\n", 632 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 633 goto bad; 634 } 635 wdr->ctl_ioh = cp->ctl_baseioh; 636 637 for (i = 0; i < WDC_NREG; i++) { 638 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 639 i, i == 0 ? 4 : 1, 640 &wdr->cmd_iohs[i]) != 0) { 641 aprint_error("%s: couldn't subregion %s channel " 642 "cmd regs\n", 643 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 644 goto bad; 645 } 646 } 647 wdc_init_shadow_regs(wdc_cp); 648 wdr->data32iot = wdr->cmd_iot; 649 wdr->data32ioh = wdr->cmd_iohs[0]; 650 wdcattach(wdc_cp); 651 return; 652 653 bad: 654 cp->ata_channel.ch_flags |= ATACH_DISABLED; 655 } 656 657 static void 658 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 659 { 660 struct pciide_channel *cp; 661 pcireg_t scs_cmd; 662 pci_intr_handle_t intrhandle; 663 const char *intrstr; 664 int channel; 665 666 if (pciide_chipen(sc, pa) == 0) 667 return; 668 669 #define SII3114_RESET_BITS \ 670 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 671 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 672 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 673 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 674 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 675 676 /* 677 * Reset everything and then unblock all of the interrupts. 678 */ 679 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 680 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 681 scs_cmd | SII3114_RESET_BITS); 682 delay(50 * 1000); 683 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 684 scs_cmd & SCS_CMD_M66EN); 685 delay(50 * 1000); 686 687 /* 688 * On the 3114, the BA5 register space is always enabled. In 689 * order to use the 3114 in any sane way, we must use this BA5 690 * register space, and so we consider it an error if we cannot 691 * map it. 692 * 693 * As a consequence of using BA5, our register mapping is different 694 * from a normal PCI IDE controller's, and so we are unable to use 695 * most of the common PCI IDE register mapping functions. 696 */ 697 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 698 PCI_MAPREG_TYPE_MEM| 699 PCI_MAPREG_MEM_TYPE_32BIT, 0, 700 &sc->sc_ba5_st, &sc->sc_ba5_sh, 701 NULL, NULL) != 0) { 702 aprint_error("%s: unable to map SATALink BA5 " 703 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 704 return; 705 } 706 sc->sc_ba5_en = 1; 707 708 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 709 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 710 711 /* 712 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 713 * channel 2. This is required at all times for proper operation 714 * when using the BA5 register space (otherwise interrupts from 715 * all 4 channels won't work). 716 */ 717 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 718 719 aprint_normal("%s: bus-master DMA support present", 720 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 721 sii3114_mapreg_dma(sc, pa); 722 aprint_normal("\n"); 723 724 sii_fixup_cacheline(sc, pa); 725 726 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 727 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 728 if (sc->sc_dma_ok) { 729 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 730 sc->sc_wdcdev.irqack = pciide_irqack; 731 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 732 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 733 } 734 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 735 736 /* We can use SControl and SStatus to probe for drives. */ 737 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 738 739 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 740 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 741 742 wdc_allocate_regs(&sc->sc_wdcdev); 743 744 /* Map and establish the interrupt handler. */ 745 if (pci_intr_map(pa, &intrhandle) != 0) { 746 aprint_error("%s: couldn't map native-PCI interrupt\n", 747 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 748 return; 749 } 750 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 751 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 752 /* XXX */ 753 pciide_pci_intr, sc); 754 if (sc->sc_pci_ih != NULL) { 755 aprint_normal("%s: using %s for native-PCI interrupt\n", 756 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 757 intrstr ? intrstr : "unknown interrupt"); 758 } else { 759 aprint_error("%s: couldn't establish native-PCI interrupt", 760 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 761 if (intrstr != NULL) 762 aprint_normal(" at %s", intrstr); 763 aprint_normal("\n"); 764 return; 765 } 766 767 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 768 channel++) { 769 cp = &sc->pciide_channels[channel]; 770 if (sii3114_chansetup(sc, channel) == 0) 771 continue; 772 sii3114_mapchan(cp); 773 } 774 } 775 776 static void 777 sii3112_drv_probe(struct ata_channel *chp) 778 { 779 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 780 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 781 uint32_t scontrol, sstatus; 782 uint8_t scnt, sn, cl, ch; 783 int i, s; 784 785 /* XXX This should be done by other code. */ 786 for (i = 0; i < 2; i++) { 787 chp->ch_drive[i].chnl_softc = chp; 788 chp->ch_drive[i].drive = i; 789 } 790 791 /* 792 * The 3112 is a 2-port part, and only has one drive per channel 793 * (each port emulates a master drive). 794 * 795 * The 3114 is similar, but has 4 channels. 796 */ 797 798 /* 799 * Request communication initialization sequence, any speed. 800 * Performing this is the equivalent of an ATA Reset. 801 */ 802 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 803 804 /* 805 * XXX We don't yet support SATA power management; disable all 806 * power management state transitions. 807 */ 808 scontrol |= SControl_IPM_NONE; 809 810 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 811 delay(50 * 1000); 812 scontrol &= ~SControl_DET_INIT; 813 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 814 delay(50 * 1000); 815 816 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 817 #if 0 818 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 819 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus, 820 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 821 #endif 822 switch (sstatus & SStatus_DET_mask) { 823 case SStatus_DET_NODEV: 824 /* No device; be silent. */ 825 break; 826 827 case SStatus_DET_DEV_NE: 828 aprint_error("%s: port %d: device connected, but " 829 "communication not established\n", 830 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 831 break; 832 833 case SStatus_DET_OFFLINE: 834 aprint_error("%s: port %d: PHY offline\n", 835 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 836 break; 837 838 case SStatus_DET_DEV: 839 /* 840 * XXX ATAPI detection doesn't currently work. Don't 841 * XXX know why. But, it's not like the standard method 842 * XXX can detect an ATAPI device connected via a SATA/PATA 843 * XXX bridge, so at least this is no worse. --thorpej 844 */ 845 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 846 WDSD_IBM | (0 << 4)); 847 delay(10); /* 400ns delay */ 848 /* Save register contents. */ 849 scnt = bus_space_read_1(wdr->cmd_iot, 850 wdr->cmd_iohs[wd_seccnt], 0); 851 sn = bus_space_read_1(wdr->cmd_iot, 852 wdr->cmd_iohs[wd_sector], 0); 853 cl = bus_space_read_1(wdr->cmd_iot, 854 wdr->cmd_iohs[wd_cyl_lo], 0); 855 ch = bus_space_read_1(wdr->cmd_iot, 856 wdr->cmd_iohs[wd_cyl_hi], 0); 857 #if 0 858 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 859 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 860 scnt, sn, cl, ch); 861 #endif 862 /* 863 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 864 * cases we get wrong values here, so ignore it. 865 */ 866 s = splbio(); 867 if (cl == 0x14 && ch == 0xeb) 868 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 869 else 870 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 871 splx(s); 872 873 aprint_normal("%s: port %d: device present, speed: %s\n", 874 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 875 sata_speed(sstatus)); 876 break; 877 878 default: 879 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 880 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus); 881 } 882 } 883 884 static void 885 sii3112_setup_channel(struct ata_channel *chp) 886 { 887 struct ata_drive_datas *drvp; 888 int drive, s; 889 u_int32_t idedma_ctl, dtm; 890 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 891 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 892 893 /* setup DMA if needed */ 894 pciide_channel_dma_setup(cp); 895 896 idedma_ctl = 0; 897 dtm = 0; 898 899 for (drive = 0; drive < 2; drive++) { 900 drvp = &chp->ch_drive[drive]; 901 /* If no drive, skip */ 902 if ((drvp->drive_flags & DRIVE) == 0) 903 continue; 904 if (drvp->drive_flags & DRIVE_UDMA) { 905 /* use Ultra/DMA */ 906 s = splbio(); 907 drvp->drive_flags &= ~DRIVE_DMA; 908 splx(s); 909 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 910 dtm |= DTM_IDEx_DMA; 911 } else if (drvp->drive_flags & DRIVE_DMA) { 912 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 913 dtm |= DTM_IDEx_DMA; 914 } else { 915 dtm |= DTM_IDEx_PIO; 916 } 917 } 918 919 /* 920 * Nothing to do to setup modes; it is meaningless in S-ATA 921 * (but many S-ATA drives still want to get the SET_FEATURE 922 * command). 923 */ 924 if (idedma_ctl != 0) { 925 /* Add software bits in status register */ 926 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 927 idedma_ctl); 928 } 929 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 930 } 931
Indexes created Mon Sep 29 21:09:56 GMT 2025