satalink.c revision 1.28.6.2
1 /* $NetBSD: satalink.c,v 1.28.6.2 2006/08/11 15:44:26 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.28.6.2 2006/08/11 15:44:26 yamt Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/pci/pciide_sii3112_reg.h> 51 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 #include <dev/ata/atareg.h> 55 56 /* 57 * Register map for BA5 register space, indexed by channel. 58 */ 59 static const struct { 60 bus_addr_t ba5_IDEDMA_CMD; 61 bus_addr_t ba5_IDEDMA_CTL; 62 bus_addr_t ba5_IDEDMA_TBL; 63 bus_addr_t ba5_IDEDMA_CMD2; 64 bus_addr_t ba5_IDEDMA_CTL2; 65 bus_addr_t ba5_IDE_TF0; 66 bus_addr_t ba5_IDE_TF1; 67 bus_addr_t ba5_IDE_TF2; 68 bus_addr_t ba5_IDE_TF3; 69 bus_addr_t ba5_IDE_TF4; 70 bus_addr_t ba5_IDE_TF5; 71 bus_addr_t ba5_IDE_TF6; 72 bus_addr_t ba5_IDE_TF7; 73 bus_addr_t ba5_IDE_TF8; 74 bus_addr_t ba5_IDE_RAD; 75 bus_addr_t ba5_IDE_TF9; 76 bus_addr_t ba5_IDE_TF10; 77 bus_addr_t ba5_IDE_TF11; 78 bus_addr_t ba5_IDE_TF12; 79 bus_addr_t ba5_IDE_TF13; 80 bus_addr_t ba5_IDE_TF14; 81 bus_addr_t ba5_IDE_TF15; 82 bus_addr_t ba5_IDE_TF16; 83 bus_addr_t ba5_IDE_TF17; 84 bus_addr_t ba5_IDE_TF18; 85 bus_addr_t ba5_IDE_TF19; 86 bus_addr_t ba5_IDE_RABC; 87 bus_addr_t ba5_IDE_CMD_STS; 88 bus_addr_t ba5_IDE_CFG_STS; 89 bus_addr_t ba5_IDE_DTM; 90 bus_addr_t ba5_SControl; 91 bus_addr_t ba5_SStatus; 92 bus_addr_t ba5_SError; 93 bus_addr_t ba5_SActive; /* 3114 */ 94 bus_addr_t ba5_SMisc; 95 bus_addr_t ba5_PHY_CONFIG; 96 bus_addr_t ba5_SIEN; 97 bus_addr_t ba5_SFISCfg; 98 } satalink_ba5_regmap[] = { 99 { /* Channel 0 */ 100 .ba5_IDEDMA_CMD = 0x000, 101 .ba5_IDEDMA_CTL = 0x002, 102 .ba5_IDEDMA_TBL = 0x004, 103 .ba5_IDEDMA_CMD2 = 0x010, 104 .ba5_IDEDMA_CTL2 = 0x012, 105 .ba5_IDE_TF0 = 0x080, /* wd_data */ 106 .ba5_IDE_TF1 = 0x081, /* wd_error */ 107 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 108 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 109 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 110 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 111 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 112 .ba5_IDE_TF7 = 0x087, /* wd_command */ 113 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 114 .ba5_IDE_RAD = 0x08c, 115 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 116 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 117 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 118 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 119 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 120 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 121 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 122 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 123 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 124 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 125 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 126 .ba5_IDE_RABC = 0x09c, 127 .ba5_IDE_CMD_STS = 0x0a0, 128 .ba5_IDE_CFG_STS = 0x0a1, 129 .ba5_IDE_DTM = 0x0b4, 130 .ba5_SControl = 0x100, 131 .ba5_SStatus = 0x104, 132 .ba5_SError = 0x108, 133 .ba5_SActive = 0x10c, 134 .ba5_SMisc = 0x140, 135 .ba5_PHY_CONFIG = 0x144, 136 .ba5_SIEN = 0x148, 137 .ba5_SFISCfg = 0x14c, 138 }, 139 { /* Channel 1 */ 140 .ba5_IDEDMA_CMD = 0x008, 141 .ba5_IDEDMA_CTL = 0x00a, 142 .ba5_IDEDMA_TBL = 0x00c, 143 .ba5_IDEDMA_CMD2 = 0x018, 144 .ba5_IDEDMA_CTL2 = 0x01a, 145 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 146 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 147 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 148 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 149 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 150 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 151 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 152 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 153 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 154 .ba5_IDE_RAD = 0x0cc, 155 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 156 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 157 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 158 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 159 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 160 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 161 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 162 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 163 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 164 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 165 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 166 .ba5_IDE_RABC = 0x0dc, 167 .ba5_IDE_CMD_STS = 0x0e0, 168 .ba5_IDE_CFG_STS = 0x0e1, 169 .ba5_IDE_DTM = 0x0f4, 170 .ba5_SControl = 0x180, 171 .ba5_SStatus = 0x184, 172 .ba5_SError = 0x188, 173 .ba5_SActive = 0x18c, 174 .ba5_SMisc = 0x1c0, 175 .ba5_PHY_CONFIG = 0x1c4, 176 .ba5_SIEN = 0x1c8, 177 .ba5_SFISCfg = 0x1cc, 178 }, 179 { /* Channel 2 (3114) */ 180 .ba5_IDEDMA_CMD = 0x200, 181 .ba5_IDEDMA_CTL = 0x202, 182 .ba5_IDEDMA_TBL = 0x204, 183 .ba5_IDEDMA_CMD2 = 0x210, 184 .ba5_IDEDMA_CTL2 = 0x212, 185 .ba5_IDE_TF0 = 0x280, /* wd_data */ 186 .ba5_IDE_TF1 = 0x281, /* wd_error */ 187 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 188 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 189 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 190 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 191 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 192 .ba5_IDE_TF7 = 0x287, /* wd_command */ 193 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 194 .ba5_IDE_RAD = 0x28c, 195 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 196 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 197 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 198 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 199 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 200 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 201 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 202 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 203 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 204 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 205 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 206 .ba5_IDE_RABC = 0x29c, 207 .ba5_IDE_CMD_STS = 0x2a0, 208 .ba5_IDE_CFG_STS = 0x2a1, 209 .ba5_IDE_DTM = 0x2b4, 210 .ba5_SControl = 0x300, 211 .ba5_SStatus = 0x304, 212 .ba5_SError = 0x308, 213 .ba5_SActive = 0x30c, 214 .ba5_SMisc = 0x340, 215 .ba5_PHY_CONFIG = 0x344, 216 .ba5_SIEN = 0x348, 217 .ba5_SFISCfg = 0x34c, 218 }, 219 { /* Channel 3 (3114) */ 220 .ba5_IDEDMA_CMD = 0x208, 221 .ba5_IDEDMA_CTL = 0x20a, 222 .ba5_IDEDMA_TBL = 0x20c, 223 .ba5_IDEDMA_CMD2 = 0x218, 224 .ba5_IDEDMA_CTL2 = 0x21a, 225 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 226 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 227 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 228 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 229 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 230 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 231 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 232 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 233 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 234 .ba5_IDE_RAD = 0x2cc, 235 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 236 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 237 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 238 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 239 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 240 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 241 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 242 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 243 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 244 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 245 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 246 .ba5_IDE_RABC = 0x2dc, 247 .ba5_IDE_CMD_STS = 0x2e0, 248 .ba5_IDE_CFG_STS = 0x2e1, 249 .ba5_IDE_DTM = 0x2f4, 250 .ba5_SControl = 0x380, 251 .ba5_SStatus = 0x384, 252 .ba5_SError = 0x388, 253 .ba5_SActive = 0x38c, 254 .ba5_SMisc = 0x3c0, 255 .ba5_PHY_CONFIG = 0x3c4, 256 .ba5_SIEN = 0x3c8, 257 .ba5_SFISCfg = 0x3cc, 258 }, 259 }; 260 261 #define ba5_SIS 0x214 /* summary interrupt status */ 262 263 /* Interrupt steering bit in BA5[0x200]. */ 264 #define IDEDMA_CMD_INT_STEER (1U << 1) 265 266 static int satalink_match(struct device *, struct cfdata *, void *); 267 static void satalink_attach(struct device *, struct device *, void *); 268 269 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 270 satalink_match, satalink_attach, NULL, NULL); 271 272 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 273 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 274 static void sii3112_drv_probe(struct ata_channel*); 275 static void sii3112_setup_channel(struct ata_channel*); 276 277 static const struct pciide_product_desc pciide_satalink_products[] = { 278 { PCI_PRODUCT_CMDTECH_3112, 279 0, 280 "Silicon Image SATALink 3112", 281 sii3112_chip_map, 282 }, 283 { PCI_PRODUCT_CMDTECH_3512, 284 0, 285 "Silicon Image SATALink 3512", 286 sii3112_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 289 0, 290 "Adaptec AAR-1210SA serial ATA RAID controller", 291 sii3112_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_3114, 294 0, 295 "Silicon Image SATALink 3114", 296 sii3114_chip_map, 297 }, 298 { 0, 299 0, 300 NULL, 301 NULL 302 } 303 }; 304 305 static int 306 satalink_match(struct device *parent, struct cfdata *match, void *aux) 307 { 308 struct pci_attach_args *pa = aux; 309 310 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 311 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 312 return (2); 313 } 314 return (0); 315 } 316 317 static void 318 satalink_attach(struct device *parent, struct device *self, void *aux) 319 { 320 struct pci_attach_args *pa = aux; 321 struct pciide_softc *sc = (struct pciide_softc *)self; 322 323 pciide_common_attach(sc, pa, 324 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 325 326 } 327 328 static inline uint32_t 329 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 330 { 331 uint32_t rv; 332 int s; 333 334 s = splbio(); 335 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 336 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 337 splx(s); 338 339 return (rv); 340 } 341 342 static inline uint32_t 343 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 344 { 345 346 if (__predict_true(sc->sc_ba5_en != 0)) 347 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 348 349 return (ba5_read_4_ind(sc, reg)); 350 } 351 352 #define BA5_READ_4(sc, chan, reg) \ 353 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 354 355 static inline void 356 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 357 { 358 int s; 359 360 s = splbio(); 361 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 362 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 363 splx(s); 364 } 365 366 static inline void 367 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 368 { 369 370 if (__predict_true(sc->sc_ba5_en != 0)) 371 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 372 else 373 ba5_write_4_ind(sc, reg, val); 374 } 375 376 #define BA5_WRITE_4(sc, chan, reg, val) \ 377 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 378 379 /* 380 * When the Silicon Image 3112 retries a PCI memory read command, 381 * it may retry it as a memory read multiple command under some 382 * circumstances. This can totally confuse some PCI controllers, 383 * so ensure that it will never do this by making sure that the 384 * Read Threshold (FIFO Read Request Control) field of the FIFO 385 * Valid Byte Count and Control registers for both channels (BA5 386 * offset 0x40 and 0x44) are set to be at least as large as the 387 * cacheline size register. 388 * This may also happen on the 3114 (ragge 050527) 389 */ 390 static void 391 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa) 392 { 393 pcireg_t cls, reg40, reg44; 394 395 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 396 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 397 cls *= 4; 398 if (cls > 224) { 399 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 400 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 401 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 402 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 403 cls = 224; 404 } 405 if (cls < 32) 406 cls = 32; 407 cls = (cls + 31) / 32; 408 reg40 = ba5_read_4(sc, 0x40); 409 reg44 = ba5_read_4(sc, 0x44); 410 if ((reg40 & 0x7) < cls) 411 ba5_write_4(sc, 0x40, (reg40 & ~0x07) | cls); 412 if ((reg44 & 0x7) < cls) 413 ba5_write_4(sc, 0x44, (reg44 & ~0x07) | cls); 414 } 415 416 static void 417 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 418 { 419 struct pciide_channel *cp; 420 bus_size_t cmdsize, ctlsize; 421 pcireg_t interface, scs_cmd, cfgctl; 422 int channel; 423 424 if (pciide_chipen(sc, pa) == 0) 425 return; 426 427 #define SII3112_RESET_BITS \ 428 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 429 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 430 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 431 432 /* 433 * Reset everything and then unblock all of the interrupts. 434 */ 435 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 436 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 437 scs_cmd | SII3112_RESET_BITS); 438 delay(50 * 1000); 439 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 440 scs_cmd & SCS_CMD_BA5_EN); 441 delay(50 * 1000); 442 443 if (scs_cmd & SCS_CMD_BA5_EN) { 444 aprint_verbose("%s: SATALink BA5 register space enabled\n", 445 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 446 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 447 PCI_MAPREG_TYPE_MEM| 448 PCI_MAPREG_MEM_TYPE_32BIT, 0, 449 &sc->sc_ba5_st, &sc->sc_ba5_sh, 450 NULL, NULL) != 0) 451 aprint_error("%s: unable to map SATALink BA5 " 452 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 453 else 454 sc->sc_ba5_en = 1; 455 } else { 456 aprint_verbose("%s: SATALink BA5 register space disabled\n", 457 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 458 459 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 460 SII3112_PCI_CFGCTL); 461 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 462 cfgctl | CFGCTL_BA5INDEN); 463 } 464 465 aprint_normal("%s: bus-master DMA support present", 466 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 467 pciide_mapreg_dma(sc, pa); 468 aprint_normal("\n"); 469 470 /* 471 * Rev. <= 0x01 of the 3112 have a bug that can cause data 472 * corruption if DMA transfers cross an 8K boundary. This is 473 * apparently hard to tickle, but we'll go ahead and play it 474 * safe. 475 */ 476 if (PCI_REVISION(pa->pa_class) <= 0x01) { 477 sc->sc_dma_maxsegsz = 8192; 478 sc->sc_dma_boundary = 8192; 479 } 480 481 sii_fixup_cacheline(sc, pa); 482 483 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 484 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 485 if (sc->sc_dma_ok) { 486 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 487 sc->sc_wdcdev.irqack = pciide_irqack; 488 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 489 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 490 } 491 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 492 493 /* We can use SControl and SStatus to probe for drives. */ 494 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 495 496 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 497 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 498 499 wdc_allocate_regs(&sc->sc_wdcdev); 500 501 /* 502 * The 3112 either identifies itself as a RAID storage device 503 * or a Misc storage device. Fake up the interface bits for 504 * what our driver expects. 505 */ 506 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 507 interface = PCI_INTERFACE(pa->pa_class); 508 } else { 509 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 510 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 511 } 512 513 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 514 channel++) { 515 cp = &sc->pciide_channels[channel]; 516 if (pciide_chansetup(sc, channel, interface) == 0) 517 continue; 518 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 519 pciide_pci_intr); 520 } 521 } 522 523 static void 524 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 525 { 526 struct pciide_channel *pc; 527 int chan, reg; 528 bus_size_t size; 529 530 sc->sc_wdcdev.dma_arg = sc; 531 sc->sc_wdcdev.dma_init = pciide_dma_init; 532 sc->sc_wdcdev.dma_start = pciide_dma_start; 533 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 534 535 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 536 PCIIDE_OPTIONS_NODMA) { 537 aprint_normal( 538 ", but unused (forced off by config file)"); 539 sc->sc_dma_ok = 0; 540 return; 541 } 542 543 /* 544 * Slice off a subregion of BA5 for each of the channel's DMA 545 * registers. 546 */ 547 548 sc->sc_dma_iot = sc->sc_ba5_st; 549 for (chan = 0; chan < 4; chan++) { 550 pc = &sc->pciide_channels[chan]; 551 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 552 size = 4; 553 if (size > (IDEDMA_SCH_OFFSET - reg)) 554 size = IDEDMA_SCH_OFFSET - reg; 555 if (bus_space_subregion(sc->sc_ba5_st, 556 sc->sc_ba5_sh, 557 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 558 size, &pc->dma_iohs[reg]) != 0) { 559 sc->sc_dma_ok = 0; 560 aprint_normal(", but can't subregion offset " 561 "%lu size %lu", 562 (u_long) satalink_ba5_regmap[ 563 chan].ba5_IDEDMA_CMD + reg, 564 (u_long) size); 565 return; 566 } 567 } 568 } 569 570 /* DMA registers all set up! */ 571 sc->sc_dmat = pa->pa_dmat; 572 sc->sc_dma_ok = 1; 573 } 574 575 static int 576 sii3114_chansetup(struct pciide_softc *sc, int channel) 577 { 578 static const char *channel_names[] = { 579 "port 0", 580 "port 1", 581 "port 2", 582 "port 3", 583 }; 584 struct pciide_channel *cp = &sc->pciide_channels[channel]; 585 586 sc->wdc_chanarray[channel] = &cp->ata_channel; 587 588 /* 589 * We must always keep the Interrupt Steering bit set in channel 2's 590 * IDEDMA_CMD register. 591 */ 592 if (channel == 2) 593 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 594 595 cp->name = channel_names[channel]; 596 cp->ata_channel.ch_channel = channel; 597 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 598 cp->ata_channel.ch_queue = 599 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 600 cp->ata_channel.ch_ndrive = 2; 601 if (cp->ata_channel.ch_queue == NULL) { 602 aprint_error("%s %s channel: " 603 "can't allocate memory for command queue", 604 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 605 return (0); 606 } 607 return (1); 608 } 609 610 static void 611 sii3114_mapchan(struct pciide_channel *cp) 612 { 613 struct ata_channel *wdc_cp = &cp->ata_channel; 614 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 615 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 616 int i; 617 618 cp->compat = 0; 619 cp->ih = sc->sc_pci_ih; 620 621 wdr->cmd_iot = sc->sc_ba5_st; 622 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 623 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 624 9, &wdr->cmd_baseioh) != 0) { 625 aprint_error("%s: couldn't subregion %s cmd base\n", 626 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 627 goto bad; 628 } 629 630 wdr->ctl_iot = sc->sc_ba5_st; 631 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 632 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 633 1, &cp->ctl_baseioh) != 0) { 634 aprint_error("%s: couldn't subregion %s ctl base\n", 635 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 636 goto bad; 637 } 638 wdr->ctl_ioh = cp->ctl_baseioh; 639 640 for (i = 0; i < WDC_NREG; i++) { 641 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 642 i, i == 0 ? 4 : 1, 643 &wdr->cmd_iohs[i]) != 0) { 644 aprint_error("%s: couldn't subregion %s channel " 645 "cmd regs\n", 646 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 647 goto bad; 648 } 649 } 650 wdc_init_shadow_regs(wdc_cp); 651 wdr->data32iot = wdr->cmd_iot; 652 wdr->data32ioh = wdr->cmd_iohs[0]; 653 wdcattach(wdc_cp); 654 return; 655 656 bad: 657 cp->ata_channel.ch_flags |= ATACH_DISABLED; 658 } 659 660 static void 661 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 662 { 663 struct pciide_channel *cp; 664 pcireg_t scs_cmd; 665 pci_intr_handle_t intrhandle; 666 const char *intrstr; 667 int channel; 668 669 if (pciide_chipen(sc, pa) == 0) 670 return; 671 672 #define SII3114_RESET_BITS \ 673 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 674 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 675 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 676 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 677 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 678 679 /* 680 * Reset everything and then unblock all of the interrupts. 681 */ 682 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 683 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 684 scs_cmd | SII3114_RESET_BITS); 685 delay(50 * 1000); 686 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 687 scs_cmd & SCS_CMD_M66EN); 688 delay(50 * 1000); 689 690 /* 691 * On the 3114, the BA5 register space is always enabled. In 692 * order to use the 3114 in any sane way, we must use this BA5 693 * register space, and so we consider it an error if we cannot 694 * map it. 695 * 696 * As a consequence of using BA5, our register mapping is different 697 * from a normal PCI IDE controller's, and so we are unable to use 698 * most of the common PCI IDE register mapping functions. 699 */ 700 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 701 PCI_MAPREG_TYPE_MEM| 702 PCI_MAPREG_MEM_TYPE_32BIT, 0, 703 &sc->sc_ba5_st, &sc->sc_ba5_sh, 704 NULL, NULL) != 0) { 705 aprint_error("%s: unable to map SATALink BA5 " 706 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 707 return; 708 } 709 sc->sc_ba5_en = 1; 710 711 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 712 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 713 714 /* 715 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 716 * channel 2. This is required at all times for proper operation 717 * when using the BA5 register space (otherwise interrupts from 718 * all 4 channels won't work). 719 */ 720 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 721 722 aprint_normal("%s: bus-master DMA support present", 723 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 724 sii3114_mapreg_dma(sc, pa); 725 aprint_normal("\n"); 726 727 sii_fixup_cacheline(sc, pa); 728 729 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 730 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 731 if (sc->sc_dma_ok) { 732 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 733 sc->sc_wdcdev.irqack = pciide_irqack; 734 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 735 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 736 } 737 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 738 739 /* We can use SControl and SStatus to probe for drives. */ 740 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 741 742 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 743 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 744 745 wdc_allocate_regs(&sc->sc_wdcdev); 746 747 /* Map and establish the interrupt handler. */ 748 if (pci_intr_map(pa, &intrhandle) != 0) { 749 aprint_error("%s: couldn't map native-PCI interrupt\n", 750 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 751 return; 752 } 753 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 754 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 755 /* XXX */ 756 pciide_pci_intr, sc); 757 if (sc->sc_pci_ih != NULL) { 758 aprint_normal("%s: using %s for native-PCI interrupt\n", 759 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 760 intrstr ? intrstr : "unknown interrupt"); 761 } else { 762 aprint_error("%s: couldn't establish native-PCI interrupt", 763 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 764 if (intrstr != NULL) 765 aprint_normal(" at %s", intrstr); 766 aprint_normal("\n"); 767 return; 768 } 769 770 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 771 channel++) { 772 cp = &sc->pciide_channels[channel]; 773 if (sii3114_chansetup(sc, channel) == 0) 774 continue; 775 sii3114_mapchan(cp); 776 } 777 } 778 779 static void 780 sii3112_drv_probe(struct ata_channel *chp) 781 { 782 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 783 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 784 uint32_t scontrol, sstatus; 785 uint8_t scnt, sn, cl, ch; 786 int i, s; 787 788 /* XXX This should be done by other code. */ 789 for (i = 0; i < 2; i++) { 790 chp->ch_drive[i].chnl_softc = chp; 791 chp->ch_drive[i].drive = i; 792 } 793 794 /* 795 * The 3112 is a 2-port part, and only has one drive per channel 796 * (each port emulates a master drive). 797 * 798 * The 3114 is similar, but has 4 channels. 799 */ 800 801 /* 802 * Request communication initialization sequence, any speed. 803 * Performing this is the equivalent of an ATA Reset. 804 */ 805 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 806 807 /* 808 * XXX We don't yet support SATA power management; disable all 809 * power management state transitions. 810 */ 811 scontrol |= SControl_IPM_NONE; 812 813 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 814 delay(50 * 1000); 815 scontrol &= ~SControl_DET_INIT; 816 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 817 delay(50 * 1000); 818 819 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 820 #if 0 821 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 822 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus, 823 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 824 #endif 825 switch (sstatus & SStatus_DET_mask) { 826 case SStatus_DET_NODEV: 827 /* No device; be silent. */ 828 break; 829 830 case SStatus_DET_DEV_NE: 831 aprint_error("%s: port %d: device connected, but " 832 "communication not established\n", 833 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 834 break; 835 836 case SStatus_DET_OFFLINE: 837 aprint_error("%s: port %d: PHY offline\n", 838 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 839 break; 840 841 case SStatus_DET_DEV: 842 /* 843 * XXX ATAPI detection doesn't currently work. Don't 844 * XXX know why. But, it's not like the standard method 845 * XXX can detect an ATAPI device connected via a SATA/PATA 846 * XXX bridge, so at least this is no worse. --thorpej 847 */ 848 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 849 WDSD_IBM | (0 << 4)); 850 delay(10); /* 400ns delay */ 851 /* Save register contents. */ 852 scnt = bus_space_read_1(wdr->cmd_iot, 853 wdr->cmd_iohs[wd_seccnt], 0); 854 sn = bus_space_read_1(wdr->cmd_iot, 855 wdr->cmd_iohs[wd_sector], 0); 856 cl = bus_space_read_1(wdr->cmd_iot, 857 wdr->cmd_iohs[wd_cyl_lo], 0); 858 ch = bus_space_read_1(wdr->cmd_iot, 859 wdr->cmd_iohs[wd_cyl_hi], 0); 860 #if 0 861 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 862 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 863 scnt, sn, cl, ch); 864 #endif 865 /* 866 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 867 * cases we get wrong values here, so ignore it. 868 */ 869 s = splbio(); 870 if (cl == 0x14 && ch == 0xeb) 871 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 872 else 873 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 874 splx(s); 875 876 aprint_normal("%s: port %d: device present, speed: %s\n", 877 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 878 sata_speed(sstatus)); 879 break; 880 881 default: 882 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 883 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus); 884 } 885 } 886 887 static void 888 sii3112_setup_channel(struct ata_channel *chp) 889 { 890 struct ata_drive_datas *drvp; 891 int drive, s; 892 u_int32_t idedma_ctl, dtm; 893 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 894 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 895 896 /* setup DMA if needed */ 897 pciide_channel_dma_setup(cp); 898 899 idedma_ctl = 0; 900 dtm = 0; 901 902 for (drive = 0; drive < 2; drive++) { 903 drvp = &chp->ch_drive[drive]; 904 /* If no drive, skip */ 905 if ((drvp->drive_flags & DRIVE) == 0) 906 continue; 907 if (drvp->drive_flags & DRIVE_UDMA) { 908 /* use Ultra/DMA */ 909 s = splbio(); 910 drvp->drive_flags &= ~DRIVE_DMA; 911 splx(s); 912 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 913 dtm |= DTM_IDEx_DMA; 914 } else if (drvp->drive_flags & DRIVE_DMA) { 915 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 916 dtm |= DTM_IDEx_DMA; 917 } else { 918 dtm |= DTM_IDEx_PIO; 919 } 920 } 921 922 /* 923 * Nothing to do to setup modes; it is meaningless in S-ATA 924 * (but many S-ATA drives still want to get the SET_FEATURE 925 * command). 926 */ 927 if (idedma_ctl != 0) { 928 /* Add software bits in status register */ 929 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 930 idedma_ctl); 931 } 932 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 933 } 934
Indexes created Thu Oct 02 14:10:14 GMT 2025