satalink.c revision 1.3
1 /* $NetBSD: satalink.c,v 1.3 2003/12/15 00:37:38 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 51 static int satalink_match(struct device *, struct cfdata *, void *); 52 static void satalink_attach(struct device *, struct device *, void *); 53 54 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 55 satalink_match, satalink_attach, NULL, NULL); 56 57 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 58 static int sii3112_drv_probe(struct channel_softc*); 59 static void sii3112_setup_channel(struct channel_softc*); 60 61 static const struct pciide_product_desc pciide_satalink_products[] = { 62 { PCI_PRODUCT_CMDTECH_3112, 63 0, 64 "Silicon Image SATALink 3112", 65 sii3112_chip_map, 66 }, 67 { 0, 68 0, 69 NULL, 70 NULL 71 } 72 }; 73 74 static int 75 satalink_match(struct device *parent, struct cfdata *match, void *aux) 76 { 77 struct pci_attach_args *pa = aux; 78 79 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 80 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 81 return (2); 82 } 83 return (0); 84 } 85 86 static void 87 satalink_attach(struct device *parent, struct device *self, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 struct pciide_softc *sc = (struct pciide_softc *)self; 91 92 pciide_common_attach(sc, pa, 93 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 94 95 } 96 97 static __inline uint32_t 98 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 99 { 100 101 if (__predict_true(sc->sc_ba5_en != 0)) 102 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 103 104 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 105 return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA)); 106 } 107 108 static __inline void 109 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 110 { 111 112 if (__predict_true(sc->sc_ba5_en != 0)) 113 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 114 else { 115 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, 116 reg); 117 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, 118 val); 119 } 120 } 121 122 static void 123 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 124 { 125 struct pciide_channel *cp; 126 bus_size_t cmdsize, ctlsize; 127 pcireg_t interface, scs_cmd, cfgctl; 128 int channel; 129 130 if (pciide_chipen(sc, pa) == 0) 131 return; 132 133 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 134 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 135 scs_cmd & SCS_CMD_BA5_EN); 136 137 if (scs_cmd & SCS_CMD_BA5_EN) { 138 aprint_verbose("%s: SATALink BA5 register space enabled\n", 139 sc->sc_wdcdev.sc_dev.dv_xname); 140 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 141 PCI_MAPREG_TYPE_MEM| 142 PCI_MAPREG_MEM_TYPE_32BIT, 0, 143 &sc->sc_ba5_st, &sc->sc_ba5_sh, 144 NULL, NULL) != 0) 145 aprint_error("%s: unable to map SATALink BA5 " 146 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 147 else 148 sc->sc_ba5_en = 1; 149 } else { 150 aprint_verbose("%s: SATALink BA5 register space disabled\n", 151 sc->sc_wdcdev.sc_dev.dv_xname); 152 153 /* Enable indirect BA5 addressing. */ 154 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 155 SII3112_PCI_CFGCTL); 156 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 157 cfgctl | CFGCTL_BA5INDEN); 158 } 159 160 aprint_normal("%s: bus-master DMA support present", 161 sc->sc_wdcdev.sc_dev.dv_xname); 162 pciide_mapreg_dma(sc, pa); 163 aprint_normal("\n"); 164 165 /* 166 * Rev. <= 0x01 of the 3112 have a bug that can cause data 167 * corruption if DMA transfers cross an 8K boundary. This is 168 * apparently hard to tickle, but we'll go ahead and play it 169 * safe. 170 */ 171 if (PCI_REVISION(pa->pa_class) <= 0x01) { 172 sc->sc_dma_maxsegsz = 8192; 173 sc->sc_dma_boundary = 8192; 174 } 175 176 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 177 WDC_CAPABILITY_MODE; 178 sc->sc_wdcdev.PIO_cap = 4; 179 if (sc->sc_dma_ok) { 180 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 181 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 182 sc->sc_wdcdev.irqack = pciide_irqack; 183 sc->sc_wdcdev.DMA_cap = 2; 184 sc->sc_wdcdev.UDMA_cap = 6; 185 } 186 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 187 188 /* We can use SControl and SStatus to probe for drives. */ 189 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE; 190 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 191 192 sc->sc_wdcdev.channels = sc->wdc_chanarray; 193 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 194 195 /* 196 * The 3112 either identifies itself as a RAID storage device 197 * or a Misc storage device. Fake up the interface bits for 198 * what our driver expects. 199 */ 200 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 201 interface = PCI_INTERFACE(pa->pa_class); 202 } else { 203 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 204 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 205 } 206 207 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 208 cp = &sc->pciide_channels[channel]; 209 if (pciide_chansetup(sc, channel, interface) == 0) 210 continue; 211 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 212 pciide_pci_intr); 213 } 214 } 215 216 static const char *sata_speed[] = { 217 "no negotiated speed", 218 "1.5Gb/s", 219 "<unknown 2>", 220 "<unknown 3>", 221 "<unknown 4>", 222 "<unknown 5>", 223 "<unknown 6>", 224 "<unknown 7>", 225 "<unknown 8>", 226 "<unknown 9>", 227 "<unknown 10>", 228 "<unknown 11>", 229 "<unknown 12>", 230 "<unknown 13>", 231 "<unknown 14>", 232 "<unknown 15>", 233 }; 234 235 static int 236 sii3112_drv_probe(struct channel_softc *chp) 237 { 238 struct pciide_channel *cp = (struct pciide_channel *)chp; 239 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 240 uint32_t scontrol, sstatus; 241 int rv = 0; 242 uint8_t scnt, sn, cl, ch; 243 244 /* 245 * The 3112 is a 2-port part, and only has one drive per channel 246 * (each port emulates a master drive). 247 */ 248 249 /* 250 * Request communication initialization sequence, any speed. 251 * Performing this is the equivalent of an ATA Reset. 252 */ 253 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 254 255 /* 256 * XXX We don't yet support SATA power management; disable all 257 * power management state transitions. 258 */ 259 scontrol |= SControl_IPM_NONE; 260 261 ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); 262 delay(500); 263 scontrol &= ~SControl_DET_INIT; 264 ba5_write_4(sc, chp->channel == 0 ? 0x100 : 0x180, scontrol); 265 delay(500); 266 267 sstatus = ba5_read_4(sc, chp->channel == 0 ? 0x104 : 0x184); 268 switch (sstatus & SStatus_DET_mask) { 269 case SStatus_DET_NODEV: 270 /* No device; be silent. */ 271 break; 272 273 case SStatus_DET_DEV_NE: 274 aprint_error("%s: port %d: device connected, but " 275 "communication not established\n", 276 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 277 break; 278 279 case SStatus_DET_OFFLINE: 280 aprint_error("%s: port %d: PHY offline\n", 281 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 282 break; 283 284 case SStatus_DET_DEV: 285 /* 286 * XXX ATAPI detection doesn't currently work. Don't 287 * XXX know why. But, it's not like the standard method 288 * XXX can detect an ATAPI device connected via a SATA/PATA 289 * XXX bridge, so at least this is no worse. --thorpej 290 */ 291 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 292 WDSD_IBM | (0 << 4)); 293 delay(10); /* 400ns delay */ 294 /* Save register contents. */ 295 scnt = bus_space_read_1(chp->cmd_iot, 296 chp->cmd_iohs[wd_seccnt], 0); 297 sn = bus_space_read_1(chp->cmd_iot, 298 chp->cmd_iohs[wd_sector], 0); 299 cl = bus_space_read_1(chp->cmd_iot, 300 chp->cmd_iohs[wd_cyl_lo], 0); 301 ch = bus_space_read_1(chp->cmd_iot, 302 chp->cmd_iohs[wd_cyl_hi], 0); 303 #if 0 304 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 305 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 306 scnt, sn, cl, ch); 307 #endif 308 /* 309 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 310 * cases we get wrong values here, so ignore it. 311 */ 312 if (cl == 0x14 && ch == 0xeb) 313 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 314 else 315 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 316 317 aprint_normal("%s: port %d: device present, speed: %s\n", 318 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 319 sata_speed[(sstatus & SStatus_SPD_mask) >> 320 SStatus_SPD_shift]); 321 rv |= (1 << 0); 322 break; 323 324 default: 325 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 326 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 327 } 328 329 return (rv); 330 } 331 332 static void 333 sii3112_setup_channel(struct channel_softc *chp) 334 { 335 struct ata_drive_datas *drvp; 336 int drive; 337 u_int32_t idedma_ctl, dtm; 338 struct pciide_channel *cp = (struct pciide_channel*)chp; 339 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 340 341 /* setup DMA if needed */ 342 pciide_channel_dma_setup(cp); 343 344 idedma_ctl = 0; 345 dtm = 0; 346 347 for (drive = 0; drive < 2; drive++) { 348 drvp = &chp->ch_drive[drive]; 349 /* If no drive, skip */ 350 if ((drvp->drive_flags & DRIVE) == 0) 351 continue; 352 if (drvp->drive_flags & DRIVE_UDMA) { 353 /* use Ultra/DMA */ 354 drvp->drive_flags &= ~DRIVE_DMA; 355 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 356 dtm |= DTM_IDEx_DMA; 357 } else if (drvp->drive_flags & DRIVE_DMA) { 358 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 359 dtm |= DTM_IDEx_DMA; 360 } else { 361 dtm |= DTM_IDEx_PIO; 362 } 363 } 364 365 /* 366 * Nothing to do to setup modes; it is meaningless in S-ATA 367 * (but many S-ATA drives still want to get the SET_FEATURE 368 * command). 369 */ 370 if (idedma_ctl != 0) { 371 /* Add software bits in status register */ 372 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 373 idedma_ctl); 374 } 375 pci_conf_write(sc->sc_pc, sc->sc_tag, 376 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 377 } 378
Indexes created Thu Oct 02 14:10:14 GMT 2025