satalink.c revision 1.35
1 /* $NetBSD: satalink.c,v 1.35 2007/12/27 15:14:23 ws Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.35 2007/12/27 15:14:23 ws Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/malloc.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciidereg.h> 49 #include <dev/pci/pciidevar.h> 50 #include <dev/pci/pciide_sii3112_reg.h> 51 52 #include <dev/ata/satareg.h> 53 #include <dev/ata/satavar.h> 54 #include <dev/ata/atareg.h> 55 56 /* 57 * Register map for BA5 register space, indexed by channel. 58 */ 59 static const struct { 60 bus_addr_t ba5_IDEDMA_CMD; 61 bus_addr_t ba5_IDEDMA_CTL; 62 bus_addr_t ba5_IDEDMA_TBL; 63 bus_addr_t ba5_IDEDMA_CMD2; 64 bus_addr_t ba5_IDEDMA_CTL2; 65 bus_addr_t ba5_IDE_TF0; 66 bus_addr_t ba5_IDE_TF1; 67 bus_addr_t ba5_IDE_TF2; 68 bus_addr_t ba5_IDE_TF3; 69 bus_addr_t ba5_IDE_TF4; 70 bus_addr_t ba5_IDE_TF5; 71 bus_addr_t ba5_IDE_TF6; 72 bus_addr_t ba5_IDE_TF7; 73 bus_addr_t ba5_IDE_TF8; 74 bus_addr_t ba5_IDE_RAD; 75 bus_addr_t ba5_IDE_TF9; 76 bus_addr_t ba5_IDE_TF10; 77 bus_addr_t ba5_IDE_TF11; 78 bus_addr_t ba5_IDE_TF12; 79 bus_addr_t ba5_IDE_TF13; 80 bus_addr_t ba5_IDE_TF14; 81 bus_addr_t ba5_IDE_TF15; 82 bus_addr_t ba5_IDE_TF16; 83 bus_addr_t ba5_IDE_TF17; 84 bus_addr_t ba5_IDE_TF18; 85 bus_addr_t ba5_IDE_TF19; 86 bus_addr_t ba5_IDE_RABC; 87 bus_addr_t ba5_IDE_CMD_STS; 88 bus_addr_t ba5_IDE_CFG_STS; 89 bus_addr_t ba5_IDE_DTM; 90 bus_addr_t ba5_SControl; 91 bus_addr_t ba5_SStatus; 92 bus_addr_t ba5_SError; 93 bus_addr_t ba5_SActive; /* 3114 */ 94 bus_addr_t ba5_SMisc; 95 bus_addr_t ba5_PHY_CONFIG; 96 bus_addr_t ba5_SIEN; 97 bus_addr_t ba5_SFISCfg; 98 } satalink_ba5_regmap[] = { 99 { /* Channel 0 */ 100 .ba5_IDEDMA_CMD = 0x000, 101 .ba5_IDEDMA_CTL = 0x002, 102 .ba5_IDEDMA_TBL = 0x004, 103 .ba5_IDEDMA_CMD2 = 0x010, 104 .ba5_IDEDMA_CTL2 = 0x012, 105 .ba5_IDE_TF0 = 0x080, /* wd_data */ 106 .ba5_IDE_TF1 = 0x081, /* wd_error */ 107 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 108 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 109 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 110 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 111 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 112 .ba5_IDE_TF7 = 0x087, /* wd_command */ 113 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 114 .ba5_IDE_RAD = 0x08c, 115 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 116 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 117 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 118 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 119 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 120 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 121 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 122 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 123 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 124 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 125 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 126 .ba5_IDE_RABC = 0x09c, 127 .ba5_IDE_CMD_STS = 0x0a0, 128 .ba5_IDE_CFG_STS = 0x0a1, 129 .ba5_IDE_DTM = 0x0b4, 130 .ba5_SControl = 0x100, 131 .ba5_SStatus = 0x104, 132 .ba5_SError = 0x108, 133 .ba5_SActive = 0x10c, 134 .ba5_SMisc = 0x140, 135 .ba5_PHY_CONFIG = 0x144, 136 .ba5_SIEN = 0x148, 137 .ba5_SFISCfg = 0x14c, 138 }, 139 { /* Channel 1 */ 140 .ba5_IDEDMA_CMD = 0x008, 141 .ba5_IDEDMA_CTL = 0x00a, 142 .ba5_IDEDMA_TBL = 0x00c, 143 .ba5_IDEDMA_CMD2 = 0x018, 144 .ba5_IDEDMA_CTL2 = 0x01a, 145 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 146 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 147 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 148 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 149 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 150 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 151 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 152 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 153 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 154 .ba5_IDE_RAD = 0x0cc, 155 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 156 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 157 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 158 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 159 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 160 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 161 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 162 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 163 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 164 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 165 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 166 .ba5_IDE_RABC = 0x0dc, 167 .ba5_IDE_CMD_STS = 0x0e0, 168 .ba5_IDE_CFG_STS = 0x0e1, 169 .ba5_IDE_DTM = 0x0f4, 170 .ba5_SControl = 0x180, 171 .ba5_SStatus = 0x184, 172 .ba5_SError = 0x188, 173 .ba5_SActive = 0x18c, 174 .ba5_SMisc = 0x1c0, 175 .ba5_PHY_CONFIG = 0x1c4, 176 .ba5_SIEN = 0x1c8, 177 .ba5_SFISCfg = 0x1cc, 178 }, 179 { /* Channel 2 (3114) */ 180 .ba5_IDEDMA_CMD = 0x200, 181 .ba5_IDEDMA_CTL = 0x202, 182 .ba5_IDEDMA_TBL = 0x204, 183 .ba5_IDEDMA_CMD2 = 0x210, 184 .ba5_IDEDMA_CTL2 = 0x212, 185 .ba5_IDE_TF0 = 0x280, /* wd_data */ 186 .ba5_IDE_TF1 = 0x281, /* wd_error */ 187 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 188 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 189 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 190 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 191 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 192 .ba5_IDE_TF7 = 0x287, /* wd_command */ 193 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 194 .ba5_IDE_RAD = 0x28c, 195 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 196 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 197 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 198 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 199 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 200 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 201 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 202 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 203 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 204 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 205 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 206 .ba5_IDE_RABC = 0x29c, 207 .ba5_IDE_CMD_STS = 0x2a0, 208 .ba5_IDE_CFG_STS = 0x2a1, 209 .ba5_IDE_DTM = 0x2b4, 210 .ba5_SControl = 0x300, 211 .ba5_SStatus = 0x304, 212 .ba5_SError = 0x308, 213 .ba5_SActive = 0x30c, 214 .ba5_SMisc = 0x340, 215 .ba5_PHY_CONFIG = 0x344, 216 .ba5_SIEN = 0x348, 217 .ba5_SFISCfg = 0x34c, 218 }, 219 { /* Channel 3 (3114) */ 220 .ba5_IDEDMA_CMD = 0x208, 221 .ba5_IDEDMA_CTL = 0x20a, 222 .ba5_IDEDMA_TBL = 0x20c, 223 .ba5_IDEDMA_CMD2 = 0x218, 224 .ba5_IDEDMA_CTL2 = 0x21a, 225 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 226 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 227 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 228 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 229 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 230 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 231 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 232 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 233 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 234 .ba5_IDE_RAD = 0x2cc, 235 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 236 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 237 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 238 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 239 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 240 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 241 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 242 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 243 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 244 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 245 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 246 .ba5_IDE_RABC = 0x2dc, 247 .ba5_IDE_CMD_STS = 0x2e0, 248 .ba5_IDE_CFG_STS = 0x2e1, 249 .ba5_IDE_DTM = 0x2f4, 250 .ba5_SControl = 0x380, 251 .ba5_SStatus = 0x384, 252 .ba5_SError = 0x388, 253 .ba5_SActive = 0x38c, 254 .ba5_SMisc = 0x3c0, 255 .ba5_PHY_CONFIG = 0x3c4, 256 .ba5_SIEN = 0x3c8, 257 .ba5_SFISCfg = 0x3cc, 258 }, 259 }; 260 261 #define ba5_SIS 0x214 /* summary interrupt status */ 262 263 /* Interrupt steering bit in BA5[0x200]. */ 264 #define IDEDMA_CMD_INT_STEER (1U << 1) 265 266 static int satalink_match(struct device *, struct cfdata *, void *); 267 static void satalink_attach(struct device *, struct device *, void *); 268 269 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 270 satalink_match, satalink_attach, NULL, NULL); 271 272 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 273 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 274 static void sii3112_drv_probe(struct ata_channel*); 275 static void sii3112_setup_channel(struct ata_channel*); 276 277 static const struct pciide_product_desc pciide_satalink_products[] = { 278 { PCI_PRODUCT_CMDTECH_3112, 279 0, 280 "Silicon Image SATALink 3112", 281 sii3112_chip_map, 282 }, 283 { PCI_PRODUCT_CMDTECH_3512, 284 0, 285 "Silicon Image SATALink 3512", 286 sii3112_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 289 0, 290 "Adaptec AAR-1210SA serial ATA RAID controller", 291 sii3112_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_3114, 294 0, 295 "Silicon Image SATALink 3114", 296 sii3114_chip_map, 297 }, 298 { 0, 299 0, 300 NULL, 301 NULL 302 } 303 }; 304 305 static int 306 satalink_match(struct device *parent, struct cfdata *match, 307 void *aux) 308 { 309 struct pci_attach_args *pa = aux; 310 311 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 312 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 313 return (2); 314 } 315 return (0); 316 } 317 318 static void 319 satalink_attach(struct device *parent, struct device *self, void *aux) 320 { 321 struct pci_attach_args *pa = aux; 322 struct pciide_softc *sc = (struct pciide_softc *)self; 323 324 pciide_common_attach(sc, pa, 325 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 326 327 } 328 329 static inline uint32_t 330 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 331 { 332 uint32_t rv; 333 int s; 334 335 s = splbio(); 336 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 337 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 338 splx(s); 339 340 return (rv); 341 } 342 343 static inline uint32_t 344 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 345 { 346 347 if (__predict_true(sc->sc_ba5_en != 0)) 348 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 349 350 return (ba5_read_4_ind(sc, reg)); 351 } 352 353 #define BA5_READ_4(sc, chan, reg) \ 354 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 355 356 static inline void 357 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 358 { 359 int s; 360 361 s = splbio(); 362 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 363 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 364 splx(s); 365 } 366 367 static inline void 368 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 369 { 370 371 if (__predict_true(sc->sc_ba5_en != 0)) 372 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 373 else 374 ba5_write_4_ind(sc, reg, val); 375 } 376 377 #define BA5_WRITE_4(sc, chan, reg, val) \ 378 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 379 380 /* 381 * When the Silicon Image 3112 retries a PCI memory read command, 382 * it may retry it as a memory read multiple command under some 383 * circumstances. This can totally confuse some PCI controllers, 384 * so ensure that it will never do this by making sure that the 385 * Read Threshold (FIFO Read Request Control) field of the FIFO 386 * Valid Byte Count and Control registers for both channels (BA5 387 * offset 0x40 and 0x44) are set to be at least as large as the 388 * cacheline size register. 389 * This may also happen on the 3114 (ragge 050527) 390 */ 391 static void 392 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa, int n) 393 { 394 pcireg_t cls, reg; 395 int i; 396 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 397 398 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 399 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 400 cls *= 4; 401 if (cls > 224) { 402 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 403 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 404 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 405 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 406 cls = 224; 407 } 408 if (cls < 32) 409 cls = 32; 410 cls = (cls + 31) / 32; 411 for (i = 0; i < n; i++) { 412 reg = ba5_read_4(sc, addr[i]); 413 if ((reg & 0x7) < cls) 414 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 415 } 416 } 417 418 static void 419 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 420 { 421 struct pciide_channel *cp; 422 bus_size_t cmdsize, ctlsize; 423 pcireg_t interface, scs_cmd, cfgctl; 424 int channel; 425 426 if (pciide_chipen(sc, pa) == 0) 427 return; 428 429 #define SII3112_RESET_BITS \ 430 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 431 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 432 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 433 434 /* 435 * Reset everything and then unblock all of the interrupts. 436 */ 437 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 438 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 439 scs_cmd | SII3112_RESET_BITS); 440 delay(50 * 1000); 441 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 442 scs_cmd & SCS_CMD_BA5_EN); 443 delay(50 * 1000); 444 445 if (scs_cmd & SCS_CMD_BA5_EN) { 446 aprint_verbose("%s: SATALink BA5 register space enabled\n", 447 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 448 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 449 PCI_MAPREG_TYPE_MEM| 450 PCI_MAPREG_MEM_TYPE_32BIT, 0, 451 &sc->sc_ba5_st, &sc->sc_ba5_sh, 452 NULL, NULL) != 0) 453 aprint_error("%s: unable to map SATALink BA5 " 454 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 455 else 456 sc->sc_ba5_en = 1; 457 } else { 458 aprint_verbose("%s: SATALink BA5 register space disabled\n", 459 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 460 461 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 462 SII3112_PCI_CFGCTL); 463 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 464 cfgctl | CFGCTL_BA5INDEN); 465 } 466 467 aprint_verbose("%s: bus-master DMA support present", 468 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 469 pciide_mapreg_dma(sc, pa); 470 aprint_verbose("\n"); 471 472 /* 473 * Rev. <= 0x01 of the 3112 have a bug that can cause data 474 * corruption if DMA transfers cross an 8K boundary. This is 475 * apparently hard to tickle, but we'll go ahead and play it 476 * safe. 477 */ 478 if (PCI_REVISION(pa->pa_class) <= 0x01) { 479 sc->sc_dma_maxsegsz = 8192; 480 sc->sc_dma_boundary = 8192; 481 } 482 483 sii_fixup_cacheline(sc, pa, 2); 484 485 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 486 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 487 if (sc->sc_dma_ok) { 488 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 489 sc->sc_wdcdev.irqack = pciide_irqack; 490 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 491 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 492 } 493 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 494 495 /* We can use SControl and SStatus to probe for drives. */ 496 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 497 498 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 499 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 500 501 wdc_allocate_regs(&sc->sc_wdcdev); 502 503 /* 504 * The 3112 either identifies itself as a RAID storage device 505 * or a Misc storage device. Fake up the interface bits for 506 * what our driver expects. 507 */ 508 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 509 interface = PCI_INTERFACE(pa->pa_class); 510 } else { 511 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 512 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 513 } 514 515 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 516 channel++) { 517 cp = &sc->pciide_channels[channel]; 518 if (pciide_chansetup(sc, channel, interface) == 0) 519 continue; 520 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 521 pciide_pci_intr); 522 } 523 } 524 525 static void 526 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 527 { 528 struct pciide_channel *pc; 529 int chan, reg; 530 bus_size_t size; 531 532 sc->sc_wdcdev.dma_arg = sc; 533 sc->sc_wdcdev.dma_init = pciide_dma_init; 534 sc->sc_wdcdev.dma_start = pciide_dma_start; 535 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 536 537 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 538 PCIIDE_OPTIONS_NODMA) { 539 aprint_verbose( 540 ", but unused (forced off by config file)"); 541 sc->sc_dma_ok = 0; 542 return; 543 } 544 545 /* 546 * Slice off a subregion of BA5 for each of the channel's DMA 547 * registers. 548 */ 549 550 sc->sc_dma_iot = sc->sc_ba5_st; 551 for (chan = 0; chan < 4; chan++) { 552 pc = &sc->pciide_channels[chan]; 553 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 554 size = 4; 555 if (size > (IDEDMA_SCH_OFFSET - reg)) 556 size = IDEDMA_SCH_OFFSET - reg; 557 if (bus_space_subregion(sc->sc_ba5_st, 558 sc->sc_ba5_sh, 559 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 560 size, &pc->dma_iohs[reg]) != 0) { 561 sc->sc_dma_ok = 0; 562 aprint_verbose(", but can't subregion offset " 563 "%lu size %lu", 564 (u_long) satalink_ba5_regmap[ 565 chan].ba5_IDEDMA_CMD + reg, 566 (u_long) size); 567 return; 568 } 569 } 570 } 571 572 /* DMA registers all set up! */ 573 sc->sc_dmat = pa->pa_dmat; 574 sc->sc_dma_ok = 1; 575 } 576 577 static int 578 sii3114_chansetup(struct pciide_softc *sc, int channel) 579 { 580 static const char *channel_names[] = { 581 "port 0", 582 "port 1", 583 "port 2", 584 "port 3", 585 }; 586 struct pciide_channel *cp = &sc->pciide_channels[channel]; 587 588 sc->wdc_chanarray[channel] = &cp->ata_channel; 589 590 /* 591 * We must always keep the Interrupt Steering bit set in channel 2's 592 * IDEDMA_CMD register. 593 */ 594 if (channel == 2) 595 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 596 597 cp->name = channel_names[channel]; 598 cp->ata_channel.ch_channel = channel; 599 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 600 cp->ata_channel.ch_queue = 601 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 602 cp->ata_channel.ch_ndrive = 2; 603 if (cp->ata_channel.ch_queue == NULL) { 604 aprint_error("%s %s channel: " 605 "can't allocate memory for command queue", 606 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 607 return (0); 608 } 609 return (1); 610 } 611 612 static void 613 sii3114_mapchan(struct pciide_channel *cp) 614 { 615 struct ata_channel *wdc_cp = &cp->ata_channel; 616 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 617 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 618 int i; 619 620 cp->compat = 0; 621 cp->ih = sc->sc_pci_ih; 622 623 wdr->cmd_iot = sc->sc_ba5_st; 624 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 625 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 626 9, &wdr->cmd_baseioh) != 0) { 627 aprint_error("%s: couldn't subregion %s cmd base\n", 628 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 629 goto bad; 630 } 631 632 wdr->ctl_iot = sc->sc_ba5_st; 633 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 634 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 635 1, &cp->ctl_baseioh) != 0) { 636 aprint_error("%s: couldn't subregion %s ctl base\n", 637 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 638 goto bad; 639 } 640 wdr->ctl_ioh = cp->ctl_baseioh; 641 642 for (i = 0; i < WDC_NREG; i++) { 643 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 644 i, i == 0 ? 4 : 1, 645 &wdr->cmd_iohs[i]) != 0) { 646 aprint_error("%s: couldn't subregion %s channel " 647 "cmd regs\n", 648 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 649 goto bad; 650 } 651 } 652 wdc_init_shadow_regs(wdc_cp); 653 wdr->data32iot = wdr->cmd_iot; 654 wdr->data32ioh = wdr->cmd_iohs[0]; 655 wdcattach(wdc_cp); 656 return; 657 658 bad: 659 cp->ata_channel.ch_flags |= ATACH_DISABLED; 660 } 661 662 static void 663 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 664 { 665 struct pciide_channel *cp; 666 pcireg_t scs_cmd; 667 pci_intr_handle_t intrhandle; 668 const char *intrstr; 669 int channel; 670 671 if (pciide_chipen(sc, pa) == 0) 672 return; 673 674 #define SII3114_RESET_BITS \ 675 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 676 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 677 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 678 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 679 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 680 681 /* 682 * Reset everything and then unblock all of the interrupts. 683 */ 684 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 685 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 686 scs_cmd | SII3114_RESET_BITS); 687 delay(50 * 1000); 688 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 689 scs_cmd & SCS_CMD_M66EN); 690 delay(50 * 1000); 691 692 /* 693 * On the 3114, the BA5 register space is always enabled. In 694 * order to use the 3114 in any sane way, we must use this BA5 695 * register space, and so we consider it an error if we cannot 696 * map it. 697 * 698 * As a consequence of using BA5, our register mapping is different 699 * from a normal PCI IDE controller's, and so we are unable to use 700 * most of the common PCI IDE register mapping functions. 701 */ 702 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 703 PCI_MAPREG_TYPE_MEM| 704 PCI_MAPREG_MEM_TYPE_32BIT, 0, 705 &sc->sc_ba5_st, &sc->sc_ba5_sh, 706 NULL, NULL) != 0) { 707 aprint_error("%s: unable to map SATALink BA5 " 708 "register space\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 709 return; 710 } 711 sc->sc_ba5_en = 1; 712 713 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 714 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 715 716 /* 717 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 718 * channel 2. This is required at all times for proper operation 719 * when using the BA5 register space (otherwise interrupts from 720 * all 4 channels won't work). 721 */ 722 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 723 724 aprint_verbose("%s: bus-master DMA support present", 725 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 726 sii3114_mapreg_dma(sc, pa); 727 aprint_verbose("\n"); 728 729 sii_fixup_cacheline(sc, pa, 4); 730 731 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 732 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 733 if (sc->sc_dma_ok) { 734 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 735 sc->sc_wdcdev.irqack = pciide_irqack; 736 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 737 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 738 } 739 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 740 741 /* We can use SControl and SStatus to probe for drives. */ 742 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 743 744 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 745 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 746 747 wdc_allocate_regs(&sc->sc_wdcdev); 748 749 /* Map and establish the interrupt handler. */ 750 if (pci_intr_map(pa, &intrhandle) != 0) { 751 aprint_error("%s: couldn't map native-PCI interrupt\n", 752 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 753 return; 754 } 755 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 756 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 757 /* XXX */ 758 pciide_pci_intr, sc); 759 if (sc->sc_pci_ih != NULL) { 760 aprint_normal("%s: using %s for native-PCI interrupt\n", 761 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 762 intrstr ? intrstr : "unknown interrupt"); 763 } else { 764 aprint_error("%s: couldn't establish native-PCI interrupt", 765 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 766 if (intrstr != NULL) 767 aprint_normal(" at %s", intrstr); 768 aprint_normal("\n"); 769 return; 770 } 771 772 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 773 channel++) { 774 cp = &sc->pciide_channels[channel]; 775 if (sii3114_chansetup(sc, channel) == 0) 776 continue; 777 sii3114_mapchan(cp); 778 } 779 } 780 781 /* Probe the drives using SATA registers. 782 * Note we can't use wdc_sataprobe as we may not be able to map ba5 783 */ 784 static void 785 sii3112_drv_probe(struct ata_channel *chp) 786 { 787 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 788 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 789 uint32_t scontrol, sstatus; 790 uint8_t scnt, sn, cl, ch; 791 int i, s; 792 793 /* XXX This should be done by other code. */ 794 for (i = 0; i < 2; i++) { 795 chp->ch_drive[i].chnl_softc = chp; 796 chp->ch_drive[i].drive = i; 797 } 798 799 /* 800 * The 3112 is a 2-port part, and only has one drive per channel 801 * (each port emulates a master drive). 802 * 803 * The 3114 is similar, but has 4 channels. 804 */ 805 806 /* 807 * Request communication initialization sequence, any speed. 808 * Performing this is the equivalent of an ATA Reset. 809 */ 810 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 811 812 /* 813 * XXX We don't yet support SATA power management; disable all 814 * power management state transitions. 815 */ 816 scontrol |= SControl_IPM_NONE; 817 818 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 819 delay(50 * 1000); 820 scontrol &= ~SControl_DET_INIT; 821 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 822 delay(50 * 1000); 823 824 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 825 #if 0 826 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 827 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus, 828 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 829 #endif 830 switch (sstatus & SStatus_DET_mask) { 831 case SStatus_DET_NODEV: 832 /* No device; be silent. */ 833 break; 834 835 case SStatus_DET_DEV_NE: 836 aprint_error("%s: port %d: device connected, but " 837 "communication not established\n", 838 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 839 break; 840 841 case SStatus_DET_OFFLINE: 842 aprint_error("%s: port %d: PHY offline\n", 843 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel); 844 break; 845 846 case SStatus_DET_DEV: 847 /* 848 * XXX ATAPI detection doesn't currently work. Don't 849 * XXX know why. But, it's not like the standard method 850 * XXX can detect an ATAPI device connected via a SATA/PATA 851 * XXX bridge, so at least this is no worse. --thorpej 852 */ 853 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 854 WDSD_IBM | (0 << 4)); 855 delay(10); /* 400ns delay */ 856 /* Save register contents. */ 857 scnt = bus_space_read_1(wdr->cmd_iot, 858 wdr->cmd_iohs[wd_seccnt], 0); 859 sn = bus_space_read_1(wdr->cmd_iot, 860 wdr->cmd_iohs[wd_sector], 0); 861 cl = bus_space_read_1(wdr->cmd_iot, 862 wdr->cmd_iohs[wd_cyl_lo], 0); 863 ch = bus_space_read_1(wdr->cmd_iot, 864 wdr->cmd_iohs[wd_cyl_hi], 0); 865 #if 0 866 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 867 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 868 scnt, sn, cl, ch); 869 #endif 870 /* 871 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 872 * cases we get wrong values here, so ignore it. 873 */ 874 s = splbio(); 875 if (cl == 0x14 && ch == 0xeb) 876 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 877 else 878 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 879 splx(s); 880 881 aprint_normal("%s: port %d: device present, speed: %s\n", 882 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, 883 sata_speed(sstatus)); 884 break; 885 886 default: 887 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 888 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, chp->ch_channel, sstatus); 889 } 890 } 891 892 static void 893 sii3112_setup_channel(struct ata_channel *chp) 894 { 895 struct ata_drive_datas *drvp; 896 int drive, s; 897 u_int32_t idedma_ctl, dtm; 898 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 899 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 900 901 /* setup DMA if needed */ 902 pciide_channel_dma_setup(cp); 903 904 idedma_ctl = 0; 905 dtm = 0; 906 907 for (drive = 0; drive < 2; drive++) { 908 drvp = &chp->ch_drive[drive]; 909 /* If no drive, skip */ 910 if ((drvp->drive_flags & DRIVE) == 0) 911 continue; 912 if (drvp->drive_flags & DRIVE_UDMA) { 913 /* use Ultra/DMA */ 914 s = splbio(); 915 drvp->drive_flags &= ~DRIVE_DMA; 916 splx(s); 917 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 918 dtm |= DTM_IDEx_DMA; 919 } else if (drvp->drive_flags & DRIVE_DMA) { 920 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 921 dtm |= DTM_IDEx_DMA; 922 } else { 923 dtm |= DTM_IDEx_PIO; 924 } 925 } 926 927 /* 928 * Nothing to do to setup modes; it is meaningless in S-ATA 929 * (but many S-ATA drives still want to get the SET_FEATURE 930 * command). 931 */ 932 if (idedma_ctl != 0) { 933 /* Add software bits in status register */ 934 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 935 idedma_ctl); 936 } 937 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 938 } 939
Indexes created Mon Sep 29 21:09:56 GMT 2025