satalink.c revision 1.39.2.2
1 /* $NetBSD: satalink.c,v 1.39.2.2 2010/08/17 06:46:34 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.39.2.2 2010/08/17 06:46:34 uebayasi Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_sii3112_reg.h> 44 45 #include <dev/ata/satareg.h> 46 #include <dev/ata/satavar.h> 47 #include <dev/ata/atareg.h> 48 49 /* 50 * Register map for BA5 register space, indexed by channel. 51 */ 52 static const struct { 53 bus_addr_t ba5_IDEDMA_CMD; 54 bus_addr_t ba5_IDEDMA_CTL; 55 bus_addr_t ba5_IDEDMA_TBL; 56 bus_addr_t ba5_IDEDMA_CMD2; 57 bus_addr_t ba5_IDEDMA_CTL2; 58 bus_addr_t ba5_IDE_TF0; 59 bus_addr_t ba5_IDE_TF1; 60 bus_addr_t ba5_IDE_TF2; 61 bus_addr_t ba5_IDE_TF3; 62 bus_addr_t ba5_IDE_TF4; 63 bus_addr_t ba5_IDE_TF5; 64 bus_addr_t ba5_IDE_TF6; 65 bus_addr_t ba5_IDE_TF7; 66 bus_addr_t ba5_IDE_TF8; 67 bus_addr_t ba5_IDE_RAD; 68 bus_addr_t ba5_IDE_TF9; 69 bus_addr_t ba5_IDE_TF10; 70 bus_addr_t ba5_IDE_TF11; 71 bus_addr_t ba5_IDE_TF12; 72 bus_addr_t ba5_IDE_TF13; 73 bus_addr_t ba5_IDE_TF14; 74 bus_addr_t ba5_IDE_TF15; 75 bus_addr_t ba5_IDE_TF16; 76 bus_addr_t ba5_IDE_TF17; 77 bus_addr_t ba5_IDE_TF18; 78 bus_addr_t ba5_IDE_TF19; 79 bus_addr_t ba5_IDE_RABC; 80 bus_addr_t ba5_IDE_CMD_STS; 81 bus_addr_t ba5_IDE_CFG_STS; 82 bus_addr_t ba5_IDE_DTM; 83 bus_addr_t ba5_SControl; 84 bus_addr_t ba5_SStatus; 85 bus_addr_t ba5_SError; 86 bus_addr_t ba5_SActive; /* 3114 */ 87 bus_addr_t ba5_SMisc; 88 bus_addr_t ba5_PHY_CONFIG; 89 bus_addr_t ba5_SIEN; 90 bus_addr_t ba5_SFISCfg; 91 } satalink_ba5_regmap[] = { 92 { /* Channel 0 */ 93 .ba5_IDEDMA_CMD = 0x000, 94 .ba5_IDEDMA_CTL = 0x002, 95 .ba5_IDEDMA_TBL = 0x004, 96 .ba5_IDEDMA_CMD2 = 0x010, 97 .ba5_IDEDMA_CTL2 = 0x012, 98 .ba5_IDE_TF0 = 0x080, /* wd_data */ 99 .ba5_IDE_TF1 = 0x081, /* wd_error */ 100 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 101 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 102 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 103 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 104 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 105 .ba5_IDE_TF7 = 0x087, /* wd_command */ 106 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 107 .ba5_IDE_RAD = 0x08c, 108 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 109 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 110 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 111 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 112 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 113 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 114 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 115 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 116 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 117 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 118 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 119 .ba5_IDE_RABC = 0x09c, 120 .ba5_IDE_CMD_STS = 0x0a0, 121 .ba5_IDE_CFG_STS = 0x0a1, 122 .ba5_IDE_DTM = 0x0b4, 123 .ba5_SControl = 0x100, 124 .ba5_SStatus = 0x104, 125 .ba5_SError = 0x108, 126 .ba5_SActive = 0x10c, 127 .ba5_SMisc = 0x140, 128 .ba5_PHY_CONFIG = 0x144, 129 .ba5_SIEN = 0x148, 130 .ba5_SFISCfg = 0x14c, 131 }, 132 { /* Channel 1 */ 133 .ba5_IDEDMA_CMD = 0x008, 134 .ba5_IDEDMA_CTL = 0x00a, 135 .ba5_IDEDMA_TBL = 0x00c, 136 .ba5_IDEDMA_CMD2 = 0x018, 137 .ba5_IDEDMA_CTL2 = 0x01a, 138 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 139 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 140 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 141 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 142 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 143 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 144 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 145 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 146 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 147 .ba5_IDE_RAD = 0x0cc, 148 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 149 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 150 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 151 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 152 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 153 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 154 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 155 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 156 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 157 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 158 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 159 .ba5_IDE_RABC = 0x0dc, 160 .ba5_IDE_CMD_STS = 0x0e0, 161 .ba5_IDE_CFG_STS = 0x0e1, 162 .ba5_IDE_DTM = 0x0f4, 163 .ba5_SControl = 0x180, 164 .ba5_SStatus = 0x184, 165 .ba5_SError = 0x188, 166 .ba5_SActive = 0x18c, 167 .ba5_SMisc = 0x1c0, 168 .ba5_PHY_CONFIG = 0x1c4, 169 .ba5_SIEN = 0x1c8, 170 .ba5_SFISCfg = 0x1cc, 171 }, 172 { /* Channel 2 (3114) */ 173 .ba5_IDEDMA_CMD = 0x200, 174 .ba5_IDEDMA_CTL = 0x202, 175 .ba5_IDEDMA_TBL = 0x204, 176 .ba5_IDEDMA_CMD2 = 0x210, 177 .ba5_IDEDMA_CTL2 = 0x212, 178 .ba5_IDE_TF0 = 0x280, /* wd_data */ 179 .ba5_IDE_TF1 = 0x281, /* wd_error */ 180 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 181 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 182 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 183 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 184 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 185 .ba5_IDE_TF7 = 0x287, /* wd_command */ 186 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 187 .ba5_IDE_RAD = 0x28c, 188 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 189 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 190 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 191 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 192 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 193 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 194 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 195 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 196 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 197 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 198 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 199 .ba5_IDE_RABC = 0x29c, 200 .ba5_IDE_CMD_STS = 0x2a0, 201 .ba5_IDE_CFG_STS = 0x2a1, 202 .ba5_IDE_DTM = 0x2b4, 203 .ba5_SControl = 0x300, 204 .ba5_SStatus = 0x304, 205 .ba5_SError = 0x308, 206 .ba5_SActive = 0x30c, 207 .ba5_SMisc = 0x340, 208 .ba5_PHY_CONFIG = 0x344, 209 .ba5_SIEN = 0x348, 210 .ba5_SFISCfg = 0x34c, 211 }, 212 { /* Channel 3 (3114) */ 213 .ba5_IDEDMA_CMD = 0x208, 214 .ba5_IDEDMA_CTL = 0x20a, 215 .ba5_IDEDMA_TBL = 0x20c, 216 .ba5_IDEDMA_CMD2 = 0x218, 217 .ba5_IDEDMA_CTL2 = 0x21a, 218 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 219 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 220 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 221 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 222 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 223 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 224 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 225 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 226 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 227 .ba5_IDE_RAD = 0x2cc, 228 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 229 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 230 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 231 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 232 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 233 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 234 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 235 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 236 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 237 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 238 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 239 .ba5_IDE_RABC = 0x2dc, 240 .ba5_IDE_CMD_STS = 0x2e0, 241 .ba5_IDE_CFG_STS = 0x2e1, 242 .ba5_IDE_DTM = 0x2f4, 243 .ba5_SControl = 0x380, 244 .ba5_SStatus = 0x384, 245 .ba5_SError = 0x388, 246 .ba5_SActive = 0x38c, 247 .ba5_SMisc = 0x3c0, 248 .ba5_PHY_CONFIG = 0x3c4, 249 .ba5_SIEN = 0x3c8, 250 .ba5_SFISCfg = 0x3cc, 251 }, 252 }; 253 254 #define ba5_SIS 0x214 /* summary interrupt status */ 255 256 /* Interrupt steering bit in BA5[0x200]. */ 257 #define IDEDMA_CMD_INT_STEER (1U << 1) 258 259 static int satalink_match(device_t, cfdata_t, void *); 260 static void satalink_attach(device_t, device_t, void *); 261 262 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), 263 satalink_match, satalink_attach, NULL, NULL); 264 265 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 266 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 267 static void sii3112_drv_probe(struct ata_channel*); 268 static void sii3112_setup_channel(struct ata_channel*); 269 270 static const struct pciide_product_desc pciide_satalink_products[] = { 271 { PCI_PRODUCT_CMDTECH_3112, 272 0, 273 "Silicon Image SATALink 3112", 274 sii3112_chip_map, 275 }, 276 { PCI_PRODUCT_CMDTECH_240, 277 0, 278 "Silicon Image SATALink Sil240", 279 sii3112_chip_map, 280 }, 281 { PCI_PRODUCT_CMDTECH_3512, 282 0, 283 "Silicon Image SATALink 3512", 284 sii3112_chip_map, 285 }, 286 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 287 0, 288 "Adaptec AAR-1210SA serial ATA RAID controller", 289 sii3112_chip_map, 290 }, 291 { PCI_PRODUCT_CMDTECH_3114, 292 0, 293 "Silicon Image SATALink 3114", 294 sii3114_chip_map, 295 }, 296 { PCI_PRODUCT_ATI_IXP_SATA_300, 297 0, 298 "ATI IXP 300 SATA", 299 sii3112_chip_map, 300 }, 301 { 0, 302 0, 303 NULL, 304 NULL 305 } 306 }; 307 308 static int 309 satalink_match(device_t parent, cfdata_t match, void *aux) 310 { 311 struct pci_attach_args *pa = aux; 312 313 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 314 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 315 return (2); 316 } 317 return (0); 318 } 319 320 static void 321 satalink_attach(device_t parent, device_t self, void *aux) 322 { 323 struct pci_attach_args *pa = aux; 324 struct pciide_softc *sc = device_private(self); 325 326 sc->sc_wdcdev.sc_atac.atac_dev = self; 327 328 pciide_common_attach(sc, pa, 329 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 330 331 } 332 333 static inline uint32_t 334 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 335 { 336 uint32_t rv; 337 int s; 338 339 s = splbio(); 340 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 341 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 342 splx(s); 343 344 return (rv); 345 } 346 347 static inline uint32_t 348 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 349 { 350 351 if (__predict_true(sc->sc_ba5_en != 0)) 352 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 353 354 return (ba5_read_4_ind(sc, reg)); 355 } 356 357 #define BA5_READ_4(sc, chan, reg) \ 358 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 359 360 static inline void 361 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 362 { 363 int s; 364 365 s = splbio(); 366 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 367 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 368 splx(s); 369 } 370 371 static inline void 372 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 373 { 374 375 if (__predict_true(sc->sc_ba5_en != 0)) 376 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 377 else 378 ba5_write_4_ind(sc, reg, val); 379 } 380 381 #define BA5_WRITE_4(sc, chan, reg, val) \ 382 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 383 384 /* 385 * When the Silicon Image 3112 retries a PCI memory read command, 386 * it may retry it as a memory read multiple command under some 387 * circumstances. This can totally confuse some PCI controllers, 388 * so ensure that it will never do this by making sure that the 389 * Read Threshold (FIFO Read Request Control) field of the FIFO 390 * Valid Byte Count and Control registers for both channels (BA5 391 * offset 0x40 and 0x44) are set to be at least as large as the 392 * cacheline size register. 393 * This may also happen on the 3114 (ragge 050527) 394 */ 395 static void 396 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa, int n) 397 { 398 pcireg_t cls, reg; 399 int i; 400 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 401 402 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 403 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 404 cls *= 4; 405 if (cls > 224) { 406 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 407 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 408 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 409 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 410 cls = 224; 411 } 412 if (cls < 32) 413 cls = 32; 414 cls = (cls + 31) / 32; 415 for (i = 0; i < n; i++) { 416 reg = ba5_read_4(sc, addr[i]); 417 if ((reg & 0x7) < cls) 418 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 419 } 420 } 421 422 static void 423 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 424 { 425 struct pciide_channel *cp; 426 bus_size_t cmdsize, ctlsize; 427 pcireg_t interface, scs_cmd, cfgctl; 428 int channel; 429 430 if (pciide_chipen(sc, pa) == 0) 431 return; 432 433 #define SII3112_RESET_BITS \ 434 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 435 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 436 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 437 438 /* 439 * Reset everything and then unblock all of the interrupts. 440 */ 441 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 442 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 443 scs_cmd | SII3112_RESET_BITS); 444 delay(50 * 1000); 445 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 446 scs_cmd & SCS_CMD_BA5_EN); 447 delay(50 * 1000); 448 449 if (scs_cmd & SCS_CMD_BA5_EN) { 450 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 451 "SATALink BA5 register space enabled\n"); 452 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 453 PCI_MAPREG_TYPE_MEM| 454 PCI_MAPREG_MEM_TYPE_32BIT, 0, 455 &sc->sc_ba5_st, &sc->sc_ba5_sh, 456 NULL, NULL) != 0) 457 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 458 "unable to map SATALink BA5 register space\n"); 459 else 460 sc->sc_ba5_en = 1; 461 } else { 462 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 463 "SATALink BA5 register space disabled\n"); 464 465 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 466 SII3112_PCI_CFGCTL); 467 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 468 cfgctl | CFGCTL_BA5INDEN); 469 } 470 471 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 472 "bus-master DMA support present"); 473 pciide_mapreg_dma(sc, pa); 474 aprint_verbose("\n"); 475 476 /* 477 * Rev. <= 0x01 of the 3112 have a bug that can cause data 478 * corruption if DMA transfers cross an 8K boundary. This is 479 * apparently hard to tickle, but we'll go ahead and play it 480 * safe. 481 */ 482 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 || 483 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) && 484 PCI_REVISION(pa->pa_class) <= 0x01) { 485 sc->sc_dma_maxsegsz = 8192; 486 sc->sc_dma_boundary = 8192; 487 } 488 489 sii_fixup_cacheline(sc, pa, 2); 490 491 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 492 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 493 if (sc->sc_dma_ok) { 494 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 495 sc->sc_wdcdev.irqack = pciide_irqack; 496 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 497 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 498 } 499 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 500 501 /* We can use SControl and SStatus to probe for drives. */ 502 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 503 504 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 505 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 506 507 wdc_allocate_regs(&sc->sc_wdcdev); 508 509 /* 510 * The 3112 either identifies itself as a RAID storage device 511 * or a Misc storage device. Fake up the interface bits for 512 * what our driver expects. 513 */ 514 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 515 interface = PCI_INTERFACE(pa->pa_class); 516 } else { 517 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 518 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 519 } 520 521 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 522 channel++) { 523 cp = &sc->pciide_channels[channel]; 524 if (pciide_chansetup(sc, channel, interface) == 0) 525 continue; 526 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 527 pciide_pci_intr); 528 } 529 } 530 531 static void 532 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 533 { 534 struct pciide_channel *pc; 535 int chan, reg; 536 bus_size_t size; 537 538 sc->sc_wdcdev.dma_arg = sc; 539 sc->sc_wdcdev.dma_init = pciide_dma_init; 540 sc->sc_wdcdev.dma_start = pciide_dma_start; 541 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 542 543 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 544 PCIIDE_OPTIONS_NODMA) { 545 aprint_verbose( 546 ", but unused (forced off by config file)"); 547 sc->sc_dma_ok = 0; 548 return; 549 } 550 551 /* 552 * Slice off a subregion of BA5 for each of the channel's DMA 553 * registers. 554 */ 555 556 sc->sc_dma_iot = sc->sc_ba5_st; 557 for (chan = 0; chan < 4; chan++) { 558 pc = &sc->pciide_channels[chan]; 559 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 560 size = 4; 561 if (size > (IDEDMA_SCH_OFFSET - reg)) 562 size = IDEDMA_SCH_OFFSET - reg; 563 if (bus_space_subregion(sc->sc_ba5_st, 564 sc->sc_ba5_sh, 565 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 566 size, &pc->dma_iohs[reg]) != 0) { 567 sc->sc_dma_ok = 0; 568 aprint_verbose(", but can't subregion offset " 569 "%lu size %lu", 570 (u_long) satalink_ba5_regmap[ 571 chan].ba5_IDEDMA_CMD + reg, 572 (u_long) size); 573 return; 574 } 575 } 576 } 577 578 /* DMA registers all set up! */ 579 sc->sc_dmat = pa->pa_dmat; 580 sc->sc_dma_ok = 1; 581 } 582 583 static int 584 sii3114_chansetup(struct pciide_softc *sc, int channel) 585 { 586 static const char *channel_names[] = { 587 "port 0", 588 "port 1", 589 "port 2", 590 "port 3", 591 }; 592 struct pciide_channel *cp = &sc->pciide_channels[channel]; 593 594 sc->wdc_chanarray[channel] = &cp->ata_channel; 595 596 /* 597 * We must always keep the Interrupt Steering bit set in channel 2's 598 * IDEDMA_CMD register. 599 */ 600 if (channel == 2) 601 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 602 603 cp->name = channel_names[channel]; 604 cp->ata_channel.ch_channel = channel; 605 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 606 cp->ata_channel.ch_queue = 607 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 608 cp->ata_channel.ch_ndrive = 2; 609 if (cp->ata_channel.ch_queue == NULL) { 610 aprint_error("%s %s channel: " 611 "can't allocate memory for command queue", 612 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 613 return (0); 614 } 615 return (1); 616 } 617 618 static void 619 sii3114_mapchan(struct pciide_channel *cp) 620 { 621 struct ata_channel *wdc_cp = &cp->ata_channel; 622 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 623 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 624 int i; 625 626 cp->compat = 0; 627 cp->ih = sc->sc_pci_ih; 628 629 wdr->cmd_iot = sc->sc_ba5_st; 630 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 631 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 632 9, &wdr->cmd_baseioh) != 0) { 633 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 634 "couldn't subregion %s cmd base\n", cp->name); 635 goto bad; 636 } 637 638 wdr->ctl_iot = sc->sc_ba5_st; 639 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 640 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 641 1, &cp->ctl_baseioh) != 0) { 642 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 643 "couldn't subregion %s ctl base\n", cp->name); 644 goto bad; 645 } 646 wdr->ctl_ioh = cp->ctl_baseioh; 647 648 for (i = 0; i < WDC_NREG; i++) { 649 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 650 i, i == 0 ? 4 : 1, 651 &wdr->cmd_iohs[i]) != 0) { 652 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 653 "couldn't subregion %s channel cmd regs\n", 654 cp->name); 655 goto bad; 656 } 657 } 658 wdc_init_shadow_regs(wdc_cp); 659 wdr->data32iot = wdr->cmd_iot; 660 wdr->data32ioh = wdr->cmd_iohs[0]; 661 wdcattach(wdc_cp); 662 return; 663 664 bad: 665 cp->ata_channel.ch_flags |= ATACH_DISABLED; 666 } 667 668 static void 669 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 670 { 671 struct pciide_channel *cp; 672 pcireg_t scs_cmd; 673 pci_intr_handle_t intrhandle; 674 const char *intrstr; 675 int channel; 676 677 if (pciide_chipen(sc, pa) == 0) 678 return; 679 680 #define SII3114_RESET_BITS \ 681 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 682 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 683 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 684 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 685 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 686 687 /* 688 * Reset everything and then unblock all of the interrupts. 689 */ 690 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 691 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 692 scs_cmd | SII3114_RESET_BITS); 693 delay(50 * 1000); 694 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 695 scs_cmd & SCS_CMD_M66EN); 696 delay(50 * 1000); 697 698 /* 699 * On the 3114, the BA5 register space is always enabled. In 700 * order to use the 3114 in any sane way, we must use this BA5 701 * register space, and so we consider it an error if we cannot 702 * map it. 703 * 704 * As a consequence of using BA5, our register mapping is different 705 * from a normal PCI IDE controller's, and so we are unable to use 706 * most of the common PCI IDE register mapping functions. 707 */ 708 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 709 PCI_MAPREG_TYPE_MEM| 710 PCI_MAPREG_MEM_TYPE_32BIT, 0, 711 &sc->sc_ba5_st, &sc->sc_ba5_sh, 712 NULL, NULL) != 0) { 713 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 714 "unable to map SATALink BA5 register space\n"); 715 return; 716 } 717 sc->sc_ba5_en = 1; 718 719 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 720 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 721 722 /* 723 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 724 * channel 2. This is required at all times for proper operation 725 * when using the BA5 register space (otherwise interrupts from 726 * all 4 channels won't work). 727 */ 728 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 729 730 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 731 "bus-master DMA support present"); 732 sii3114_mapreg_dma(sc, pa); 733 aprint_verbose("\n"); 734 735 sii_fixup_cacheline(sc, pa, 4); 736 737 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 738 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 739 if (sc->sc_dma_ok) { 740 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 741 sc->sc_wdcdev.irqack = pciide_irqack; 742 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 743 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 744 } 745 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 746 747 /* We can use SControl and SStatus to probe for drives. */ 748 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 749 750 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 751 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 752 753 wdc_allocate_regs(&sc->sc_wdcdev); 754 755 /* Map and establish the interrupt handler. */ 756 if (pci_intr_map(pa, &intrhandle) != 0) { 757 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 758 "couldn't map native-PCI interrupt\n"); 759 return; 760 } 761 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 762 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 763 /* XXX */ 764 pciide_pci_intr, sc); 765 if (sc->sc_pci_ih != NULL) { 766 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 767 "using %s for native-PCI interrupt\n", 768 intrstr ? intrstr : "unknown interrupt"); 769 } else { 770 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 771 "couldn't establish native-PCI interrupt"); 772 if (intrstr != NULL) 773 aprint_error(" at %s", intrstr); 774 aprint_error("\n"); 775 return; 776 } 777 778 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 779 channel++) { 780 cp = &sc->pciide_channels[channel]; 781 if (sii3114_chansetup(sc, channel) == 0) 782 continue; 783 sii3114_mapchan(cp); 784 } 785 } 786 787 /* Probe the drives using SATA registers. 788 * Note we can't use wdc_sataprobe as we may not be able to map ba5 789 */ 790 static void 791 sii3112_drv_probe(struct ata_channel *chp) 792 { 793 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 794 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 795 uint32_t scontrol, sstatus; 796 uint8_t scnt, sn, cl, ch; 797 int i, s; 798 799 /* XXX This should be done by other code. */ 800 for (i = 0; i < 2; i++) { 801 chp->ch_drive[i].chnl_softc = chp; 802 chp->ch_drive[i].drive = i; 803 } 804 805 /* 806 * The 3112 is a 2-port part, and only has one drive per channel 807 * (each port emulates a master drive). 808 * 809 * The 3114 is similar, but has 4 channels. 810 */ 811 812 /* 813 * Request communication initialization sequence, any speed. 814 * Performing this is the equivalent of an ATA Reset. 815 */ 816 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 817 818 /* 819 * XXX We don't yet support SATA power management; disable all 820 * power management state transitions. 821 */ 822 scontrol |= SControl_IPM_NONE; 823 824 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 825 delay(50 * 1000); 826 scontrol &= ~SControl_DET_INIT; 827 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 828 delay(50 * 1000); 829 830 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 831 #if 0 832 aprint_normal_dev(&sc->sc_wdcdev.sc_atac.atac_dev, 833 "port %d: SStatus=0x%08x, SControl=0x%08x\n", 834 chp->ch_channel, sstatus, 835 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 836 #endif 837 switch (sstatus & SStatus_DET_mask) { 838 case SStatus_DET_NODEV: 839 /* No device; be silent. */ 840 break; 841 842 case SStatus_DET_DEV_NE: 843 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 844 "port %d: device connected, but " 845 "communication not established\n", chp->ch_channel); 846 break; 847 848 case SStatus_DET_OFFLINE: 849 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 850 "port %d: PHY offline\n", chp->ch_channel); 851 break; 852 853 case SStatus_DET_DEV: 854 /* 855 * XXX ATAPI detection doesn't currently work. Don't 856 * XXX know why. But, it's not like the standard method 857 * XXX can detect an ATAPI device connected via a SATA/PATA 858 * XXX bridge, so at least this is no worse. --thorpej 859 */ 860 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 861 WDSD_IBM | (0 << 4)); 862 delay(10); /* 400ns delay */ 863 /* Save register contents. */ 864 scnt = bus_space_read_1(wdr->cmd_iot, 865 wdr->cmd_iohs[wd_seccnt], 0); 866 sn = bus_space_read_1(wdr->cmd_iot, 867 wdr->cmd_iohs[wd_sector], 0); 868 cl = bus_space_read_1(wdr->cmd_iot, 869 wdr->cmd_iohs[wd_cyl_lo], 0); 870 ch = bus_space_read_1(wdr->cmd_iot, 871 wdr->cmd_iohs[wd_cyl_hi], 0); 872 #if 0 873 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 874 device_xname(&sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel, 875 scnt, sn, cl, ch); 876 #endif 877 /* 878 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 879 * cases we get wrong values here, so ignore it. 880 */ 881 s = splbio(); 882 if (cl == 0x14 && ch == 0xeb) 883 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 884 else 885 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 886 splx(s); 887 888 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 889 "port %d: device present, speed: %s\n", 890 chp->ch_channel, 891 sata_speed(sstatus)); 892 break; 893 894 default: 895 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 896 "port %d: unknown SStatus: 0x%08x\n", 897 chp->ch_channel, sstatus); 898 } 899 } 900 901 static void 902 sii3112_setup_channel(struct ata_channel *chp) 903 { 904 struct ata_drive_datas *drvp; 905 int drive, s; 906 u_int32_t idedma_ctl, dtm; 907 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 908 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 909 910 /* setup DMA if needed */ 911 pciide_channel_dma_setup(cp); 912 913 idedma_ctl = 0; 914 dtm = 0; 915 916 for (drive = 0; drive < 2; drive++) { 917 drvp = &chp->ch_drive[drive]; 918 /* If no drive, skip */ 919 if ((drvp->drive_flags & DRIVE) == 0) 920 continue; 921 if (drvp->drive_flags & DRIVE_UDMA) { 922 /* use Ultra/DMA */ 923 s = splbio(); 924 drvp->drive_flags &= ~DRIVE_DMA; 925 splx(s); 926 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 927 dtm |= DTM_IDEx_DMA; 928 } else if (drvp->drive_flags & DRIVE_DMA) { 929 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 930 dtm |= DTM_IDEx_DMA; 931 } else { 932 dtm |= DTM_IDEx_PIO; 933 } 934 } 935 936 /* 937 * Nothing to do to setup modes; it is meaningless in S-ATA 938 * (but many S-ATA drives still want to get the SET_FEATURE 939 * command). 940 */ 941 if (idedma_ctl != 0) { 942 /* Add software bits in status register */ 943 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 944 idedma_ctl); 945 } 946 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 947 } 948
Indexes created Thu Oct 02 14:10:14 GMT 2025