satalink.c revision 1.4
1 /* $NetBSD: satalink.c,v 1.4 2003/12/19 03:33:52 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 51 /* 52 * Register map for BA5 register space, indexed by channel. 53 */ 54 static const struct { 55 bus_addr_t ba5_IDEDMA_CMD; 56 bus_addr_t ba5_IDEDMA_CTL; 57 bus_addr_t ba5_IDEDMA_TBL; 58 bus_addr_t ba5_IDEDMA_CMD2; 59 bus_addr_t ba5_IDEDMA_CTL2; 60 bus_addr_t ba5_IDE_TF0; 61 bus_addr_t ba5_IDE_TF1; 62 bus_addr_t ba5_IDE_TF2; 63 bus_addr_t ba5_IDE_TF3; 64 bus_addr_t ba5_IDE_TF4; 65 bus_addr_t ba5_IDE_TF5; 66 bus_addr_t ba5_IDE_TF6; 67 bus_addr_t ba5_IDE_TF7; 68 bus_addr_t ba5_IDE_TF8; 69 bus_addr_t ba5_IDE_RAD; 70 bus_addr_t ba5_IDE_TF9; 71 bus_addr_t ba5_IDE_TF10; 72 bus_addr_t ba5_IDE_TF11; 73 bus_addr_t ba5_IDE_TF12; 74 bus_addr_t ba5_IDE_TF13; 75 bus_addr_t ba5_IDE_TF14; 76 bus_addr_t ba5_IDE_TF15; 77 bus_addr_t ba5_IDE_TF16; 78 bus_addr_t ba5_IDE_TF17; 79 bus_addr_t ba5_IDE_TF18; 80 bus_addr_t ba5_IDE_TF19; 81 bus_addr_t ba5_IDE_RABC; 82 bus_addr_t ba5_IDE_CMD_STS; 83 bus_addr_t ba5_IDE_CFG_STS; 84 bus_addr_t ba5_IDE_DTM; 85 bus_addr_t ba5_SControl; 86 bus_addr_t ba5_SStatus; 87 bus_addr_t ba5_SError; 88 } satalink_ba5_regmap[] = { 89 { 90 .ba5_IDEDMA_CMD = 0x000, 91 .ba5_IDEDMA_CTL = 0x002, 92 .ba5_IDEDMA_TBL = 0x004, 93 .ba5_IDEDMA_CMD2 = 0x010, 94 .ba5_IDEDMA_CTL2 = 0x012, 95 .ba5_IDE_TF0 = 0x080, /* wd_data */ 96 .ba5_IDE_TF1 = 0x081, /* wd_error */ 97 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 98 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 99 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 100 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 101 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 102 .ba5_IDE_TF7 = 0x087, /* wd_command */ 103 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 104 .ba5_IDE_RAD = 0x08c, 105 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 106 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 107 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 108 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 109 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 110 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 111 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 112 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 113 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 114 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 115 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 116 .ba5_IDE_RABC = 0x09c, 117 .ba5_IDE_CMD_STS = 0x0a0, 118 .ba5_IDE_CFG_STS = 0x0a1, 119 .ba5_IDE_DTM = 0x0b4, 120 .ba5_SControl = 0x100, 121 .ba5_SStatus = 0x104, 122 .ba5_SError = 0x108, 123 }, 124 { 125 .ba5_IDEDMA_CMD = 0x008, 126 .ba5_IDEDMA_CTL = 0x00a, 127 .ba5_IDEDMA_TBL = 0x00c, 128 .ba5_IDEDMA_CMD2 = 0x018, 129 .ba5_IDEDMA_CTL2 = 0x01a, 130 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 131 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 132 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 133 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 134 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 135 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 136 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 137 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 138 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 139 .ba5_IDE_RAD = 0x0cc, 140 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 141 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 142 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 143 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 144 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 145 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 146 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 147 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 148 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 149 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 150 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 151 .ba5_IDE_RABC = 0x0dc, 152 .ba5_IDE_CMD_STS = 0x0e0, 153 .ba5_IDE_CFG_STS = 0x0e1, 154 .ba5_IDE_DTM = 0x0f4, 155 .ba5_SControl = 0x180, 156 .ba5_SStatus = 0x184, 157 .ba5_SError = 0x188, 158 } 159 }; 160 161 static int satalink_match(struct device *, struct cfdata *, void *); 162 static void satalink_attach(struct device *, struct device *, void *); 163 164 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 165 satalink_match, satalink_attach, NULL, NULL); 166 167 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 168 static int sii3112_drv_probe(struct channel_softc*); 169 static void sii3112_setup_channel(struct channel_softc*); 170 171 static const struct pciide_product_desc pciide_satalink_products[] = { 172 { PCI_PRODUCT_CMDTECH_3112, 173 0, 174 "Silicon Image SATALink 3112", 175 sii3112_chip_map, 176 }, 177 { 0, 178 0, 179 NULL, 180 NULL 181 } 182 }; 183 184 static int 185 satalink_match(struct device *parent, struct cfdata *match, void *aux) 186 { 187 struct pci_attach_args *pa = aux; 188 189 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 190 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 191 return (2); 192 } 193 return (0); 194 } 195 196 static void 197 satalink_attach(struct device *parent, struct device *self, void *aux) 198 { 199 struct pci_attach_args *pa = aux; 200 struct pciide_softc *sc = (struct pciide_softc *)self; 201 202 pciide_common_attach(sc, pa, 203 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 204 205 } 206 207 static __inline uint32_t 208 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 209 { 210 211 if (__predict_true(sc->sc_ba5_en != 0)) 212 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 213 214 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 215 return (pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA)); 216 } 217 218 #define BA5_READ_4(sc, chan, reg) \ 219 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 220 221 static __inline void 222 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 223 { 224 225 if (__predict_true(sc->sc_ba5_en != 0)) 226 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 227 else { 228 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, 229 reg); 230 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, 231 val); 232 } 233 } 234 235 #define BA5_WRITE_4(sc, chan, reg, val) \ 236 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 237 238 static void 239 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 240 { 241 struct pciide_channel *cp; 242 bus_size_t cmdsize, ctlsize; 243 pcireg_t interface, scs_cmd, cfgctl; 244 int channel; 245 246 if (pciide_chipen(sc, pa) == 0) 247 return; 248 249 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 250 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 251 scs_cmd & SCS_CMD_BA5_EN); 252 253 if (scs_cmd & SCS_CMD_BA5_EN) { 254 aprint_verbose("%s: SATALink BA5 register space enabled\n", 255 sc->sc_wdcdev.sc_dev.dv_xname); 256 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 257 PCI_MAPREG_TYPE_MEM| 258 PCI_MAPREG_MEM_TYPE_32BIT, 0, 259 &sc->sc_ba5_st, &sc->sc_ba5_sh, 260 NULL, NULL) != 0) 261 aprint_error("%s: unable to map SATALink BA5 " 262 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 263 else 264 sc->sc_ba5_en = 1; 265 } else { 266 aprint_verbose("%s: SATALink BA5 register space disabled\n", 267 sc->sc_wdcdev.sc_dev.dv_xname); 268 269 /* Enable indirect BA5 addressing. */ 270 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 271 SII3112_PCI_CFGCTL); 272 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 273 cfgctl | CFGCTL_BA5INDEN); 274 } 275 276 aprint_normal("%s: bus-master DMA support present", 277 sc->sc_wdcdev.sc_dev.dv_xname); 278 pciide_mapreg_dma(sc, pa); 279 aprint_normal("\n"); 280 281 /* 282 * Rev. <= 0x01 of the 3112 have a bug that can cause data 283 * corruption if DMA transfers cross an 8K boundary. This is 284 * apparently hard to tickle, but we'll go ahead and play it 285 * safe. 286 */ 287 if (PCI_REVISION(pa->pa_class) <= 0x01) { 288 sc->sc_dma_maxsegsz = 8192; 289 sc->sc_dma_boundary = 8192; 290 } 291 292 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 293 WDC_CAPABILITY_MODE; 294 sc->sc_wdcdev.PIO_cap = 4; 295 if (sc->sc_dma_ok) { 296 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 297 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 298 sc->sc_wdcdev.irqack = pciide_irqack; 299 sc->sc_wdcdev.DMA_cap = 2; 300 sc->sc_wdcdev.UDMA_cap = 6; 301 } 302 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 303 304 /* We can use SControl and SStatus to probe for drives. */ 305 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE; 306 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 307 308 sc->sc_wdcdev.channels = sc->wdc_chanarray; 309 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 310 311 /* 312 * The 3112 either identifies itself as a RAID storage device 313 * or a Misc storage device. Fake up the interface bits for 314 * what our driver expects. 315 */ 316 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 317 interface = PCI_INTERFACE(pa->pa_class); 318 } else { 319 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 320 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 321 } 322 323 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 324 cp = &sc->pciide_channels[channel]; 325 if (pciide_chansetup(sc, channel, interface) == 0) 326 continue; 327 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 328 pciide_pci_intr); 329 } 330 } 331 332 static const char *sata_speed[] = { 333 "no negotiated speed", 334 "1.5Gb/s", 335 "<unknown 2>", 336 "<unknown 3>", 337 "<unknown 4>", 338 "<unknown 5>", 339 "<unknown 6>", 340 "<unknown 7>", 341 "<unknown 8>", 342 "<unknown 9>", 343 "<unknown 10>", 344 "<unknown 11>", 345 "<unknown 12>", 346 "<unknown 13>", 347 "<unknown 14>", 348 "<unknown 15>", 349 }; 350 351 static int 352 sii3112_drv_probe(struct channel_softc *chp) 353 { 354 struct pciide_channel *cp = (struct pciide_channel *)chp; 355 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 356 uint32_t scontrol, sstatus; 357 int rv = 0; 358 uint8_t scnt, sn, cl, ch; 359 360 /* 361 * The 3112 is a 2-port part, and only has one drive per channel 362 * (each port emulates a master drive). 363 */ 364 365 /* 366 * Request communication initialization sequence, any speed. 367 * Performing this is the equivalent of an ATA Reset. 368 */ 369 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 370 371 /* 372 * XXX We don't yet support SATA power management; disable all 373 * power management state transitions. 374 */ 375 scontrol |= SControl_IPM_NONE; 376 377 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 378 delay(500); 379 scontrol &= ~SControl_DET_INIT; 380 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 381 delay(500); 382 383 sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); 384 switch (sstatus & SStatus_DET_mask) { 385 case SStatus_DET_NODEV: 386 /* No device; be silent. */ 387 break; 388 389 case SStatus_DET_DEV_NE: 390 aprint_error("%s: port %d: device connected, but " 391 "communication not established\n", 392 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 393 break; 394 395 case SStatus_DET_OFFLINE: 396 aprint_error("%s: port %d: PHY offline\n", 397 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 398 break; 399 400 case SStatus_DET_DEV: 401 /* 402 * XXX ATAPI detection doesn't currently work. Don't 403 * XXX know why. But, it's not like the standard method 404 * XXX can detect an ATAPI device connected via a SATA/PATA 405 * XXX bridge, so at least this is no worse. --thorpej 406 */ 407 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 408 WDSD_IBM | (0 << 4)); 409 delay(10); /* 400ns delay */ 410 /* Save register contents. */ 411 scnt = bus_space_read_1(chp->cmd_iot, 412 chp->cmd_iohs[wd_seccnt], 0); 413 sn = bus_space_read_1(chp->cmd_iot, 414 chp->cmd_iohs[wd_sector], 0); 415 cl = bus_space_read_1(chp->cmd_iot, 416 chp->cmd_iohs[wd_cyl_lo], 0); 417 ch = bus_space_read_1(chp->cmd_iot, 418 chp->cmd_iohs[wd_cyl_hi], 0); 419 #if 0 420 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 421 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 422 scnt, sn, cl, ch); 423 #endif 424 /* 425 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 426 * cases we get wrong values here, so ignore it. 427 */ 428 if (cl == 0x14 && ch == 0xeb) 429 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 430 else 431 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 432 433 aprint_normal("%s: port %d: device present, speed: %s\n", 434 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 435 sata_speed[(sstatus & SStatus_SPD_mask) >> 436 SStatus_SPD_shift]); 437 rv |= (1 << 0); 438 break; 439 440 default: 441 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 442 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 443 } 444 445 return (rv); 446 } 447 448 static void 449 sii3112_setup_channel(struct channel_softc *chp) 450 { 451 struct ata_drive_datas *drvp; 452 int drive; 453 u_int32_t idedma_ctl, dtm; 454 struct pciide_channel *cp = (struct pciide_channel*)chp; 455 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 456 457 /* setup DMA if needed */ 458 pciide_channel_dma_setup(cp); 459 460 idedma_ctl = 0; 461 dtm = 0; 462 463 for (drive = 0; drive < 2; drive++) { 464 drvp = &chp->ch_drive[drive]; 465 /* If no drive, skip */ 466 if ((drvp->drive_flags & DRIVE) == 0) 467 continue; 468 if (drvp->drive_flags & DRIVE_UDMA) { 469 /* use Ultra/DMA */ 470 drvp->drive_flags &= ~DRIVE_DMA; 471 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 472 dtm |= DTM_IDEx_DMA; 473 } else if (drvp->drive_flags & DRIVE_DMA) { 474 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 475 dtm |= DTM_IDEx_DMA; 476 } else { 477 dtm |= DTM_IDEx_PIO; 478 } 479 } 480 481 /* 482 * Nothing to do to setup modes; it is meaningless in S-ATA 483 * (but many S-ATA drives still want to get the SET_FEATURE 484 * command). 485 */ 486 if (idedma_ctl != 0) { 487 /* Add software bits in status register */ 488 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 489 idedma_ctl); 490 } 491 pci_conf_write(sc->sc_pc, sc->sc_tag, 492 chp->channel == 0 ? SII3112_DTM_IDE0 : SII3112_DTM_IDE1, dtm); 493 } 494
Indexes created Mon Sep 29 21:09:56 GMT 2025