satalink.c revision 1.40
1 /* $NetBSD: satalink.c,v 1.40 2010/03/23 03:24:53 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.40 2010/03/23 03:24:53 mrg Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_sii3112_reg.h> 44 45 #include <dev/ata/satareg.h> 46 #include <dev/ata/satavar.h> 47 #include <dev/ata/atareg.h> 48 49 /* 50 * Register map for BA5 register space, indexed by channel. 51 */ 52 static const struct { 53 bus_addr_t ba5_IDEDMA_CMD; 54 bus_addr_t ba5_IDEDMA_CTL; 55 bus_addr_t ba5_IDEDMA_TBL; 56 bus_addr_t ba5_IDEDMA_CMD2; 57 bus_addr_t ba5_IDEDMA_CTL2; 58 bus_addr_t ba5_IDE_TF0; 59 bus_addr_t ba5_IDE_TF1; 60 bus_addr_t ba5_IDE_TF2; 61 bus_addr_t ba5_IDE_TF3; 62 bus_addr_t ba5_IDE_TF4; 63 bus_addr_t ba5_IDE_TF5; 64 bus_addr_t ba5_IDE_TF6; 65 bus_addr_t ba5_IDE_TF7; 66 bus_addr_t ba5_IDE_TF8; 67 bus_addr_t ba5_IDE_RAD; 68 bus_addr_t ba5_IDE_TF9; 69 bus_addr_t ba5_IDE_TF10; 70 bus_addr_t ba5_IDE_TF11; 71 bus_addr_t ba5_IDE_TF12; 72 bus_addr_t ba5_IDE_TF13; 73 bus_addr_t ba5_IDE_TF14; 74 bus_addr_t ba5_IDE_TF15; 75 bus_addr_t ba5_IDE_TF16; 76 bus_addr_t ba5_IDE_TF17; 77 bus_addr_t ba5_IDE_TF18; 78 bus_addr_t ba5_IDE_TF19; 79 bus_addr_t ba5_IDE_RABC; 80 bus_addr_t ba5_IDE_CMD_STS; 81 bus_addr_t ba5_IDE_CFG_STS; 82 bus_addr_t ba5_IDE_DTM; 83 bus_addr_t ba5_SControl; 84 bus_addr_t ba5_SStatus; 85 bus_addr_t ba5_SError; 86 bus_addr_t ba5_SActive; /* 3114 */ 87 bus_addr_t ba5_SMisc; 88 bus_addr_t ba5_PHY_CONFIG; 89 bus_addr_t ba5_SIEN; 90 bus_addr_t ba5_SFISCfg; 91 } satalink_ba5_regmap[] = { 92 { /* Channel 0 */ 93 .ba5_IDEDMA_CMD = 0x000, 94 .ba5_IDEDMA_CTL = 0x002, 95 .ba5_IDEDMA_TBL = 0x004, 96 .ba5_IDEDMA_CMD2 = 0x010, 97 .ba5_IDEDMA_CTL2 = 0x012, 98 .ba5_IDE_TF0 = 0x080, /* wd_data */ 99 .ba5_IDE_TF1 = 0x081, /* wd_error */ 100 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 101 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 102 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 103 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 104 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 105 .ba5_IDE_TF7 = 0x087, /* wd_command */ 106 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 107 .ba5_IDE_RAD = 0x08c, 108 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 109 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 110 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 111 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 112 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 113 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 114 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 115 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 116 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 117 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 118 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 119 .ba5_IDE_RABC = 0x09c, 120 .ba5_IDE_CMD_STS = 0x0a0, 121 .ba5_IDE_CFG_STS = 0x0a1, 122 .ba5_IDE_DTM = 0x0b4, 123 .ba5_SControl = 0x100, 124 .ba5_SStatus = 0x104, 125 .ba5_SError = 0x108, 126 .ba5_SActive = 0x10c, 127 .ba5_SMisc = 0x140, 128 .ba5_PHY_CONFIG = 0x144, 129 .ba5_SIEN = 0x148, 130 .ba5_SFISCfg = 0x14c, 131 }, 132 { /* Channel 1 */ 133 .ba5_IDEDMA_CMD = 0x008, 134 .ba5_IDEDMA_CTL = 0x00a, 135 .ba5_IDEDMA_TBL = 0x00c, 136 .ba5_IDEDMA_CMD2 = 0x018, 137 .ba5_IDEDMA_CTL2 = 0x01a, 138 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 139 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 140 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 141 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 142 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 143 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 144 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 145 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 146 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 147 .ba5_IDE_RAD = 0x0cc, 148 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 149 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 150 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 151 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 152 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 153 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 154 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 155 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 156 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 157 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 158 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 159 .ba5_IDE_RABC = 0x0dc, 160 .ba5_IDE_CMD_STS = 0x0e0, 161 .ba5_IDE_CFG_STS = 0x0e1, 162 .ba5_IDE_DTM = 0x0f4, 163 .ba5_SControl = 0x180, 164 .ba5_SStatus = 0x184, 165 .ba5_SError = 0x188, 166 .ba5_SActive = 0x18c, 167 .ba5_SMisc = 0x1c0, 168 .ba5_PHY_CONFIG = 0x1c4, 169 .ba5_SIEN = 0x1c8, 170 .ba5_SFISCfg = 0x1cc, 171 }, 172 { /* Channel 2 (3114) */ 173 .ba5_IDEDMA_CMD = 0x200, 174 .ba5_IDEDMA_CTL = 0x202, 175 .ba5_IDEDMA_TBL = 0x204, 176 .ba5_IDEDMA_CMD2 = 0x210, 177 .ba5_IDEDMA_CTL2 = 0x212, 178 .ba5_IDE_TF0 = 0x280, /* wd_data */ 179 .ba5_IDE_TF1 = 0x281, /* wd_error */ 180 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 181 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 182 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 183 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 184 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 185 .ba5_IDE_TF7 = 0x287, /* wd_command */ 186 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 187 .ba5_IDE_RAD = 0x28c, 188 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 189 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 190 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 191 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 192 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 193 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 194 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 195 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 196 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 197 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 198 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 199 .ba5_IDE_RABC = 0x29c, 200 .ba5_IDE_CMD_STS = 0x2a0, 201 .ba5_IDE_CFG_STS = 0x2a1, 202 .ba5_IDE_DTM = 0x2b4, 203 .ba5_SControl = 0x300, 204 .ba5_SStatus = 0x304, 205 .ba5_SError = 0x308, 206 .ba5_SActive = 0x30c, 207 .ba5_SMisc = 0x340, 208 .ba5_PHY_CONFIG = 0x344, 209 .ba5_SIEN = 0x348, 210 .ba5_SFISCfg = 0x34c, 211 }, 212 { /* Channel 3 (3114) */ 213 .ba5_IDEDMA_CMD = 0x208, 214 .ba5_IDEDMA_CTL = 0x20a, 215 .ba5_IDEDMA_TBL = 0x20c, 216 .ba5_IDEDMA_CMD2 = 0x218, 217 .ba5_IDEDMA_CTL2 = 0x21a, 218 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 219 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 220 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 221 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 222 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 223 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 224 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 225 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 226 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 227 .ba5_IDE_RAD = 0x2cc, 228 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 229 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 230 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 231 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 232 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 233 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 234 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 235 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 236 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 237 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 238 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 239 .ba5_IDE_RABC = 0x2dc, 240 .ba5_IDE_CMD_STS = 0x2e0, 241 .ba5_IDE_CFG_STS = 0x2e1, 242 .ba5_IDE_DTM = 0x2f4, 243 .ba5_SControl = 0x380, 244 .ba5_SStatus = 0x384, 245 .ba5_SError = 0x388, 246 .ba5_SActive = 0x38c, 247 .ba5_SMisc = 0x3c0, 248 .ba5_PHY_CONFIG = 0x3c4, 249 .ba5_SIEN = 0x3c8, 250 .ba5_SFISCfg = 0x3cc, 251 }, 252 }; 253 254 #define ba5_SIS 0x214 /* summary interrupt status */ 255 256 /* Interrupt steering bit in BA5[0x200]. */ 257 #define IDEDMA_CMD_INT_STEER (1U << 1) 258 259 static int satalink_match(device_t, cfdata_t, void *); 260 static void satalink_attach(device_t, device_t, void *); 261 262 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), 263 satalink_match, satalink_attach, NULL, NULL); 264 265 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 266 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 267 static void sii3112_drv_probe(struct ata_channel*); 268 static void sii3112_setup_channel(struct ata_channel*); 269 270 static const struct pciide_product_desc pciide_satalink_products[] = { 271 { PCI_PRODUCT_CMDTECH_3112, 272 0, 273 "Silicon Image SATALink 3112", 274 sii3112_chip_map, 275 }, 276 { PCI_PRODUCT_CMDTECH_3512, 277 0, 278 "Silicon Image SATALink 3512", 279 sii3112_chip_map, 280 }, 281 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 282 0, 283 "Adaptec AAR-1210SA serial ATA RAID controller", 284 sii3112_chip_map, 285 }, 286 { PCI_PRODUCT_CMDTECH_3114, 287 0, 288 "Silicon Image SATALink 3114", 289 sii3114_chip_map, 290 }, 291 { 0, 292 0, 293 NULL, 294 NULL 295 } 296 }; 297 298 static int 299 satalink_match(device_t parent, cfdata_t match, void *aux) 300 { 301 struct pci_attach_args *pa = aux; 302 303 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 304 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 305 return (2); 306 } 307 return (0); 308 } 309 310 static void 311 satalink_attach(device_t parent, device_t self, void *aux) 312 { 313 struct pci_attach_args *pa = aux; 314 struct pciide_softc *sc = device_private(self); 315 316 sc->sc_wdcdev.sc_atac.atac_dev = self; 317 318 pciide_common_attach(sc, pa, 319 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 320 321 } 322 323 static inline uint32_t 324 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 325 { 326 uint32_t rv; 327 int s; 328 329 s = splbio(); 330 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 331 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 332 splx(s); 333 334 return (rv); 335 } 336 337 static inline uint32_t 338 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 339 { 340 341 if (__predict_true(sc->sc_ba5_en != 0)) 342 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 343 344 return (ba5_read_4_ind(sc, reg)); 345 } 346 347 #define BA5_READ_4(sc, chan, reg) \ 348 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 349 350 static inline void 351 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 352 { 353 int s; 354 355 s = splbio(); 356 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 357 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 358 splx(s); 359 } 360 361 static inline void 362 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 363 { 364 365 if (__predict_true(sc->sc_ba5_en != 0)) 366 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 367 else 368 ba5_write_4_ind(sc, reg, val); 369 } 370 371 #define BA5_WRITE_4(sc, chan, reg, val) \ 372 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 373 374 /* 375 * When the Silicon Image 3112 retries a PCI memory read command, 376 * it may retry it as a memory read multiple command under some 377 * circumstances. This can totally confuse some PCI controllers, 378 * so ensure that it will never do this by making sure that the 379 * Read Threshold (FIFO Read Request Control) field of the FIFO 380 * Valid Byte Count and Control registers for both channels (BA5 381 * offset 0x40 and 0x44) are set to be at least as large as the 382 * cacheline size register. 383 * This may also happen on the 3114 (ragge 050527) 384 */ 385 static void 386 sii_fixup_cacheline(struct pciide_softc *sc, struct pci_attach_args *pa, int n) 387 { 388 pcireg_t cls, reg; 389 int i; 390 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 391 392 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 393 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 394 cls *= 4; 395 if (cls > 224) { 396 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 397 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 398 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 399 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 400 cls = 224; 401 } 402 if (cls < 32) 403 cls = 32; 404 cls = (cls + 31) / 32; 405 for (i = 0; i < n; i++) { 406 reg = ba5_read_4(sc, addr[i]); 407 if ((reg & 0x7) < cls) 408 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 409 } 410 } 411 412 static void 413 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 414 { 415 struct pciide_channel *cp; 416 bus_size_t cmdsize, ctlsize; 417 pcireg_t interface, scs_cmd, cfgctl; 418 int channel; 419 420 if (pciide_chipen(sc, pa) == 0) 421 return; 422 423 #define SII3112_RESET_BITS \ 424 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 425 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 426 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 427 428 /* 429 * Reset everything and then unblock all of the interrupts. 430 */ 431 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 432 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 433 scs_cmd | SII3112_RESET_BITS); 434 delay(50 * 1000); 435 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 436 scs_cmd & SCS_CMD_BA5_EN); 437 delay(50 * 1000); 438 439 if (scs_cmd & SCS_CMD_BA5_EN) { 440 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 441 "SATALink BA5 register space enabled\n"); 442 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 443 PCI_MAPREG_TYPE_MEM| 444 PCI_MAPREG_MEM_TYPE_32BIT, 0, 445 &sc->sc_ba5_st, &sc->sc_ba5_sh, 446 NULL, NULL) != 0) 447 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 448 "unable to map SATALink BA5 register space\n"); 449 else 450 sc->sc_ba5_en = 1; 451 } else { 452 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 453 "SATALink BA5 register space disabled\n"); 454 455 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 456 SII3112_PCI_CFGCTL); 457 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 458 cfgctl | CFGCTL_BA5INDEN); 459 } 460 461 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 462 "bus-master DMA support present"); 463 pciide_mapreg_dma(sc, pa); 464 aprint_verbose("\n"); 465 466 /* 467 * Rev. <= 0x01 of the 3112 have a bug that can cause data 468 * corruption if DMA transfers cross an 8K boundary. This is 469 * apparently hard to tickle, but we'll go ahead and play it 470 * safe. 471 */ 472 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 || 473 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) && 474 PCI_REVISION(pa->pa_class) <= 0x01) { 475 sc->sc_dma_maxsegsz = 8192; 476 sc->sc_dma_boundary = 8192; 477 } 478 479 sii_fixup_cacheline(sc, pa, 2); 480 481 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 482 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 483 if (sc->sc_dma_ok) { 484 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 485 sc->sc_wdcdev.irqack = pciide_irqack; 486 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 487 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 488 } 489 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 490 491 /* We can use SControl and SStatus to probe for drives. */ 492 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 493 494 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 495 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 496 497 wdc_allocate_regs(&sc->sc_wdcdev); 498 499 /* 500 * The 3112 either identifies itself as a RAID storage device 501 * or a Misc storage device. Fake up the interface bits for 502 * what our driver expects. 503 */ 504 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 505 interface = PCI_INTERFACE(pa->pa_class); 506 } else { 507 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 508 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 509 } 510 511 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 512 channel++) { 513 cp = &sc->pciide_channels[channel]; 514 if (pciide_chansetup(sc, channel, interface) == 0) 515 continue; 516 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 517 pciide_pci_intr); 518 } 519 } 520 521 static void 522 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 523 { 524 struct pciide_channel *pc; 525 int chan, reg; 526 bus_size_t size; 527 528 sc->sc_wdcdev.dma_arg = sc; 529 sc->sc_wdcdev.dma_init = pciide_dma_init; 530 sc->sc_wdcdev.dma_start = pciide_dma_start; 531 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 532 533 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 534 PCIIDE_OPTIONS_NODMA) { 535 aprint_verbose( 536 ", but unused (forced off by config file)"); 537 sc->sc_dma_ok = 0; 538 return; 539 } 540 541 /* 542 * Slice off a subregion of BA5 for each of the channel's DMA 543 * registers. 544 */ 545 546 sc->sc_dma_iot = sc->sc_ba5_st; 547 for (chan = 0; chan < 4; chan++) { 548 pc = &sc->pciide_channels[chan]; 549 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 550 size = 4; 551 if (size > (IDEDMA_SCH_OFFSET - reg)) 552 size = IDEDMA_SCH_OFFSET - reg; 553 if (bus_space_subregion(sc->sc_ba5_st, 554 sc->sc_ba5_sh, 555 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 556 size, &pc->dma_iohs[reg]) != 0) { 557 sc->sc_dma_ok = 0; 558 aprint_verbose(", but can't subregion offset " 559 "%lu size %lu", 560 (u_long) satalink_ba5_regmap[ 561 chan].ba5_IDEDMA_CMD + reg, 562 (u_long) size); 563 return; 564 } 565 } 566 } 567 568 /* DMA registers all set up! */ 569 sc->sc_dmat = pa->pa_dmat; 570 sc->sc_dma_ok = 1; 571 } 572 573 static int 574 sii3114_chansetup(struct pciide_softc *sc, int channel) 575 { 576 static const char *channel_names[] = { 577 "port 0", 578 "port 1", 579 "port 2", 580 "port 3", 581 }; 582 struct pciide_channel *cp = &sc->pciide_channels[channel]; 583 584 sc->wdc_chanarray[channel] = &cp->ata_channel; 585 586 /* 587 * We must always keep the Interrupt Steering bit set in channel 2's 588 * IDEDMA_CMD register. 589 */ 590 if (channel == 2) 591 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 592 593 cp->name = channel_names[channel]; 594 cp->ata_channel.ch_channel = channel; 595 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 596 cp->ata_channel.ch_queue = 597 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 598 cp->ata_channel.ch_ndrive = 2; 599 if (cp->ata_channel.ch_queue == NULL) { 600 aprint_error("%s %s channel: " 601 "can't allocate memory for command queue", 602 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 603 return (0); 604 } 605 return (1); 606 } 607 608 static void 609 sii3114_mapchan(struct pciide_channel *cp) 610 { 611 struct ata_channel *wdc_cp = &cp->ata_channel; 612 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 613 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 614 int i; 615 616 cp->compat = 0; 617 cp->ih = sc->sc_pci_ih; 618 619 wdr->cmd_iot = sc->sc_ba5_st; 620 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 621 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 622 9, &wdr->cmd_baseioh) != 0) { 623 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 624 "couldn't subregion %s cmd base\n", cp->name); 625 goto bad; 626 } 627 628 wdr->ctl_iot = sc->sc_ba5_st; 629 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 630 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 631 1, &cp->ctl_baseioh) != 0) { 632 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 633 "couldn't subregion %s ctl base\n", cp->name); 634 goto bad; 635 } 636 wdr->ctl_ioh = cp->ctl_baseioh; 637 638 for (i = 0; i < WDC_NREG; i++) { 639 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 640 i, i == 0 ? 4 : 1, 641 &wdr->cmd_iohs[i]) != 0) { 642 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 643 "couldn't subregion %s channel cmd regs\n", 644 cp->name); 645 goto bad; 646 } 647 } 648 wdc_init_shadow_regs(wdc_cp); 649 wdr->data32iot = wdr->cmd_iot; 650 wdr->data32ioh = wdr->cmd_iohs[0]; 651 wdcattach(wdc_cp); 652 return; 653 654 bad: 655 cp->ata_channel.ch_flags |= ATACH_DISABLED; 656 } 657 658 static void 659 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 660 { 661 struct pciide_channel *cp; 662 pcireg_t scs_cmd; 663 pci_intr_handle_t intrhandle; 664 const char *intrstr; 665 int channel; 666 667 if (pciide_chipen(sc, pa) == 0) 668 return; 669 670 #define SII3114_RESET_BITS \ 671 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 672 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 673 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 674 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 675 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 676 677 /* 678 * Reset everything and then unblock all of the interrupts. 679 */ 680 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 681 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 682 scs_cmd | SII3114_RESET_BITS); 683 delay(50 * 1000); 684 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 685 scs_cmd & SCS_CMD_M66EN); 686 delay(50 * 1000); 687 688 /* 689 * On the 3114, the BA5 register space is always enabled. In 690 * order to use the 3114 in any sane way, we must use this BA5 691 * register space, and so we consider it an error if we cannot 692 * map it. 693 * 694 * As a consequence of using BA5, our register mapping is different 695 * from a normal PCI IDE controller's, and so we are unable to use 696 * most of the common PCI IDE register mapping functions. 697 */ 698 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 699 PCI_MAPREG_TYPE_MEM| 700 PCI_MAPREG_MEM_TYPE_32BIT, 0, 701 &sc->sc_ba5_st, &sc->sc_ba5_sh, 702 NULL, NULL) != 0) { 703 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 704 "unable to map SATALink BA5 register space\n"); 705 return; 706 } 707 sc->sc_ba5_en = 1; 708 709 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 710 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 711 712 /* 713 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 714 * channel 2. This is required at all times for proper operation 715 * when using the BA5 register space (otherwise interrupts from 716 * all 4 channels won't work). 717 */ 718 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 719 720 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 721 "bus-master DMA support present"); 722 sii3114_mapreg_dma(sc, pa); 723 aprint_verbose("\n"); 724 725 sii_fixup_cacheline(sc, pa, 4); 726 727 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 728 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 729 if (sc->sc_dma_ok) { 730 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 731 sc->sc_wdcdev.irqack = pciide_irqack; 732 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 733 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 734 } 735 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 736 737 /* We can use SControl and SStatus to probe for drives. */ 738 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 739 740 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 741 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 742 743 wdc_allocate_regs(&sc->sc_wdcdev); 744 745 /* Map and establish the interrupt handler. */ 746 if (pci_intr_map(pa, &intrhandle) != 0) { 747 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 748 "couldn't map native-PCI interrupt\n"); 749 return; 750 } 751 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 752 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 753 /* XXX */ 754 pciide_pci_intr, sc); 755 if (sc->sc_pci_ih != NULL) { 756 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 757 "using %s for native-PCI interrupt\n", 758 intrstr ? intrstr : "unknown interrupt"); 759 } else { 760 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 761 "couldn't establish native-PCI interrupt"); 762 if (intrstr != NULL) 763 aprint_error(" at %s", intrstr); 764 aprint_error("\n"); 765 return; 766 } 767 768 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 769 channel++) { 770 cp = &sc->pciide_channels[channel]; 771 if (sii3114_chansetup(sc, channel) == 0) 772 continue; 773 sii3114_mapchan(cp); 774 } 775 } 776 777 /* Probe the drives using SATA registers. 778 * Note we can't use wdc_sataprobe as we may not be able to map ba5 779 */ 780 static void 781 sii3112_drv_probe(struct ata_channel *chp) 782 { 783 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 784 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 785 uint32_t scontrol, sstatus; 786 uint8_t scnt, sn, cl, ch; 787 int i, s; 788 789 /* XXX This should be done by other code. */ 790 for (i = 0; i < 2; i++) { 791 chp->ch_drive[i].chnl_softc = chp; 792 chp->ch_drive[i].drive = i; 793 } 794 795 /* 796 * The 3112 is a 2-port part, and only has one drive per channel 797 * (each port emulates a master drive). 798 * 799 * The 3114 is similar, but has 4 channels. 800 */ 801 802 /* 803 * Request communication initialization sequence, any speed. 804 * Performing this is the equivalent of an ATA Reset. 805 */ 806 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 807 808 /* 809 * XXX We don't yet support SATA power management; disable all 810 * power management state transitions. 811 */ 812 scontrol |= SControl_IPM_NONE; 813 814 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 815 delay(50 * 1000); 816 scontrol &= ~SControl_DET_INIT; 817 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 818 delay(50 * 1000); 819 820 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 821 #if 0 822 aprint_normal_dev(&sc->sc_wdcdev.sc_atac.atac_dev, 823 "port %d: SStatus=0x%08x, SControl=0x%08x\n", 824 chp->ch_channel, sstatus, 825 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 826 #endif 827 switch (sstatus & SStatus_DET_mask) { 828 case SStatus_DET_NODEV: 829 /* No device; be silent. */ 830 break; 831 832 case SStatus_DET_DEV_NE: 833 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 834 "port %d: device connected, but " 835 "communication not established\n", chp->ch_channel); 836 break; 837 838 case SStatus_DET_OFFLINE: 839 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 840 "port %d: PHY offline\n", chp->ch_channel); 841 break; 842 843 case SStatus_DET_DEV: 844 /* 845 * XXX ATAPI detection doesn't currently work. Don't 846 * XXX know why. But, it's not like the standard method 847 * XXX can detect an ATAPI device connected via a SATA/PATA 848 * XXX bridge, so at least this is no worse. --thorpej 849 */ 850 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 851 WDSD_IBM | (0 << 4)); 852 delay(10); /* 400ns delay */ 853 /* Save register contents. */ 854 scnt = bus_space_read_1(wdr->cmd_iot, 855 wdr->cmd_iohs[wd_seccnt], 0); 856 sn = bus_space_read_1(wdr->cmd_iot, 857 wdr->cmd_iohs[wd_sector], 0); 858 cl = bus_space_read_1(wdr->cmd_iot, 859 wdr->cmd_iohs[wd_cyl_lo], 0); 860 ch = bus_space_read_1(wdr->cmd_iot, 861 wdr->cmd_iohs[wd_cyl_hi], 0); 862 #if 0 863 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 864 device_xname(&sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel, 865 scnt, sn, cl, ch); 866 #endif 867 /* 868 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 869 * cases we get wrong values here, so ignore it. 870 */ 871 s = splbio(); 872 if (cl == 0x14 && ch == 0xeb) 873 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 874 else 875 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 876 splx(s); 877 878 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 879 "port %d: device present, speed: %s\n", 880 chp->ch_channel, 881 sata_speed(sstatus)); 882 break; 883 884 default: 885 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 886 "port %d: unknown SStatus: 0x%08x\n", 887 chp->ch_channel, sstatus); 888 } 889 } 890 891 static void 892 sii3112_setup_channel(struct ata_channel *chp) 893 { 894 struct ata_drive_datas *drvp; 895 int drive, s; 896 u_int32_t idedma_ctl, dtm; 897 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 898 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 899 900 /* setup DMA if needed */ 901 pciide_channel_dma_setup(cp); 902 903 idedma_ctl = 0; 904 dtm = 0; 905 906 for (drive = 0; drive < 2; drive++) { 907 drvp = &chp->ch_drive[drive]; 908 /* If no drive, skip */ 909 if ((drvp->drive_flags & DRIVE) == 0) 910 continue; 911 if (drvp->drive_flags & DRIVE_UDMA) { 912 /* use Ultra/DMA */ 913 s = splbio(); 914 drvp->drive_flags &= ~DRIVE_DMA; 915 splx(s); 916 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 917 dtm |= DTM_IDEx_DMA; 918 } else if (drvp->drive_flags & DRIVE_DMA) { 919 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 920 dtm |= DTM_IDEx_DMA; 921 } else { 922 dtm |= DTM_IDEx_PIO; 923 } 924 } 925 926 /* 927 * Nothing to do to setup modes; it is meaningless in S-ATA 928 * (but many S-ATA drives still want to get the SET_FEATURE 929 * command). 930 */ 931 if (idedma_ctl != 0) { 932 /* Add software bits in status register */ 933 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 934 idedma_ctl); 935 } 936 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 937 } 938
Indexes created Mon Sep 29 18:09:42 GMT 2025