satalink.c revision 1.48
1 /* $NetBSD: satalink.c,v 1.48 2012/07/31 15:50:36 bouyer Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: satalink.c,v 1.48 2012/07/31 15:50:36 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/malloc.h> 38 39 #include <dev/pci/pcivar.h> 40 #include <dev/pci/pcidevs.h> 41 #include <dev/pci/pciidereg.h> 42 #include <dev/pci/pciidevar.h> 43 #include <dev/pci/pciide_sii3112_reg.h> 44 45 #include <dev/ata/satareg.h> 46 #include <dev/ata/satavar.h> 47 #include <dev/ata/atareg.h> 48 49 /* 50 * Register map for BA5 register space, indexed by channel. 51 */ 52 static const struct { 53 bus_addr_t ba5_IDEDMA_CMD; 54 bus_addr_t ba5_IDEDMA_CTL; 55 bus_addr_t ba5_IDEDMA_TBL; 56 bus_addr_t ba5_IDEDMA_CMD2; 57 bus_addr_t ba5_IDEDMA_CTL2; 58 bus_addr_t ba5_IDE_TF0; 59 bus_addr_t ba5_IDE_TF1; 60 bus_addr_t ba5_IDE_TF2; 61 bus_addr_t ba5_IDE_TF3; 62 bus_addr_t ba5_IDE_TF4; 63 bus_addr_t ba5_IDE_TF5; 64 bus_addr_t ba5_IDE_TF6; 65 bus_addr_t ba5_IDE_TF7; 66 bus_addr_t ba5_IDE_TF8; 67 bus_addr_t ba5_IDE_RAD; 68 bus_addr_t ba5_IDE_TF9; 69 bus_addr_t ba5_IDE_TF10; 70 bus_addr_t ba5_IDE_TF11; 71 bus_addr_t ba5_IDE_TF12; 72 bus_addr_t ba5_IDE_TF13; 73 bus_addr_t ba5_IDE_TF14; 74 bus_addr_t ba5_IDE_TF15; 75 bus_addr_t ba5_IDE_TF16; 76 bus_addr_t ba5_IDE_TF17; 77 bus_addr_t ba5_IDE_TF18; 78 bus_addr_t ba5_IDE_TF19; 79 bus_addr_t ba5_IDE_RABC; 80 bus_addr_t ba5_IDE_CMD_STS; 81 bus_addr_t ba5_IDE_CFG_STS; 82 bus_addr_t ba5_IDE_DTM; 83 bus_addr_t ba5_SControl; 84 bus_addr_t ba5_SStatus; 85 bus_addr_t ba5_SError; 86 bus_addr_t ba5_SActive; /* 3114 */ 87 bus_addr_t ba5_SMisc; 88 bus_addr_t ba5_PHY_CONFIG; 89 bus_addr_t ba5_SIEN; 90 bus_addr_t ba5_SFISCfg; 91 } satalink_ba5_regmap[] = { 92 { /* Channel 0 */ 93 .ba5_IDEDMA_CMD = 0x000, 94 .ba5_IDEDMA_CTL = 0x002, 95 .ba5_IDEDMA_TBL = 0x004, 96 .ba5_IDEDMA_CMD2 = 0x010, 97 .ba5_IDEDMA_CTL2 = 0x012, 98 .ba5_IDE_TF0 = 0x080, /* wd_data */ 99 .ba5_IDE_TF1 = 0x081, /* wd_error */ 100 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 101 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 102 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 103 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 104 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 105 .ba5_IDE_TF7 = 0x087, /* wd_command */ 106 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 107 .ba5_IDE_RAD = 0x08c, 108 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 109 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 110 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 111 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 112 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 113 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 114 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 115 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 116 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 117 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 118 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 119 .ba5_IDE_RABC = 0x09c, 120 .ba5_IDE_CMD_STS = 0x0a0, 121 .ba5_IDE_CFG_STS = 0x0a1, 122 .ba5_IDE_DTM = 0x0b4, 123 .ba5_SControl = 0x100, 124 .ba5_SStatus = 0x104, 125 .ba5_SError = 0x108, 126 .ba5_SActive = 0x10c, 127 .ba5_SMisc = 0x140, 128 .ba5_PHY_CONFIG = 0x144, 129 .ba5_SIEN = 0x148, 130 .ba5_SFISCfg = 0x14c, 131 }, 132 { /* Channel 1 */ 133 .ba5_IDEDMA_CMD = 0x008, 134 .ba5_IDEDMA_CTL = 0x00a, 135 .ba5_IDEDMA_TBL = 0x00c, 136 .ba5_IDEDMA_CMD2 = 0x018, 137 .ba5_IDEDMA_CTL2 = 0x01a, 138 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 139 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 140 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 141 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 142 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 143 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 144 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 145 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 146 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 147 .ba5_IDE_RAD = 0x0cc, 148 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 149 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 150 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 151 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 152 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 153 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 154 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 155 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 156 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 157 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 158 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 159 .ba5_IDE_RABC = 0x0dc, 160 .ba5_IDE_CMD_STS = 0x0e0, 161 .ba5_IDE_CFG_STS = 0x0e1, 162 .ba5_IDE_DTM = 0x0f4, 163 .ba5_SControl = 0x180, 164 .ba5_SStatus = 0x184, 165 .ba5_SError = 0x188, 166 .ba5_SActive = 0x18c, 167 .ba5_SMisc = 0x1c0, 168 .ba5_PHY_CONFIG = 0x1c4, 169 .ba5_SIEN = 0x1c8, 170 .ba5_SFISCfg = 0x1cc, 171 }, 172 { /* Channel 2 (3114) */ 173 .ba5_IDEDMA_CMD = 0x200, 174 .ba5_IDEDMA_CTL = 0x202, 175 .ba5_IDEDMA_TBL = 0x204, 176 .ba5_IDEDMA_CMD2 = 0x210, 177 .ba5_IDEDMA_CTL2 = 0x212, 178 .ba5_IDE_TF0 = 0x280, /* wd_data */ 179 .ba5_IDE_TF1 = 0x281, /* wd_error */ 180 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 181 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 182 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 183 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 184 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 185 .ba5_IDE_TF7 = 0x287, /* wd_command */ 186 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 187 .ba5_IDE_RAD = 0x28c, 188 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 189 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 190 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 191 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 192 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 193 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 194 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 195 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 196 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 197 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 198 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 199 .ba5_IDE_RABC = 0x29c, 200 .ba5_IDE_CMD_STS = 0x2a0, 201 .ba5_IDE_CFG_STS = 0x2a1, 202 .ba5_IDE_DTM = 0x2b4, 203 .ba5_SControl = 0x300, 204 .ba5_SStatus = 0x304, 205 .ba5_SError = 0x308, 206 .ba5_SActive = 0x30c, 207 .ba5_SMisc = 0x340, 208 .ba5_PHY_CONFIG = 0x344, 209 .ba5_SIEN = 0x348, 210 .ba5_SFISCfg = 0x34c, 211 }, 212 { /* Channel 3 (3114) */ 213 .ba5_IDEDMA_CMD = 0x208, 214 .ba5_IDEDMA_CTL = 0x20a, 215 .ba5_IDEDMA_TBL = 0x20c, 216 .ba5_IDEDMA_CMD2 = 0x218, 217 .ba5_IDEDMA_CTL2 = 0x21a, 218 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 219 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 220 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 221 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 222 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 223 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 224 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 225 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 226 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 227 .ba5_IDE_RAD = 0x2cc, 228 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 229 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 230 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 231 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 232 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 233 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 234 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 235 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 236 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 237 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 238 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 239 .ba5_IDE_RABC = 0x2dc, 240 .ba5_IDE_CMD_STS = 0x2e0, 241 .ba5_IDE_CFG_STS = 0x2e1, 242 .ba5_IDE_DTM = 0x2f4, 243 .ba5_SControl = 0x380, 244 .ba5_SStatus = 0x384, 245 .ba5_SError = 0x388, 246 .ba5_SActive = 0x38c, 247 .ba5_SMisc = 0x3c0, 248 .ba5_PHY_CONFIG = 0x3c4, 249 .ba5_SIEN = 0x3c8, 250 .ba5_SFISCfg = 0x3cc, 251 }, 252 }; 253 254 #define ba5_SIS 0x214 /* summary interrupt status */ 255 256 /* Interrupt steering bit in BA5[0x200]. */ 257 #define IDEDMA_CMD_INT_STEER (1U << 1) 258 259 static int satalink_match(device_t, cfdata_t, void *); 260 static void satalink_attach(device_t, device_t, void *); 261 262 CFATTACH_DECL_NEW(satalink, sizeof(struct pciide_softc), 263 satalink_match, satalink_attach, NULL, NULL); 264 265 static void sii3112_chip_map(struct pciide_softc*, 266 const struct pci_attach_args*); 267 static void sii3114_chip_map(struct pciide_softc*, 268 const struct pci_attach_args*); 269 static void sii3112_drv_probe(struct ata_channel*); 270 static void sii3112_setup_channel(struct ata_channel*); 271 272 static const struct pciide_product_desc pciide_satalink_products[] = { 273 { PCI_PRODUCT_CMDTECH_3112, 274 0, 275 "Silicon Image SATALink 3112", 276 sii3112_chip_map, 277 }, 278 { PCI_PRODUCT_CMDTECH_240, 279 0, 280 "Silicon Image SATALink Sil240", 281 sii3112_chip_map, 282 }, 283 { PCI_PRODUCT_CMDTECH_3512, 284 0, 285 "Silicon Image SATALink 3512", 286 sii3112_chip_map, 287 }, 288 { PCI_PRODUCT_CMDTECH_AAR_1210SA, 289 0, 290 "Adaptec AAR-1210SA serial ATA RAID controller", 291 sii3112_chip_map, 292 }, 293 { PCI_PRODUCT_CMDTECH_3114, 294 0, 295 "Silicon Image SATALink 3114", 296 sii3114_chip_map, 297 }, 298 { PCI_PRODUCT_ATI_IXP_SATA_300, 299 0, 300 "ATI IXP 300 SATA", 301 sii3112_chip_map, 302 }, 303 { 0, 304 0, 305 NULL, 306 NULL 307 } 308 }; 309 310 static int 311 satalink_match(device_t parent, cfdata_t match, void *aux) 312 { 313 struct pci_attach_args *pa = aux; 314 315 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 316 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 317 return (2); 318 } 319 return (0); 320 } 321 322 static void 323 satalink_attach(device_t parent, device_t self, void *aux) 324 { 325 struct pci_attach_args *pa = aux; 326 struct pciide_softc *sc = device_private(self); 327 328 sc->sc_wdcdev.sc_atac.atac_dev = self; 329 330 pciide_common_attach(sc, pa, 331 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 332 333 } 334 335 static inline uint32_t 336 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 337 { 338 uint32_t rv; 339 int s; 340 341 s = splbio(); 342 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 343 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 344 splx(s); 345 346 return (rv); 347 } 348 349 static inline uint32_t 350 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 351 { 352 353 if (__predict_true(sc->sc_ba5_en != 0)) 354 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 355 356 return (ba5_read_4_ind(sc, reg)); 357 } 358 359 #define BA5_READ_4(sc, chan, reg) \ 360 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 361 362 static inline void 363 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 364 { 365 int s; 366 367 s = splbio(); 368 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 369 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 370 splx(s); 371 } 372 373 static inline void 374 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 375 { 376 377 if (__predict_true(sc->sc_ba5_en != 0)) 378 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 379 else 380 ba5_write_4_ind(sc, reg, val); 381 } 382 383 #define BA5_WRITE_4(sc, chan, reg, val) \ 384 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 385 386 /* 387 * When the Silicon Image 3112 retries a PCI memory read command, 388 * it may retry it as a memory read multiple command under some 389 * circumstances. This can totally confuse some PCI controllers, 390 * so ensure that it will never do this by making sure that the 391 * Read Threshold (FIFO Read Request Control) field of the FIFO 392 * Valid Byte Count and Control registers for both channels (BA5 393 * offset 0x40 and 0x44) are set to be at least as large as the 394 * cacheline size register. 395 * This may also happen on the 3114 (ragge 050527) 396 */ 397 static void 398 sii_fixup_cacheline(struct pciide_softc *sc, const struct pci_attach_args *pa, 399 int n) 400 { 401 pcireg_t cls, reg; 402 int i; 403 static bus_addr_t addr[] = { 0x40, 0x44, 0x240, 0x244 }; 404 405 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 406 cls = (cls >> PCI_CACHELINE_SHIFT) & PCI_CACHELINE_MASK; 407 cls *= 4; 408 if (cls > 224) { 409 cls = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 410 cls &= ~(PCI_CACHELINE_MASK << PCI_CACHELINE_SHIFT); 411 cls |= ((224/4) << PCI_CACHELINE_SHIFT); 412 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG, cls); 413 cls = 224; 414 } 415 if (cls < 32) 416 cls = 32; 417 cls = (cls + 31) / 32; 418 for (i = 0; i < n; i++) { 419 reg = ba5_read_4(sc, addr[i]); 420 if ((reg & 0x7) < cls) 421 ba5_write_4(sc, addr[i], (reg & 0x07) | cls); 422 } 423 } 424 425 static void 426 sii3112_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 427 { 428 struct pciide_channel *cp; 429 pcireg_t interface, scs_cmd, cfgctl; 430 int channel; 431 432 if (pciide_chipen(sc, pa) == 0) 433 return; 434 435 #define SII3112_RESET_BITS \ 436 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 437 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 438 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 439 440 /* 441 * Reset everything and then unblock all of the interrupts. 442 */ 443 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 444 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 445 scs_cmd | SII3112_RESET_BITS); 446 delay(50 * 1000); 447 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 448 scs_cmd & SCS_CMD_BA5_EN); 449 delay(50 * 1000); 450 451 if (scs_cmd & SCS_CMD_BA5_EN) { 452 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 453 "SATALink BA5 register space enabled\n"); 454 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 455 PCI_MAPREG_TYPE_MEM| 456 PCI_MAPREG_MEM_TYPE_32BIT, 0, 457 &sc->sc_ba5_st, &sc->sc_ba5_sh, 458 NULL, &sc->sc_ba5_ss) != 0) 459 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 460 "unable to map SATALink BA5 register space\n"); 461 else 462 sc->sc_ba5_en = 1; 463 } else { 464 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 465 "SATALink BA5 register space disabled\n"); 466 467 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 468 SII3112_PCI_CFGCTL); 469 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 470 cfgctl | CFGCTL_BA5INDEN); 471 } 472 473 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 474 "bus-master DMA support present"); 475 pciide_mapreg_dma(sc, pa); 476 aprint_verbose("\n"); 477 478 /* 479 * Rev. <= 0x01 of the 3112 have a bug that can cause data 480 * corruption if DMA transfers cross an 8K boundary. This is 481 * apparently hard to tickle, but we'll go ahead and play it 482 * safe. 483 */ 484 if ((PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_3112 || 485 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_CMDTECH_AAR_1210SA) && 486 PCI_REVISION(pa->pa_class) <= 0x01) { 487 sc->sc_dma_maxsegsz = 8192; 488 sc->sc_dma_boundary = 8192; 489 } 490 491 sii_fixup_cacheline(sc, pa, 2); 492 493 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 494 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 495 if (sc->sc_dma_ok) { 496 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 497 sc->sc_wdcdev.irqack = pciide_irqack; 498 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 499 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 500 } 501 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 502 503 /* We can use SControl and SStatus to probe for drives. */ 504 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 505 506 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 507 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 508 sc->sc_wdcdev.wdc_maxdrives = 1; 509 510 wdc_allocate_regs(&sc->sc_wdcdev); 511 512 /* 513 * The 3112 either identifies itself as a RAID storage device 514 * or a Misc storage device. Fake up the interface bits for 515 * what our driver expects. 516 */ 517 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 518 interface = PCI_INTERFACE(pa->pa_class); 519 } else { 520 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 521 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 522 } 523 524 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 525 channel++) { 526 cp = &sc->pciide_channels[channel]; 527 if (pciide_chansetup(sc, channel, interface) == 0) 528 continue; 529 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 530 } 531 } 532 533 static void 534 sii3114_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 535 { 536 struct pciide_channel *pc; 537 int chan, reg; 538 bus_size_t size; 539 540 sc->sc_wdcdev.dma_arg = sc; 541 sc->sc_wdcdev.dma_init = pciide_dma_init; 542 sc->sc_wdcdev.dma_start = pciide_dma_start; 543 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 544 545 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 546 PCIIDE_OPTIONS_NODMA) { 547 aprint_verbose( 548 ", but unused (forced off by config file)"); 549 sc->sc_dma_ok = 0; 550 return; 551 } 552 553 /* 554 * Slice off a subregion of BA5 for each of the channel's DMA 555 * registers. 556 */ 557 558 sc->sc_dma_iot = sc->sc_ba5_st; 559 for (chan = 0; chan < 4; chan++) { 560 pc = &sc->pciide_channels[chan]; 561 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 562 size = 4; 563 if (size > (IDEDMA_SCH_OFFSET - reg)) 564 size = IDEDMA_SCH_OFFSET - reg; 565 if (bus_space_subregion(sc->sc_ba5_st, 566 sc->sc_ba5_sh, 567 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 568 size, &pc->dma_iohs[reg]) != 0) { 569 sc->sc_dma_ok = 0; 570 aprint_verbose(", but can't subregion offset " 571 "%lu size %lu", 572 (u_long) satalink_ba5_regmap[ 573 chan].ba5_IDEDMA_CMD + reg, 574 (u_long) size); 575 return; 576 } 577 } 578 } 579 580 /* DMA registers all set up! */ 581 sc->sc_dmat = pa->pa_dmat; 582 sc->sc_dma_ok = 1; 583 } 584 585 static int 586 sii3114_chansetup(struct pciide_softc *sc, int channel) 587 { 588 static const char *channel_names[] = { 589 "port 0", 590 "port 1", 591 "port 2", 592 "port 3", 593 }; 594 struct pciide_channel *cp = &sc->pciide_channels[channel]; 595 596 sc->wdc_chanarray[channel] = &cp->ata_channel; 597 598 /* 599 * We must always keep the Interrupt Steering bit set in channel 2's 600 * IDEDMA_CMD register. 601 */ 602 if (channel == 2) 603 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 604 605 cp->name = channel_names[channel]; 606 cp->ata_channel.ch_channel = channel; 607 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac; 608 cp->ata_channel.ch_queue = 609 malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT); 610 if (cp->ata_channel.ch_queue == NULL) { 611 aprint_error("%s %s channel: " 612 "can't allocate memory for command queue", 613 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name); 614 return (0); 615 } 616 return (1); 617 } 618 619 static void 620 sii3114_mapchan(struct pciide_channel *cp) 621 { 622 struct ata_channel *wdc_cp = &cp->ata_channel; 623 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 624 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 625 int i; 626 627 cp->compat = 0; 628 cp->ih = sc->sc_pci_ih; 629 630 wdr->cmd_iot = sc->sc_ba5_st; 631 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 632 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF0, 633 9, &wdr->cmd_baseioh) != 0) { 634 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 635 "couldn't subregion %s cmd base\n", cp->name); 636 goto bad; 637 } 638 639 wdr->ctl_iot = sc->sc_ba5_st; 640 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 641 satalink_ba5_regmap[wdc_cp->ch_channel].ba5_IDE_TF8, 642 1, &cp->ctl_baseioh) != 0) { 643 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 644 "couldn't subregion %s ctl base\n", cp->name); 645 goto bad; 646 } 647 wdr->ctl_ioh = cp->ctl_baseioh; 648 649 for (i = 0; i < WDC_NREG; i++) { 650 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 651 i, i == 0 ? 4 : 1, 652 &wdr->cmd_iohs[i]) != 0) { 653 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 654 "couldn't subregion %s channel cmd regs\n", 655 cp->name); 656 goto bad; 657 } 658 } 659 wdc_init_shadow_regs(wdc_cp); 660 wdr->data32iot = wdr->cmd_iot; 661 wdr->data32ioh = wdr->cmd_iohs[0]; 662 wdcattach(wdc_cp); 663 return; 664 665 bad: 666 cp->ata_channel.ch_flags |= ATACH_DISABLED; 667 } 668 669 static void 670 sii3114_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 671 { 672 struct pciide_channel *cp; 673 pcireg_t scs_cmd; 674 pci_intr_handle_t intrhandle; 675 const char *intrstr; 676 int channel; 677 678 if (pciide_chipen(sc, pa) == 0) 679 return; 680 681 #define SII3114_RESET_BITS \ 682 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 683 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 684 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 685 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 686 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 687 688 /* 689 * Reset everything and then unblock all of the interrupts. 690 */ 691 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 692 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 693 scs_cmd | SII3114_RESET_BITS); 694 delay(50 * 1000); 695 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 696 scs_cmd & SCS_CMD_M66EN); 697 delay(50 * 1000); 698 699 /* 700 * On the 3114, the BA5 register space is always enabled. In 701 * order to use the 3114 in any sane way, we must use this BA5 702 * register space, and so we consider it an error if we cannot 703 * map it. 704 * 705 * As a consequence of using BA5, our register mapping is different 706 * from a normal PCI IDE controller's, and so we are unable to use 707 * most of the common PCI IDE register mapping functions. 708 */ 709 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 710 PCI_MAPREG_TYPE_MEM| 711 PCI_MAPREG_MEM_TYPE_32BIT, 0, 712 &sc->sc_ba5_st, &sc->sc_ba5_sh, 713 NULL, &sc->sc_ba5_ss) != 0) { 714 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 715 "unable to map SATALink BA5 register space\n"); 716 return; 717 } 718 sc->sc_ba5_en = 1; 719 720 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 721 "%dMHz PCI bus\n", (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 722 723 /* 724 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 725 * channel 2. This is required at all times for proper operation 726 * when using the BA5 register space (otherwise interrupts from 727 * all 4 channels won't work). 728 */ 729 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 730 731 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 732 "bus-master DMA support present"); 733 sii3114_mapreg_dma(sc, pa); 734 aprint_verbose("\n"); 735 736 sii_fixup_cacheline(sc, pa, 4); 737 738 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 739 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 740 if (sc->sc_dma_ok) { 741 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 742 sc->sc_wdcdev.irqack = pciide_irqack; 743 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 744 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 745 } 746 sc->sc_wdcdev.sc_atac.atac_set_modes = sii3112_setup_channel; 747 748 /* We can use SControl and SStatus to probe for drives. */ 749 sc->sc_wdcdev.sc_atac.atac_probe = sii3112_drv_probe; 750 751 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 752 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 753 sc->sc_wdcdev.wdc_maxdrives = 1; 754 755 wdc_allocate_regs(&sc->sc_wdcdev); 756 757 /* Map and establish the interrupt handler. */ 758 if (pci_intr_map(pa, &intrhandle) != 0) { 759 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 760 "couldn't map native-PCI interrupt\n"); 761 return; 762 } 763 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 764 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 765 /* XXX */ 766 pciide_pci_intr, sc); 767 if (sc->sc_pci_ih != NULL) { 768 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 769 "using %s for native-PCI interrupt\n", 770 intrstr ? intrstr : "unknown interrupt"); 771 } else { 772 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 773 "couldn't establish native-PCI interrupt"); 774 if (intrstr != NULL) 775 aprint_error(" at %s", intrstr); 776 aprint_error("\n"); 777 return; 778 } 779 780 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 781 channel++) { 782 cp = &sc->pciide_channels[channel]; 783 if (sii3114_chansetup(sc, channel) == 0) 784 continue; 785 sii3114_mapchan(cp); 786 } 787 } 788 789 /* Probe the drives using SATA registers. 790 * Note we can't use wdc_sataprobe as we may not be able to map ba5 791 */ 792 static void 793 sii3112_drv_probe(struct ata_channel *chp) 794 { 795 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 796 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 797 uint32_t scontrol, sstatus; 798 uint8_t scnt, sn, cl, ch; 799 int s; 800 801 /* 802 * The 3112 is a 2-port part, and only has one drive per channel 803 * (each port emulates a master drive). 804 * 805 * The 3114 is similar, but has 4 channels. 806 */ 807 808 /* 809 * Request communication initialization sequence, any speed. 810 * Performing this is the equivalent of an ATA Reset. 811 */ 812 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 813 814 /* 815 * XXX We don't yet support SATA power management; disable all 816 * power management state transitions. 817 */ 818 scontrol |= SControl_IPM_NONE; 819 820 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 821 delay(50 * 1000); 822 scontrol &= ~SControl_DET_INIT; 823 BA5_WRITE_4(sc, chp->ch_channel, ba5_SControl, scontrol); 824 delay(50 * 1000); 825 826 sstatus = BA5_READ_4(sc, chp->ch_channel, ba5_SStatus); 827 #if 0 828 aprint_normal_dev(&sc->sc_wdcdev.sc_atac.atac_dev, 829 "port %d: SStatus=0x%08x, SControl=0x%08x\n", 830 chp->ch_channel, sstatus, 831 BA5_READ_4(sc, chp->ch_channel, ba5_SControl)); 832 #endif 833 switch (sstatus & SStatus_DET_mask) { 834 case SStatus_DET_NODEV: 835 /* No device; be silent. */ 836 break; 837 838 case SStatus_DET_DEV_NE: 839 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 840 "port %d: device connected, but " 841 "communication not established\n", chp->ch_channel); 842 break; 843 844 case SStatus_DET_OFFLINE: 845 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 846 "port %d: PHY offline\n", chp->ch_channel); 847 break; 848 849 case SStatus_DET_DEV: 850 /* 851 * XXX ATAPI detection doesn't currently work. Don't 852 * XXX know why. But, it's not like the standard method 853 * XXX can detect an ATAPI device connected via a SATA/PATA 854 * XXX bridge, so at least this is no worse. --thorpej 855 */ 856 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 857 WDSD_IBM | (0 << 4)); 858 delay(10); /* 400ns delay */ 859 /* Save register contents. */ 860 scnt = bus_space_read_1(wdr->cmd_iot, 861 wdr->cmd_iohs[wd_seccnt], 0); 862 sn = bus_space_read_1(wdr->cmd_iot, 863 wdr->cmd_iohs[wd_sector], 0); 864 cl = bus_space_read_1(wdr->cmd_iot, 865 wdr->cmd_iohs[wd_cyl_lo], 0); 866 ch = bus_space_read_1(wdr->cmd_iot, 867 wdr->cmd_iohs[wd_cyl_hi], 0); 868 #if 0 869 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 870 device_xname(&sc->sc_wdcdev.sc_atac.atac_dev), chp->ch_channel, 871 scnt, sn, cl, ch); 872 #endif 873 if (atabus_alloc_drives(chp, 1) != 0) 874 return; 875 /* 876 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 877 * cases we get wrong values here, so ignore it. 878 */ 879 s = splbio(); 880 if (cl == 0x14 && ch == 0xeb) 881 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 882 else 883 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 884 splx(s); 885 886 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 887 "port %d: device present, speed: %s\n", 888 chp->ch_channel, 889 sata_speed(sstatus)); 890 break; 891 892 default: 893 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 894 "port %d: unknown SStatus: 0x%08x\n", 895 chp->ch_channel, sstatus); 896 } 897 } 898 899 static void 900 sii3112_setup_channel(struct ata_channel *chp) 901 { 902 struct ata_drive_datas *drvp; 903 int drive, s; 904 u_int32_t idedma_ctl, dtm; 905 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 906 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 907 908 /* setup DMA if needed */ 909 pciide_channel_dma_setup(cp); 910 911 idedma_ctl = 0; 912 dtm = 0; 913 914 for (drive = 0; drive < 2; drive++) { 915 drvp = &chp->ch_drive[drive]; 916 /* If no drive, skip */ 917 if (drvp->drive_type == ATA_DRIVET_NONE) 918 continue; 919 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 920 /* use Ultra/DMA */ 921 s = splbio(); 922 drvp->drive_flags &= ~ATA_DRIVE_DMA; 923 splx(s); 924 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 925 dtm |= DTM_IDEx_DMA; 926 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 927 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 928 dtm |= DTM_IDEx_DMA; 929 } else { 930 dtm |= DTM_IDEx_PIO; 931 } 932 } 933 934 /* 935 * Nothing to do to setup modes; it is meaningless in S-ATA 936 * (but many S-ATA drives still want to get the SET_FEATURE 937 * command). 938 */ 939 if (idedma_ctl != 0) { 940 /* Add software bits in status register */ 941 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 942 idedma_ctl); 943 } 944 BA5_WRITE_4(sc, chp->ch_channel, ba5_IDE_DTM, dtm); 945 } 946
Indexes created Mon Sep 29 18:09:42 GMT 2025