satalink.c revision 1.5
1 /* $NetBSD: satalink.c,v 1.5 2003/12/20 03:51:27 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2003 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of Wasabi Systems, Inc. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/malloc.h> 42 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/pciidereg.h> 46 #include <dev/pci/pciidevar.h> 47 #include <dev/pci/pciide_sii3112_reg.h> 48 49 #include <dev/ata/satareg.h> 50 51 /* 52 * Register map for BA5 register space, indexed by channel. 53 */ 54 static const struct { 55 bus_addr_t ba5_IDEDMA_CMD; 56 bus_addr_t ba5_IDEDMA_CTL; 57 bus_addr_t ba5_IDEDMA_TBL; 58 bus_addr_t ba5_IDEDMA_CMD2; 59 bus_addr_t ba5_IDEDMA_CTL2; 60 bus_addr_t ba5_IDE_TF0; 61 bus_addr_t ba5_IDE_TF1; 62 bus_addr_t ba5_IDE_TF2; 63 bus_addr_t ba5_IDE_TF3; 64 bus_addr_t ba5_IDE_TF4; 65 bus_addr_t ba5_IDE_TF5; 66 bus_addr_t ba5_IDE_TF6; 67 bus_addr_t ba5_IDE_TF7; 68 bus_addr_t ba5_IDE_TF8; 69 bus_addr_t ba5_IDE_RAD; 70 bus_addr_t ba5_IDE_TF9; 71 bus_addr_t ba5_IDE_TF10; 72 bus_addr_t ba5_IDE_TF11; 73 bus_addr_t ba5_IDE_TF12; 74 bus_addr_t ba5_IDE_TF13; 75 bus_addr_t ba5_IDE_TF14; 76 bus_addr_t ba5_IDE_TF15; 77 bus_addr_t ba5_IDE_TF16; 78 bus_addr_t ba5_IDE_TF17; 79 bus_addr_t ba5_IDE_TF18; 80 bus_addr_t ba5_IDE_TF19; 81 bus_addr_t ba5_IDE_RABC; 82 bus_addr_t ba5_IDE_CMD_STS; 83 bus_addr_t ba5_IDE_CFG_STS; 84 bus_addr_t ba5_IDE_DTM; 85 bus_addr_t ba5_SControl; 86 bus_addr_t ba5_SStatus; 87 bus_addr_t ba5_SError; 88 bus_addr_t ba5_SActive; /* 3114 */ 89 bus_addr_t ba5_SMisc; 90 bus_addr_t ba5_PHY_CONFIG; 91 bus_addr_t ba5_SIEN; 92 bus_addr_t ba5_SFISCfg; 93 } satalink_ba5_regmap[] = { 94 { /* Channel 0 */ 95 .ba5_IDEDMA_CMD = 0x000, 96 .ba5_IDEDMA_CTL = 0x002, 97 .ba5_IDEDMA_TBL = 0x004, 98 .ba5_IDEDMA_CMD2 = 0x010, 99 .ba5_IDEDMA_CTL2 = 0x012, 100 .ba5_IDE_TF0 = 0x080, /* wd_data */ 101 .ba5_IDE_TF1 = 0x081, /* wd_error */ 102 .ba5_IDE_TF2 = 0x082, /* wd_seccnt */ 103 .ba5_IDE_TF3 = 0x083, /* wd_sector */ 104 .ba5_IDE_TF4 = 0x084, /* wd_cyl_lo */ 105 .ba5_IDE_TF5 = 0x085, /* wd_cyl_hi */ 106 .ba5_IDE_TF6 = 0x086, /* wd_sdh */ 107 .ba5_IDE_TF7 = 0x087, /* wd_command */ 108 .ba5_IDE_TF8 = 0x08a, /* wd_altsts */ 109 .ba5_IDE_RAD = 0x08c, 110 .ba5_IDE_TF9 = 0x091, /* Features 2 */ 111 .ba5_IDE_TF10 = 0x092, /* Sector Count 2 */ 112 .ba5_IDE_TF11 = 0x093, /* Start Sector 2 */ 113 .ba5_IDE_TF12 = 0x094, /* Cylinder Low 2 */ 114 .ba5_IDE_TF13 = 0x095, /* Cylinder High 2 */ 115 .ba5_IDE_TF14 = 0x096, /* Device/Head 2 */ 116 .ba5_IDE_TF15 = 0x097, /* Cmd Sts 2 */ 117 .ba5_IDE_TF16 = 0x098, /* Sector Count 2 ext */ 118 .ba5_IDE_TF17 = 0x099, /* Start Sector 2 ext */ 119 .ba5_IDE_TF18 = 0x09a, /* Cyl Low 2 ext */ 120 .ba5_IDE_TF19 = 0x09b, /* Cyl High 2 ext */ 121 .ba5_IDE_RABC = 0x09c, 122 .ba5_IDE_CMD_STS = 0x0a0, 123 .ba5_IDE_CFG_STS = 0x0a1, 124 .ba5_IDE_DTM = 0x0b4, 125 .ba5_SControl = 0x100, 126 .ba5_SStatus = 0x104, 127 .ba5_SError = 0x108, 128 .ba5_SActive = 0x10c, 129 .ba5_SMisc = 0x140, 130 .ba5_PHY_CONFIG = 0x144, 131 .ba5_SIEN = 0x148, 132 .ba5_SFISCfg = 0x14c, 133 }, 134 { /* Channel 1 */ 135 .ba5_IDEDMA_CMD = 0x008, 136 .ba5_IDEDMA_CTL = 0x00a, 137 .ba5_IDEDMA_TBL = 0x00c, 138 .ba5_IDEDMA_CMD2 = 0x018, 139 .ba5_IDEDMA_CTL2 = 0x01a, 140 .ba5_IDE_TF0 = 0x0c0, /* wd_data */ 141 .ba5_IDE_TF1 = 0x0c1, /* wd_error */ 142 .ba5_IDE_TF2 = 0x0c2, /* wd_seccnt */ 143 .ba5_IDE_TF3 = 0x0c3, /* wd_sector */ 144 .ba5_IDE_TF4 = 0x0c4, /* wd_cyl_lo */ 145 .ba5_IDE_TF5 = 0x0c5, /* wd_cyl_hi */ 146 .ba5_IDE_TF6 = 0x0c6, /* wd_sdh */ 147 .ba5_IDE_TF7 = 0x0c7, /* wd_command */ 148 .ba5_IDE_TF8 = 0x0ca, /* wd_altsts */ 149 .ba5_IDE_RAD = 0x0cc, 150 .ba5_IDE_TF9 = 0x0d1, /* Features 2 */ 151 .ba5_IDE_TF10 = 0x0d2, /* Sector Count 2 */ 152 .ba5_IDE_TF11 = 0x0d3, /* Start Sector 2 */ 153 .ba5_IDE_TF12 = 0x0d4, /* Cylinder Low 2 */ 154 .ba5_IDE_TF13 = 0x0d5, /* Cylinder High 2 */ 155 .ba5_IDE_TF14 = 0x0d6, /* Device/Head 2 */ 156 .ba5_IDE_TF15 = 0x0d7, /* Cmd Sts 2 */ 157 .ba5_IDE_TF16 = 0x0d8, /* Sector Count 2 ext */ 158 .ba5_IDE_TF17 = 0x0d9, /* Start Sector 2 ext */ 159 .ba5_IDE_TF18 = 0x0da, /* Cyl Low 2 ext */ 160 .ba5_IDE_TF19 = 0x0db, /* Cyl High 2 ext */ 161 .ba5_IDE_RABC = 0x0dc, 162 .ba5_IDE_CMD_STS = 0x0e0, 163 .ba5_IDE_CFG_STS = 0x0e1, 164 .ba5_IDE_DTM = 0x0f4, 165 .ba5_SControl = 0x180, 166 .ba5_SStatus = 0x184, 167 .ba5_SError = 0x188, 168 .ba5_SActive = 0x18c, 169 .ba5_SMisc = 0x1c0, 170 .ba5_PHY_CONFIG = 0x1c4, 171 .ba5_SIEN = 0x1c8, 172 .ba5_SFISCfg = 0x1cc, 173 }, 174 { /* Channel 2 (3114) */ 175 .ba5_IDEDMA_CMD = 0x200, 176 .ba5_IDEDMA_CTL = 0x202, 177 .ba5_IDEDMA_TBL = 0x204, 178 .ba5_IDEDMA_CMD2 = 0x210, 179 .ba5_IDEDMA_CTL2 = 0x212, 180 .ba5_IDE_TF0 = 0x280, /* wd_data */ 181 .ba5_IDE_TF1 = 0x281, /* wd_error */ 182 .ba5_IDE_TF2 = 0x282, /* wd_seccnt */ 183 .ba5_IDE_TF3 = 0x283, /* wd_sector */ 184 .ba5_IDE_TF4 = 0x284, /* wd_cyl_lo */ 185 .ba5_IDE_TF5 = 0x285, /* wd_cyl_hi */ 186 .ba5_IDE_TF6 = 0x286, /* wd_sdh */ 187 .ba5_IDE_TF7 = 0x287, /* wd_command */ 188 .ba5_IDE_TF8 = 0x28a, /* wd_altsts */ 189 .ba5_IDE_RAD = 0x28c, 190 .ba5_IDE_TF9 = 0x291, /* Features 2 */ 191 .ba5_IDE_TF10 = 0x292, /* Sector Count 2 */ 192 .ba5_IDE_TF11 = 0x293, /* Start Sector 2 */ 193 .ba5_IDE_TF12 = 0x294, /* Cylinder Low 2 */ 194 .ba5_IDE_TF13 = 0x295, /* Cylinder High 2 */ 195 .ba5_IDE_TF14 = 0x296, /* Device/Head 2 */ 196 .ba5_IDE_TF15 = 0x297, /* Cmd Sts 2 */ 197 .ba5_IDE_TF16 = 0x298, /* Sector Count 2 ext */ 198 .ba5_IDE_TF17 = 0x299, /* Start Sector 2 ext */ 199 .ba5_IDE_TF18 = 0x29a, /* Cyl Low 2 ext */ 200 .ba5_IDE_TF19 = 0x29b, /* Cyl High 2 ext */ 201 .ba5_IDE_RABC = 0x29c, 202 .ba5_IDE_CMD_STS = 0x2a0, 203 .ba5_IDE_CFG_STS = 0x2a1, 204 .ba5_IDE_DTM = 0x2b4, 205 .ba5_SControl = 0x300, 206 .ba5_SStatus = 0x304, 207 .ba5_SError = 0x308, 208 .ba5_SActive = 0x30c, 209 .ba5_SMisc = 0x340, 210 .ba5_PHY_CONFIG = 0x344, 211 .ba5_SIEN = 0x348, 212 .ba5_SFISCfg = 0x34c, 213 }, 214 { /* Channel 3 (3114) */ 215 .ba5_IDEDMA_CMD = 0x208, 216 .ba5_IDEDMA_CTL = 0x20a, 217 .ba5_IDEDMA_TBL = 0x20c, 218 .ba5_IDEDMA_CMD2 = 0x218, 219 .ba5_IDEDMA_CTL2 = 0x21a, 220 .ba5_IDE_TF0 = 0x2c0, /* wd_data */ 221 .ba5_IDE_TF1 = 0x2c1, /* wd_error */ 222 .ba5_IDE_TF2 = 0x2c2, /* wd_seccnt */ 223 .ba5_IDE_TF3 = 0x2c3, /* wd_sector */ 224 .ba5_IDE_TF4 = 0x2c4, /* wd_cyl_lo */ 225 .ba5_IDE_TF5 = 0x2c5, /* wd_cyl_hi */ 226 .ba5_IDE_TF6 = 0x2c6, /* wd_sdh */ 227 .ba5_IDE_TF7 = 0x2c7, /* wd_command */ 228 .ba5_IDE_TF8 = 0x2ca, /* wd_altsts */ 229 .ba5_IDE_RAD = 0x2cc, 230 .ba5_IDE_TF9 = 0x2d1, /* Features 2 */ 231 .ba5_IDE_TF10 = 0x2d2, /* Sector Count 2 */ 232 .ba5_IDE_TF11 = 0x2d3, /* Start Sector 2 */ 233 .ba5_IDE_TF12 = 0x2d4, /* Cylinder Low 2 */ 234 .ba5_IDE_TF13 = 0x2d5, /* Cylinder High 2 */ 235 .ba5_IDE_TF14 = 0x2d6, /* Device/Head 2 */ 236 .ba5_IDE_TF15 = 0x2d7, /* Cmd Sts 2 */ 237 .ba5_IDE_TF16 = 0x2d8, /* Sector Count 2 ext */ 238 .ba5_IDE_TF17 = 0x2d9, /* Start Sector 2 ext */ 239 .ba5_IDE_TF18 = 0x2da, /* Cyl Low 2 ext */ 240 .ba5_IDE_TF19 = 0x2db, /* Cyl High 2 ext */ 241 .ba5_IDE_RABC = 0x2dc, 242 .ba5_IDE_CMD_STS = 0x2e0, 243 .ba5_IDE_CFG_STS = 0x2e1, 244 .ba5_IDE_DTM = 0x2f4, 245 .ba5_SControl = 0x380, 246 .ba5_SStatus = 0x384, 247 .ba5_SError = 0x388, 248 .ba5_SActive = 0x38c, 249 .ba5_SMisc = 0x3c0, 250 .ba5_PHY_CONFIG = 0x3c4, 251 .ba5_SIEN = 0x3c8, 252 .ba5_SFISCfg = 0x3cc, 253 }, 254 }; 255 256 #define ba5_SIS 0x214 /* summary interrupt status */ 257 258 /* Interrupt steering bit in BA5[0x200]. */ 259 #define IDEDMA_CMD_INT_STEER (1U << 1) 260 261 static int satalink_match(struct device *, struct cfdata *, void *); 262 static void satalink_attach(struct device *, struct device *, void *); 263 264 CFATTACH_DECL(satalink, sizeof(struct pciide_softc), 265 satalink_match, satalink_attach, NULL, NULL); 266 267 static void sii3112_chip_map(struct pciide_softc*, struct pci_attach_args*); 268 static void sii3114_chip_map(struct pciide_softc*, struct pci_attach_args*); 269 static int sii3112_drv_probe(struct channel_softc*); 270 static void sii3112_setup_channel(struct channel_softc*); 271 272 static const struct pciide_product_desc pciide_satalink_products[] = { 273 { PCI_PRODUCT_CMDTECH_3112, 274 0, 275 "Silicon Image SATALink 3112", 276 sii3112_chip_map, 277 }, 278 { PCI_PRODUCT_CMDTECH_3114, 279 0, 280 "Silicon Image SATALink 3114", 281 sii3114_chip_map, 282 }, 283 { 0, 284 0, 285 NULL, 286 NULL 287 } 288 }; 289 290 static int 291 satalink_match(struct device *parent, struct cfdata *match, void *aux) 292 { 293 struct pci_attach_args *pa = aux; 294 295 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_CMDTECH) { 296 if (pciide_lookup_product(pa->pa_id, pciide_satalink_products)) 297 return (2); 298 } 299 return (0); 300 } 301 302 static void 303 satalink_attach(struct device *parent, struct device *self, void *aux) 304 { 305 struct pci_attach_args *pa = aux; 306 struct pciide_softc *sc = (struct pciide_softc *)self; 307 308 pciide_common_attach(sc, pa, 309 pciide_lookup_product(pa->pa_id, pciide_satalink_products)); 310 311 } 312 313 static __inline uint32_t 314 ba5_read_4_ind(struct pciide_softc *sc, bus_addr_t reg) 315 { 316 uint32_t rv; 317 int s; 318 319 s = splbio(); 320 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 321 rv = pci_conf_read(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA); 322 splx(s); 323 324 return (rv); 325 } 326 327 static __inline uint32_t 328 ba5_read_4(struct pciide_softc *sc, bus_addr_t reg) 329 { 330 331 if (__predict_true(sc->sc_ba5_en != 0)) 332 return (bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg)); 333 334 return (ba5_read_4_ind(sc, reg)); 335 } 336 337 #define BA5_READ_4(sc, chan, reg) \ 338 ba5_read_4((sc), satalink_ba5_regmap[(chan)].reg) 339 340 static __inline void 341 ba5_write_4_ind(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 342 { 343 int s; 344 345 s = splbio(); 346 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_ADDR, reg); 347 pci_conf_write(sc->sc_pc, sc->sc_tag, SII3112_BA5_IND_DATA, val); 348 splx(s); 349 } 350 351 static __inline void 352 ba5_write_4(struct pciide_softc *sc, bus_addr_t reg, uint32_t val) 353 { 354 355 if (__predict_true(sc->sc_ba5_en != 0)) 356 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, reg, val); 357 else 358 ba5_write_4_ind(sc, reg, val); 359 } 360 361 #define BA5_WRITE_4(sc, chan, reg, val) \ 362 ba5_write_4((sc), satalink_ba5_regmap[(chan)].reg, (val)) 363 364 static void 365 sii3112_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 366 { 367 struct pciide_channel *cp; 368 bus_size_t cmdsize, ctlsize; 369 pcireg_t interface, scs_cmd, cfgctl; 370 int channel; 371 372 if (pciide_chipen(sc, pa) == 0) 373 return; 374 375 #define SII3112_RESET_BITS \ 376 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 377 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 378 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET) 379 380 /* 381 * Reset everything and then unblock all of the interrupts. 382 */ 383 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 384 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 385 scs_cmd | SII3112_RESET_BITS); 386 delay(50 * 1000); 387 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 388 scs_cmd & SCS_CMD_BA5_EN); 389 delay(50 * 1000); 390 391 if (scs_cmd & SCS_CMD_BA5_EN) { 392 aprint_verbose("%s: SATALink BA5 register space enabled\n", 393 sc->sc_wdcdev.sc_dev.dv_xname); 394 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 395 PCI_MAPREG_TYPE_MEM| 396 PCI_MAPREG_MEM_TYPE_32BIT, 0, 397 &sc->sc_ba5_st, &sc->sc_ba5_sh, 398 NULL, NULL) != 0) 399 aprint_error("%s: unable to map SATALink BA5 " 400 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 401 else 402 sc->sc_ba5_en = 1; 403 } else { 404 aprint_verbose("%s: SATALink BA5 register space disabled\n", 405 sc->sc_wdcdev.sc_dev.dv_xname); 406 407 cfgctl = pci_conf_read(pa->pa_pc, pa->pa_tag, 408 SII3112_PCI_CFGCTL); 409 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_PCI_CFGCTL, 410 cfgctl | CFGCTL_BA5INDEN); 411 } 412 413 aprint_normal("%s: bus-master DMA support present", 414 sc->sc_wdcdev.sc_dev.dv_xname); 415 pciide_mapreg_dma(sc, pa); 416 aprint_normal("\n"); 417 418 /* 419 * Rev. <= 0x01 of the 3112 have a bug that can cause data 420 * corruption if DMA transfers cross an 8K boundary. This is 421 * apparently hard to tickle, but we'll go ahead and play it 422 * safe. 423 */ 424 if (PCI_REVISION(pa->pa_class) <= 0x01) { 425 sc->sc_dma_maxsegsz = 8192; 426 sc->sc_dma_boundary = 8192; 427 } 428 429 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 430 WDC_CAPABILITY_MODE; 431 sc->sc_wdcdev.PIO_cap = 4; 432 if (sc->sc_dma_ok) { 433 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 434 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 435 sc->sc_wdcdev.irqack = pciide_irqack; 436 sc->sc_wdcdev.DMA_cap = 2; 437 sc->sc_wdcdev.UDMA_cap = 6; 438 } 439 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 440 441 /* We can use SControl and SStatus to probe for drives. */ 442 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE; 443 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 444 445 sc->sc_wdcdev.channels = sc->wdc_chanarray; 446 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 447 448 /* 449 * The 3112 either identifies itself as a RAID storage device 450 * or a Misc storage device. Fake up the interface bits for 451 * what our driver expects. 452 */ 453 if (PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_MASS_STORAGE_IDE) { 454 interface = PCI_INTERFACE(pa->pa_class); 455 } else { 456 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 457 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 458 } 459 460 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 461 cp = &sc->pciide_channels[channel]; 462 if (pciide_chansetup(sc, channel, interface) == 0) 463 continue; 464 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 465 pciide_pci_intr); 466 } 467 } 468 469 static void 470 sii3114_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 471 { 472 struct pciide_channel *pc; 473 int chan, reg; 474 bus_size_t size; 475 476 sc->sc_wdcdev.dma_arg = sc; 477 sc->sc_wdcdev.dma_init = pciide_dma_init; 478 sc->sc_wdcdev.dma_start = pciide_dma_start; 479 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 480 481 if (sc->sc_wdcdev.sc_dev.dv_cfdata->cf_flags & 482 PCIIDE_OPTIONS_NODMA) { 483 aprint_normal( 484 ", but unused (forced off by config file)"); 485 sc->sc_dma_ok = 0; 486 return; 487 } 488 489 /* 490 * Slice off a subregion of BA5 for each of the channel's DMA 491 * registers. 492 */ 493 494 sc->sc_dma_iot = sc->sc_ba5_st; 495 for (chan = 0; chan < 4; chan++) { 496 pc = &sc->pciide_channels[chan]; 497 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 498 size = 4; 499 if (size > (IDEDMA_SCH_OFFSET - reg)) 500 size = IDEDMA_SCH_OFFSET - reg; 501 if (bus_space_subregion(sc->sc_ba5_st, 502 sc->sc_ba5_sh, 503 satalink_ba5_regmap[chan].ba5_IDEDMA_CMD + reg, 504 size, &pc->dma_iohs[reg]) != 0) { 505 sc->sc_dma_ok = 0; 506 aprint_normal(", but can't subregion offset " 507 "%lu size %lu", 508 (u_long) satalink_ba5_regmap[ 509 chan].ba5_IDEDMA_CMD + reg, 510 (u_long) size); 511 return; 512 } 513 } 514 } 515 516 /* DMA registers all set up! */ 517 sc->sc_dmat = pa->pa_dmat; 518 sc->sc_dma_ok = 1; 519 } 520 521 static int 522 sii3114_chansetup(struct pciide_softc *sc, int channel) 523 { 524 static const char *channel_names[] = { 525 "port 0", 526 "port 1", 527 "port 2", 528 "port 3", 529 }; 530 struct pciide_channel *cp = &sc->pciide_channels[channel]; 531 532 sc->wdc_chanarray[channel] = &cp->wdc_channel; 533 534 /* 535 * We must always keep the Interrupt Steering bit set in channel 2's 536 * IDEDMA_CMD register. 537 */ 538 if (channel == 2) 539 cp->idedma_cmd = IDEDMA_CMD_INT_STEER; 540 541 cp->name = channel_names[channel]; 542 cp->wdc_channel.channel = channel; 543 cp->wdc_channel.wdc = &sc->sc_wdcdev; 544 cp->wdc_channel.ch_queue = 545 malloc(sizeof(struct channel_queue), M_DEVBUF, M_NOWAIT); 546 if (cp->wdc_channel.ch_queue == NULL) { 547 aprint_error("%s %s channel: " 548 "can't allocate memory for command queue", 549 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 550 return (0); 551 } 552 return (1); 553 } 554 555 static void 556 sii3114_mapchan(struct pciide_channel *cp) 557 { 558 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 559 struct channel_softc *wdc_cp = &cp->wdc_channel; 560 int i; 561 562 cp->compat = 0; 563 cp->ih = sc->sc_pci_ih; 564 565 wdc_cp->cmd_iot = sc->sc_ba5_st; 566 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 567 satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF0, 568 9, &wdc_cp->cmd_baseioh) != 0) { 569 aprint_error("%s: couldn't subregion %s cmd base\n", 570 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 571 goto bad; 572 } 573 574 wdc_cp->ctl_iot = sc->sc_ba5_st; 575 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 576 satalink_ba5_regmap[wdc_cp->channel].ba5_IDE_TF9, 577 1, &cp->ctl_baseioh) != 0) { 578 aprint_error("%s: couldn't subregion %s ctl base\n", 579 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 580 goto bad; 581 } 582 wdc_cp->ctl_ioh = cp->ctl_baseioh; 583 584 for (i = 0; i < WDC_NREG; i++) { 585 if (bus_space_subregion(wdc_cp->cmd_iot, wdc_cp->cmd_baseioh, 586 i, i == 0 ? 4 : 1, 587 &wdc_cp->cmd_iohs[i]) != 0) { 588 aprint_error("%s: couldn't subregion %s channel " 589 "cmd regs\n", 590 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 591 goto bad; 592 } 593 } 594 wdc_cp->data32iot = wdc_cp->cmd_iot; 595 wdc_cp->data32ioh = wdc_cp->cmd_iohs[0]; 596 wdcattach(wdc_cp); 597 return; 598 599 bad: 600 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 601 } 602 603 static void 604 sii3114_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 605 { 606 struct pciide_channel *cp; 607 pcireg_t scs_cmd; 608 pci_intr_handle_t intrhandle; 609 const char *intrstr; 610 int channel; 611 612 if (pciide_chipen(sc, pa) == 0) 613 return; 614 615 #define SII3114_RESET_BITS \ 616 (SCS_CMD_PBM_RESET | SCS_CMD_ARB_RESET | \ 617 SCS_CMD_FF1_RESET | SCS_CMD_FF0_RESET | \ 618 SCS_CMD_FF3_RESET | SCS_CMD_FF2_RESET | \ 619 SCS_CMD_IDE1_RESET | SCS_CMD_IDE0_RESET | \ 620 SCS_CMD_IDE3_RESET | SCS_CMD_IDE2_RESET) 621 622 /* 623 * Reset everything and then unblock all of the interrupts. 624 */ 625 scs_cmd = pci_conf_read(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD); 626 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 627 scs_cmd | SII3114_RESET_BITS); 628 delay(50 * 1000); 629 pci_conf_write(pa->pa_pc, pa->pa_tag, SII3112_SCS_CMD, 630 scs_cmd & SCS_CMD_M66EN); 631 delay(50 * 1000); 632 633 /* 634 * On the 3114, the BA5 register space is always enabled. In 635 * order to use the 3114 in any sane way, we must use this BA5 636 * register space, and so we consider it an error if we cannot 637 * map it. 638 * 639 * As a consequence of using BA5, our register mapping is different 640 * from a normal PCI IDE controller's, and so we are unable to use 641 * most of the common PCI IDE register mapping functions. 642 */ 643 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 644 PCI_MAPREG_TYPE_MEM| 645 PCI_MAPREG_MEM_TYPE_32BIT, 0, 646 &sc->sc_ba5_st, &sc->sc_ba5_sh, 647 NULL, NULL) != 0) { 648 aprint_error("%s: unable to map SATALink BA5 " 649 "register space\n", sc->sc_wdcdev.sc_dev.dv_xname); 650 return; 651 } 652 sc->sc_ba5_en = 1; 653 654 aprint_verbose("%s: %dMHz PCI bus\n", sc->sc_wdcdev.sc_dev.dv_xname, 655 (scs_cmd & SCS_CMD_M66EN) ? 66 : 33); 656 657 /* 658 * Set the Interrupt Steering bit in the IDEDMA_CMD register of 659 * channel 2. This is required at all times for proper operation 660 * when using the BA5 register space (otherwise interrupts from 661 * all 4 channels won't work). 662 */ 663 BA5_WRITE_4(sc, 2, ba5_IDEDMA_CMD, IDEDMA_CMD_INT_STEER); 664 665 aprint_normal("%s: bus-master DMA support present", 666 sc->sc_wdcdev.sc_dev.dv_xname); 667 sii3114_mapreg_dma(sc, pa); 668 aprint_normal("\n"); 669 670 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 671 WDC_CAPABILITY_MODE; 672 sc->sc_wdcdev.PIO_cap = 4; 673 if (sc->sc_dma_ok) { 674 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_UDMA; 675 sc->sc_wdcdev.cap |= WDC_CAPABILITY_IRQACK; 676 sc->sc_wdcdev.irqack = pciide_irqack; 677 sc->sc_wdcdev.DMA_cap = 2; 678 sc->sc_wdcdev.UDMA_cap = 6; 679 } 680 sc->sc_wdcdev.set_modes = sii3112_setup_channel; 681 682 /* We can use SControl and SStatus to probe for drives. */ 683 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DRVPROBE; 684 sc->sc_wdcdev.drv_probe = sii3112_drv_probe; 685 686 sc->sc_wdcdev.channels = sc->wdc_chanarray; 687 sc->sc_wdcdev.nchannels = 4; 688 689 /* Map and establish the interrupt handler. */ 690 if (pci_intr_map(pa, &intrhandle) != 0) { 691 aprint_error("%s: couldn't map native-PCI interrupt\n", 692 sc->sc_wdcdev.sc_dev.dv_xname); 693 return; 694 } 695 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 696 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 697 /* XXX */ 698 pciide_pci_intr, sc); 699 if (sc->sc_pci_ih != NULL) { 700 aprint_normal("%s: using %s for native-PCI interrupt\n", 701 sc->sc_wdcdev.sc_dev.dv_xname, 702 intrstr ? intrstr : "unknown interrupt"); 703 } else { 704 aprint_error("%s: couldn't establish native-PCI interrupt", 705 sc->sc_wdcdev.sc_dev.dv_xname); 706 if (intrstr != NULL) 707 aprint_normal(" at %s", intrstr); 708 aprint_normal("\n"); 709 return; 710 } 711 712 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 713 cp = &sc->pciide_channels[channel]; 714 if (sii3114_chansetup(sc, channel) == 0) 715 continue; 716 sii3114_mapchan(cp); 717 } 718 } 719 720 static const char *sata_speed[] = { 721 "no negotiated speed", 722 "1.5Gb/s", 723 "<unknown 2>", 724 "<unknown 3>", 725 "<unknown 4>", 726 "<unknown 5>", 727 "<unknown 6>", 728 "<unknown 7>", 729 "<unknown 8>", 730 "<unknown 9>", 731 "<unknown 10>", 732 "<unknown 11>", 733 "<unknown 12>", 734 "<unknown 13>", 735 "<unknown 14>", 736 "<unknown 15>", 737 }; 738 739 static int 740 sii3112_drv_probe(struct channel_softc *chp) 741 { 742 struct pciide_channel *cp = (struct pciide_channel *)chp; 743 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 744 uint32_t scontrol, sstatus; 745 int rv = 0; 746 uint8_t scnt, sn, cl, ch; 747 748 /* 749 * The 3112 is a 2-port part, and only has one drive per channel 750 * (each port emulates a master drive). 751 * 752 * The 3114 is similar, but has 4 channels. 753 */ 754 755 /* 756 * Request communication initialization sequence, any speed. 757 * Performing this is the equivalent of an ATA Reset. 758 */ 759 scontrol = SControl_DET_INIT | SControl_SPD_ANY; 760 761 /* 762 * XXX We don't yet support SATA power management; disable all 763 * power management state transitions. 764 */ 765 scontrol |= SControl_IPM_NONE; 766 767 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 768 delay(50 * 1000); 769 scontrol &= ~SControl_DET_INIT; 770 BA5_WRITE_4(sc, chp->channel, ba5_SControl, scontrol); 771 delay(50 * 1000); 772 773 sstatus = BA5_READ_4(sc, chp->channel, ba5_SStatus); 774 #if 0 775 aprint_normal("%s: port %d: SStatus=0x%08x, SControl=0x%08x\n", 776 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus, 777 BA5_READ_4(sc, chp->channel, ba5_SControl)); 778 #endif 779 switch (sstatus & SStatus_DET_mask) { 780 case SStatus_DET_NODEV: 781 /* No device; be silent. */ 782 break; 783 784 case SStatus_DET_DEV_NE: 785 aprint_error("%s: port %d: device connected, but " 786 "communication not established\n", 787 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 788 break; 789 790 case SStatus_DET_OFFLINE: 791 aprint_error("%s: port %d: PHY offline\n", 792 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel); 793 break; 794 795 case SStatus_DET_DEV: 796 /* 797 * XXX ATAPI detection doesn't currently work. Don't 798 * XXX know why. But, it's not like the standard method 799 * XXX can detect an ATAPI device connected via a SATA/PATA 800 * XXX bridge, so at least this is no worse. --thorpej 801 */ 802 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 803 WDSD_IBM | (0 << 4)); 804 delay(10); /* 400ns delay */ 805 /* Save register contents. */ 806 scnt = bus_space_read_1(chp->cmd_iot, 807 chp->cmd_iohs[wd_seccnt], 0); 808 sn = bus_space_read_1(chp->cmd_iot, 809 chp->cmd_iohs[wd_sector], 0); 810 cl = bus_space_read_1(chp->cmd_iot, 811 chp->cmd_iohs[wd_cyl_lo], 0); 812 ch = bus_space_read_1(chp->cmd_iot, 813 chp->cmd_iohs[wd_cyl_hi], 0); 814 #if 0 815 printf("%s: port %d: scnt=0x%x sn=0x%x cl=0x%x ch=0x%x\n", 816 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 817 scnt, sn, cl, ch); 818 #endif 819 /* 820 * scnt and sn are supposed to be 0x1 for ATAPI, but in some 821 * cases we get wrong values here, so ignore it. 822 */ 823 if (cl == 0x14 && ch == 0xeb) 824 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 825 else 826 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 827 828 aprint_normal("%s: port %d: device present, speed: %s\n", 829 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, 830 sata_speed[(sstatus & SStatus_SPD_mask) >> 831 SStatus_SPD_shift]); 832 rv |= (1 << 0); 833 break; 834 835 default: 836 aprint_error("%s: port %d: unknown SStatus: 0x%08x\n", 837 sc->sc_wdcdev.sc_dev.dv_xname, chp->channel, sstatus); 838 } 839 840 return (rv); 841 } 842 843 static void 844 sii3112_setup_channel(struct channel_softc *chp) 845 { 846 struct ata_drive_datas *drvp; 847 int drive; 848 u_int32_t idedma_ctl, dtm; 849 struct pciide_channel *cp = (struct pciide_channel*)chp; 850 struct pciide_softc *sc = (struct pciide_softc*)cp->wdc_channel.wdc; 851 852 /* setup DMA if needed */ 853 pciide_channel_dma_setup(cp); 854 855 idedma_ctl = 0; 856 dtm = 0; 857 858 for (drive = 0; drive < 2; drive++) { 859 drvp = &chp->ch_drive[drive]; 860 /* If no drive, skip */ 861 if ((drvp->drive_flags & DRIVE) == 0) 862 continue; 863 if (drvp->drive_flags & DRIVE_UDMA) { 864 /* use Ultra/DMA */ 865 drvp->drive_flags &= ~DRIVE_DMA; 866 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 867 dtm |= DTM_IDEx_DMA; 868 } else if (drvp->drive_flags & DRIVE_DMA) { 869 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 870 dtm |= DTM_IDEx_DMA; 871 } else { 872 dtm |= DTM_IDEx_PIO; 873 } 874 } 875 876 /* 877 * Nothing to do to setup modes; it is meaningless in S-ATA 878 * (but many S-ATA drives still want to get the SET_FEATURE 879 * command). 880 */ 881 if (idedma_ctl != 0) { 882 /* Add software bits in status register */ 883 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 884 idedma_ctl); 885 } 886 BA5_WRITE_4(sc, chp->channel, ba5_IDE_DTM, dtm); 887 } 888
Indexes created Mon Sep 29 21:09:56 GMT 2025