sdhc_pci.c revision 1.1.6.2
1 /* $NetBSD: sdhc_pci.c,v 1.1.6.2 2009/05/13 17:20:29 jym Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.1.6.2 2009/05/13 17:20:29 jym Exp $"); 22 23 #include <sys/param.h> 24 #include <sys/device.h> 25 #include <sys/systm.h> 26 #include <sys/malloc.h> 27 #include <sys/pmf.h> 28 29 #include <dev/pci/pcivar.h> 30 #include <dev/pci/pcidevs.h> 31 32 #include <dev/sdmmc/sdhcreg.h> 33 #include <dev/sdmmc/sdhcvar.h> 34 #include <dev/sdmmc/sdmmcvar.h> 35 36 /* PCI base address registers */ 37 #define SDHC_PCI_BAR_START PCI_MAPREG_START 38 #define SDHC_PCI_BAR_END PCI_MAPREG_END 39 40 /* PCI interface classes */ 41 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 42 #define SDHC_PCI_INTERFACE_DMA 0x01 43 #define SDHC_PCI_INTERFACE_VENDOR 0x02 44 45 /* 46 * 8-bit PCI configuration register that tells us how many slots there 47 * are and which BAR entry corresponds to the first slot. 48 */ 49 #define SDHC_PCI_CONF_SLOT_INFO 0x40 50 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 51 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 52 53 struct sdhc_pci_softc { 54 struct sdhc_softc sc; 55 void *sc_ih; 56 }; 57 58 static int sdhc_pci_match(device_t, cfdata_t, void *); 59 static void sdhc_pci_attach(device_t, device_t, void *); 60 61 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 62 sdhc_pci_match, sdhc_pci_attach, NULL, NULL); 63 64 #ifdef SDHC_DEBUG 65 #define DPRINTF(s) printf s 66 #else 67 #define DPRINTF(s) /**/ 68 #endif 69 70 /* XXX */ 71 #define PCI_PRODUCT_TI_PCI7XX1_FLASH 0x8033 72 #define PCI_PRODUCT_TI_PCI7XX1_SD 0x8034 73 #define PCI_PRODUCT_ENE_SDCARD 0x0550 74 75 static const struct sdhc_pci_quirk { 76 pci_vendor_id_t vendor; 77 pci_product_id_t product; 78 pci_vendor_id_t subvendor; 79 pci_product_id_t subproduct; 80 u_int function; 81 82 uint32_t flags; 83 #define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0) 84 #define SDHC_PCI_QUIRK_TI_HACK (1U << 1) 85 #define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2) 86 } sdhc_pci_quirk_table[] = { 87 { 88 PCI_VENDOR_TI, 89 PCI_PRODUCT_TI_PCI7XX1_SD, 90 0xffff, 91 0xffff, 92 4, 93 SDHC_PCI_QUIRK_TI_HACK 94 }, 95 96 { 97 PCI_VENDOR_ENE, 98 PCI_PRODUCT_ENE_SDCARD, 99 0xffff, 100 0xffff, 101 0, 102 SDHC_PCI_QUIRK_NO_PWR0 103 }, 104 }; 105 106 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 107 108 static uint32_t 109 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 110 { 111 const struct sdhc_pci_quirk *q; 112 pcireg_t id; 113 pci_vendor_id_t vendor; 114 pci_product_id_t product; 115 int i; 116 117 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 118 q = &sdhc_pci_quirk_table[i]; 119 120 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 121 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 122 if ((q->function != ~0) 123 && (pa->pa_function != q->function)) 124 continue; 125 126 if ((q->subvendor == 0xffff) 127 && (q->subproduct == 0xffff)) 128 return q->flags; 129 130 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 131 PCI_SUBSYS_ID_REG); 132 vendor = PCI_VENDOR(id); 133 product = PCI_PRODUCT(id); 134 135 if ((q->subvendor != 0xffff) 136 && (q->subproduct != 0xffff)) { 137 if ((vendor == q->subvendor) 138 && (product == q->subproduct)) 139 return q->flags; 140 } else if (q->subvendor != 0xffff) { 141 if (product == q->subproduct) 142 return q->flags; 143 } else { 144 if (vendor == q->subvendor) 145 return q->flags; 146 } 147 } 148 } 149 150 return 0; 151 } 152 153 static int 154 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 155 { 156 struct pci_attach_args *pa = aux; 157 158 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 159 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 160 return 1; 161 162 return 0; 163 } 164 165 static void 166 sdhc_pci_attach(device_t parent, device_t self, void *aux) 167 { 168 struct sdhc_pci_softc *sc = device_private(self); 169 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 170 pci_chipset_tag_t pc = pa->pa_pc; 171 pcitag_t tag = pa->pa_tag; 172 pci_intr_handle_t ih; 173 pcireg_t csr; 174 pcireg_t slotinfo; 175 char devinfo[256]; 176 char const *intrstr; 177 int nslots; 178 int reg; 179 int cnt; 180 bus_space_tag_t iot; 181 bus_space_handle_t ioh; 182 bus_size_t size; 183 uint32_t flags; 184 185 sc->sc.sc_dev = self; 186 sc->sc.sc_dmat = pa->pa_dmat; 187 sc->sc.sc_host = NULL; 188 189 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof(devinfo)); 190 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, 191 PCI_REVISION(pa->pa_class)); 192 aprint_naive("\n"); 193 194 /* Some controllers needs special treatment. */ 195 flags = sdhc_pci_lookup_quirk_flags(pa); 196 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 197 sdhc_pci_quirk_ti_hack(pa); 198 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 199 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 200 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 201 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 202 203 /* 204 * Map and attach all hosts supported by the host controller. 205 */ 206 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 207 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 208 209 /* Allocate an array big enough to hold all the possible hosts */ 210 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 211 M_DEVBUF, M_NOWAIT | M_ZERO); 212 if (sc->sc.sc_host == NULL) { 213 aprint_error_dev(self, "couldn't alloc memory\n"); 214 goto err; 215 } 216 217 /* Enable the device. */ 218 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 219 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 220 csr | PCI_COMMAND_MASTER_ENABLE); 221 222 /* Map and establish the interrupt. */ 223 if (pci_intr_map(pa, &ih)) { 224 aprint_error_dev(self, "couldn't map interrupt\n"); 225 goto err; 226 } 227 228 intrstr = pci_intr_string(pc, ih); 229 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, sdhc_intr, sc); 230 if (sc->sc_ih == NULL) { 231 aprint_error_dev(self, "couldn't establish interrupt\n"); 232 goto err; 233 } 234 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 235 236 /* Enable use of DMA if supported by the interface. */ 237 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 238 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 239 240 /* XXX: handle 64-bit BARs */ 241 cnt = 0; 242 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 243 sizeof(uint32_t); 244 reg < SDHC_PCI_BAR_END && nslots > 0; 245 reg += sizeof(uint32_t), nslots--) { 246 if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0, 247 &iot, &ioh, NULL, &size)) { 248 continue; 249 } 250 251 cnt++; 252 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 253 /* XXX: sc->sc_host leak */ 254 aprint_error_dev(self, 255 "couldn't initialize host (0x%x)\n", reg); 256 } 257 } 258 if (cnt == 0) { 259 aprint_error_dev(self, "couldn't map register\n"); 260 goto err; 261 } 262 263 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 264 sdhc_shutdown)) { 265 aprint_error_dev(self, "couldn't establish powerhook\n"); 266 } 267 268 return; 269 270 err: 271 if (sc->sc.sc_host != NULL) 272 free(sc->sc.sc_host, M_DEVBUF); 273 } 274 275 /* TI specific register */ 276 #define SDHC_PCI_GENERAL_CTL 0x4c 277 #define MMC_SD_DIS 0x02 278 279 static void 280 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 281 { 282 pci_chipset_tag_t pc = pa->pa_pc; 283 pcitag_t tag; 284 pcireg_t id, reg; 285 286 /* Look at func 3 for the flash device */ 287 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, 3); 288 id = pci_conf_read(pc, tag, PCI_ID_REG); 289 if (PCI_PRODUCT(id) != PCI_PRODUCT_TI_PCI7XX1_FLASH) 290 return; 291 292 /* 293 * Disable MMC/SD on the flash media controller so the 294 * SD host takes over. 295 */ 296 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 297 reg |= MMC_SD_DIS; 298 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 299 } 300
Indexes created Wed Oct 22 13:09:56 GMT 2025