sdhc_pci.c revision 1.14.2.1
1 /* $NetBSD: sdhc_pci.c,v 1.14.2.1 2021/12/03 19:31:19 martin Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.14.2.1 2021/12/03 19:31:19 martin Exp $"); 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/systm.h> 30 #include <sys/malloc.h> 31 #include <sys/pmf.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 36 #include <dev/sdmmc/sdhcreg.h> 37 #include <dev/sdmmc/sdhcvar.h> 38 #include <dev/sdmmc/sdmmcvar.h> 39 40 /* PCI base address registers */ 41 #define SDHC_PCI_BAR_START PCI_MAPREG_START 42 #define SDHC_PCI_BAR_END PCI_MAPREG_END 43 44 /* PCI interface classes */ 45 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 46 #define SDHC_PCI_INTERFACE_DMA 0x01 47 #define SDHC_PCI_INTERFACE_VENDOR 0x02 48 49 /* 50 * 8-bit PCI configuration register that tells us how many slots there 51 * are and which BAR entry corresponds to the first slot. 52 */ 53 #define SDHC_PCI_CONF_SLOT_INFO 0x40 54 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 55 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 56 57 struct sdhc_pci_softc { 58 struct sdhc_softc sc; 59 pci_chipset_tag_t sc_pc; 60 void *sc_ih; 61 }; 62 63 static int sdhc_pci_match(device_t, cfdata_t, void *); 64 static void sdhc_pci_attach(device_t, device_t, void *); 65 static int sdhc_pci_detach(device_t, int); 66 67 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 68 sdhc_pci_match, sdhc_pci_attach, sdhc_pci_detach, NULL); 69 70 #ifdef SDHC_DEBUG 71 #define DPRINTF(s) printf s 72 #else 73 #define DPRINTF(s) /**/ 74 #endif 75 76 static const struct sdhc_pci_quirk { 77 pci_vendor_id_t vendor; 78 pci_product_id_t product; 79 pci_vendor_id_t subvendor; 80 pci_product_id_t subproduct; 81 u_int function; 82 83 uint32_t flags; 84 #define SDHC_PCI_QUIRK_FORCE_DMA __BIT(0) 85 #define SDHC_PCI_QUIRK_TI_HACK __BIT(1) 86 #define SDHC_PCI_QUIRK_NO_PWR0 __BIT(2) 87 #define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK __BIT(3) 88 #define SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK __BIT(4) 89 #define SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET __BIT(5) 90 } sdhc_pci_quirk_table[] = { 91 { 92 PCI_VENDOR_TI, 93 PCI_PRODUCT_TI_PCI72111SD, 94 0xffff, 95 0xffff, 96 4, 97 SDHC_PCI_QUIRK_TI_HACK 98 }, 99 100 { 101 PCI_VENDOR_TI, 102 PCI_PRODUCT_TI_PCIXX12SD, 103 0xffff, 104 0xffff, 105 3, 106 SDHC_PCI_QUIRK_TI_HACK 107 }, 108 109 { 110 PCI_VENDOR_ENE, 111 PCI_PRODUCT_ENE_CB712, 112 0xffff, 113 0xffff, 114 0, 115 SDHC_PCI_QUIRK_NO_PWR0 116 }, 117 { 118 PCI_VENDOR_RICOH, 119 PCI_PRODUCT_RICOH_Rx5U823, 120 0xffff, 121 0xffff, 122 0, 123 SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK 124 }, 125 { 126 PCI_VENDOR_RICOH, 127 PCI_PRODUCT_RICOH_Rx5C822, 128 0xffff, 129 0xffff, 130 ~0, 131 SDHC_PCI_QUIRK_FORCE_DMA 132 }, 133 134 { 135 PCI_VENDOR_RICOH, 136 PCI_PRODUCT_RICOH_Rx5U822, 137 0xffff, 138 0xffff, 139 ~0, 140 SDHC_PCI_QUIRK_FORCE_DMA 141 }, 142 143 { 144 PCI_VENDOR_INTEL, 145 PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC, 146 0xffff, 147 0xffff, 148 ~0, 149 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 150 }, 151 152 { 153 PCI_VENDOR_INTEL, 154 PCI_PRODUCT_INTEL_BSW_SSC_MMC, 155 0xffff, 156 0xffff, 157 ~0, 158 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 159 }, 160 161 { 162 PCI_VENDOR_INTEL, 163 PCI_PRODUCT_INTEL_100SERIES_LP_EMMC, 164 0xffff, 165 0xffff, 166 ~0, 167 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 168 }, 169 }; 170 171 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 172 static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *); 173 static void sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *, 174 struct sdhc_host *); 175 176 static uint32_t 177 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 178 { 179 const struct sdhc_pci_quirk *q; 180 pcireg_t id; 181 pci_vendor_id_t vendor; 182 pci_product_id_t product; 183 int i; 184 185 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 186 q = &sdhc_pci_quirk_table[i]; 187 188 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 189 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 190 if ((q->function != ~0) 191 && (pa->pa_function != q->function)) 192 continue; 193 194 if ((q->subvendor == 0xffff) 195 && (q->subproduct == 0xffff)) 196 return (q->flags); 197 198 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 199 PCI_SUBSYS_ID_REG); 200 vendor = PCI_VENDOR(id); 201 product = PCI_PRODUCT(id); 202 203 if ((q->subvendor != 0xffff) 204 && (q->subproduct != 0xffff)) { 205 if ((vendor == q->subvendor) 206 && (product == q->subproduct)) 207 return (q->flags); 208 } else if (q->subvendor != 0xffff) { 209 if (product == q->subproduct) 210 return (q->flags); 211 } else { 212 if (vendor == q->subvendor) 213 return (q->flags); 214 } 215 } 216 } 217 return (0); 218 } 219 220 static int 221 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 222 { 223 struct pci_attach_args *pa = aux; 224 225 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 226 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 227 return (1); 228 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH && 229 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 || 230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823)) 231 return (1); 232 return (0); 233 } 234 235 static void 236 sdhc_pci_attach(device_t parent, device_t self, void *aux) 237 { 238 struct sdhc_pci_softc *sc = device_private(self); 239 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 240 pci_chipset_tag_t pc = pa->pa_pc; 241 pcitag_t tag = pa->pa_tag; 242 pci_intr_handle_t ih; 243 pcireg_t csr; 244 pcireg_t slotinfo; 245 char const *intrstr; 246 int nslots; 247 int reg; 248 int cnt; 249 bus_space_tag_t iot; 250 bus_space_handle_t ioh; 251 bus_size_t size; 252 uint32_t flags; 253 int width; 254 char intrbuf[PCI_INTRSTR_LEN]; 255 256 sc->sc.sc_dev = self; 257 sc->sc.sc_dmat = pa->pa_dmat; 258 sc->sc.sc_host = NULL; 259 260 sc->sc_pc = pc; 261 262 pci_aprint_devinfo(pa, NULL); 263 264 /* Some controllers needs special treatment. */ 265 flags = sdhc_pci_lookup_quirk_flags(pa); 266 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 267 sdhc_pci_quirk_ti_hack(pa); 268 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 269 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 270 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 271 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 272 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK)) 273 sdhc_pci_quirk_ricoh_lower_freq_hack(pa); 274 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK)) 275 SET(sc->sc.sc_flags, SDHC_FLAG_SLOW_SDR50); 276 if (ISSET(flags, SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET)) 277 sc->sc.sc_vendor_hw_reset = sdhc_pci_intel_emmc_hw_reset; 278 279 /* 280 * Map and attach all hosts supported by the host controller. 281 */ 282 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 283 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 284 285 /* Allocate an array big enough to hold all the possible hosts */ 286 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 287 M_DEVBUF, M_NOWAIT | M_ZERO); 288 if (sc->sc.sc_host == NULL) { 289 aprint_error_dev(self, "couldn't alloc memory\n"); 290 goto err; 291 } 292 293 /* Enable the device. */ 294 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 295 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 296 csr | PCI_COMMAND_MASTER_ENABLE); 297 298 /* Map and establish the interrupt. */ 299 if (pci_intr_map(pa, &ih)) { 300 aprint_error_dev(self, "couldn't map interrupt\n"); 301 goto err; 302 } 303 304 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 305 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_SDMMC, sdhc_intr, 306 &sc->sc, device_xname(self)); 307 if (sc->sc_ih == NULL) { 308 aprint_error_dev(self, "couldn't establish interrupt\n"); 309 goto err; 310 } 311 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 312 313 /* Enable use of DMA if supported by the interface. */ 314 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 315 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 316 317 cnt = 0; 318 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 319 sizeof(uint32_t); 320 reg < SDHC_PCI_BAR_END && nslots > 0; 321 reg += width, nslots--) { 322 pcireg_t type; 323 324 type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, reg); 325 if (type == PCI_MAPREG_TYPE_IO) 326 break; 327 else if (PCI_MAPREG_MEM_TYPE(type) 328 == PCI_MAPREG_MEM_TYPE_64BIT) 329 width = 8; 330 else 331 width = 4; 332 333 if (pci_mapreg_map(pa, reg, type, 0, 334 &iot, &ioh, NULL, &size)) { 335 continue; 336 } 337 338 cnt++; 339 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 340 /* XXX: sc->sc_host leak */ 341 aprint_error_dev(self, 342 "couldn't initialize host (0x%x)\n", reg); 343 } 344 } 345 if (cnt == 0) { 346 aprint_error_dev(self, "couldn't map register\n"); 347 goto err; 348 } 349 350 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 351 sdhc_shutdown)) { 352 aprint_error_dev(self, "couldn't establish powerhook\n"); 353 } 354 355 return; 356 357 err: 358 if (sc->sc.sc_host != NULL) { 359 free(sc->sc.sc_host, M_DEVBUF); 360 sc->sc.sc_host = NULL; 361 } 362 } 363 364 static int 365 sdhc_pci_detach(device_t self, int flags) 366 { 367 struct sdhc_pci_softc * const sc = device_private(self); 368 int rv; 369 370 rv = sdhc_detach(&sc->sc, flags); 371 if (rv) 372 return rv; 373 374 if (sc->sc_ih != NULL) { 375 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 376 sc->sc_ih = NULL; 377 } 378 379 if (sc->sc.sc_host != NULL) { 380 free(sc->sc.sc_host, M_DEVBUF); 381 sc->sc.sc_host = NULL; 382 } 383 384 return rv; 385 } 386 387 static void 388 sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val) 389 { 390 pcireg_t r; 391 392 r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 393 r &= ~(0xff << ((reg & 0x3) * 8)); 394 r |= (val << ((reg & 0x3) * 8)); 395 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r); 396 } 397 398 /* TI specific register */ 399 #define SDHC_PCI_GENERAL_CTL 0x4c 400 #define MMC_SD_DIS 0x02 401 402 static void 403 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 404 { 405 pci_chipset_tag_t pc = pa->pa_pc; 406 pcitag_t tag; 407 pcireg_t id, reg; 408 409 /* Look at func - 1 for the flash device */ 410 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1); 411 id = pci_conf_read(pc, tag, PCI_ID_REG); 412 if (PCI_VENDOR(id) != PCI_VENDOR_TI) { 413 return; 414 } 415 switch (PCI_PRODUCT(id)) { 416 case PCI_PRODUCT_TI_PCI72111FM: 417 case PCI_PRODUCT_TI_PCIXX12FM: 418 break; 419 default: 420 return; 421 } 422 423 /* 424 * Disable MMC/SD on the flash media controller so the 425 * SD host takes over. 426 */ 427 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 428 reg |= MMC_SD_DIS; 429 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 430 } 431 432 /* Ricoh specific register */ 433 #define SDHC_PCI_MODE_KEY 0xf9 434 #define SDHC_PCI_MODE 0x150 435 #define SDHC_PCI_MODE_SD20 0x10 436 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 437 #define SDHC_PCI_BASE_FREQ 0xe1 438 439 /* Some RICOH controllers need to be bumped into the right mode. */ 440 static void 441 sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa) 442 { 443 /* Enable SD2.0 mode. */ 444 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc); 445 sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20); 446 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00); 447 448 /* 449 * Some SD/MMC cards don't work with the default base 450 * clock frequency of 200MHz. Lower it to 50Hz. 451 */ 452 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01); 453 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50); 454 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00); 455 printf("quirked\n"); 456 } 457 458 static void 459 sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *sc, struct sdhc_host *hp) 460 { 461 kmutex_t *plock = sdhc_host_lock(hp); 462 uint8_t reg; 463 464 mutex_enter(plock); 465 466 reg = sdhc_host_read_1(hp, SDHC_POWER_CTL); 467 reg |= 0x10; 468 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 469 470 sdmmc_delay(10); 471 472 reg &= ~0x10; 473 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 474 475 sdmmc_delay(1000); 476 477 mutex_exit(plock); 478 } 479
Indexes created Wed Oct 22 13:09:56 GMT 2025