sdhc_pci.c revision 1.16
1 /* $NetBSD: sdhc_pci.c,v 1.16 2019/11/10 21:16:36 chs Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.16 2019/11/10 21:16:36 chs Exp $"); 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/systm.h> 30 #include <sys/malloc.h> 31 #include <sys/pmf.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 36 #include <dev/sdmmc/sdhcreg.h> 37 #include <dev/sdmmc/sdhcvar.h> 38 #include <dev/sdmmc/sdmmcvar.h> 39 40 /* PCI base address registers */ 41 #define SDHC_PCI_BAR_START PCI_MAPREG_START 42 #define SDHC_PCI_BAR_END PCI_MAPREG_END 43 44 /* PCI interface classes */ 45 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 46 #define SDHC_PCI_INTERFACE_DMA 0x01 47 #define SDHC_PCI_INTERFACE_VENDOR 0x02 48 49 /* 50 * 8-bit PCI configuration register that tells us how many slots there 51 * are and which BAR entry corresponds to the first slot. 52 */ 53 #define SDHC_PCI_CONF_SLOT_INFO 0x40 54 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 55 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 56 57 struct sdhc_pci_softc { 58 struct sdhc_softc sc; 59 pci_chipset_tag_t sc_pc; 60 void *sc_ih; 61 }; 62 63 static int sdhc_pci_match(device_t, cfdata_t, void *); 64 static void sdhc_pci_attach(device_t, device_t, void *); 65 static int sdhc_pci_detach(device_t, int); 66 67 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 68 sdhc_pci_match, sdhc_pci_attach, sdhc_pci_detach, NULL); 69 70 #ifdef SDHC_DEBUG 71 #define DPRINTF(s) printf s 72 #else 73 #define DPRINTF(s) /**/ 74 #endif 75 76 static const struct sdhc_pci_quirk { 77 pci_vendor_id_t vendor; 78 pci_product_id_t product; 79 pci_vendor_id_t subvendor; 80 pci_product_id_t subproduct; 81 u_int function; 82 83 uint32_t flags; 84 #define SDHC_PCI_QUIRK_FORCE_DMA __BIT(0) 85 #define SDHC_PCI_QUIRK_TI_HACK __BIT(1) 86 #define SDHC_PCI_QUIRK_NO_PWR0 __BIT(2) 87 #define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK __BIT(3) 88 #define SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK __BIT(4) 89 #define SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET __BIT(5) 90 } sdhc_pci_quirk_table[] = { 91 { 92 PCI_VENDOR_TI, 93 PCI_PRODUCT_TI_PCI72111SD, 94 0xffff, 95 0xffff, 96 4, 97 SDHC_PCI_QUIRK_TI_HACK 98 }, 99 100 { 101 PCI_VENDOR_TI, 102 PCI_PRODUCT_TI_PCIXX12SD, 103 0xffff, 104 0xffff, 105 3, 106 SDHC_PCI_QUIRK_TI_HACK 107 }, 108 109 { 110 PCI_VENDOR_ENE, 111 PCI_PRODUCT_ENE_CB712, 112 0xffff, 113 0xffff, 114 0, 115 SDHC_PCI_QUIRK_NO_PWR0 116 }, 117 { 118 PCI_VENDOR_RICOH, 119 PCI_PRODUCT_RICOH_Rx5U823, 120 0xffff, 121 0xffff, 122 0, 123 SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK 124 }, 125 { 126 PCI_VENDOR_RICOH, 127 PCI_PRODUCT_RICOH_Rx5C822, 128 0xffff, 129 0xffff, 130 ~0, 131 SDHC_PCI_QUIRK_FORCE_DMA 132 }, 133 134 { 135 PCI_VENDOR_RICOH, 136 PCI_PRODUCT_RICOH_Rx5U822, 137 0xffff, 138 0xffff, 139 ~0, 140 SDHC_PCI_QUIRK_FORCE_DMA 141 }, 142 143 { 144 PCI_VENDOR_INTEL, 145 PCI_PRODUCT_INTEL_BAYTRAIL_SCC_MMC, 146 0xffff, 147 0xffff, 148 ~0, 149 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 150 }, 151 152 { 153 PCI_VENDOR_INTEL, 154 PCI_PRODUCT_INTEL_BSW_SSC_MMC, 155 0xffff, 156 0xffff, 157 ~0, 158 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 159 }, 160 161 { 162 PCI_VENDOR_INTEL, 163 PCI_PRODUCT_INTEL_100SERIES_LP_EMMC, 164 0xffff, 165 0xffff, 166 ~0, 167 SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET 168 }, 169 }; 170 171 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 172 static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *); 173 static void sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *, 174 struct sdhc_host *); 175 176 static uint32_t 177 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 178 { 179 const struct sdhc_pci_quirk *q; 180 pcireg_t id; 181 pci_vendor_id_t vendor; 182 pci_product_id_t product; 183 int i; 184 185 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 186 q = &sdhc_pci_quirk_table[i]; 187 188 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 189 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 190 if ((q->function != ~0) 191 && (pa->pa_function != q->function)) 192 continue; 193 194 if ((q->subvendor == 0xffff) 195 && (q->subproduct == 0xffff)) 196 return (q->flags); 197 198 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 199 PCI_SUBSYS_ID_REG); 200 vendor = PCI_VENDOR(id); 201 product = PCI_PRODUCT(id); 202 203 if ((q->subvendor != 0xffff) 204 && (q->subproduct != 0xffff)) { 205 if ((vendor == q->subvendor) 206 && (product == q->subproduct)) 207 return (q->flags); 208 } else if (q->subvendor != 0xffff) { 209 if (product == q->subproduct) 210 return (q->flags); 211 } else { 212 if (vendor == q->subvendor) 213 return (q->flags); 214 } 215 } 216 } 217 return (0); 218 } 219 220 static int 221 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 222 { 223 struct pci_attach_args *pa = aux; 224 225 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 226 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 227 return (1); 228 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH && 229 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 || 230 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823)) 231 return (1); 232 return (0); 233 } 234 235 static void 236 sdhc_pci_attach(device_t parent, device_t self, void *aux) 237 { 238 struct sdhc_pci_softc *sc = device_private(self); 239 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 240 pci_chipset_tag_t pc = pa->pa_pc; 241 pcitag_t tag = pa->pa_tag; 242 pci_intr_handle_t ih; 243 pcireg_t csr; 244 pcireg_t slotinfo; 245 char const *intrstr; 246 int nslots; 247 int reg; 248 int cnt; 249 bus_space_tag_t iot; 250 bus_space_handle_t ioh; 251 bus_size_t size; 252 uint32_t flags; 253 char intrbuf[PCI_INTRSTR_LEN]; 254 255 sc->sc.sc_dev = self; 256 sc->sc.sc_dmat = pa->pa_dmat; 257 sc->sc.sc_host = NULL; 258 259 sc->sc_pc = pc; 260 261 pci_aprint_devinfo(pa, NULL); 262 263 /* Some controllers needs special treatment. */ 264 flags = sdhc_pci_lookup_quirk_flags(pa); 265 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 266 sdhc_pci_quirk_ti_hack(pa); 267 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 268 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 269 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 270 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 271 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK)) 272 sdhc_pci_quirk_ricoh_lower_freq_hack(pa); 273 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_SLOW_SDR50_HACK)) 274 SET(sc->sc.sc_flags, SDHC_FLAG_SLOW_SDR50); 275 if (ISSET(flags, SDHC_PCI_QUIRK_INTEL_EMMC_HW_RESET)) 276 sc->sc.sc_vendor_hw_reset = sdhc_pci_intel_emmc_hw_reset; 277 278 /* 279 * Map and attach all hosts supported by the host controller. 280 */ 281 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 282 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 283 284 /* Allocate an array big enough to hold all the possible hosts */ 285 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 286 M_DEVBUF, M_WAITOK | M_ZERO); 287 288 /* Enable the device. */ 289 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 290 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 291 csr | PCI_COMMAND_MASTER_ENABLE); 292 293 /* Map and establish the interrupt. */ 294 if (pci_intr_map(pa, &ih)) { 295 aprint_error_dev(self, "couldn't map interrupt\n"); 296 goto err; 297 } 298 299 intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf)); 300 sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_SDMMC, sdhc_intr, 301 &sc->sc, device_xname(self)); 302 if (sc->sc_ih == NULL) { 303 aprint_error_dev(self, "couldn't establish interrupt\n"); 304 goto err; 305 } 306 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 307 308 /* Enable use of DMA if supported by the interface. */ 309 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 310 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 311 312 /* XXX: handle 64-bit BARs */ 313 cnt = 0; 314 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 315 sizeof(uint32_t); 316 reg < SDHC_PCI_BAR_END && nslots > 0; 317 reg += sizeof(uint32_t), nslots--) { 318 if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0, 319 &iot, &ioh, NULL, &size)) { 320 continue; 321 } 322 323 cnt++; 324 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 325 /* XXX: sc->sc_host leak */ 326 aprint_error_dev(self, 327 "couldn't initialize host (0x%x)\n", reg); 328 } 329 } 330 if (cnt == 0) { 331 aprint_error_dev(self, "couldn't map register\n"); 332 goto err; 333 } 334 335 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 336 sdhc_shutdown)) { 337 aprint_error_dev(self, "couldn't establish powerhook\n"); 338 } 339 340 return; 341 342 err: 343 if (sc->sc.sc_host != NULL) { 344 free(sc->sc.sc_host, M_DEVBUF); 345 sc->sc.sc_host = NULL; 346 } 347 } 348 349 static int 350 sdhc_pci_detach(device_t self, int flags) 351 { 352 struct sdhc_pci_softc * const sc = device_private(self); 353 int rv; 354 355 rv = sdhc_detach(&sc->sc, flags); 356 if (rv) 357 return rv; 358 359 if (sc->sc_ih != NULL) { 360 pci_intr_disestablish(sc->sc_pc, sc->sc_ih); 361 sc->sc_ih = NULL; 362 } 363 364 if (sc->sc.sc_host != NULL) { 365 free(sc->sc.sc_host, M_DEVBUF); 366 sc->sc.sc_host = NULL; 367 } 368 369 return rv; 370 } 371 372 static void 373 sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val) 374 { 375 pcireg_t r; 376 377 r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 378 r &= ~(0xff << ((reg & 0x3) * 8)); 379 r |= (val << ((reg & 0x3) * 8)); 380 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r); 381 } 382 383 /* TI specific register */ 384 #define SDHC_PCI_GENERAL_CTL 0x4c 385 #define MMC_SD_DIS 0x02 386 387 static void 388 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 389 { 390 pci_chipset_tag_t pc = pa->pa_pc; 391 pcitag_t tag; 392 pcireg_t id, reg; 393 394 /* Look at func - 1 for the flash device */ 395 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1); 396 id = pci_conf_read(pc, tag, PCI_ID_REG); 397 if (PCI_VENDOR(id) != PCI_VENDOR_TI) { 398 return; 399 } 400 switch (PCI_PRODUCT(id)) { 401 case PCI_PRODUCT_TI_PCI72111FM: 402 case PCI_PRODUCT_TI_PCIXX12FM: 403 break; 404 default: 405 return; 406 } 407 408 /* 409 * Disable MMC/SD on the flash media controller so the 410 * SD host takes over. 411 */ 412 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 413 reg |= MMC_SD_DIS; 414 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 415 } 416 417 /* Ricoh specific register */ 418 #define SDHC_PCI_MODE_KEY 0xf9 419 #define SDHC_PCI_MODE 0x150 420 #define SDHC_PCI_MODE_SD20 0x10 421 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 422 #define SDHC_PCI_BASE_FREQ 0xe1 423 424 /* Some RICOH controllers need to be bumped into the right mode. */ 425 static void 426 sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa) 427 { 428 /* Enable SD2.0 mode. */ 429 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc); 430 sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20); 431 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00); 432 433 /* 434 * Some SD/MMC cards don't work with the default base 435 * clock frequency of 200MHz. Lower it to 50MHz. 436 */ 437 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01); 438 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50); 439 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00); 440 } 441 442 static void 443 sdhc_pci_intel_emmc_hw_reset(struct sdhc_softc *sc, struct sdhc_host *hp) 444 { 445 kmutex_t *plock = sdhc_host_lock(hp); 446 uint8_t reg; 447 448 mutex_enter(plock); 449 450 reg = sdhc_host_read_1(hp, SDHC_POWER_CTL); 451 reg |= 0x10; 452 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 453 454 sdmmc_delay(10); 455 456 reg &= ~0x10; 457 sdhc_host_write_1(hp, SDHC_POWER_CTL, reg); 458 459 sdmmc_delay(1000); 460 461 mutex_exit(plock); 462 } 463
Indexes created Wed Oct 22 13:09:56 GMT 2025