sdhc_pci.c revision 1.7
1 /* $NetBSD: sdhc_pci.c,v 1.7 2012/03/02 18:20:33 nonaka Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.7 2012/03/02 18:20:33 nonaka Exp $"); 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/systm.h> 30 #include <sys/malloc.h> 31 #include <sys/pmf.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 36 #include <dev/sdmmc/sdhcreg.h> 37 #include <dev/sdmmc/sdhcvar.h> 38 #include <dev/sdmmc/sdmmcvar.h> 39 40 /* PCI base address registers */ 41 #define SDHC_PCI_BAR_START PCI_MAPREG_START 42 #define SDHC_PCI_BAR_END PCI_MAPREG_END 43 44 /* PCI interface classes */ 45 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 46 #define SDHC_PCI_INTERFACE_DMA 0x01 47 #define SDHC_PCI_INTERFACE_VENDOR 0x02 48 49 /* 50 * 8-bit PCI configuration register that tells us how many slots there 51 * are and which BAR entry corresponds to the first slot. 52 */ 53 #define SDHC_PCI_CONF_SLOT_INFO 0x40 54 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 55 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 56 57 struct sdhc_pci_softc { 58 struct sdhc_softc sc; 59 void *sc_ih; 60 }; 61 62 static int sdhc_pci_match(device_t, cfdata_t, void *); 63 static void sdhc_pci_attach(device_t, device_t, void *); 64 65 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 66 sdhc_pci_match, sdhc_pci_attach, NULL, NULL); 67 68 #ifdef SDHC_DEBUG 69 #define DPRINTF(s) printf s 70 #else 71 #define DPRINTF(s) /**/ 72 #endif 73 74 static const struct sdhc_pci_quirk { 75 pci_vendor_id_t vendor; 76 pci_product_id_t product; 77 pci_vendor_id_t subvendor; 78 pci_product_id_t subproduct; 79 u_int function; 80 81 uint32_t flags; 82 #define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0) 83 #define SDHC_PCI_QUIRK_TI_HACK (1U << 1) 84 #define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2) 85 #define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK (1U << 3) 86 } sdhc_pci_quirk_table[] = { 87 { 88 PCI_VENDOR_TI, 89 PCI_PRODUCT_TI_PCI72111SD, 90 0xffff, 91 0xffff, 92 4, 93 SDHC_PCI_QUIRK_TI_HACK 94 }, 95 96 { 97 PCI_VENDOR_TI, 98 PCI_PRODUCT_TI_PCIXX12SD, 99 0xffff, 100 0xffff, 101 3, 102 SDHC_PCI_QUIRK_TI_HACK 103 }, 104 105 { 106 PCI_VENDOR_ENE, 107 PCI_PRODUCT_ENE_CB712, 108 0xffff, 109 0xffff, 110 0, 111 SDHC_PCI_QUIRK_NO_PWR0 112 }, 113 114 { 115 PCI_VENDOR_RICOH, 116 PCI_PRODUCT_RICOH_Rx5U823, 117 0xffff, 118 0xffff, 119 0, 120 SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK 121 }, 122 }; 123 124 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 125 static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *); 126 127 static uint32_t 128 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 129 { 130 const struct sdhc_pci_quirk *q; 131 pcireg_t id; 132 pci_vendor_id_t vendor; 133 pci_product_id_t product; 134 int i; 135 136 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 137 q = &sdhc_pci_quirk_table[i]; 138 139 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 140 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 141 if ((q->function != ~0) 142 && (pa->pa_function != q->function)) 143 continue; 144 145 if ((q->subvendor == 0xffff) 146 && (q->subproduct == 0xffff)) 147 return (q->flags); 148 149 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 150 PCI_SUBSYS_ID_REG); 151 vendor = PCI_VENDOR(id); 152 product = PCI_PRODUCT(id); 153 154 if ((q->subvendor != 0xffff) 155 && (q->subproduct != 0xffff)) { 156 if ((vendor == q->subvendor) 157 && (product == q->subproduct)) 158 return (q->flags); 159 } else if (q->subvendor != 0xffff) { 160 if (product == q->subproduct) 161 return (q->flags); 162 } else { 163 if (vendor == q->subvendor) 164 return (q->flags); 165 } 166 } 167 } 168 return (0); 169 } 170 171 static int 172 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 173 { 174 struct pci_attach_args *pa = aux; 175 176 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 177 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 178 return (1); 179 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH && 180 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 || 181 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823)) 182 return (1); 183 return (0); 184 } 185 186 static void 187 sdhc_pci_attach(device_t parent, device_t self, void *aux) 188 { 189 struct sdhc_pci_softc *sc = device_private(self); 190 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 191 pci_chipset_tag_t pc = pa->pa_pc; 192 pcitag_t tag = pa->pa_tag; 193 pci_intr_handle_t ih; 194 pcireg_t csr; 195 pcireg_t slotinfo; 196 char const *intrstr; 197 int nslots; 198 int reg; 199 int cnt; 200 bus_space_tag_t iot; 201 bus_space_handle_t ioh; 202 bus_size_t size; 203 uint32_t flags; 204 205 sc->sc.sc_dev = self; 206 sc->sc.sc_dmat = pa->pa_dmat; 207 sc->sc.sc_host = NULL; 208 209 pci_aprint_devinfo(pa, NULL); 210 211 /* Some controllers needs special treatment. */ 212 flags = sdhc_pci_lookup_quirk_flags(pa); 213 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 214 sdhc_pci_quirk_ti_hack(pa); 215 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 216 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 217 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 218 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 219 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK)) 220 sdhc_pci_quirk_ricoh_lower_freq_hack(pa); 221 222 /* 223 * Map and attach all hosts supported by the host controller. 224 */ 225 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 226 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 227 228 /* Allocate an array big enough to hold all the possible hosts */ 229 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 230 M_DEVBUF, M_NOWAIT | M_ZERO); 231 if (sc->sc.sc_host == NULL) { 232 aprint_error_dev(self, "couldn't alloc memory\n"); 233 goto err; 234 } 235 236 /* Enable the device. */ 237 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 238 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 239 csr | PCI_COMMAND_MASTER_ENABLE); 240 241 /* Map and establish the interrupt. */ 242 if (pci_intr_map(pa, &ih)) { 243 aprint_error_dev(self, "couldn't map interrupt\n"); 244 goto err; 245 } 246 247 intrstr = pci_intr_string(pc, ih); 248 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, sdhc_intr, &sc->sc); 249 if (sc->sc_ih == NULL) { 250 aprint_error_dev(self, "couldn't establish interrupt\n"); 251 goto err; 252 } 253 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 254 255 /* Enable use of DMA if supported by the interface. */ 256 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 257 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 258 259 /* XXX: handle 64-bit BARs */ 260 cnt = 0; 261 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 262 sizeof(uint32_t); 263 reg < SDHC_PCI_BAR_END && nslots > 0; 264 reg += sizeof(uint32_t), nslots--) { 265 if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0, 266 &iot, &ioh, NULL, &size)) { 267 continue; 268 } 269 270 cnt++; 271 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 272 /* XXX: sc->sc_host leak */ 273 aprint_error_dev(self, 274 "couldn't initialize host (0x%x)\n", reg); 275 } 276 } 277 if (cnt == 0) { 278 aprint_error_dev(self, "couldn't map register\n"); 279 goto err; 280 } 281 282 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 283 sdhc_shutdown)) { 284 aprint_error_dev(self, "couldn't establish powerhook\n"); 285 } 286 287 return; 288 289 err: 290 if (sc->sc.sc_host != NULL) 291 free(sc->sc.sc_host, M_DEVBUF); 292 } 293 294 static void 295 sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val) 296 { 297 pcireg_t r; 298 299 r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 300 r &= ~(0xff << ((reg & 0x3) * 8)); 301 r |= (val << ((reg & 0x3) * 8)); 302 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r); 303 } 304 305 /* TI specific register */ 306 #define SDHC_PCI_GENERAL_CTL 0x4c 307 #define MMC_SD_DIS 0x02 308 309 static void 310 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 311 { 312 pci_chipset_tag_t pc = pa->pa_pc; 313 pcitag_t tag; 314 pcireg_t id, reg; 315 316 /* Look at func - 1 for the flash device */ 317 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1); 318 id = pci_conf_read(pc, tag, PCI_ID_REG); 319 if (PCI_VENDOR(id) != PCI_VENDOR_TI) { 320 return; 321 } 322 switch (PCI_PRODUCT(id)) { 323 case PCI_PRODUCT_TI_PCI72111FM: 324 case PCI_PRODUCT_TI_PCIXX12FM: 325 break; 326 default: 327 return; 328 } 329 330 /* 331 * Disable MMC/SD on the flash media controller so the 332 * SD host takes over. 333 */ 334 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 335 reg |= MMC_SD_DIS; 336 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 337 } 338 339 /* Ricoh specific register */ 340 #define SDHC_PCI_MODE_KEY 0xf9 341 #define SDHC_PCI_MODE 0x150 342 #define SDHC_PCI_MODE_SD20 0x10 343 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 344 #define SDHC_PCI_BASE_FREQ 0xe1 345 346 /* Some RICOH controllers need to be bumped into the right mode. */ 347 static void 348 sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa) 349 { 350 351 /* Enable SD2.0 mode. */ 352 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc); 353 sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20); 354 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00); 355 356 /* 357 * Some SD/MMC cards don't work with the default base 358 * clock frequency of 200MHz. Lower it to 50Hz. 359 */ 360 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01); 361 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50); 362 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00); 363 } 364
Indexes created Thu Oct 23 18:09:57 GMT 2025