sdhc_pci.c revision 1.8
1 /* $NetBSD: sdhc_pci.c,v 1.8 2012/07/12 17:37:24 jakllsch Exp $ */ 2 /* $OpenBSD: sdhc_pci.c,v 1.7 2007/10/30 18:13:45 chl Exp $ */ 3 4 /* 5 * Copyright (c) 2006 Uwe Stuehler <uwe (at) openbsd.org> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include <sys/cdefs.h> 21 __KERNEL_RCSID(0, "$NetBSD: sdhc_pci.c,v 1.8 2012/07/12 17:37:24 jakllsch Exp $"); 22 23 #ifdef _KERNEL_OPT 24 #include "opt_sdmmc.h" 25 #endif 26 27 #include <sys/param.h> 28 #include <sys/device.h> 29 #include <sys/systm.h> 30 #include <sys/malloc.h> 31 #include <sys/pmf.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 36 #include <dev/sdmmc/sdhcreg.h> 37 #include <dev/sdmmc/sdhcvar.h> 38 #include <dev/sdmmc/sdmmcvar.h> 39 40 /* PCI base address registers */ 41 #define SDHC_PCI_BAR_START PCI_MAPREG_START 42 #define SDHC_PCI_BAR_END PCI_MAPREG_END 43 44 /* PCI interface classes */ 45 #define SDHC_PCI_INTERFACE_NO_DMA 0x00 46 #define SDHC_PCI_INTERFACE_DMA 0x01 47 #define SDHC_PCI_INTERFACE_VENDOR 0x02 48 49 /* 50 * 8-bit PCI configuration register that tells us how many slots there 51 * are and which BAR entry corresponds to the first slot. 52 */ 53 #define SDHC_PCI_CONF_SLOT_INFO 0x40 54 #define SDHC_PCI_NUM_SLOTS(info) ((((info) >> 4) & 0x7) + 1) 55 #define SDHC_PCI_FIRST_BAR(info) ((info) & 0x7) 56 57 struct sdhc_pci_softc { 58 struct sdhc_softc sc; 59 void *sc_ih; 60 }; 61 62 static int sdhc_pci_match(device_t, cfdata_t, void *); 63 static void sdhc_pci_attach(device_t, device_t, void *); 64 65 CFATTACH_DECL_NEW(sdhc_pci, sizeof(struct sdhc_pci_softc), 66 sdhc_pci_match, sdhc_pci_attach, NULL, NULL); 67 68 #ifdef SDHC_DEBUG 69 #define DPRINTF(s) printf s 70 #else 71 #define DPRINTF(s) /**/ 72 #endif 73 74 static const struct sdhc_pci_quirk { 75 pci_vendor_id_t vendor; 76 pci_product_id_t product; 77 pci_vendor_id_t subvendor; 78 pci_product_id_t subproduct; 79 u_int function; 80 81 uint32_t flags; 82 #define SDHC_PCI_QUIRK_FORCE_DMA (1U << 0) 83 #define SDHC_PCI_QUIRK_TI_HACK (1U << 1) 84 #define SDHC_PCI_QUIRK_NO_PWR0 (1U << 2) 85 #define SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK (1U << 3) 86 } sdhc_pci_quirk_table[] = { 87 { 88 PCI_VENDOR_TI, 89 PCI_PRODUCT_TI_PCI72111SD, 90 0xffff, 91 0xffff, 92 4, 93 SDHC_PCI_QUIRK_TI_HACK 94 }, 95 96 { 97 PCI_VENDOR_TI, 98 PCI_PRODUCT_TI_PCIXX12SD, 99 0xffff, 100 0xffff, 101 3, 102 SDHC_PCI_QUIRK_TI_HACK 103 }, 104 105 { 106 PCI_VENDOR_ENE, 107 PCI_PRODUCT_ENE_CB712, 108 0xffff, 109 0xffff, 110 0, 111 SDHC_PCI_QUIRK_NO_PWR0 112 }, 113 114 { 115 PCI_VENDOR_RICOH, 116 PCI_PRODUCT_RICOH_Rx5U823, 117 0xffff, 118 0xffff, 119 0, 120 SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK 121 }, 122 123 { 124 PCI_VENDOR_RICOH, 125 PCI_PRODUCT_RICOH_Rx5C822, 126 0xffff, 127 0xffff, 128 ~0, 129 SDHC_PCI_QUIRK_FORCE_DMA 130 }, 131 }; 132 133 static void sdhc_pci_quirk_ti_hack(struct pci_attach_args *); 134 static void sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *); 135 136 static uint32_t 137 sdhc_pci_lookup_quirk_flags(struct pci_attach_args *pa) 138 { 139 const struct sdhc_pci_quirk *q; 140 pcireg_t id; 141 pci_vendor_id_t vendor; 142 pci_product_id_t product; 143 int i; 144 145 for (i = 0; i < __arraycount(sdhc_pci_quirk_table); i++) { 146 q = &sdhc_pci_quirk_table[i]; 147 148 if ((PCI_VENDOR(pa->pa_id) == q->vendor) 149 && (PCI_PRODUCT(pa->pa_id) == q->product)) { 150 if ((q->function != ~0) 151 && (pa->pa_function != q->function)) 152 continue; 153 154 if ((q->subvendor == 0xffff) 155 && (q->subproduct == 0xffff)) 156 return (q->flags); 157 158 id = pci_conf_read(pa->pa_pc, pa->pa_tag, 159 PCI_SUBSYS_ID_REG); 160 vendor = PCI_VENDOR(id); 161 product = PCI_PRODUCT(id); 162 163 if ((q->subvendor != 0xffff) 164 && (q->subproduct != 0xffff)) { 165 if ((vendor == q->subvendor) 166 && (product == q->subproduct)) 167 return (q->flags); 168 } else if (q->subvendor != 0xffff) { 169 if (product == q->subproduct) 170 return (q->flags); 171 } else { 172 if (vendor == q->subvendor) 173 return (q->flags); 174 } 175 } 176 } 177 return (0); 178 } 179 180 static int 181 sdhc_pci_match(device_t parent, cfdata_t cf, void *aux) 182 { 183 struct pci_attach_args *pa = aux; 184 185 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_SYSTEM && 186 PCI_SUBCLASS(pa->pa_class) == PCI_SUBCLASS_SYSTEM_SDHC) 187 return (1); 188 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_RICOH && 189 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U822 || 190 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_RICOH_Rx5U823)) 191 return (1); 192 return (0); 193 } 194 195 static void 196 sdhc_pci_attach(device_t parent, device_t self, void *aux) 197 { 198 struct sdhc_pci_softc *sc = device_private(self); 199 struct pci_attach_args *pa = (struct pci_attach_args *)aux; 200 pci_chipset_tag_t pc = pa->pa_pc; 201 pcitag_t tag = pa->pa_tag; 202 pci_intr_handle_t ih; 203 pcireg_t csr; 204 pcireg_t slotinfo; 205 char const *intrstr; 206 int nslots; 207 int reg; 208 int cnt; 209 bus_space_tag_t iot; 210 bus_space_handle_t ioh; 211 bus_size_t size; 212 uint32_t flags; 213 214 sc->sc.sc_dev = self; 215 sc->sc.sc_dmat = pa->pa_dmat; 216 sc->sc.sc_host = NULL; 217 218 pci_aprint_devinfo(pa, NULL); 219 220 /* Some controllers needs special treatment. */ 221 flags = sdhc_pci_lookup_quirk_flags(pa); 222 if (ISSET(flags, SDHC_PCI_QUIRK_TI_HACK)) 223 sdhc_pci_quirk_ti_hack(pa); 224 if (ISSET(flags, SDHC_PCI_QUIRK_FORCE_DMA)) 225 SET(sc->sc.sc_flags, SDHC_FLAG_FORCE_DMA); 226 if (ISSET(flags, SDHC_PCI_QUIRK_NO_PWR0)) 227 SET(sc->sc.sc_flags, SDHC_FLAG_NO_PWR0); 228 if (ISSET(flags, SDHC_PCI_QUIRK_RICOH_LOWER_FREQ_HACK)) 229 sdhc_pci_quirk_ricoh_lower_freq_hack(pa); 230 231 /* 232 * Map and attach all hosts supported by the host controller. 233 */ 234 slotinfo = pci_conf_read(pc, tag, SDHC_PCI_CONF_SLOT_INFO); 235 nslots = SDHC_PCI_NUM_SLOTS(slotinfo); 236 237 /* Allocate an array big enough to hold all the possible hosts */ 238 sc->sc.sc_host = malloc(sizeof(struct sdhc_host *) * nslots, 239 M_DEVBUF, M_NOWAIT | M_ZERO); 240 if (sc->sc.sc_host == NULL) { 241 aprint_error_dev(self, "couldn't alloc memory\n"); 242 goto err; 243 } 244 245 /* Enable the device. */ 246 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 247 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, 248 csr | PCI_COMMAND_MASTER_ENABLE); 249 250 /* Map and establish the interrupt. */ 251 if (pci_intr_map(pa, &ih)) { 252 aprint_error_dev(self, "couldn't map interrupt\n"); 253 goto err; 254 } 255 256 intrstr = pci_intr_string(pc, ih); 257 sc->sc_ih = pci_intr_establish(pc, ih, IPL_SDMMC, sdhc_intr, &sc->sc); 258 if (sc->sc_ih == NULL) { 259 aprint_error_dev(self, "couldn't establish interrupt\n"); 260 goto err; 261 } 262 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 263 264 /* Enable use of DMA if supported by the interface. */ 265 if ((PCI_INTERFACE(pa->pa_class) == SDHC_PCI_INTERFACE_DMA)) 266 SET(sc->sc.sc_flags, SDHC_FLAG_USE_DMA); 267 268 /* XXX: handle 64-bit BARs */ 269 cnt = 0; 270 for (reg = SDHC_PCI_BAR_START + SDHC_PCI_FIRST_BAR(slotinfo) * 271 sizeof(uint32_t); 272 reg < SDHC_PCI_BAR_END && nslots > 0; 273 reg += sizeof(uint32_t), nslots--) { 274 if (pci_mapreg_map(pa, reg, PCI_MAPREG_TYPE_MEM, 0, 275 &iot, &ioh, NULL, &size)) { 276 continue; 277 } 278 279 cnt++; 280 if (sdhc_host_found(&sc->sc, iot, ioh, size) != 0) { 281 /* XXX: sc->sc_host leak */ 282 aprint_error_dev(self, 283 "couldn't initialize host (0x%x)\n", reg); 284 } 285 } 286 if (cnt == 0) { 287 aprint_error_dev(self, "couldn't map register\n"); 288 goto err; 289 } 290 291 if (!pmf_device_register1(self, sdhc_suspend, sdhc_resume, 292 sdhc_shutdown)) { 293 aprint_error_dev(self, "couldn't establish powerhook\n"); 294 } 295 296 return; 297 298 err: 299 if (sc->sc.sc_host != NULL) 300 free(sc->sc.sc_host, M_DEVBUF); 301 } 302 303 static void 304 sdhc_pci_conf_write(struct pci_attach_args *pa, int reg, uint8_t val) 305 { 306 pcireg_t r; 307 308 r = pci_conf_read(pa->pa_pc, pa->pa_tag, reg & ~0x3); 309 r &= ~(0xff << ((reg & 0x3) * 8)); 310 r |= (val << ((reg & 0x3) * 8)); 311 pci_conf_write(pa->pa_pc, pa->pa_tag, reg & ~0x3, r); 312 } 313 314 /* TI specific register */ 315 #define SDHC_PCI_GENERAL_CTL 0x4c 316 #define MMC_SD_DIS 0x02 317 318 static void 319 sdhc_pci_quirk_ti_hack(struct pci_attach_args *pa) 320 { 321 pci_chipset_tag_t pc = pa->pa_pc; 322 pcitag_t tag; 323 pcireg_t id, reg; 324 325 /* Look at func - 1 for the flash device */ 326 tag = pci_make_tag(pc, pa->pa_bus, pa->pa_device, pa->pa_function - 1); 327 id = pci_conf_read(pc, tag, PCI_ID_REG); 328 if (PCI_VENDOR(id) != PCI_VENDOR_TI) { 329 return; 330 } 331 switch (PCI_PRODUCT(id)) { 332 case PCI_PRODUCT_TI_PCI72111FM: 333 case PCI_PRODUCT_TI_PCIXX12FM: 334 break; 335 default: 336 return; 337 } 338 339 /* 340 * Disable MMC/SD on the flash media controller so the 341 * SD host takes over. 342 */ 343 reg = pci_conf_read(pc, tag, SDHC_PCI_GENERAL_CTL); 344 reg |= MMC_SD_DIS; 345 pci_conf_write(pc, tag, SDHC_PCI_GENERAL_CTL, reg); 346 } 347 348 /* Ricoh specific register */ 349 #define SDHC_PCI_MODE_KEY 0xf9 350 #define SDHC_PCI_MODE 0x150 351 #define SDHC_PCI_MODE_SD20 0x10 352 #define SDHC_PCI_BASE_FREQ_KEY 0xfc 353 #define SDHC_PCI_BASE_FREQ 0xe1 354 355 /* Some RICOH controllers need to be bumped into the right mode. */ 356 static void 357 sdhc_pci_quirk_ricoh_lower_freq_hack(struct pci_attach_args *pa) 358 { 359 360 /* Enable SD2.0 mode. */ 361 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0xfc); 362 sdhc_pci_conf_write(pa, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20); 363 sdhc_pci_conf_write(pa, SDHC_PCI_MODE_KEY, 0x00); 364 365 /* 366 * Some SD/MMC cards don't work with the default base 367 * clock frequency of 200MHz. Lower it to 50Hz. 368 */ 369 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x01); 370 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ, 50); 371 sdhc_pci_conf_write(pa, SDHC_PCI_BASE_FREQ_KEY, 0x00); 372 } 373
Indexes created Thu Oct 23 18:09:57 GMT 2025