siisata_pci.c revision 1.1
1/* $NetBSD: siisata_pci.c,v 1.1 2008/05/23 21:11:40 jnemeth Exp $ */ 2/* Id: siisata_pci.c,v 1.11 2008/05/21 16:20:11 jakllsch Exp */ 3 4/* 5 * Copyright (c) 2006 Manuel Bouyer. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 */ 33 34/*- 35 * Copyright (c) 2007, 2008 Jonathan A. Kollasch. 36 * All rights reserved. 37 * 38 * Redistribution and use in source and binary forms, with or without 39 * modification, are permitted provided that the following conditions 40 * are met: 41 * 1. Redistributions of source code must retain the above copyright 42 * notice, this list of conditions and the following disclaimer. 43 * 2. Redistributions in binary form must reproduce the above copyright 44 * notice, this list of conditions and the following disclaimer in the 45 * documentation and/or other materials provided with the distribution. 46 * 47 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 48 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 49 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 50 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 52 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 53 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 54 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 55 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 56 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 57 * 58 */ 59 60#include <sys/cdefs.h> 61 62 63#include <sys/types.h> 64#include <sys/malloc.h> 65#include <sys/param.h> 66#include <sys/kernel.h> 67#include <sys/systm.h> 68 69#include <uvm/uvm_extern.h> 70 71#include <dev/pci/pcivar.h> 72#include <dev/pci/pcidevs.h> 73#include <dev/ic/siisatavar.h> 74 75struct siisata_pci_softc { 76 struct siisata_softc si_sc; 77 pci_chipset_tag_t sc_pc; 78 pcitag_t sc_pcitag; 79}; 80 81static int siisata_pci_match(device_t, cfdata_t, void *); 82static void siisata_pci_attach(device_t, device_t, void *); 83static bool siisata_pci_resume(device_t PMF_FN_PROTO); 84 85static const struct siisata_pci_product { 86 pci_vendor_id_t spp_vendor; 87 pci_product_id_t spp_product; 88 int spp_ports; 89 int spp_chip; 90 91} siisata_pci_products[] = { 92 { 93 PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3124, 94 4, 3124 95 }, 96 { 97 PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3132, 98 2, 3132 99 }, 100 { 101 PCI_VENDOR_CMDTECH, PCI_PRODUCT_CMDTECH_3531, 102 1, 3531 103 }, 104 { 105 0, 0, 106 0, 0 107 }, 108}; 109 110CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc), 111 siisata_pci_match, siisata_pci_attach, NULL, NULL); 112 113static const struct siisata_pci_product * 114siisata_pci_lookup(const struct pci_attach_args * pa) 115{ 116 const struct siisata_pci_product *spp; 117 118 for (spp = siisata_pci_products; spp->spp_ports > 0; spp++) { 119 if (PCI_VENDOR(pa->pa_id) == spp->spp_vendor && 120 PCI_PRODUCT(pa->pa_id) == spp->spp_product) 121 return spp; 122 } 123 return NULL; 124} 125 126static int 127siisata_pci_match(device_t parent, cfdata_t match, void *aux) 128{ 129 struct pci_attach_args *pa = aux; 130 131 if (siisata_pci_lookup(pa) != NULL) 132 return 3; 133 134 return 0; 135} 136 137static bool 138siisata_pci_resume(device_t dv PMF_FN_ARGS) 139{ 140 struct siisata_pci_softc *psc = device_private(dv); 141 struct siisata_softc *sc = &psc->si_sc; 142 int s; 143 144 s = splbio(); 145 siisata_resume(sc); 146 splx(s); 147 148 return true; 149} 150 151static void 152siisata_pci_attach(device_t parent, device_t self, void *aux) 153{ 154 struct pci_attach_args *pa = aux; 155 struct siisata_pci_softc *psc = device_private(self); 156 struct siisata_softc *sc = &psc->si_sc; 157 char devinfo[256]; 158 const char *intrstr; 159 pci_intr_handle_t intrhandle; 160 pcireg_t csr, memtype; 161 const struct siisata_pci_product *spp; 162 void *ih; 163 bus_space_tag_t memt; 164 bus_space_handle_t memh; 165 uint32_t gcreg; 166 int memh_valid; 167 bus_size_t grsize, prsize; 168 169 sc->sc_atac.atac_dev = self; 170 171 psc->sc_pc = pa->pa_pc; 172 psc->sc_pcitag = pa->pa_tag; 173 174 pci_devinfo(pa->pa_id, pa->pa_class, 1, devinfo, sizeof(devinfo)); 175 aprint_naive(": SATA-II HBA\n"); 176 aprint_normal(": %s\n", devinfo); 177 178 /* map bar0 */ 179#if 1 180 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0); 181#else 182 memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; 183#endif 184 switch (memtype) { 185 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 186 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 187 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0, 188 memtype, 0, &memt, &memh, NULL, &grsize) == 0); 189 break; 190 default: 191 memh_valid = 0; 192 } 193 if (memh_valid) { 194 sc->sc_grt = memt; 195 sc->sc_grh = memh; 196 } else { 197 aprint_error("%s: unable to map device global registers\n", 198 SIISATANAME(sc)); 199 return; 200 } 201 202 /* map bar1 */ 203#if 1 204 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1); 205#else 206 memtype = PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT; 207#endif 208 switch (memtype) { 209 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 210 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 211 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1, 212 memtype, 0, &memt, &memh, NULL, &prsize) == 0); 213 break; 214 default: 215 memh_valid = 0; 216 } 217 if (memh_valid) { 218 sc->sc_prt = memt; 219 sc->sc_prh = memh; 220 } else { 221 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 222 aprint_error("%s: unable to map device port registers\n", 223 SIISATANAME(sc)); 224 return; 225 } 226 227 if (pci_dma64_available(pa)) { 228 sc->sc_dmat = pa->pa_dmat64; 229 sc->sc_have_dma64 = 1; 230 aprint_debug("64-bit PCI DMA available\n"); 231 } else { 232 sc->sc_dmat = pa->pa_dmat; 233 sc->sc_have_dma64 = 0; 234 } 235 236 /* map interrupt */ 237 if (pci_intr_map(pa, &intrhandle) != 0) { 238 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 239 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 240 aprint_error("%s: couldn't map interrupt\n", SIISATANAME(sc)); 241 return; 242 } 243 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 244 ih = pci_intr_establish(pa->pa_pc, intrhandle, 245 IPL_BIO, siisata_intr, sc); 246 if (ih == NULL) { 247 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 248 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 249 aprint_error("%s: couldn't establish interrupt" 250 "at %s\n", SIISATANAME(sc), intrstr); 251 return; 252 } 253 aprint_normal("%s: interrupting at %s\n", SIISATANAME(sc), 254 intrstr ? intrstr : "unknown interrupt"); 255 256 /* fill in number of ports on this device */ 257 spp = siisata_pci_lookup(pa); 258 if (spp != NULL) { 259 sc->sc_atac.atac_nchannels = spp->spp_ports; 260 sc->sc_chip = spp->spp_chip; 261 } else 262 /* _match() should prevent us from getting here */ 263 panic("siisata: the universe might be falling apart!\n"); 264 265 gcreg = GRREAD(sc, GR_GC); 266 267 aprint_normal("%s: SiI%d on ", SIISATANAME(sc), sc->sc_chip); 268 if (sc->sc_chip == 3124) { 269 aprint_normal("%d-bit, ", (gcreg & GR_GC_REQ64) ? 64 : 32); 270 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) { 271 case 0: 272 aprint_normal("%d", (gcreg & GR_GC_M66EN) ? 66 : 33); 273 break; 274 case GR_GC_TRDY: 275 aprint_normal("%d", 66); 276 break; 277 case GR_GC_STOP: 278 aprint_normal("%d", 100); 279 break; 280 case GR_GC_STOP | GR_GC_TRDY: 281 aprint_normal("%d", 133); 282 break; 283 default: 284 break; 285 } 286 aprint_normal("MHz PCI%s bus.", (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) ? "-X" : ""); 287 } else { 288 /* XXX - but only x1 devices so far */ 289 aprint_normal("PCI-Express x1 port."); 290 } 291 if (gcreg & GR_GC_3GBPS) 292 aprint_normal(" 3.0Gb/s capable.\n"); 293 else 294 aprint_normal("\n"); 295 296 /* enable bus mastering in case the firmware didn't */ 297 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 298 csr |= PCI_COMMAND_MASTER_ENABLE; 299 csr |= PCI_COMMAND_MEM_ENABLE; 300 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 301 302 siisata_attach(sc); 303 304 if (!pmf_device_register(self, NULL, siisata_pci_resume)) 305 aprint_error_dev(self, "couldn't establish power handler\n"); 306} 307 308