siisata_pci.c revision 1.18
1/* $NetBSD: siisata_pci.c,v 1.18 2018/10/22 21:40:45 jdolecek Exp $ */ 2 3/* 4 * Copyright (c) 2006 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 */ 27 28/* 29 * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 30 * All rights reserved. 31 * 32 * Redistribution and use in source and binary forms, with or without 33 * modification, are permitted provided that the following conditions 34 * are met: 35 * 1. Redistributions of source code must retain the above copyright 36 * notice, this list of conditions and the following disclaimer. 37 * 2. Redistributions in binary form must reproduce the above copyright 38 * notice, this list of conditions and the following disclaimer in the 39 * documentation and/or other materials provided with the distribution. 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53#include <sys/cdefs.h> 54__KERNEL_RCSID(0, "$NetBSD: siisata_pci.c,v 1.18 2018/10/22 21:40:45 jdolecek Exp $"); 55 56#include <sys/types.h> 57#include <sys/malloc.h> 58#include <sys/param.h> 59#include <sys/kernel.h> 60#include <sys/systm.h> 61 62#include <dev/pci/pcivar.h> 63#include <dev/pci/pcidevs.h> 64#include <dev/ic/siisatavar.h> 65 66struct siisata_pci_softc { 67 struct siisata_softc si_sc; 68 pci_chipset_tag_t sc_pc; 69 pcitag_t sc_pcitag; 70 pci_intr_handle_t *sc_pihp; 71 void *sc_ih; 72}; 73 74static int siisata_pci_match(device_t, cfdata_t, void *); 75static void siisata_pci_attach(device_t, device_t, void *); 76static int siisata_pci_detach(device_t, int); 77static bool siisata_pci_resume(device_t, const pmf_qual_t *); 78 79struct siisata_pci_board { 80 pci_vendor_id_t spb_vend; 81 pci_product_id_t spb_prod; 82 uint16_t spb_port; 83 uint16_t spb_chip; 84}; 85 86static const struct siisata_pci_board siisata_pci_boards[] = { 87 { 88 .spb_vend = PCI_VENDOR_CMDTECH, 89 .spb_prod = PCI_PRODUCT_CMDTECH_3124, 90 .spb_port = 4, 91 .spb_chip = 3124, 92 }, 93 { 94 .spb_vend = PCI_VENDOR_CMDTECH, 95 .spb_prod = PCI_PRODUCT_CMDTECH_3132, 96 .spb_port = 2, 97 .spb_chip = 3132, 98 }, 99 { 100 .spb_vend = PCI_VENDOR_CMDTECH, 101 .spb_prod = PCI_PRODUCT_CMDTECH_AAR_1220SA, 102 .spb_port = 2, 103 .spb_chip = 3132, 104 }, 105 { 106 .spb_vend = PCI_VENDOR_CMDTECH, 107 .spb_prod = PCI_PRODUCT_CMDTECH_3531, 108 .spb_port = 1, 109 .spb_chip = 3531, 110 }, 111}; 112 113CFATTACH_DECL_NEW(siisata_pci, sizeof(struct siisata_pci_softc), 114 siisata_pci_match, siisata_pci_attach, siisata_pci_detach, NULL); 115 116static const struct siisata_pci_board * 117siisata_pci_lookup(const struct pci_attach_args * pa) 118{ 119 int i; 120 121 for (i = 0; i < __arraycount(siisata_pci_boards); i++) { 122 if (siisata_pci_boards[i].spb_vend != PCI_VENDOR(pa->pa_id)) 123 continue; 124 if (siisata_pci_boards[i].spb_prod == PCI_PRODUCT(pa->pa_id)) 125 return &siisata_pci_boards[i]; 126 } 127 128 return NULL; 129} 130 131static int 132siisata_pci_match(device_t parent, cfdata_t match, void *aux) 133{ 134 struct pci_attach_args *pa = aux; 135 136 if (siisata_pci_lookup(pa) != NULL) 137 return 3; 138 139 return 0; 140} 141 142static void 143siisata_pci_attach(device_t parent, device_t self, void *aux) 144{ 145 struct pci_attach_args *pa = aux; 146 struct siisata_pci_softc *psc = device_private(self); 147 struct siisata_softc *sc = &psc->si_sc; 148 const char *intrstr; 149 pcireg_t csr, memtype; 150 const struct siisata_pci_board *spbp; 151 bus_space_tag_t memt; 152 bus_space_handle_t memh; 153 uint32_t gcreg; 154 int memh_valid; 155 bus_size_t grsize, prsize; 156 char intrbuf[PCI_INTRSTR_LEN]; 157 158 sc->sc_atac.atac_dev = self; 159 160 psc->sc_pc = pa->pa_pc; 161 psc->sc_pcitag = pa->pa_tag; 162 163 pci_aprint_devinfo(pa, "SATA-II HBA"); 164 165 /* map BAR 0, global registers */ 166 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR0); 167 switch (memtype) { 168 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 169 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 170 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR0, 171 memtype, 0, &memt, &memh, NULL, &grsize) == 0); 172 break; 173 default: 174 memh_valid = 0; 175 } 176 if (memh_valid) { 177 sc->sc_grt = memt; 178 sc->sc_grh = memh; 179 sc->sc_grs = grsize; 180 } else { 181 aprint_error_dev(self, "couldn't map global registers\n"); 182 return; 183 } 184 185 /* map BAR 1, port registers */ 186 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, SIISATA_PCI_BAR1); 187 switch (memtype) { 188 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 189 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 190 memh_valid = (pci_mapreg_map(pa, SIISATA_PCI_BAR1, 191 memtype, 0, &memt, &memh, NULL, &prsize) == 0); 192 break; 193 default: 194 memh_valid = 0; 195 } 196 if (memh_valid) { 197 sc->sc_prt = memt; 198 sc->sc_prh = memh; 199 sc->sc_prs = prsize; 200 } else { 201 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 202 aprint_error_dev(self, "couldn't map port registers\n"); 203 return; 204 } 205 206 if (pci_dma64_available(pa)) 207 sc->sc_dmat = pa->pa_dmat64; 208 else 209 sc->sc_dmat = pa->pa_dmat; 210 211 /* map interrupt */ 212 if (pci_intr_alloc(pa, &psc->sc_pihp, NULL, 0) != 0) { 213 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 214 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 215 aprint_error_dev(self, "couldn't map interrupt\n"); 216 return; 217 } 218 intrstr = pci_intr_string(pa->pa_pc, psc->sc_pihp[0], intrbuf, 219 sizeof(intrbuf)); 220 psc->sc_ih = pci_intr_establish_xname(pa->pa_pc, psc->sc_pihp[0], 221 IPL_BIO, siisata_intr, sc, device_xname(self)); 222 if (psc->sc_ih == NULL) { 223 bus_space_unmap(sc->sc_grt, sc->sc_grh, grsize); 224 bus_space_unmap(sc->sc_prt, sc->sc_prh, prsize); 225 aprint_error_dev(self, "couldn't establish interrupt at %s\n", 226 intrstr); 227 return; 228 } 229 aprint_normal_dev(self, "interrupting at %s\n", 230 intrstr ? intrstr : "unknown interrupt"); 231 232 /* fill in number of ports on this device */ 233 spbp = siisata_pci_lookup(pa); 234 KASSERT(spbp != NULL); 235 sc->sc_atac.atac_nchannels = spbp->spb_port; 236 237 /* set the necessary bits in case the firmware didn't */ 238 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 239 csr |= PCI_COMMAND_MASTER_ENABLE; 240 csr |= PCI_COMMAND_MEM_ENABLE; 241 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr); 242 243 gcreg = GRREAD(sc, GR_GC); 244 245 aprint_verbose_dev(self, "SiI%d, %sGb/s\n", 246 spbp->spb_chip, (gcreg & GR_GC_3GBPS) ? "3.0" : "1.5" ); 247 if (spbp->spb_chip == 3124) { 248 short width; 249 short speed; 250 char pcix = 1; 251 252 width = (gcreg & GR_GC_REQ64) ? 64 : 32; 253 254 switch (gcreg & (GR_GC_DEVSEL | GR_GC_STOP | GR_GC_TRDY)) { 255 case 0: 256 speed = (gcreg & GR_GC_M66EN) ? 66 : 33; 257 pcix = 0; 258 break; 259 case GR_GC_TRDY: 260 speed = 66; 261 break; 262 case GR_GC_STOP: 263 speed = 100; 264 break; 265 case GR_GC_STOP | GR_GC_TRDY: 266 speed = 133; 267 break; 268 default: 269 speed = -1; 270 break; 271 } 272 aprint_verbose_dev(self, "%hd-bit %hdMHz PCI%s\n", 273 width, speed, pcix ? "-X" : ""); 274 } 275 276 siisata_attach(sc); 277 278 if (!pmf_device_register(self, NULL, siisata_pci_resume)) 279 aprint_error_dev(self, "couldn't establish power handler\n"); 280} 281 282static int 283siisata_pci_detach(device_t dv, int flags) 284{ 285 struct siisata_pci_softc *psc = device_private(dv); 286 struct siisata_softc *sc = &psc->si_sc; 287 int rv; 288 289 rv = siisata_detach(sc, flags); 290 if (rv) 291 return rv; 292 293 if (psc->sc_ih != NULL) { 294 pci_intr_disestablish(psc->sc_pc, psc->sc_ih); 295 psc->sc_ih = NULL; 296 } 297 298 if (psc->sc_pihp != NULL) { 299 pci_intr_release(psc->sc_pc, psc->sc_pihp, 1); 300 psc->sc_pihp = NULL; 301 } 302 303 bus_space_unmap(sc->sc_prt, sc->sc_prh, sc->sc_prs); 304 bus_space_unmap(sc->sc_grt, sc->sc_grh, sc->sc_grs); 305 306 return 0; 307} 308 309static bool 310siisata_pci_resume(device_t dv, const pmf_qual_t *qual) 311{ 312 struct siisata_pci_softc *psc = device_private(dv); 313 struct siisata_softc *sc = &psc->si_sc; 314 int s; 315 316 s = splbio(); 317 siisata_resume(sc); 318 splx(s); 319 320 return true; 321} 322